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5710de45 PW |
1 | /* |
2 | * (C) Copyright 2009 | |
3 | * Marvell Semiconductor <www.marvell.com> | |
4 | * Written-by: Prafulla Wadaskar <prafulla@marvell.com> | |
5 | * | |
6 | * Derived from drivers/spi/mpc8xxx_spi.c | |
7 | * | |
1a459660 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
5710de45 PW |
9 | */ |
10 | ||
11 | #include <common.h> | |
12 | #include <malloc.h> | |
13 | #include <spi.h> | |
a7efd719 | 14 | #include <asm/io.h> |
3dc23f78 | 15 | #include <asm/arch/soc.h> |
4aceea20 | 16 | #ifdef CONFIG_KIRKWOOD |
5710de45 | 17 | #include <asm/arch/mpp.h> |
4aceea20 | 18 | #endif |
3e972cb9 | 19 | #include <asm/arch-mvebu/spi.h> |
5710de45 | 20 | |
4fd7717e SR |
21 | static struct kwspi_registers *spireg = |
22 | (struct kwspi_registers *)MVEBU_SPI_BASE; | |
5710de45 | 23 | |
4aceea20 | 24 | #ifdef CONFIG_KIRKWOOD |
0299046e | 25 | static u32 cs_spi_mpp_back[2]; |
4aceea20 | 26 | #endif |
ca880679 | 27 | |
5710de45 PW |
28 | struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, |
29 | unsigned int max_hz, unsigned int mode) | |
30 | { | |
31 | struct spi_slave *slave; | |
32 | u32 data; | |
4aceea20 | 33 | #ifdef CONFIG_KIRKWOOD |
9d86f0c3 AA |
34 | static const u32 kwspi_mpp_config[2][2] = { |
35 | { MPP0_SPI_SCn, 0 }, /* if cs == 0 */ | |
36 | { MPP7_SPI_SCn, 0 } /* if cs != 0 */ | |
37 | }; | |
4aceea20 | 38 | #endif |
5710de45 PW |
39 | |
40 | if (!spi_cs_is_valid(bus, cs)) | |
41 | return NULL; | |
42 | ||
d3504fee | 43 | slave = spi_alloc_slave_base(bus, cs); |
5710de45 PW |
44 | if (!slave) |
45 | return NULL; | |
46 | ||
c032174f | 47 | writel(KWSPI_SMEMRDY, &spireg->ctrl); |
5710de45 PW |
48 | |
49 | /* calculate spi clock prescaller using max_hz */ | |
8203b201 VL |
50 | data = ((CONFIG_SYS_TCLK / 2) / max_hz) + 0x10; |
51 | data = data < KWSPI_CLKPRESCL_MIN ? KWSPI_CLKPRESCL_MIN : data; | |
52 | data = data > KWSPI_CLKPRESCL_MASK ? KWSPI_CLKPRESCL_MASK : data; | |
5710de45 PW |
53 | |
54 | /* program spi clock prescaller using max_hz */ | |
55 | writel(KWSPI_ADRLEN_3BYTE | data, &spireg->cfg); | |
bf9b86dc | 56 | debug("data = 0x%08x\n", data); |
5710de45 PW |
57 | |
58 | writel(KWSPI_SMEMRDIRQ, &spireg->irq_cause); | |
3f843551 | 59 | writel(KWSPI_IRQMASK, &spireg->irq_mask); |
5710de45 | 60 | |
4aceea20 | 61 | #ifdef CONFIG_KIRKWOOD |
5710de45 | 62 | /* program mpp registers to select SPI_CSn */ |
9d86f0c3 | 63 | kirkwood_mpp_conf(kwspi_mpp_config[cs ? 1 : 0], cs_spi_mpp_back); |
4aceea20 | 64 | #endif |
5710de45 PW |
65 | |
66 | return slave; | |
67 | } | |
68 | ||
69 | void spi_free_slave(struct spi_slave *slave) | |
70 | { | |
4aceea20 | 71 | #ifdef CONFIG_KIRKWOOD |
ca880679 | 72 | kirkwood_mpp_conf(cs_spi_mpp_back, NULL); |
4aceea20 | 73 | #endif |
5710de45 PW |
74 | free(slave); |
75 | } | |
76 | ||
ac486e3b VL |
77 | #if defined(CONFIG_SYS_KW_SPI_MPP) |
78 | u32 spi_mpp_backup[4]; | |
79 | #endif | |
80 | ||
24934fea VL |
81 | __attribute__((weak)) int board_spi_claim_bus(struct spi_slave *slave) |
82 | { | |
83 | return 0; | |
84 | } | |
85 | ||
5710de45 PW |
86 | int spi_claim_bus(struct spi_slave *slave) |
87 | { | |
ac486e3b VL |
88 | #if defined(CONFIG_SYS_KW_SPI_MPP) |
89 | u32 config; | |
90 | u32 spi_mpp_config[4]; | |
91 | ||
92 | config = CONFIG_SYS_KW_SPI_MPP; | |
93 | ||
94 | if (config & MOSI_MPP6) | |
95 | spi_mpp_config[0] = MPP6_SPI_MOSI; | |
96 | else | |
97 | spi_mpp_config[0] = MPP1_SPI_MOSI; | |
98 | ||
99 | if (config & SCK_MPP10) | |
100 | spi_mpp_config[1] = MPP10_SPI_SCK; | |
101 | else | |
102 | spi_mpp_config[1] = MPP2_SPI_SCK; | |
103 | ||
104 | if (config & MISO_MPP11) | |
105 | spi_mpp_config[2] = MPP11_SPI_MISO; | |
106 | else | |
107 | spi_mpp_config[2] = MPP3_SPI_MISO; | |
108 | ||
109 | spi_mpp_config[3] = 0; | |
110 | spi_mpp_backup[3] = 0; | |
111 | ||
112 | /* set new spi mpp and save current mpp config */ | |
113 | kirkwood_mpp_conf(spi_mpp_config, spi_mpp_backup); | |
ac486e3b VL |
114 | #endif |
115 | ||
24934fea VL |
116 | return board_spi_claim_bus(slave); |
117 | } | |
118 | ||
119 | __attribute__((weak)) void board_spi_release_bus(struct spi_slave *slave) | |
120 | { | |
5710de45 PW |
121 | } |
122 | ||
123 | void spi_release_bus(struct spi_slave *slave) | |
124 | { | |
ac486e3b VL |
125 | #if defined(CONFIG_SYS_KW_SPI_MPP) |
126 | kirkwood_mpp_conf(spi_mpp_backup, NULL); | |
127 | #endif | |
24934fea VL |
128 | |
129 | board_spi_release_bus(slave); | |
5710de45 PW |
130 | } |
131 | ||
132 | #ifndef CONFIG_SPI_CS_IS_VALID | |
133 | /* | |
134 | * you can define this function board specific | |
135 | * define above CONFIG in board specific config file and | |
136 | * provide the function in board specific src file | |
137 | */ | |
138 | int spi_cs_is_valid(unsigned int bus, unsigned int cs) | |
139 | { | |
bf9b86dc | 140 | return bus == 0 && (cs == 0 || cs == 1); |
5710de45 PW |
141 | } |
142 | #endif | |
143 | ||
efa4e43a MW |
144 | void spi_init(void) |
145 | { | |
146 | } | |
147 | ||
18dd3b22 SR |
148 | static void _spi_cs_activate(struct kwspi_registers *reg) |
149 | { | |
150 | setbits_le32(®->ctrl, KWSPI_CSN_ACT); | |
151 | } | |
152 | ||
153 | static void _spi_cs_deactivate(struct kwspi_registers *reg) | |
154 | { | |
155 | clrbits_le32(®->ctrl, KWSPI_CSN_ACT); | |
156 | } | |
157 | ||
5710de45 PW |
158 | void spi_cs_activate(struct spi_slave *slave) |
159 | { | |
18dd3b22 | 160 | _spi_cs_activate(spireg); |
5710de45 PW |
161 | } |
162 | ||
163 | void spi_cs_deactivate(struct spi_slave *slave) | |
164 | { | |
18dd3b22 | 165 | _spi_cs_deactivate(spireg); |
5710de45 PW |
166 | } |
167 | ||
18dd3b22 SR |
168 | static int _spi_xfer(struct kwspi_registers *reg, unsigned int bitlen, |
169 | const void *dout, void *din, unsigned long flags) | |
5710de45 PW |
170 | { |
171 | unsigned int tmpdout, tmpdin; | |
172 | int tm, isread = 0; | |
173 | ||
18dd3b22 | 174 | debug("spi_xfer: dout %p din %p bitlen %u\n", dout, din, bitlen); |
5710de45 PW |
175 | |
176 | if (flags & SPI_XFER_BEGIN) | |
18dd3b22 | 177 | _spi_cs_activate(reg); |
5710de45 PW |
178 | |
179 | /* | |
180 | * handle data in 8-bit chunks | |
181 | * TBD: 2byte xfer mode to be enabled | |
182 | */ | |
18dd3b22 | 183 | clrsetbits_le32(®->cfg, KWSPI_XFERLEN_MASK, KWSPI_XFERLEN_1BYTE); |
5710de45 PW |
184 | |
185 | while (bitlen > 4) { | |
186 | debug("loopstart bitlen %d\n", bitlen); | |
187 | tmpdout = 0; | |
188 | ||
189 | /* Shift data so it's msb-justified */ | |
190 | if (dout) | |
bf9b86dc | 191 | tmpdout = *(u32 *)dout & 0xff; |
5710de45 | 192 | |
18dd3b22 SR |
193 | clrbits_le32(®->irq_cause, KWSPI_SMEMRDIRQ); |
194 | writel(tmpdout, ®->dout); /* Write the data out */ | |
5710de45 PW |
195 | debug("*** spi_xfer: ... %08x written, bitlen %d\n", |
196 | tmpdout, bitlen); | |
197 | ||
198 | /* | |
199 | * Wait for SPI transmit to get out | |
200 | * or time out (1 second = 1000 ms) | |
201 | * The NE event must be read and cleared first | |
202 | */ | |
203 | for (tm = 0, isread = 0; tm < KWSPI_TIMEOUT; ++tm) { | |
18dd3b22 | 204 | if (readl(®->irq_cause) & KWSPI_SMEMRDIRQ) { |
5710de45 | 205 | isread = 1; |
18dd3b22 | 206 | tmpdin = readl(®->din); |
bf9b86dc SR |
207 | debug("spi_xfer: din %p..%08x read\n", |
208 | din, tmpdin); | |
5710de45 PW |
209 | |
210 | if (din) { | |
bf9b86dc | 211 | *((u8 *)din) = (u8)tmpdin; |
5710de45 PW |
212 | din += 1; |
213 | } | |
214 | if (dout) | |
215 | dout += 1; | |
216 | bitlen -= 8; | |
217 | } | |
218 | if (isread) | |
219 | break; | |
220 | } | |
221 | if (tm >= KWSPI_TIMEOUT) | |
222 | printf("*** spi_xfer: Time out during SPI transfer\n"); | |
223 | ||
224 | debug("loopend bitlen %d\n", bitlen); | |
225 | } | |
226 | ||
227 | if (flags & SPI_XFER_END) | |
18dd3b22 | 228 | _spi_cs_deactivate(reg); |
5710de45 PW |
229 | |
230 | return 0; | |
231 | } | |
18dd3b22 SR |
232 | |
233 | int spi_xfer(struct spi_slave *slave, unsigned int bitlen, | |
234 | const void *dout, void *din, unsigned long flags) | |
235 | { | |
236 | return _spi_xfer(spireg, bitlen, dout, din, flags); | |
237 | } |