[thirdparty/u-boot.git] / drivers / spi / kirkwood_spi.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2009
 * Marvell Semiconductor <www.marvell.com>
 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
 *
 * Derived from drivers/spi/mpc8xxx_spi.c
 */

#include <common.h>
#include <dm.h>
#include <malloc.h>
#include <spi.h>
#include <asm/io.h>
#include <asm/arch/soc.h>
#ifdef CONFIG_KIRKWOOD
#include <asm/arch/mpp.h>
#endif
#include <asm/arch-mvebu/spi.h>

static void _spi_cs_activate(struct kwspi_registers *reg)
{
	setbits_le32(&reg->ctrl, KWSPI_CSN_ACT);
}

static void _spi_cs_deactivate(struct kwspi_registers *reg)
{
	clrbits_le32(&reg->ctrl, KWSPI_CSN_ACT);
}

static int _spi_xfer(struct kwspi_registers *reg, unsigned int bitlen,
		     const void *dout, void *din, unsigned long flags)
{
	unsigned int tmpdout, tmpdin;
	int tm, isread = 0;

	debug("spi_xfer: dout %p din %p bitlen %u\n", dout, din, bitlen);

	if (flags & SPI_XFER_BEGIN)
		_spi_cs_activate(reg);

	/*
	 * handle data in 8-bit chunks
	 * TBD: 2byte xfer mode to be enabled
	 */
	clrsetbits_le32(&reg->cfg, KWSPI_XFERLEN_MASK, KWSPI_XFERLEN_1BYTE);

	while (bitlen > 4) {
		debug("loopstart bitlen %d\n", bitlen);
		tmpdout = 0;

		/* Shift data so it's msb-justified */
		if (dout)
			tmpdout = *(u32 *)dout & 0xff;

		clrbits_le32(&reg->irq_cause, KWSPI_SMEMRDIRQ);
		writel(tmpdout, &reg->dout);	/* Write the data out */
		debug("*** spi_xfer: ... %08x written, bitlen %d\n",
		      tmpdout, bitlen);

		/*
		 * Wait for SPI transmit to get out
		 * or time out (1 second = 1000 ms)
		 * The NE event must be read and cleared first
		 */
		for (tm = 0, isread = 0; tm < KWSPI_TIMEOUT; ++tm) {
			if (readl(&reg->irq_cause) & KWSPI_SMEMRDIRQ) {
				isread = 1;
				tmpdin = readl(&reg->din);
				debug("spi_xfer: din %p..%08x read\n",
				      din, tmpdin);

				if (din) {
					*((u8 *)din) = (u8)tmpdin;
					din += 1;
				}
				if (dout)
					dout += 1;
				bitlen -= 8;
			}
			if (isread)
				break;
		}
		if (tm >= KWSPI_TIMEOUT)
			printf("*** spi_xfer: Time out during SPI transfer\n");

		debug("loopend bitlen %d\n", bitlen);
	}

	if (flags & SPI_XFER_END)
		_spi_cs_deactivate(reg);

	return 0;
}

#ifndef CONFIG_DM_SPI

static struct kwspi_registers *spireg =
	(struct kwspi_registers *)MVEBU_SPI_BASE;

#ifdef CONFIG_KIRKWOOD
static u32 cs_spi_mpp_back[2];
#endif

struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
				unsigned int max_hz, unsigned int mode)
{
	struct spi_slave *slave;
	u32 data;
#ifdef CONFIG_KIRKWOOD
	static const u32 kwspi_mpp_config[2][2] = {
		{ MPP0_SPI_SCn, 0 }, /* if cs == 0 */
		{ MPP7_SPI_SCn, 0 } /* if cs != 0 */
	};
#endif

	if (!spi_cs_is_valid(bus, cs))
		return NULL;

	slave = spi_alloc_slave_base(bus, cs);
	if (!slave)
		return NULL;

	writel(KWSPI_SMEMRDY, &spireg->ctrl);

	/* calculate spi clock prescaller using max_hz */
	data = ((CONFIG_SYS_TCLK / 2) / max_hz) + 0x10;
	data = data < KWSPI_CLKPRESCL_MIN ? KWSPI_CLKPRESCL_MIN : data;
	data = data > KWSPI_CLKPRESCL_MASK ? KWSPI_CLKPRESCL_MASK : data;

	/* program spi clock prescaller using max_hz */
	writel(KWSPI_ADRLEN_3BYTE | data, &spireg->cfg);
	debug("data = 0x%08x\n", data);

	writel(KWSPI_SMEMRDIRQ, &spireg->irq_cause);
	writel(KWSPI_IRQMASK, &spireg->irq_mask);

#ifdef CONFIG_KIRKWOOD
	/* program mpp registers to select  SPI_CSn */
	kirkwood_mpp_conf(kwspi_mpp_config[cs ? 1 : 0], cs_spi_mpp_back);
#endif

	return slave;
}

void spi_free_slave(struct spi_slave *slave)
{
#ifdef CONFIG_KIRKWOOD
	kirkwood_mpp_conf(cs_spi_mpp_back, NULL);
#endif
	free(slave);
}

#if defined(CONFIG_SYS_KW_SPI_MPP)
u32 spi_mpp_backup[4];
#endif

__attribute__((weak)) int board_spi_claim_bus(struct spi_slave *slave)
{
	return 0;
}

int spi_claim_bus(struct spi_slave *slave)
{
#if defined(CONFIG_SYS_KW_SPI_MPP)
	u32 config;
	u32 spi_mpp_config[4];

	config = CONFIG_SYS_KW_SPI_MPP;

	if (config & MOSI_MPP6)
		spi_mpp_config[0] = MPP6_SPI_MOSI;
	else
		spi_mpp_config[0] = MPP1_SPI_MOSI;

	if (config & SCK_MPP10)
		spi_mpp_config[1] = MPP10_SPI_SCK;
	else
		spi_mpp_config[1] = MPP2_SPI_SCK;

	if (config & MISO_MPP11)
		spi_mpp_config[2] = MPP11_SPI_MISO;
	else
		spi_mpp_config[2] = MPP3_SPI_MISO;

	spi_mpp_config[3] = 0;
	spi_mpp_backup[3] = 0;

	/* set new spi mpp and save current mpp config */
	kirkwood_mpp_conf(spi_mpp_config, spi_mpp_backup);
#endif

	return board_spi_claim_bus(slave);
}

__attribute__((weak)) void board_spi_release_bus(struct spi_slave *slave)
{
}

void spi_release_bus(struct spi_slave *slave)
{
#if defined(CONFIG_SYS_KW_SPI_MPP)
	kirkwood_mpp_conf(spi_mpp_backup, NULL);
#endif

	board_spi_release_bus(slave);
}

#ifndef CONFIG_SPI_CS_IS_VALID
/*
 * you can define this function board specific
 * define above CONFIG in board specific config file and
 * provide the function in board specific src file
 */
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
	return bus == 0 && (cs == 0 || cs == 1);
}
#endif

void spi_init(void)
{
}

void spi_cs_activate(struct spi_slave *slave)
{
	_spi_cs_activate(spireg);
}

void spi_cs_deactivate(struct spi_slave *slave)
{
	_spi_cs_deactivate(spireg);
}

int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
	     const void *dout, void *din, unsigned long flags)
{
	return _spi_xfer(spireg, bitlen, dout, din, flags);
}

#else

/* Here now the DM part */

struct mvebu_spi_dev {
	bool			is_errata_50mhz_ac;
};

struct mvebu_spi_platdata {
	struct kwspi_registers *spireg;
};

struct mvebu_spi_priv {
	struct kwspi_registers *spireg;
};

static int mvebu_spi_set_speed(struct udevice *bus, uint hz)
{
	struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
	struct kwspi_registers *reg = plat->spireg;
	u32 data;

	/* calculate spi clock prescaller using max_hz */
	data = ((CONFIG_SYS_TCLK / 2) / hz) + 0x10;
	data = data < KWSPI_CLKPRESCL_MIN ? KWSPI_CLKPRESCL_MIN : data;
	data = data > KWSPI_CLKPRESCL_MASK ? KWSPI_CLKPRESCL_MASK : data;

	/* program spi clock prescaler using max_hz */
	writel(KWSPI_ADRLEN_3BYTE | data, &reg->cfg);
	debug("data = 0x%08x\n", data);

	return 0;
}

static void mvebu_spi_50mhz_ac_timing_erratum(struct udevice *bus, uint mode)
{
	struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
	struct kwspi_registers *reg = plat->spireg;
	u32 data;

	/*
	 * Erratum description: (Erratum NO. FE-9144572) The device
	 * SPI interface supports frequencies of up to 50 MHz.
	 * However, due to this erratum, when the device core clock is
	 * 250 MHz and the SPI interfaces is configured for 50MHz SPI
	 * clock and CPOL=CPHA=1 there might occur data corruption on
	 * reads from the SPI device.
	 * Erratum Workaround:
	 * Work in one of the following configurations:
	 * 1. Set CPOL=CPHA=0 in "SPI Interface Configuration
	 * Register".
	 * 2. Set TMISO_SAMPLE value to 0x2 in "SPI Timing Parameters 1
	 * Register" before setting the interface.
	 */
	data = readl(&reg->timing1);
	data &= ~KW_SPI_TMISO_SAMPLE_MASK;

	if (CONFIG_SYS_TCLK == 250000000 &&
	    mode & SPI_CPOL &&
	    mode & SPI_CPHA)
		data |= KW_SPI_TMISO_SAMPLE_2;
	else
		data |= KW_SPI_TMISO_SAMPLE_1;

	writel(data, &reg->timing1);
}

static int mvebu_spi_set_mode(struct udevice *bus, uint mode)
{
	struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
	struct kwspi_registers *reg = plat->spireg;
	const struct mvebu_spi_dev *drvdata;
	u32 data = readl(&reg->cfg);

	data &= ~(KWSPI_CPHA | KWSPI_CPOL | KWSPI_RXLSBF | KWSPI_TXLSBF);

	if (mode & SPI_CPHA)
		data |= KWSPI_CPHA;
	if (mode & SPI_CPOL)
		data |= KWSPI_CPOL;
	if (mode & SPI_LSB_FIRST)
		data |= (KWSPI_RXLSBF | KWSPI_TXLSBF);

	writel(data, &reg->cfg);

	drvdata = (struct mvebu_spi_dev *)dev_get_driver_data(bus);
	if (drvdata->is_errata_50mhz_ac)
		mvebu_spi_50mhz_ac_timing_erratum(bus, mode);

	return 0;
}

static int mvebu_spi_xfer(struct udevice *dev, unsigned int bitlen,
			  const void *dout, void *din, unsigned long flags)
{
	struct udevice *bus = dev->parent;
	struct mvebu_spi_platdata *plat = dev_get_platdata(bus);

	return _spi_xfer(plat->spireg, bitlen, dout, din, flags);
}

static int mvebu_spi_claim_bus(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct mvebu_spi_platdata *plat = dev_get_platdata(bus);

	/* Configure the chip-select in the CTRL register */
	clrsetbits_le32(&plat->spireg->ctrl,
			KWSPI_CS_MASK << KWSPI_CS_SHIFT,
			spi_chip_select(dev) << KWSPI_CS_SHIFT);

	return 0;
}

static int mvebu_spi_probe(struct udevice *bus)
{
	struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
	struct kwspi_registers *reg = plat->spireg;

	writel(KWSPI_SMEMRDY, &reg->ctrl);
	writel(KWSPI_SMEMRDIRQ, &reg->irq_cause);
	writel(KWSPI_IRQMASK, &reg->irq_mask);

	return 0;
}

static int mvebu_spi_ofdata_to_platdata(struct udevice *bus)
{
	struct mvebu_spi_platdata *plat = dev_get_platdata(bus);

	plat->spireg = (struct kwspi_registers *)devfdt_get_addr(bus);

	return 0;
}

static const struct dm_spi_ops mvebu_spi_ops = {
	.claim_bus	= mvebu_spi_claim_bus,
	.xfer		= mvebu_spi_xfer,
	.set_speed	= mvebu_spi_set_speed,
	.set_mode	= mvebu_spi_set_mode,
	/*
	 * cs_info is not needed, since we require all chip selects to be
	 * in the device tree explicitly
	 */
};

static const struct mvebu_spi_dev armada_xp_spi_dev_data = {
	.is_errata_50mhz_ac = false,
};

static const struct mvebu_spi_dev armada_375_spi_dev_data = {
	.is_errata_50mhz_ac = false,
};

static const struct mvebu_spi_dev armada_380_spi_dev_data = {
	.is_errata_50mhz_ac = true,
};

static const struct udevice_id mvebu_spi_ids[] = {
	{
		.compatible = "marvell,armada-375-spi",
		.data = (ulong)&armada_375_spi_dev_data
	},
	{
		.compatible = "marvell,armada-380-spi",
		.data = (ulong)&armada_380_spi_dev_data
	},
	{
		.compatible = "marvell,armada-xp-spi",
		.data = (ulong)&armada_xp_spi_dev_data
	},
	{ }
};

U_BOOT_DRIVER(mvebu_spi) = {
	.name = "mvebu_spi",
	.id = UCLASS_SPI,
	.of_match = mvebu_spi_ids,
	.ops = &mvebu_spi_ops,
	.ofdata_to_platdata = mvebu_spi_ofdata_to_platdata,
	.platdata_auto_alloc_size = sizeof(struct mvebu_spi_platdata),
	.priv_auto_alloc_size = sizeof(struct mvebu_spi_priv),
	.probe = mvebu_spi_probe,
};
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
5710de45 PW	2	/*
	3	* (C) Copyright 2009
	4	* Marvell Semiconductor <www.marvell.com>
	5	* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
	6	*
	7	* Derived from drivers/spi/mpc8xxx_spi.c
5710de45 PW	8	*/
	9
	10	#include <common.h>
9985bdb1	11	#include <dm.h>
5710de45 PW	12	#include <malloc.h>
5710de45 PW	13	#include <spi.h>
a7efd719	14	#include <asm/io.h>
3dc23f78	15	#include <asm/arch/soc.h>
4aceea20	16	#ifdef CONFIG_KIRKWOOD
5710de45	17	#include <asm/arch/mpp.h>
4aceea20	18	#endif
3e972cb9	19	#include <asm/arch-mvebu/spi.h>
5710de45	20
9985bdb1 SR	21	static void _spi_cs_activate(struct kwspi_registers *reg)
	22	{
	23	setbits_le32(&reg->ctrl, KWSPI_CSN_ACT);
	24	}
	25
	26	static void _spi_cs_deactivate(struct kwspi_registers *reg)
	27	{
	28	clrbits_le32(&reg->ctrl, KWSPI_CSN_ACT);
	29	}
	30
	31	static int _spi_xfer(struct kwspi_registers *reg, unsigned int bitlen,
	32	const void dout, void din, unsigned long flags)
	33	{
	34	unsigned int tmpdout, tmpdin;
	35	int tm, isread = 0;
	36
	37	debug("spi_xfer: dout %p din %p bitlen %u\n", dout, din, bitlen);
	38
	39	if (flags & SPI_XFER_BEGIN)
	40	_spi_cs_activate(reg);
	41
	42	/*
	43	* handle data in 8-bit chunks
	44	* TBD: 2byte xfer mode to be enabled
	45	*/
	46	clrsetbits_le32(&reg->cfg, KWSPI_XFERLEN_MASK, KWSPI_XFERLEN_1BYTE);
	47
	48	while (bitlen > 4) {
	49	debug("loopstart bitlen %d\n", bitlen);
	50	tmpdout = 0;
	51
	52	/* Shift data so it's msb-justified */
	53	if (dout)
	54	tmpdout = (u32 )dout & 0xff;
	55
	56	clrbits_le32(&reg->irq_cause, KWSPI_SMEMRDIRQ);
	57	writel(tmpdout, &reg->dout); /* Write the data out */
	58	debug("*** spi_xfer: ... %08x written, bitlen %d\n",
	59	tmpdout, bitlen);
	60
	61	/*
	62	* Wait for SPI transmit to get out
	63	* or time out (1 second = 1000 ms)
	64	* The NE event must be read and cleared first
	65	*/
	66	for (tm = 0, isread = 0; tm < KWSPI_TIMEOUT; ++tm) {
	67	if (readl(&reg->irq_cause) & KWSPI_SMEMRDIRQ) {
	68	isread = 1;
	69	tmpdin = readl(&reg->din);
	70	debug("spi_xfer: din %p..%08x read\n",
	71	din, tmpdin);
	72
	73	if (din) {
	74	((u8 )din) = (u8)tmpdin;
	75	din += 1;
	76	}
	77	if (dout)
	78	dout += 1;
	79	bitlen -= 8;
	80	}
	81	if (isread)
	82	break;
	83	}
	84	if (tm >= KWSPI_TIMEOUT)
85	printf("*** spi_xfer: Time out during SPI transfer\n");
86
87	debug("loopend bitlen %d\n", bitlen);
88	}
89
90	if (flags & SPI_XFER_END)
91	_spi_cs_deactivate(reg);
92
93	return 0;
94	}
95
96	#ifndef CONFIG_DM_SPI
97
4fd7717e SR	98	static struct kwspi_registers *spireg =
4fd7717e SR	99	(struct kwspi_registers *)MVEBU_SPI_BASE;
5710de45	100
4aceea20	101	#ifdef CONFIG_KIRKWOOD
0299046e	102	static u32 cs_spi_mpp_back[2];
4aceea20	103	#endif
ca880679	104
5710de45 PW	105	struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
	106	unsigned int max_hz, unsigned int mode)
	107	{
	108	struct spi_slave *slave;
	109	u32 data;
4aceea20	110	#ifdef CONFIG_KIRKWOOD
9d86f0c3 AA	111	static const u32 kwspi_mpp_config[2][2] = {
	112	{ MPP0_SPI_SCn, 0 }, /* if cs == 0 */
	113	{ MPP7_SPI_SCn, 0 } /* if cs != 0 */
	114	};
4aceea20	115	#endif
5710de45 PW	116
	117	if (!spi_cs_is_valid(bus, cs))
	118	return NULL;
	119
d3504fee	120	slave = spi_alloc_slave_base(bus, cs);
5710de45 PW	121	if (!slave)
	122	return NULL;
	123
c032174f	124	writel(KWSPI_SMEMRDY, &spireg->ctrl);
5710de45 PW	125
5710de45 PW	126	/* calculate spi clock prescaller using max_hz */
8203b201 VL	127	data = ((CONFIG_SYS_TCLK / 2) / max_hz) + 0x10;
	128	data = data < KWSPI_CLKPRESCL_MIN ? KWSPI_CLKPRESCL_MIN : data;
	129	data = data > KWSPI_CLKPRESCL_MASK ? KWSPI_CLKPRESCL_MASK : data;
5710de45 PW	130
	131	/* program spi clock prescaller using max_hz */
	132	writel(KWSPI_ADRLEN_3BYTE \| data, &spireg->cfg);
bf9b86dc	133	debug("data = 0x%08x\n", data);
5710de45 PW	134
5710de45 PW	135	writel(KWSPI_SMEMRDIRQ, &spireg->irq_cause);
3f843551	136	writel(KWSPI_IRQMASK, &spireg->irq_mask);
5710de45	137
4aceea20	138	#ifdef CONFIG_KIRKWOOD
5710de45	139	/* program mpp registers to select SPI_CSn */
9d86f0c3	140	kirkwood_mpp_conf(kwspi_mpp_config[cs ? 1 : 0], cs_spi_mpp_back);
4aceea20	141	#endif
5710de45 PW	142
	143	return slave;
	144	}
	145
	146	void spi_free_slave(struct spi_slave *slave)
	147	{
4aceea20	148	#ifdef CONFIG_KIRKWOOD
ca880679	149	kirkwood_mpp_conf(cs_spi_mpp_back, NULL);
4aceea20	150	#endif
5710de45 PW	151	free(slave);
	152	}
	153
ac486e3b VL	154	#if defined(CONFIG_SYS_KW_SPI_MPP)
	155	u32 spi_mpp_backup[4];
	156	#endif
	157
24934fea VL	158	__attribute__((weak)) int board_spi_claim_bus(struct spi_slave *slave)
	159	{
	160	return 0;
	161	}
	162
5710de45 PW	163	int spi_claim_bus(struct spi_slave *slave)
5710de45 PW	164	{
ac486e3b VL	165	#if defined(CONFIG_SYS_KW_SPI_MPP)
	166	u32 config;
	167	u32 spi_mpp_config[4];
	168
	169	config = CONFIG_SYS_KW_SPI_MPP;
	170
	171	if (config & MOSI_MPP6)
	172	spi_mpp_config[0] = MPP6_SPI_MOSI;
	173	else
	174	spi_mpp_config[0] = MPP1_SPI_MOSI;
	175
	176	if (config & SCK_MPP10)
	177	spi_mpp_config[1] = MPP10_SPI_SCK;
	178	else
	179	spi_mpp_config[1] = MPP2_SPI_SCK;
	180
	181	if (config & MISO_MPP11)
	182	spi_mpp_config[2] = MPP11_SPI_MISO;
	183	else
	184	spi_mpp_config[2] = MPP3_SPI_MISO;
	185
	186	spi_mpp_config[3] = 0;
	187	spi_mpp_backup[3] = 0;
	188
	189	/* set new spi mpp and save current mpp config */
	190	kirkwood_mpp_conf(spi_mpp_config, spi_mpp_backup);
ac486e3b VL	191	#endif
ac486e3b VL	192
24934fea VL	193	return board_spi_claim_bus(slave);
	194	}
	195
	196	__attribute__((weak)) void board_spi_release_bus(struct spi_slave *slave)
	197	{
5710de45 PW	198	}
	199
	200	void spi_release_bus(struct spi_slave *slave)
	201	{
ac486e3b VL	202	#if defined(CONFIG_SYS_KW_SPI_MPP)
	203	kirkwood_mpp_conf(spi_mpp_backup, NULL);
	204	#endif
24934fea VL	205
24934fea VL	206	board_spi_release_bus(slave);
5710de45 PW	207	}
	208
	209	#ifndef CONFIG_SPI_CS_IS_VALID
	210	/*
	211	* you can define this function board specific
	212	* define above CONFIG in board specific config file and
	213	* provide the function in board specific src file
	214	*/
	215	int spi_cs_is_valid(unsigned int bus, unsigned int cs)
	216	{
bf9b86dc	217	return bus == 0 && (cs == 0 \|\| cs == 1);
5710de45 PW	218	}
	219	#endif
	220
efa4e43a MW	221	void spi_init(void)
	222	{
	223	}
	224
5710de45 PW	225	void spi_cs_activate(struct spi_slave *slave)
5710de45 PW	226	{
18dd3b22	227	_spi_cs_activate(spireg);
5710de45 PW	228	}
	229
	230	void spi_cs_deactivate(struct spi_slave *slave)
	231	{
18dd3b22	232	_spi_cs_deactivate(spireg);
5710de45 PW	233	}
5710de45 PW	234
9985bdb1 SR	235	int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
9985bdb1 SR	236	const void dout, void din, unsigned long flags)
5710de45	237	{
9985bdb1 SR	238	return _spi_xfer(spireg, bitlen, dout, din, flags);
9985bdb1 SR	239	}
5710de45	240
9985bdb1	241	#else
5710de45	242
9985bdb1	243	/* Here now the DM part */
5710de45	244
df16881c CP	245	struct mvebu_spi_dev {
	246	bool is_errata_50mhz_ac;
	247	};
	248
9985bdb1 SR	249	struct mvebu_spi_platdata {
	250	struct kwspi_registers *spireg;
	251	};
5710de45	252
9985bdb1 SR	253	struct mvebu_spi_priv {
	254	struct kwspi_registers *spireg;
	255	};
5710de45	256
9985bdb1 SR	257	static int mvebu_spi_set_speed(struct udevice *bus, uint hz)
	258	{
	259	struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
	260	struct kwspi_registers *reg = plat->spireg;
	261	u32 data;
5710de45	262
9985bdb1 SR	263	/* calculate spi clock prescaller using max_hz */
	264	data = ((CONFIG_SYS_TCLK / 2) / hz) + 0x10;
	265	data = data < KWSPI_CLKPRESCL_MIN ? KWSPI_CLKPRESCL_MIN : data;
	266	data = data > KWSPI_CLKPRESCL_MASK ? KWSPI_CLKPRESCL_MASK : data;
5710de45	267
9985bdb1 SR	268	/* program spi clock prescaler using max_hz */
	269	writel(KWSPI_ADRLEN_3BYTE \| data, &reg->cfg);
	270	debug("data = 0x%08x\n", data);
5710de45	271
9985bdb1 SR	272	return 0;
9985bdb1 SR	273	}
5710de45	274
df16881c CP	275	static void mvebu_spi_50mhz_ac_timing_erratum(struct udevice *bus, uint mode)
	276	{
	277	struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
	278	struct kwspi_registers *reg = plat->spireg;
	279	u32 data;
	280
	281	/*
	282	* Erratum description: (Erratum NO. FE-9144572) The device
	283	* SPI interface supports frequencies of up to 50 MHz.
	284	* However, due to this erratum, when the device core clock is
	285	* 250 MHz and the SPI interfaces is configured for 50MHz SPI
	286	* clock and CPOL=CPHA=1 there might occur data corruption on
	287	* reads from the SPI device.
	288	* Erratum Workaround:
	289	* Work in one of the following configurations:
	290	* 1. Set CPOL=CPHA=0 in "SPI Interface Configuration
	291	* Register".
	292	* 2. Set TMISO_SAMPLE value to 0x2 in "SPI Timing Parameters 1
	293	* Register" before setting the interface.
	294	*/
	295	data = readl(&reg->timing1);
	296	data &= ~KW_SPI_TMISO_SAMPLE_MASK;
	297
	298	if (CONFIG_SYS_TCLK == 250000000 &&
	299	mode & SPI_CPOL &&
	300	mode & SPI_CPHA)
	301	data \|= KW_SPI_TMISO_SAMPLE_2;
	302	else
	303	data \|= KW_SPI_TMISO_SAMPLE_1;
	304
	305	writel(data, &reg->timing1);
	306	}
	307
9985bdb1 SR	308	static int mvebu_spi_set_mode(struct udevice *bus, uint mode)
9985bdb1 SR	309	{
ebfa18cb CP	310	struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
ebfa18cb CP	311	struct kwspi_registers *reg = plat->spireg;
df16881c	312	const struct mvebu_spi_dev *drvdata;
ebfa18cb CP	313	u32 data = readl(&reg->cfg);
	314
	315	data &= ~(KWSPI_CPHA \| KWSPI_CPOL \| KWSPI_RXLSBF \| KWSPI_TXLSBF);
	316
	317	if (mode & SPI_CPHA)
	318	data \|= KWSPI_CPHA;
	319	if (mode & SPI_CPOL)
	320	data \|= KWSPI_CPOL;
	321	if (mode & SPI_LSB_FIRST)
	322	data \|= (KWSPI_RXLSBF \| KWSPI_TXLSBF);
	323
	324	writel(data, &reg->cfg);
	325
df16881c CP	326	drvdata = (struct mvebu_spi_dev *)dev_get_driver_data(bus);
	327	if (drvdata->is_errata_50mhz_ac)
	328	mvebu_spi_50mhz_ac_timing_erratum(bus, mode);
	329
9985bdb1 SR	330	return 0;
9985bdb1 SR	331	}
5710de45	332
9985bdb1 SR	333	static int mvebu_spi_xfer(struct udevice *dev, unsigned int bitlen,
	334	const void dout, void din, unsigned long flags)
	335	{
	336	struct udevice *bus = dev->parent;
	337	struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
	338
	339	return _spi_xfer(plat->spireg, bitlen, dout, din, flags);
	340	}
	341
9fc56631 SR	342	static int mvebu_spi_claim_bus(struct udevice *dev)
	343	{
	344	struct udevice *bus = dev->parent;
	345	struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
	346
	347	/* Configure the chip-select in the CTRL register */
	348	clrsetbits_le32(&plat->spireg->ctrl,
	349	KWSPI_CS_MASK << KWSPI_CS_SHIFT,
	350	spi_chip_select(dev) << KWSPI_CS_SHIFT);
	351
	352	return 0;
	353	}
	354
9985bdb1 SR	355	static int mvebu_spi_probe(struct udevice *bus)
	356	{
	357	struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
	358	struct kwspi_registers *reg = plat->spireg;
	359
	360	writel(KWSPI_SMEMRDY, &reg->ctrl);
	361	writel(KWSPI_SMEMRDIRQ, &reg->irq_cause);
	362	writel(KWSPI_IRQMASK, &reg->irq_mask);
5710de45 PW	363
	364	return 0;
	365	}
18dd3b22	366
9985bdb1	367	static int mvebu_spi_ofdata_to_platdata(struct udevice *bus)
18dd3b22	368	{
9985bdb1 SR	369	struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
9985bdb1 SR	370
a821c4af	371	plat->spireg = (struct kwspi_registers *)devfdt_get_addr(bus);
9985bdb1 SR	372
9985bdb1 SR	373	return 0;
18dd3b22	374	}
9985bdb1 SR	375
9985bdb1 SR	376	static const struct dm_spi_ops mvebu_spi_ops = {
9fc56631	377	.claim_bus = mvebu_spi_claim_bus,
9985bdb1 SR	378	.xfer = mvebu_spi_xfer,
	379	.set_speed = mvebu_spi_set_speed,
	380	.set_mode = mvebu_spi_set_mode,
	381	/*
	382	* cs_info is not needed, since we require all chip selects to be
	383	* in the device tree explicitly
	384	*/
	385	};
	386
df16881c CP	387	static const struct mvebu_spi_dev armada_xp_spi_dev_data = {
	388	.is_errata_50mhz_ac = false,
	389	};
	390
	391	static const struct mvebu_spi_dev armada_375_spi_dev_data = {
	392	.is_errata_50mhz_ac = false,
	393	};
	394
	395	static const struct mvebu_spi_dev armada_380_spi_dev_data = {
	396	.is_errata_50mhz_ac = true,
	397	};
	398
9985bdb1	399	static const struct udevice_id mvebu_spi_ids[] = {
df16881c CP	400	{
	401	.compatible = "marvell,armada-375-spi",
	402	.data = (ulong)&armada_375_spi_dev_data
	403	},
	404	{
	405	.compatible = "marvell,armada-380-spi",
	406	.data = (ulong)&armada_380_spi_dev_data
	407	},
	408	{
	409	.compatible = "marvell,armada-xp-spi",
	410	.data = (ulong)&armada_xp_spi_dev_data
	411	},
9985bdb1 SR	412	{ }
	413	};
	414
	415	U_BOOT_DRIVER(mvebu_spi) = {
	416	.name = "mvebu_spi",
	417	.id = UCLASS_SPI,
	418	.of_match = mvebu_spi_ids,
	419	.ops = &mvebu_spi_ops,
	420	.ofdata_to_platdata = mvebu_spi_ofdata_to_platdata,
	421	.platdata_auto_alloc_size = sizeof(struct mvebu_spi_platdata),
	422	.priv_auto_alloc_size = sizeof(struct mvebu_spi_priv),
	423	.probe = mvebu_spi_probe,
	424	};
	425	#endif