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1/*
2 * Copyright (c) 2006 Ben Warren, Qstreams Networks Inc.
a47a12be 3 * With help from the common/soft_spi and arch/powerpc/cpu/mpc8260 drivers
04a9e118 4 *
1a459660 5 * SPDX-License-Identifier: GPL-2.0+
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6 */
7
8#include <common.h>
8931ab17 9
d255bb0e 10#include <malloc.h>
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11#include <spi.h>
12#include <asm/mpc8xxx_spi.h>
13
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14#define SPI_EV_NE (0x80000000 >> 22) /* Receiver Not Empty */
15#define SPI_EV_NF (0x80000000 >> 23) /* Transmitter Not Full */
04a9e118 16
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17#define SPI_MODE_LOOP (0x80000000 >> 1) /* Loopback mode */
18#define SPI_MODE_REV (0x80000000 >> 5) /* Reverse mode - MSB first */
19#define SPI_MODE_MS (0x80000000 >> 6) /* Always master */
20#define SPI_MODE_EN (0x80000000 >> 7) /* Enable interface */
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21
22#define SPI_TIMEOUT 1000
23
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24struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
25 unsigned int max_hz, unsigned int mode)
26{
27 struct spi_slave *slave;
28
29 if (!spi_cs_is_valid(bus, cs))
30 return NULL;
31
d3504fee 32 slave = spi_alloc_slave_base(bus, cs);
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33 if (!slave)
34 return NULL;
35
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36 /*
37 * TODO: Some of the code in spi_init() should probably move
38 * here, or into spi_claim_bus() below.
39 */
40
41 return slave;
42}
43
44void spi_free_slave(struct spi_slave *slave)
45{
46 free(slave);
47}
48
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49void spi_init(void)
50{
6d0f6bcf 51 volatile spi8xxx_t *spi = &((immap_t *) (CONFIG_SYS_IMMR))->spi;
04a9e118 52
2956acd5 53 /*
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54 * SPI pins on the MPC83xx are not muxed, so all we do is initialize
55 * some registers
2956acd5 56 */
04a9e118 57 spi->mode = SPI_MODE_REV | SPI_MODE_MS | SPI_MODE_EN;
a048d4bb 58 spi->mode = (spi->mode & 0xfff0ffff) | BIT(16); /* Use SYSCLK / 8
2956acd5 59 (16.67MHz typ.) */
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60 spi->event = 0xffffffff; /* Clear all SPI events */
61 spi->mask = 0x00000000; /* Mask all SPI interrupts */
62 spi->com = 0; /* LST bit doesn't do anything, so disregard */
63}
64
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65int spi_claim_bus(struct spi_slave *slave)
66{
67 return 0;
68}
69
70void spi_release_bus(struct spi_slave *slave)
71{
72
73}
74
75int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
76 void *din, unsigned long flags)
04a9e118 77{
6d0f6bcf 78 volatile spi8xxx_t *spi = &((immap_t *) (CONFIG_SYS_IMMR))->spi;
04a9e118 79 unsigned int tmpdout, tmpdin, event;
583fe6c3 80 int numBlks = DIV_ROUND_UP(bitlen, 32);
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81 int tm, isRead = 0;
82 unsigned char charSize = 32;
83
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84 debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n",
85 slave->bus, slave->cs, *(uint *) dout, *(uint *) din, bitlen);
04a9e118 86
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87 if (flags & SPI_XFER_BEGIN)
88 spi_cs_activate(slave);
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89
90 spi->event = 0xffffffff; /* Clear all SPI events */
91
92 /* handle data in 32-bit chunks */
93 while (numBlks--) {
94 tmpdout = 0;
95 charSize = (bitlen >= 32 ? 32 : bitlen);
96
97 /* Shift data so it's msb-justified */
98 tmpdout = *(u32 *) dout >> (32 - charSize);
99
100 /* The LEN field of the SPMODE register is set as follows:
101 *
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102 * Bit length setting
103 * len <= 4 3
104 * 4 < len <= 16 len - 1
105 * len > 16 0
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106 */
107
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108 spi->mode &= ~SPI_MODE_EN;
109
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110 if (bitlen <= 16) {
111 if (bitlen <= 4)
112 spi->mode = (spi->mode & 0xff0fffff) |
93e14596 113 (3 << 20);
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114 else
115 spi->mode = (spi->mode & 0xff0fffff) |
93e14596 116 ((bitlen - 1) << 20);
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117 } else {
118 spi->mode = (spi->mode & 0xff0fffff);
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119 /* Set up the next iteration if sending > 32 bits */
120 bitlen -= 32;
121 dout += 4;
122 }
123
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124 spi->mode |= SPI_MODE_EN;
125
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126 spi->tx = tmpdout; /* Write the data out */
127 debug("*** spi_xfer: ... %08x written\n", tmpdout);
128
2956acd5 129 /*
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130 * Wait for SPI transmit to get out
131 * or time out (1 second = 1000 ms)
132 * The NE event must be read and cleared first
2956acd5 133 */
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134 for (tm = 0, isRead = 0; tm < SPI_TIMEOUT; ++tm) {
135 event = spi->event;
136 if (event & SPI_EV_NE) {
137 tmpdin = spi->rx;
138 spi->event |= SPI_EV_NE;
139 isRead = 1;
140
141 *(u32 *) din = (tmpdin << (32 - charSize));
142 if (charSize == 32) {
143 /* Advance output buffer by 32 bits */
144 din += 4;
145 }
146 }
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147 /*
148 * Only bail when we've had both NE and NF events.
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149 * This will cause timeouts on RO devices, so maybe
150 * in the future put an arbitrary delay after writing
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151 * the device. Arbitrary delays suck, though...
152 */
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153 if (isRead && (event & SPI_EV_NF))
154 break;
155 }
156 if (tm >= SPI_TIMEOUT)
157 puts("*** spi_xfer: Time out during SPI transfer");
158
159 debug("*** spi_xfer: transfer ended. Value=%08x\n", tmpdin);
160 }
161
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162 if (flags & SPI_XFER_END)
163 spi_cs_deactivate(slave);
2956acd5 164
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165 return 0;
166}