[people/ms/u-boot.git] / drivers / spi / mxc_spi.c

/*
 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 */

#include <common.h>
#include <malloc.h>
#include <spi.h>
#include <asm/errno.h>
#include <asm/io.h>

#ifdef CONFIG_MX27
/* i.MX27 has a completely wrong register layout and register definitions in the
 * datasheet, the correct one is in the Freescale's Linux driver */

#error "i.MX27 CSPI not supported due to drastic differences in register definisions" \
"See linux mxc_spi driver from Freescale for details."

#else

#include <asm/arch/mx31.h>

#define MXC_CSPIRXDATA		0x00
#define MXC_CSPITXDATA		0x04
#define MXC_CSPICTRL		0x08
#define MXC_CSPIINT		0x0C
#define MXC_CSPIDMA		0x10
#define MXC_CSPISTAT		0x14
#define MXC_CSPIPERIOD		0x18
#define MXC_CSPITEST		0x1C
#define MXC_CSPIRESET		0x00

#define MXC_CSPICTRL_EN		(1 << 0)
#define MXC_CSPICTRL_MODE	(1 << 1)
#define MXC_CSPICTRL_XCH	(1 << 2)
#define MXC_CSPICTRL_SMC	(1 << 3)
#define MXC_CSPICTRL_POL	(1 << 4)
#define MXC_CSPICTRL_PHA	(1 << 5)
#define MXC_CSPICTRL_SSCTL	(1 << 6)
#define MXC_CSPICTRL_SSPOL	(1 << 7)
#define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 24)
#define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0x1f) << 8)
#define MXC_CSPICTRL_DATARATE(x)	(((x) & 0x7) << 16)

#define MXC_CSPIPERIOD_32KHZ	(1 << 15)

static unsigned long spi_bases[] = {
	0x43fa4000,
	0x50010000,
	0x53f84000,
};

#endif

struct mxc_spi_slave {
	struct spi_slave slave;
	unsigned long	base;
	u32		ctrl_reg;
	int		gpio;
};

static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
{
	return container_of(slave, struct mxc_spi_slave, slave);
}

static inline u32 reg_read(unsigned long addr)
{
	return *(volatile unsigned long*)addr;
}

static inline void reg_write(unsigned long addr, u32 val)
{
	*(volatile unsigned long*)addr = val;
}

static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen,
			   unsigned long flags)
{
	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
	unsigned int cfg_reg = reg_read(mxcs->base + MXC_CSPICTRL);

	mxcs->ctrl_reg = (mxcs->ctrl_reg & ~MXC_CSPICTRL_BITCOUNT(31)) |
		MXC_CSPICTRL_BITCOUNT(bitlen - 1);

	if (cfg_reg != mxcs->ctrl_reg)
		reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg);

	if (mxcs->gpio > 0 && (flags & SPI_XFER_BEGIN))
		mx31_gpio_set(mxcs->gpio, mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL);

	reg_write(mxcs->base + MXC_CSPITXDATA, data);

	reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg | MXC_CSPICTRL_XCH);

	while (reg_read(mxcs->base + MXC_CSPICTRL) & MXC_CSPICTRL_XCH)
		;

	if (mxcs->gpio > 0 && (flags & SPI_XFER_END)) {
		mx31_gpio_set(mxcs->gpio,
			      !(mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL));
	}

	return reg_read(mxcs->base + MXC_CSPIRXDATA);
}

int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
		void *din, unsigned long flags)
{
	int n_blks = (bitlen + 31) / 32;
	u32 *out_l, *in_l;
	int i;

	if ((int)dout & 3 || (int)din & 3) {
		printf("Error: unaligned buffers in: %p, out: %p\n", din, dout);
		return 1;
	}

	/* This driver is currently partly broken, alert the user */
	if (bitlen > 16 && (bitlen % 32)) {
		printf("Error: SPI transfer with bitlen=%d is broken.\n",
		       bitlen);
		return 1;
	}

	for (i = 0, in_l = (u32 *)din, out_l = (u32 *)dout;
	     i < n_blks;
	     i++, in_l++, out_l++, bitlen -= 32) {
		u32 data = spi_xchg_single(slave, *out_l, bitlen, flags);

		/* Check if we're only transfering 8 or 16 bits */
		if (!i) {
			if (bitlen < 9)
				*(u8 *)din = data;
			else if (bitlen < 17)
				*(u16 *)din = data;
			else
				*in_l = data;
		}
	}

	return 0;
}

void spi_init(void)
{
}

static int decode_cs(struct mxc_spi_slave *mxcs, unsigned int cs)
{
	int ret;

	/*
	 * Some SPI devices require active chip-select over multiple
	 * transactions, we achieve this using a GPIO. Still, the SPI
	 * controller has to be configured to use one of its own chipselects.
	 * To use this feature you have to call spi_setup_slave() with
	 * cs = internal_cs | (gpio << 8), and you have to use some unused
	 * on this SPI controller cs between 0 and 3.
	 */
	if (cs > 3) {
		mxcs->gpio = cs >> 8;
		cs &= 3;
		ret = mx31_gpio_direction(mxcs->gpio, MX31_GPIO_DIRECTION_OUT);
		if (ret) {
			printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
			return -EINVAL;
		}
	} else {
		mxcs->gpio = -1;
	}

	return cs;
}

struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
			unsigned int max_hz, unsigned int mode)
{
	unsigned int ctrl_reg;
	struct mxc_spi_slave *mxcs;
	int ret;

	if (bus >= ARRAY_SIZE(spi_bases))
		return NULL;

	mxcs = malloc(sizeof(struct mxc_spi_slave));
	if (!mxcs)
		return NULL;

	ret = decode_cs(mxcs, cs);
	if (ret < 0) {
		free(mxcs);
		return NULL;
	}

	cs = ret;

	ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
		MXC_CSPICTRL_BITCOUNT(31) |
		MXC_CSPICTRL_DATARATE(7) | /* FIXME: calculate data rate */
		MXC_CSPICTRL_EN |
		MXC_CSPICTRL_MODE;

	if (mode & SPI_CPHA)
		ctrl_reg |= MXC_CSPICTRL_PHA;
	if (!(mode & SPI_CPOL))
		ctrl_reg |= MXC_CSPICTRL_POL;
	if (mode & SPI_CS_HIGH)
		ctrl_reg |= MXC_CSPICTRL_SSPOL;

	mxcs->slave.bus = bus;
	mxcs->slave.cs = cs;
	mxcs->base = spi_bases[bus];
	mxcs->ctrl_reg = ctrl_reg;

	return &mxcs->slave;
}

void spi_free_slave(struct spi_slave *slave)
{
	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);

	free(mxcs);
}

int spi_claim_bus(struct spi_slave *slave)
{
	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);

	reg_write(mxcs->base + MXC_CSPIRESET, 1);
	udelay(1);
	reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg);
	reg_write(mxcs->base + MXC_CSPIPERIOD,
		  MXC_CSPIPERIOD_32KHZ);
	reg_write(mxcs->base + MXC_CSPIINT, 0);

	return 0;
}

void spi_release_bus(struct spi_slave *slave)
{
	/* TODO: Shut the controller down */
}
Commit	Line	Data
38254f45 GL	1	/*
	2	* Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License as
	6	* published by the Free Software Foundation; either version 2 of
	7	* the License, or (at your option) any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	17	* MA 02111-1307 USA
	18	*
	19	*/
	20
	21	#include <common.h>
d255bb0e	22	#include <malloc.h>
38254f45	23	#include <spi.h>
fc7a93c8	24	#include <asm/errno.h>
38254f45 GL	25	#include <asm/io.h>
	26
	27	#ifdef CONFIG_MX27
	28	/* i.MX27 has a completely wrong register layout and register definitions in the
	29	* datasheet, the correct one is in the Freescale's Linux driver */
	30
	31	#error "i.MX27 CSPI not supported due to drastic differences in register definisions" \
	32	"See linux mxc_spi driver from Freescale for details."
	33
	34	#else
	35
fc7a93c8 GL	36	#include <asm/arch/mx31.h>
fc7a93c8 GL	37
38254f45 GL	38	#define MXC_CSPIRXDATA 0x00
	39	#define MXC_CSPITXDATA 0x04
	40	#define MXC_CSPICTRL 0x08
	41	#define MXC_CSPIINT 0x0C
	42	#define MXC_CSPIDMA 0x10
	43	#define MXC_CSPISTAT 0x14
	44	#define MXC_CSPIPERIOD 0x18
	45	#define MXC_CSPITEST 0x1C
	46	#define MXC_CSPIRESET 0x00
	47
	48	#define MXC_CSPICTRL_EN (1 << 0)
	49	#define MXC_CSPICTRL_MODE (1 << 1)
	50	#define MXC_CSPICTRL_XCH (1 << 2)
	51	#define MXC_CSPICTRL_SMC (1 << 3)
	52	#define MXC_CSPICTRL_POL (1 << 4)
	53	#define MXC_CSPICTRL_PHA (1 << 5)
	54	#define MXC_CSPICTRL_SSCTL (1 << 6)
53677ef1	55	#define MXC_CSPICTRL_SSPOL (1 << 7)
38254f45 GL	56	#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24)
	57	#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8)
	58	#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
	59
	60	#define MXC_CSPIPERIOD_32KHZ (1 << 15)
	61
	62	static unsigned long spi_bases[] = {
	63	0x43fa4000,
	64	0x50010000,
	65	0x53f84000,
	66	};
	67
38254f45 GL	68	#endif
38254f45 GL	69
d255bb0e HS	70	struct mxc_spi_slave {
	71	struct spi_slave slave;
	72	unsigned long base;
	73	u32 ctrl_reg;
fc7a93c8	74	int gpio;
38254f45	75	};
d255bb0e HS	76
	77	static inline struct mxc_spi_slave to_mxc_spi_slave(struct spi_slave slave)
	78	{
	79	return container_of(slave, struct mxc_spi_slave, slave);
	80	}
38254f45 GL	81
	82	static inline u32 reg_read(unsigned long addr)
	83	{
	84	return (volatile unsigned long)addr;
	85	}
	86
	87	static inline void reg_write(unsigned long addr, u32 val)
	88	{
	89	(volatile unsigned long)addr = val;
	90	}
	91
fc7a93c8 GL	92	static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen,
fc7a93c8 GL	93	unsigned long flags)
38254f45	94	{
d255bb0e HS	95	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
d255bb0e HS	96	unsigned int cfg_reg = reg_read(mxcs->base + MXC_CSPICTRL);
38254f45	97
f9b6a157 GL	98	mxcs->ctrl_reg = (mxcs->ctrl_reg & ~MXC_CSPICTRL_BITCOUNT(31)) \|
f9b6a157 GL	99	MXC_CSPICTRL_BITCOUNT(bitlen - 1);
38254f45	100
f9b6a157 GL	101	if (cfg_reg != mxcs->ctrl_reg)
f9b6a157 GL	102	reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg);
38254f45	103
fc7a93c8 GL	104	if (mxcs->gpio > 0 && (flags & SPI_XFER_BEGIN))
	105	mx31_gpio_set(mxcs->gpio, mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL);
	106
f9b6a157	107	reg_write(mxcs->base + MXC_CSPITXDATA, data);
38254f45	108
f9b6a157	109	reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg \| MXC_CSPICTRL_XCH);
38254f45	110
d255bb0e	111	while (reg_read(mxcs->base + MXC_CSPICTRL) & MXC_CSPICTRL_XCH)
38254f45 GL	112	;
38254f45 GL	113
fc7a93c8 GL	114	if (mxcs->gpio > 0 && (flags & SPI_XFER_END)) {
	115	mx31_gpio_set(mxcs->gpio,
	116	!(mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL));
	117	}
	118
d255bb0e	119	return reg_read(mxcs->base + MXC_CSPIRXDATA);
38254f45 GL	120	}
38254f45 GL	121
d255bb0e HS	122	int spi_xfer(struct spi_slave slave, unsigned int bitlen, const void dout,
d255bb0e HS	123	void *din, unsigned long flags)
38254f45 GL	124	{
	125	int n_blks = (bitlen + 31) / 32;
	126	u32 out_l, in_l;
	127	int i;
	128
	129	if ((int)dout & 3 \|\| (int)din & 3) {
	130	printf("Error: unaligned buffers in: %p, out: %p\n", din, dout);
	131	return 1;
	132	}
	133
eff536be ML	134	/* This driver is currently partly broken, alert the user */
	135	if (bitlen > 16 && (bitlen % 32)) {
	136	printf("Error: SPI transfer with bitlen=%d is broken.\n",
	137	bitlen);
	138	return 1;
	139	}
	140
38254f45 GL	141	for (i = 0, in_l = (u32 )din, out_l = (u32 )dout;
38254f45 GL	142	i < n_blks;
f9b6a157	143	i++, in_l++, out_l++, bitlen -= 32) {
fc7a93c8	144	u32 data = spi_xchg_single(slave, *out_l, bitlen, flags);
f9b6a157 GL	145
	146	/* Check if we're only transfering 8 or 16 bits */
	147	if (!i) {
	148	if (bitlen < 9)
	149	(u8 )din = data;
	150	else if (bitlen < 17)
	151	(u16 )din = data;
eff536be ML	152	else
eff536be ML	153	*in_l = data;
f9b6a157 GL	154	}
f9b6a157 GL	155	}
38254f45 GL	156
	157	return 0;
	158	}
	159
	160	void spi_init(void)
	161	{
	162	}
	163
fc7a93c8 GL	164	static int decode_cs(struct mxc_spi_slave *mxcs, unsigned int cs)
	165	{
	166	int ret;
	167
	168	/*
	169	* Some SPI devices require active chip-select over multiple
	170	* transactions, we achieve this using a GPIO. Still, the SPI
	171	* controller has to be configured to use one of its own chipselects.
	172	* To use this feature you have to call spi_setup_slave() with
	173	* cs = internal_cs \| (gpio << 8), and you have to use some unused
	174	* on this SPI controller cs between 0 and 3.
	175	*/
	176	if (cs > 3) {
	177	mxcs->gpio = cs >> 8;
	178	cs &= 3;
	179	ret = mx31_gpio_direction(mxcs->gpio, MX31_GPIO_DIRECTION_OUT);
	180	if (ret) {
	181	printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
	182	return -EINVAL;
	183	}
	184	} else {
	185	mxcs->gpio = -1;
	186	}
	187
	188	return cs;
	189	}
	190
d255bb0e HS	191	struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
d255bb0e HS	192	unsigned int max_hz, unsigned int mode)
38254f45 GL	193	{
38254f45 GL	194	unsigned int ctrl_reg;
d255bb0e	195	struct mxc_spi_slave *mxcs;
fc7a93c8 GL	196	int ret;
	197
	198	if (bus >= ARRAY_SIZE(spi_bases))
	199	return NULL;
	200
	201	mxcs = malloc(sizeof(struct mxc_spi_slave));
	202	if (!mxcs)
	203	return NULL;
38254f45	204
fc7a93c8 GL	205	ret = decode_cs(mxcs, cs);
	206	if (ret < 0) {
	207	free(mxcs);
d255bb0e	208	return NULL;
fc7a93c8 GL	209	}
	210
	211	cs = ret;
38254f45	212
d255bb0e	213	ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) \|
38254f45 GL	214	MXC_CSPICTRL_BITCOUNT(31) \|
	215	MXC_CSPICTRL_DATARATE(7) \| /* FIXME: calculate data rate */
	216	MXC_CSPICTRL_EN \|
	217	MXC_CSPICTRL_MODE;
	218
	219	if (mode & SPI_CPHA)
	220	ctrl_reg \|= MXC_CSPICTRL_PHA;
	221	if (!(mode & SPI_CPOL))
	222	ctrl_reg \|= MXC_CSPICTRL_POL;
	223	if (mode & SPI_CS_HIGH)
	224	ctrl_reg \|= MXC_CSPICTRL_SSPOL;
	225
d255bb0e HS	226	mxcs->slave.bus = bus;
	227	mxcs->slave.cs = cs;
	228	mxcs->base = spi_bases[bus];
	229	mxcs->ctrl_reg = ctrl_reg;
	230
	231	return &mxcs->slave;
	232	}
	233
	234	void spi_free_slave(struct spi_slave *slave)
	235	{
f9b6a157 GL	236	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
	237
	238	free(mxcs);
d255bb0e HS	239	}
	240
	241	int spi_claim_bus(struct spi_slave *slave)
	242	{
	243	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
	244
	245	reg_write(mxcs->base + MXC_CSPIRESET, 1);
38254f45	246	udelay(1);
d255bb0e HS	247	reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg);
d255bb0e HS	248	reg_write(mxcs->base + MXC_CSPIPERIOD,
38254f45	249	MXC_CSPIPERIOD_32KHZ);
d255bb0e	250	reg_write(mxcs->base + MXC_CSPIINT, 0);
38254f45 GL	251
	252	return 0;
	253	}
d255bb0e HS	254
	255	void spi_release_bus(struct spi_slave *slave)
	256	{
	257	/* TODO: Shut the controller down */
	258	}