[people/ms/u-boot.git] / drivers / spi / mxs_spi.c

/*
 * Freescale i.MX28 SPI driver
 *
 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
 * on behalf of DENX Software Engineering GmbH
 *
 * SPDX-License-Identifier:	GPL-2.0+
 *
 * NOTE: This driver only supports the SPI-controller chipselects,
 *       GPIO driven chipselects are not supported.
 */

#include <common.h>
#include <malloc.h>
#include <spi.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/dma.h>

#define	MXS_SPI_MAX_TIMEOUT	1000000
#define	MXS_SPI_PORT_OFFSET	0x2000
#define MXS_SSP_CHIPSELECT_MASK		0x00300000
#define MXS_SSP_CHIPSELECT_SHIFT	20

#define MXSSSP_SMALL_TRANSFER	512

struct mxs_spi_slave {
	struct spi_slave	slave;
	uint32_t		max_khz;
	uint32_t		mode;
	struct mxs_ssp_regs	*regs;
};

static inline struct mxs_spi_slave *to_mxs_slave(struct spi_slave *slave)
{
	return container_of(slave, struct mxs_spi_slave, slave);
}

void spi_init(void)
{
}

int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
	/* MXS SPI: 4 ports and 3 chip selects maximum */
	if (!mxs_ssp_bus_id_valid(bus) || cs > 2)
		return 0;
	else
		return 1;
}

struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
				  unsigned int max_hz, unsigned int mode)
{
	struct mxs_spi_slave *mxs_slave;

	if (!spi_cs_is_valid(bus, cs)) {
		printf("mxs_spi: invalid bus %d / chip select %d\n", bus, cs);
		return NULL;
	}

	mxs_slave = spi_alloc_slave(struct mxs_spi_slave, bus, cs);
	if (!mxs_slave)
		return NULL;

	if (mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + bus))
		goto err_init;

	mxs_slave->max_khz = max_hz / 1000;
	mxs_slave->mode = mode;
	mxs_slave->regs = mxs_ssp_regs_by_bus(bus);

	return &mxs_slave->slave;

err_init:
	free(mxs_slave);
	return NULL;
}

void spi_free_slave(struct spi_slave *slave)
{
	struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
	free(mxs_slave);
}

int spi_claim_bus(struct spi_slave *slave)
{
	struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
	struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
	uint32_t reg = 0;

	mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);

	writel((slave->cs << MXS_SSP_CHIPSELECT_SHIFT) |
	       SSP_CTRL0_BUS_WIDTH_ONE_BIT,
	       &ssp_regs->hw_ssp_ctrl0);

	reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS;
	reg |= (mxs_slave->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0;
	reg |= (mxs_slave->mode & SPI_CPHA) ? SSP_CTRL1_PHASE : 0;
	writel(reg, &ssp_regs->hw_ssp_ctrl1);

	writel(0, &ssp_regs->hw_ssp_cmd0);

	mxs_set_ssp_busclock(slave->bus, mxs_slave->max_khz);

	return 0;
}

void spi_release_bus(struct spi_slave *slave)
{
}

static void mxs_spi_start_xfer(struct mxs_ssp_regs *ssp_regs)
{
	writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_set);
	writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_clr);
}

static void mxs_spi_end_xfer(struct mxs_ssp_regs *ssp_regs)
{
	writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_clr);
	writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_set);
}

static int mxs_spi_xfer_pio(struct mxs_spi_slave *slave,
			char *data, int length, int write, unsigned long flags)
{
	struct mxs_ssp_regs *ssp_regs = slave->regs;

	if (flags & SPI_XFER_BEGIN)
		mxs_spi_start_xfer(ssp_regs);

	while (length--) {
		/* We transfer 1 byte */
#if defined(CONFIG_MX23)
		writel(SSP_CTRL0_XFER_COUNT_MASK, &ssp_regs->hw_ssp_ctrl0_clr);
		writel(1, &ssp_regs->hw_ssp_ctrl0_set);
#elif defined(CONFIG_MX28)
		writel(1, &ssp_regs->hw_ssp_xfer_size);
#endif

		if ((flags & SPI_XFER_END) && !length)
			mxs_spi_end_xfer(ssp_regs);

		if (write)
			writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_clr);
		else
			writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_set);

		writel(SSP_CTRL0_RUN, &ssp_regs->hw_ssp_ctrl0_set);

		if (mxs_wait_mask_set(&ssp_regs->hw_ssp_ctrl0_reg,
			SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
			printf("MXS SPI: Timeout waiting for start\n");
			return -ETIMEDOUT;
		}

		if (write)
			writel(*data++, &ssp_regs->hw_ssp_data);

		writel(SSP_CTRL0_DATA_XFER, &ssp_regs->hw_ssp_ctrl0_set);

		if (!write) {
			if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_status_reg,
				SSP_STATUS_FIFO_EMPTY, MXS_SPI_MAX_TIMEOUT)) {
				printf("MXS SPI: Timeout waiting for data\n");
				return -ETIMEDOUT;
			}

			*data = readl(&ssp_regs->hw_ssp_data);
			data++;
		}

		if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_ctrl0_reg,
			SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
			printf("MXS SPI: Timeout waiting for finish\n");
			return -ETIMEDOUT;
		}
	}

	return 0;
}

static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
			char *data, int length, int write, unsigned long flags)
{
	const int xfer_max_sz = 0xff00;
	const int desc_count = DIV_ROUND_UP(length, xfer_max_sz) + 1;
	struct mxs_ssp_regs *ssp_regs = slave->regs;
	struct mxs_dma_desc *dp;
	uint32_t ctrl0;
	uint32_t cache_data_count;
	const uint32_t dstart = (uint32_t)data;
	int dmach;
	int tl;
	int ret = 0;

#if defined(CONFIG_MX23)
	const int mxs_spi_pio_words = 1;
#elif defined(CONFIG_MX28)
	const int mxs_spi_pio_words = 4;
#endif

	ALLOC_CACHE_ALIGN_BUFFER(struct mxs_dma_desc, desc, desc_count);

	memset(desc, 0, sizeof(struct mxs_dma_desc) * desc_count);

	ctrl0 = readl(&ssp_regs->hw_ssp_ctrl0);
	ctrl0 |= SSP_CTRL0_DATA_XFER;

	if (flags & SPI_XFER_BEGIN)
		ctrl0 |= SSP_CTRL0_LOCK_CS;
	if (!write)
		ctrl0 |= SSP_CTRL0_READ;

	if (length % ARCH_DMA_MINALIGN)
		cache_data_count = roundup(length, ARCH_DMA_MINALIGN);
	else
		cache_data_count = length;

	/* Flush data to DRAM so DMA can pick them up */
	if (write)
		flush_dcache_range(dstart, dstart + cache_data_count);

	/* Invalidate the area, so no writeback into the RAM races with DMA */
	invalidate_dcache_range(dstart, dstart + cache_data_count);

	dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + slave->slave.bus;

	dp = desc;
	while (length) {
		dp->address = (dma_addr_t)dp;
		dp->cmd.address = (dma_addr_t)data;

		/*
		 * This is correct, even though it does indeed look insane.
		 * I hereby have to, wholeheartedly, thank Freescale Inc.,
		 * for always inventing insane hardware and keeping me busy
		 * and employed ;-)
		 */
		if (write)
			dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
		else
			dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;

		/*
		 * The DMA controller can transfer large chunks (64kB) at
		 * time by setting the transfer length to 0. Setting tl to
		 * 0x10000 will overflow below and make .data contain 0.
		 * Otherwise, 0xff00 is the transfer maximum.
		 */
		if (length >= 0x10000)
			tl = 0x10000;
		else
			tl = min(length, xfer_max_sz);

		dp->cmd.data |=
			((tl & 0xffff) << MXS_DMA_DESC_BYTES_OFFSET) |
			(mxs_spi_pio_words << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
			MXS_DMA_DESC_HALT_ON_TERMINATE |
			MXS_DMA_DESC_TERMINATE_FLUSH;

		data += tl;
		length -= tl;

		if (!length) {
			dp->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM;

			if (flags & SPI_XFER_END) {
				ctrl0 &= ~SSP_CTRL0_LOCK_CS;
				ctrl0 |= SSP_CTRL0_IGNORE_CRC;
			}
		}

		/*
		 * Write CTRL0, CMD0, CMD1 and XFER_SIZE registers in
		 * case of MX28, write only CTRL0 in case of MX23 due
		 * to the difference in register layout. It is utterly
		 * essential that the XFER_SIZE register is written on
		 * a per-descriptor basis with the same size as is the
		 * descriptor!
		 */
		dp->cmd.pio_words[0] = ctrl0;
#ifdef CONFIG_MX28
		dp->cmd.pio_words[1] = 0;
		dp->cmd.pio_words[2] = 0;
		dp->cmd.pio_words[3] = tl;
#endif

		mxs_dma_desc_append(dmach, dp);

		dp++;
	}

	if (mxs_dma_go(dmach))
		ret = -EINVAL;

	/* The data arrived into DRAM, invalidate cache over them */
	if (!write)
		invalidate_dcache_range(dstart, dstart + cache_data_count);

	return ret;
}

int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
		const void *dout, void *din, unsigned long flags)
{
	struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
	struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
	int len = bitlen / 8;
	char dummy;
	int write = 0;
	char *data = NULL;
	int dma = 1;

	if (bitlen == 0) {
		if (flags & SPI_XFER_END) {
			din = (void *)&dummy;
			len = 1;
		} else
			return 0;
	}

	/* Half-duplex only */
	if (din && dout)
		return -EINVAL;
	/* No data */
	if (!din && !dout)
		return 0;

	if (dout) {
		data = (char *)dout;
		write = 1;
	} else if (din) {
		data = (char *)din;
		write = 0;
	}

	/*
	 * Check for alignment, if the buffer is aligned, do DMA transfer,
	 * PIO otherwise. This is a temporary workaround until proper bounce
	 * buffer is in place.
	 */
	if (dma) {
		if (((uint32_t)data) & (ARCH_DMA_MINALIGN - 1))
			dma = 0;
		if (((uint32_t)len) & (ARCH_DMA_MINALIGN - 1))
			dma = 0;
	}

	if (!dma || (len < MXSSSP_SMALL_TRANSFER)) {
		writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
		return mxs_spi_xfer_pio(mxs_slave, data, len, write, flags);
	} else {
		writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
		return mxs_spi_xfer_dma(mxs_slave, data, len, write, flags);
	}
}
Commit	Line	Data
ec33de3d MV	1	/*
	2	* Freescale i.MX28 SPI driver
	3	*
	4	* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
	5	* on behalf of DENX Software Engineering GmbH
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
ec33de3d MV	8	*
	9	* NOTE: This driver only supports the SPI-controller chipselects,
	10	* GPIO driven chipselects are not supported.
	11	*/
	12
	13	#include <common.h>
	14	#include <malloc.h>
	15	#include <spi.h>
	16	#include <asm/errno.h>
	17	#include <asm/io.h>
	18	#include <asm/arch/clock.h>
	19	#include <asm/arch/imx-regs.h>
	20	#include <asm/arch/sys_proto.h>
0499218d	21	#include <asm/imx-common/dma.h>
ec33de3d MV	22
	23	#define MXS_SPI_MAX_TIMEOUT 1000000
	24	#define MXS_SPI_PORT_OFFSET 0x2000
148ca64f FE	25	#define MXS_SSP_CHIPSELECT_MASK 0x00300000
148ca64f FE	26	#define MXS_SSP_CHIPSELECT_SHIFT 20
ec33de3d	27
7c5e6f7a MV	28	#define MXSSSP_SMALL_TRANSFER 512
7c5e6f7a MV	29
ec33de3d MV	30	struct mxs_spi_slave {
	31	struct spi_slave slave;
	32	uint32_t max_khz;
	33	uint32_t mode;
9c471142	34	struct mxs_ssp_regs *regs;
ec33de3d MV	35	};
	36
	37	static inline struct mxs_spi_slave to_mxs_slave(struct spi_slave slave)
	38	{
	39	return container_of(slave, struct mxs_spi_slave, slave);
	40	}
	41
	42	void spi_init(void)
	43	{
	44	}
	45
79cb14ab FE	46	int spi_cs_is_valid(unsigned int bus, unsigned int cs)
	47	{
	48	/* MXS SPI: 4 ports and 3 chip selects maximum */
3430e0bd	49	if (!mxs_ssp_bus_id_valid(bus) \|\| cs > 2)
79cb14ab FE	50	return 0;
	51	else
	52	return 1;
	53	}
	54
ec33de3d MV	55	struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
	56	unsigned int max_hz, unsigned int mode)
	57	{
	58	struct mxs_spi_slave *mxs_slave;
ec33de3d	59
79cb14ab FE	60	if (!spi_cs_is_valid(bus, cs)) {
79cb14ab FE	61	printf("mxs_spi: invalid bus %d / chip select %d\n", bus, cs);
ec33de3d MV	62	return NULL;
	63	}
	64
d3504fee	65	mxs_slave = spi_alloc_slave(struct mxs_spi_slave, bus, cs);
ec33de3d MV	66	if (!mxs_slave)
	67	return NULL;
	68
3430e0bd	69	if (mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + bus))
7c5e6f7a MV	70	goto err_init;
7c5e6f7a MV	71
ec33de3d MV	72	mxs_slave->max_khz = max_hz / 1000;
ec33de3d MV	73	mxs_slave->mode = mode;
14e26bcf	74	mxs_slave->regs = mxs_ssp_regs_by_bus(bus);
ec33de3d MV	75
ec33de3d MV	76	return &mxs_slave->slave;
7c5e6f7a MV	77
7c5e6f7a MV	78	err_init:
7c5e6f7a MV	79	free(mxs_slave);
7c5e6f7a MV	80	return NULL;
ec33de3d MV	81	}
	82
	83	void spi_free_slave(struct spi_slave *slave)
	84	{
	85	struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
	86	free(mxs_slave);
	87	}
	88
	89	int spi_claim_bus(struct spi_slave *slave)
	90	{
	91	struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
9c471142	92	struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
ec33de3d MV	93	uint32_t reg = 0;
ec33de3d MV	94
fa7a51cb	95	mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
ec33de3d	96
a928a36f MV	97	writel((slave->cs << MXS_SSP_CHIPSELECT_SHIFT) \|
	98	SSP_CTRL0_BUS_WIDTH_ONE_BIT,
	99	&ssp_regs->hw_ssp_ctrl0);
ec33de3d MV	100
	101	reg = SSP_CTRL1_SSP_MODE_SPI \| SSP_CTRL1_WORD_LENGTH_EIGHT_BITS;
	102	reg \|= (mxs_slave->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0;
	103	reg \|= (mxs_slave->mode & SPI_CPHA) ? SSP_CTRL1_PHASE : 0;
	104	writel(reg, &ssp_regs->hw_ssp_ctrl1);
	105
	106	writel(0, &ssp_regs->hw_ssp_cmd0);
	107
bf48fcb6	108	mxs_set_ssp_busclock(slave->bus, mxs_slave->max_khz);
ec33de3d MV	109
	110	return 0;
	111	}
	112
	113	void spi_release_bus(struct spi_slave *slave)
	114	{
	115	}
	116
9c471142	117	static void mxs_spi_start_xfer(struct mxs_ssp_regs *ssp_regs)
ec33de3d MV	118	{
	119	writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_set);
	120	writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_clr);
	121	}
	122
9c471142	123	static void mxs_spi_end_xfer(struct mxs_ssp_regs *ssp_regs)
ec33de3d MV	124	{
	125	writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_clr);
	126	writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_set);
	127	}
	128
ccd4d5a0 MV	129	static int mxs_spi_xfer_pio(struct mxs_spi_slave *slave,
ccd4d5a0 MV	130	char *data, int length, int write, unsigned long flags)
ec33de3d	131	{
9c471142	132	struct mxs_ssp_regs *ssp_regs = slave->regs;
c7065fa8	133
ec33de3d MV	134	if (flags & SPI_XFER_BEGIN)
	135	mxs_spi_start_xfer(ssp_regs);
	136
ccd4d5a0	137	while (length--) {
ec33de3d	138	/* We transfer 1 byte */
c96e78cc MV	139	#if defined(CONFIG_MX23)
	140	writel(SSP_CTRL0_XFER_COUNT_MASK, &ssp_regs->hw_ssp_ctrl0_clr);
	141	writel(1, &ssp_regs->hw_ssp_ctrl0_set);
	142	#elif defined(CONFIG_MX28)
ec33de3d	143	writel(1, &ssp_regs->hw_ssp_xfer_size);
c96e78cc	144	#endif
ec33de3d	145
ccd4d5a0	146	if ((flags & SPI_XFER_END) && !length)
ec33de3d MV	147	mxs_spi_end_xfer(ssp_regs);
ec33de3d MV	148
c7065fa8	149	if (write)
ec33de3d MV	150	writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_clr);
	151	else
	152	writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_set);
	153
	154	writel(SSP_CTRL0_RUN, &ssp_regs->hw_ssp_ctrl0_set);
	155
fa7a51cb	156	if (mxs_wait_mask_set(&ssp_regs->hw_ssp_ctrl0_reg,
ec33de3d MV	157	SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
ec33de3d MV	158	printf("MXS SPI: Timeout waiting for start\n");
d9fb6a4c	159	return -ETIMEDOUT;
ec33de3d MV	160	}
ec33de3d MV	161
c7065fa8 MV	162	if (write)
c7065fa8 MV	163	writel(*data++, &ssp_regs->hw_ssp_data);
ec33de3d MV	164
	165	writel(SSP_CTRL0_DATA_XFER, &ssp_regs->hw_ssp_ctrl0_set);
	166
c7065fa8	167	if (!write) {
fa7a51cb	168	if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_status_reg,
ec33de3d MV	169	SSP_STATUS_FIFO_EMPTY, MXS_SPI_MAX_TIMEOUT)) {
ec33de3d MV	170	printf("MXS SPI: Timeout waiting for data\n");
d9fb6a4c	171	return -ETIMEDOUT;
ec33de3d MV	172	}
ec33de3d MV	173
c7065fa8 MV	174	*data = readl(&ssp_regs->hw_ssp_data);
c7065fa8 MV	175	data++;
ec33de3d MV	176	}
ec33de3d MV	177
fa7a51cb	178	if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_ctrl0_reg,
ec33de3d MV	179	SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
ec33de3d MV	180	printf("MXS SPI: Timeout waiting for finish\n");
d9fb6a4c	181	return -ETIMEDOUT;
ec33de3d MV	182	}
	183	}
	184
	185	return 0;
ccd4d5a0 MV	186	}
ccd4d5a0 MV	187
7c5e6f7a MV	188	static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
	189	char *data, int length, int write, unsigned long flags)
	190	{
2c432144 MV	191	const int xfer_max_sz = 0xff00;
2c432144 MV	192	const int desc_count = DIV_ROUND_UP(length, xfer_max_sz) + 1;
9c471142	193	struct mxs_ssp_regs *ssp_regs = slave->regs;
2c432144 MV	194	struct mxs_dma_desc *dp;
2c432144 MV	195	uint32_t ctrl0;
7c5e6f7a	196	uint32_t cache_data_count;
88d15559	197	const uint32_t dstart = (uint32_t)data;
7c5e6f7a	198	int dmach;
2c432144	199	int tl;
e9f7eafd	200	int ret = 0;
2c432144	201
c96e78cc MV	202	#if defined(CONFIG_MX23)
	203	const int mxs_spi_pio_words = 1;
	204	#elif defined(CONFIG_MX28)
	205	const int mxs_spi_pio_words = 4;
	206	#endif
	207
2c432144 MV	208	ALLOC_CACHE_ALIGN_BUFFER(struct mxs_dma_desc, desc, desc_count);
	209
	210	memset(desc, 0, sizeof(struct mxs_dma_desc) * desc_count);
7c5e6f7a	211
2c432144 MV	212	ctrl0 = readl(&ssp_regs->hw_ssp_ctrl0);
2c432144 MV	213	ctrl0 \|= SSP_CTRL0_DATA_XFER;
7c5e6f7a MV	214
	215	if (flags & SPI_XFER_BEGIN)
	216	ctrl0 \|= SSP_CTRL0_LOCK_CS;
7c5e6f7a MV	217	if (!write)
	218	ctrl0 \|= SSP_CTRL0_READ;
	219
7c5e6f7a MV	220	if (length % ARCH_DMA_MINALIGN)
	221	cache_data_count = roundup(length, ARCH_DMA_MINALIGN);
	222	else
	223	cache_data_count = length;
	224
88d15559	225	/* Flush data to DRAM so DMA can pick them up */
2c432144	226	if (write)
88d15559 MV	227	flush_dcache_range(dstart, dstart + cache_data_count);
	228
	229	/* Invalidate the area, so no writeback into the RAM races with DMA */
	230	invalidate_dcache_range(dstart, dstart + cache_data_count);
7c5e6f7a	231
2c432144 MV	232	dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + slave->slave.bus;
	233
	234	dp = desc;
	235	while (length) {
	236	dp->address = (dma_addr_t)dp;
	237	dp->cmd.address = (dma_addr_t)data;
	238
	239	/*
	240	* This is correct, even though it does indeed look insane.
	241	* I hereby have to, wholeheartedly, thank Freescale Inc.,
	242	* for always inventing insane hardware and keeping me busy
	243	* and employed ;-)
	244	*/
	245	if (write)
	246	dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
	247	else
	248	dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
	249
	250	/*
	251	* The DMA controller can transfer large chunks (64kB) at
	252	* time by setting the transfer length to 0. Setting tl to
	253	* 0x10000 will overflow below and make .data contain 0.
	254	* Otherwise, 0xff00 is the transfer maximum.
	255	*/
	256	if (length >= 0x10000)
	257	tl = 0x10000;
	258	else
	259	tl = min(length, xfer_max_sz);
	260
	261	dp->cmd.data \|=
e9f7eafd	262	((tl & 0xffff) << MXS_DMA_DESC_BYTES_OFFSET) \|
c96e78cc	263	(mxs_spi_pio_words << MXS_DMA_DESC_PIO_WORDS_OFFSET) \|
2c432144 MV	264	MXS_DMA_DESC_HALT_ON_TERMINATE \|
2c432144 MV	265	MXS_DMA_DESC_TERMINATE_FLUSH;
7c5e6f7a	266
2c432144 MV	267	data += tl;
	268	length -= tl;
	269
e9f7eafd MV	270	if (!length) {
	271	dp->cmd.data \|= MXS_DMA_DESC_IRQ \| MXS_DMA_DESC_DEC_SEM;
	272
	273	if (flags & SPI_XFER_END) {
	274	ctrl0 &= ~SSP_CTRL0_LOCK_CS;
	275	ctrl0 \|= SSP_CTRL0_IGNORE_CRC;
	276	}
	277	}
	278
	279	/*
c96e78cc MV	280	* Write CTRL0, CMD0, CMD1 and XFER_SIZE registers in
	281	* case of MX28, write only CTRL0 in case of MX23 due
	282	* to the difference in register layout. It is utterly
e9f7eafd MV	283	* essential that the XFER_SIZE register is written on
	284	* a per-descriptor basis with the same size as is the
	285	* descriptor!
	286	*/
	287	dp->cmd.pio_words[0] = ctrl0;
c96e78cc	288	#ifdef CONFIG_MX28
e9f7eafd MV	289	dp->cmd.pio_words[1] = 0;
	290	dp->cmd.pio_words[2] = 0;
	291	dp->cmd.pio_words[3] = tl;
c96e78cc	292	#endif
e9f7eafd	293
2c432144 MV	294	mxs_dma_desc_append(dmach, dp);
	295
	296	dp++;
	297	}
	298
7c5e6f7a	299	if (mxs_dma_go(dmach))
e9f7eafd	300	ret = -EINVAL;
7c5e6f7a MV	301
7c5e6f7a MV	302	/* The data arrived into DRAM, invalidate cache over them */
88d15559 MV	303	if (!write)
88d15559 MV	304	invalidate_dcache_range(dstart, dstart + cache_data_count);
7c5e6f7a	305
e9f7eafd	306	return ret;
7c5e6f7a MV	307	}
7c5e6f7a MV	308
ccd4d5a0 MV	309	int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
	310	const void dout, void din, unsigned long flags)
	311	{
	312	struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
9c471142	313	struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
ccd4d5a0 MV	314	int len = bitlen / 8;
	315	char dummy;
	316	int write = 0;
	317	char *data = NULL;
7c5e6f7a	318	int dma = 1;
7c5e6f7a	319
ccd4d5a0 MV	320	if (bitlen == 0) {
	321	if (flags & SPI_XFER_END) {
	322	din = (void *)&dummy;
	323	len = 1;
	324	} else
	325	return 0;
	326	}
	327
	328	/* Half-duplex only */
	329	if (din && dout)
	330	return -EINVAL;
	331	/* No data */
	332	if (!din && !dout)
	333	return 0;
	334
	335	if (dout) {
	336	data = (char *)dout;
	337	write = 1;
	338	} else if (din) {
	339	data = (char *)din;
	340	write = 0;
	341	}
	342
7c5e6f7a MV	343	/*
	344	* Check for alignment, if the buffer is aligned, do DMA transfer,
	345	* PIO otherwise. This is a temporary workaround until proper bounce
	346	* buffer is in place.
	347	*/
	348	if (dma) {
	349	if (((uint32_t)data) & (ARCH_DMA_MINALIGN - 1))
	350	dma = 0;
	351	if (((uint32_t)len) & (ARCH_DMA_MINALIGN - 1))
	352	dma = 0;
	353	}
	354
	355	if (!dma \|\| (len < MXSSSP_SMALL_TRANSFER)) {
	356	writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
	357	return mxs_spi_xfer_pio(mxs_slave, data, len, write, flags);
	358	} else {
	359	writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
	360	return mxs_spi_xfer_dma(mxs_slave, data, len, write, flags);
	361	}
ec33de3d	362	}