]>
Commit | Line | Data |
---|---|---|
ec33de3d MV |
1 | /* |
2 | * Freescale i.MX28 SPI driver | |
3 | * | |
4 | * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> | |
5 | * on behalf of DENX Software Engineering GmbH | |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
ec33de3d MV |
8 | * |
9 | * NOTE: This driver only supports the SPI-controller chipselects, | |
10 | * GPIO driven chipselects are not supported. | |
11 | */ | |
12 | ||
13 | #include <common.h> | |
14 | #include <malloc.h> | |
cf92e05c | 15 | #include <memalign.h> |
ec33de3d | 16 | #include <spi.h> |
1221ce45 | 17 | #include <linux/errno.h> |
ec33de3d MV |
18 | #include <asm/io.h> |
19 | #include <asm/arch/clock.h> | |
20 | #include <asm/arch/imx-regs.h> | |
21 | #include <asm/arch/sys_proto.h> | |
552a848e | 22 | #include <asm/mach-imx/dma.h> |
ec33de3d MV |
23 | |
24 | #define MXS_SPI_MAX_TIMEOUT 1000000 | |
25 | #define MXS_SPI_PORT_OFFSET 0x2000 | |
148ca64f FE |
26 | #define MXS_SSP_CHIPSELECT_MASK 0x00300000 |
27 | #define MXS_SSP_CHIPSELECT_SHIFT 20 | |
ec33de3d | 28 | |
7c5e6f7a MV |
29 | #define MXSSSP_SMALL_TRANSFER 512 |
30 | ||
ec33de3d MV |
31 | struct mxs_spi_slave { |
32 | struct spi_slave slave; | |
33 | uint32_t max_khz; | |
34 | uint32_t mode; | |
9c471142 | 35 | struct mxs_ssp_regs *regs; |
ec33de3d MV |
36 | }; |
37 | ||
38 | static inline struct mxs_spi_slave *to_mxs_slave(struct spi_slave *slave) | |
39 | { | |
40 | return container_of(slave, struct mxs_spi_slave, slave); | |
41 | } | |
42 | ||
43 | void spi_init(void) | |
44 | { | |
45 | } | |
46 | ||
79cb14ab FE |
47 | int spi_cs_is_valid(unsigned int bus, unsigned int cs) |
48 | { | |
49 | /* MXS SPI: 4 ports and 3 chip selects maximum */ | |
3430e0bd | 50 | if (!mxs_ssp_bus_id_valid(bus) || cs > 2) |
79cb14ab FE |
51 | return 0; |
52 | else | |
53 | return 1; | |
54 | } | |
55 | ||
ec33de3d MV |
56 | struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, |
57 | unsigned int max_hz, unsigned int mode) | |
58 | { | |
59 | struct mxs_spi_slave *mxs_slave; | |
ec33de3d | 60 | |
79cb14ab FE |
61 | if (!spi_cs_is_valid(bus, cs)) { |
62 | printf("mxs_spi: invalid bus %d / chip select %d\n", bus, cs); | |
ec33de3d MV |
63 | return NULL; |
64 | } | |
65 | ||
d3504fee | 66 | mxs_slave = spi_alloc_slave(struct mxs_spi_slave, bus, cs); |
ec33de3d MV |
67 | if (!mxs_slave) |
68 | return NULL; | |
69 | ||
3430e0bd | 70 | if (mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + bus)) |
7c5e6f7a MV |
71 | goto err_init; |
72 | ||
ec33de3d MV |
73 | mxs_slave->max_khz = max_hz / 1000; |
74 | mxs_slave->mode = mode; | |
14e26bcf | 75 | mxs_slave->regs = mxs_ssp_regs_by_bus(bus); |
ec33de3d MV |
76 | |
77 | return &mxs_slave->slave; | |
7c5e6f7a MV |
78 | |
79 | err_init: | |
7c5e6f7a MV |
80 | free(mxs_slave); |
81 | return NULL; | |
ec33de3d MV |
82 | } |
83 | ||
84 | void spi_free_slave(struct spi_slave *slave) | |
85 | { | |
86 | struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave); | |
87 | free(mxs_slave); | |
88 | } | |
89 | ||
90 | int spi_claim_bus(struct spi_slave *slave) | |
91 | { | |
92 | struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave); | |
9c471142 | 93 | struct mxs_ssp_regs *ssp_regs = mxs_slave->regs; |
ec33de3d MV |
94 | uint32_t reg = 0; |
95 | ||
fa7a51cb | 96 | mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg); |
ec33de3d | 97 | |
a928a36f MV |
98 | writel((slave->cs << MXS_SSP_CHIPSELECT_SHIFT) | |
99 | SSP_CTRL0_BUS_WIDTH_ONE_BIT, | |
100 | &ssp_regs->hw_ssp_ctrl0); | |
ec33de3d MV |
101 | |
102 | reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS; | |
103 | reg |= (mxs_slave->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0; | |
104 | reg |= (mxs_slave->mode & SPI_CPHA) ? SSP_CTRL1_PHASE : 0; | |
105 | writel(reg, &ssp_regs->hw_ssp_ctrl1); | |
106 | ||
107 | writel(0, &ssp_regs->hw_ssp_cmd0); | |
108 | ||
bf48fcb6 | 109 | mxs_set_ssp_busclock(slave->bus, mxs_slave->max_khz); |
ec33de3d MV |
110 | |
111 | return 0; | |
112 | } | |
113 | ||
114 | void spi_release_bus(struct spi_slave *slave) | |
115 | { | |
116 | } | |
117 | ||
9c471142 | 118 | static void mxs_spi_start_xfer(struct mxs_ssp_regs *ssp_regs) |
ec33de3d MV |
119 | { |
120 | writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_set); | |
121 | writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_clr); | |
122 | } | |
123 | ||
9c471142 | 124 | static void mxs_spi_end_xfer(struct mxs_ssp_regs *ssp_regs) |
ec33de3d MV |
125 | { |
126 | writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_clr); | |
127 | writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_set); | |
128 | } | |
129 | ||
ccd4d5a0 MV |
130 | static int mxs_spi_xfer_pio(struct mxs_spi_slave *slave, |
131 | char *data, int length, int write, unsigned long flags) | |
ec33de3d | 132 | { |
9c471142 | 133 | struct mxs_ssp_regs *ssp_regs = slave->regs; |
c7065fa8 | 134 | |
ec33de3d MV |
135 | if (flags & SPI_XFER_BEGIN) |
136 | mxs_spi_start_xfer(ssp_regs); | |
137 | ||
ccd4d5a0 | 138 | while (length--) { |
ec33de3d | 139 | /* We transfer 1 byte */ |
c96e78cc MV |
140 | #if defined(CONFIG_MX23) |
141 | writel(SSP_CTRL0_XFER_COUNT_MASK, &ssp_regs->hw_ssp_ctrl0_clr); | |
142 | writel(1, &ssp_regs->hw_ssp_ctrl0_set); | |
143 | #elif defined(CONFIG_MX28) | |
ec33de3d | 144 | writel(1, &ssp_regs->hw_ssp_xfer_size); |
c96e78cc | 145 | #endif |
ec33de3d | 146 | |
ccd4d5a0 | 147 | if ((flags & SPI_XFER_END) && !length) |
ec33de3d MV |
148 | mxs_spi_end_xfer(ssp_regs); |
149 | ||
c7065fa8 | 150 | if (write) |
ec33de3d MV |
151 | writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_clr); |
152 | else | |
153 | writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_set); | |
154 | ||
155 | writel(SSP_CTRL0_RUN, &ssp_regs->hw_ssp_ctrl0_set); | |
156 | ||
fa7a51cb | 157 | if (mxs_wait_mask_set(&ssp_regs->hw_ssp_ctrl0_reg, |
ec33de3d MV |
158 | SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) { |
159 | printf("MXS SPI: Timeout waiting for start\n"); | |
d9fb6a4c | 160 | return -ETIMEDOUT; |
ec33de3d MV |
161 | } |
162 | ||
c7065fa8 MV |
163 | if (write) |
164 | writel(*data++, &ssp_regs->hw_ssp_data); | |
ec33de3d MV |
165 | |
166 | writel(SSP_CTRL0_DATA_XFER, &ssp_regs->hw_ssp_ctrl0_set); | |
167 | ||
c7065fa8 | 168 | if (!write) { |
fa7a51cb | 169 | if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_status_reg, |
ec33de3d MV |
170 | SSP_STATUS_FIFO_EMPTY, MXS_SPI_MAX_TIMEOUT)) { |
171 | printf("MXS SPI: Timeout waiting for data\n"); | |
d9fb6a4c | 172 | return -ETIMEDOUT; |
ec33de3d MV |
173 | } |
174 | ||
c7065fa8 MV |
175 | *data = readl(&ssp_regs->hw_ssp_data); |
176 | data++; | |
ec33de3d MV |
177 | } |
178 | ||
fa7a51cb | 179 | if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_ctrl0_reg, |
ec33de3d MV |
180 | SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) { |
181 | printf("MXS SPI: Timeout waiting for finish\n"); | |
d9fb6a4c | 182 | return -ETIMEDOUT; |
ec33de3d MV |
183 | } |
184 | } | |
185 | ||
186 | return 0; | |
ccd4d5a0 MV |
187 | } |
188 | ||
7c5e6f7a MV |
189 | static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave, |
190 | char *data, int length, int write, unsigned long flags) | |
191 | { | |
2c432144 MV |
192 | const int xfer_max_sz = 0xff00; |
193 | const int desc_count = DIV_ROUND_UP(length, xfer_max_sz) + 1; | |
9c471142 | 194 | struct mxs_ssp_regs *ssp_regs = slave->regs; |
2c432144 MV |
195 | struct mxs_dma_desc *dp; |
196 | uint32_t ctrl0; | |
7c5e6f7a | 197 | uint32_t cache_data_count; |
88d15559 | 198 | const uint32_t dstart = (uint32_t)data; |
7c5e6f7a | 199 | int dmach; |
2c432144 | 200 | int tl; |
e9f7eafd | 201 | int ret = 0; |
2c432144 | 202 | |
c96e78cc MV |
203 | #if defined(CONFIG_MX23) |
204 | const int mxs_spi_pio_words = 1; | |
205 | #elif defined(CONFIG_MX28) | |
206 | const int mxs_spi_pio_words = 4; | |
207 | #endif | |
208 | ||
2c432144 MV |
209 | ALLOC_CACHE_ALIGN_BUFFER(struct mxs_dma_desc, desc, desc_count); |
210 | ||
211 | memset(desc, 0, sizeof(struct mxs_dma_desc) * desc_count); | |
7c5e6f7a | 212 | |
2c432144 MV |
213 | ctrl0 = readl(&ssp_regs->hw_ssp_ctrl0); |
214 | ctrl0 |= SSP_CTRL0_DATA_XFER; | |
7c5e6f7a MV |
215 | |
216 | if (flags & SPI_XFER_BEGIN) | |
217 | ctrl0 |= SSP_CTRL0_LOCK_CS; | |
7c5e6f7a MV |
218 | if (!write) |
219 | ctrl0 |= SSP_CTRL0_READ; | |
220 | ||
7c5e6f7a MV |
221 | if (length % ARCH_DMA_MINALIGN) |
222 | cache_data_count = roundup(length, ARCH_DMA_MINALIGN); | |
223 | else | |
224 | cache_data_count = length; | |
225 | ||
88d15559 | 226 | /* Flush data to DRAM so DMA can pick them up */ |
2c432144 | 227 | if (write) |
88d15559 MV |
228 | flush_dcache_range(dstart, dstart + cache_data_count); |
229 | ||
230 | /* Invalidate the area, so no writeback into the RAM races with DMA */ | |
231 | invalidate_dcache_range(dstart, dstart + cache_data_count); | |
7c5e6f7a | 232 | |
2c432144 MV |
233 | dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + slave->slave.bus; |
234 | ||
235 | dp = desc; | |
236 | while (length) { | |
237 | dp->address = (dma_addr_t)dp; | |
238 | dp->cmd.address = (dma_addr_t)data; | |
239 | ||
240 | /* | |
241 | * This is correct, even though it does indeed look insane. | |
242 | * I hereby have to, wholeheartedly, thank Freescale Inc., | |
243 | * for always inventing insane hardware and keeping me busy | |
244 | * and employed ;-) | |
245 | */ | |
246 | if (write) | |
247 | dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ; | |
248 | else | |
249 | dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE; | |
250 | ||
251 | /* | |
252 | * The DMA controller can transfer large chunks (64kB) at | |
253 | * time by setting the transfer length to 0. Setting tl to | |
254 | * 0x10000 will overflow below and make .data contain 0. | |
255 | * Otherwise, 0xff00 is the transfer maximum. | |
256 | */ | |
257 | if (length >= 0x10000) | |
258 | tl = 0x10000; | |
259 | else | |
260 | tl = min(length, xfer_max_sz); | |
261 | ||
262 | dp->cmd.data |= | |
e9f7eafd | 263 | ((tl & 0xffff) << MXS_DMA_DESC_BYTES_OFFSET) | |
c96e78cc | 264 | (mxs_spi_pio_words << MXS_DMA_DESC_PIO_WORDS_OFFSET) | |
2c432144 MV |
265 | MXS_DMA_DESC_HALT_ON_TERMINATE | |
266 | MXS_DMA_DESC_TERMINATE_FLUSH; | |
7c5e6f7a | 267 | |
2c432144 MV |
268 | data += tl; |
269 | length -= tl; | |
270 | ||
e9f7eafd MV |
271 | if (!length) { |
272 | dp->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM; | |
273 | ||
274 | if (flags & SPI_XFER_END) { | |
275 | ctrl0 &= ~SSP_CTRL0_LOCK_CS; | |
276 | ctrl0 |= SSP_CTRL0_IGNORE_CRC; | |
277 | } | |
278 | } | |
279 | ||
280 | /* | |
c96e78cc MV |
281 | * Write CTRL0, CMD0, CMD1 and XFER_SIZE registers in |
282 | * case of MX28, write only CTRL0 in case of MX23 due | |
283 | * to the difference in register layout. It is utterly | |
e9f7eafd MV |
284 | * essential that the XFER_SIZE register is written on |
285 | * a per-descriptor basis with the same size as is the | |
286 | * descriptor! | |
287 | */ | |
288 | dp->cmd.pio_words[0] = ctrl0; | |
c96e78cc | 289 | #ifdef CONFIG_MX28 |
e9f7eafd MV |
290 | dp->cmd.pio_words[1] = 0; |
291 | dp->cmd.pio_words[2] = 0; | |
292 | dp->cmd.pio_words[3] = tl; | |
c96e78cc | 293 | #endif |
e9f7eafd | 294 | |
2c432144 MV |
295 | mxs_dma_desc_append(dmach, dp); |
296 | ||
297 | dp++; | |
298 | } | |
299 | ||
7c5e6f7a | 300 | if (mxs_dma_go(dmach)) |
e9f7eafd | 301 | ret = -EINVAL; |
7c5e6f7a MV |
302 | |
303 | /* The data arrived into DRAM, invalidate cache over them */ | |
88d15559 MV |
304 | if (!write) |
305 | invalidate_dcache_range(dstart, dstart + cache_data_count); | |
7c5e6f7a | 306 | |
e9f7eafd | 307 | return ret; |
7c5e6f7a MV |
308 | } |
309 | ||
ccd4d5a0 MV |
310 | int spi_xfer(struct spi_slave *slave, unsigned int bitlen, |
311 | const void *dout, void *din, unsigned long flags) | |
312 | { | |
313 | struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave); | |
9c471142 | 314 | struct mxs_ssp_regs *ssp_regs = mxs_slave->regs; |
ccd4d5a0 MV |
315 | int len = bitlen / 8; |
316 | char dummy; | |
317 | int write = 0; | |
318 | char *data = NULL; | |
7c5e6f7a | 319 | int dma = 1; |
7c5e6f7a | 320 | |
ccd4d5a0 MV |
321 | if (bitlen == 0) { |
322 | if (flags & SPI_XFER_END) { | |
323 | din = (void *)&dummy; | |
324 | len = 1; | |
325 | } else | |
326 | return 0; | |
327 | } | |
328 | ||
329 | /* Half-duplex only */ | |
330 | if (din && dout) | |
331 | return -EINVAL; | |
332 | /* No data */ | |
333 | if (!din && !dout) | |
334 | return 0; | |
335 | ||
336 | if (dout) { | |
337 | data = (char *)dout; | |
338 | write = 1; | |
339 | } else if (din) { | |
340 | data = (char *)din; | |
341 | write = 0; | |
342 | } | |
343 | ||
7c5e6f7a MV |
344 | /* |
345 | * Check for alignment, if the buffer is aligned, do DMA transfer, | |
346 | * PIO otherwise. This is a temporary workaround until proper bounce | |
347 | * buffer is in place. | |
348 | */ | |
349 | if (dma) { | |
350 | if (((uint32_t)data) & (ARCH_DMA_MINALIGN - 1)) | |
351 | dma = 0; | |
352 | if (((uint32_t)len) & (ARCH_DMA_MINALIGN - 1)) | |
353 | dma = 0; | |
354 | } | |
355 | ||
356 | if (!dma || (len < MXSSSP_SMALL_TRANSFER)) { | |
357 | writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr); | |
358 | return mxs_spi_xfer_pio(mxs_slave, data, len, write, flags); | |
359 | } else { | |
360 | writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set); | |
361 | return mxs_spi_xfer_dma(mxs_slave, data, len, write, flags); | |
362 | } | |
ec33de3d | 363 | } |