[people/ms/u-boot.git] / drivers / spi / mxs_spi.c

/*
 * Freescale i.MX28 SPI driver
 *
 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
 * on behalf of DENX Software Engineering GmbH
 *
 * SPDX-License-Identifier:	GPL-2.0+
 *
 * NOTE: This driver only supports the SPI-controller chipselects,
 *       GPIO driven chipselects are not supported.
 */

#include <common.h>
#include <malloc.h>
#include <spi.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/dma.h>

#define	MXS_SPI_MAX_TIMEOUT	1000000
#define	MXS_SPI_PORT_OFFSET	0x2000
#define MXS_SSP_CHIPSELECT_MASK		0x00300000
#define MXS_SSP_CHIPSELECT_SHIFT	20

#define MXSSSP_SMALL_TRANSFER	512

struct mxs_spi_slave {
	struct spi_slave	slave;
	uint32_t		max_khz;
	uint32_t		mode;
	struct mxs_ssp_regs	*regs;
};

static inline struct mxs_spi_slave *to_mxs_slave(struct spi_slave *slave)
{
	return container_of(slave, struct mxs_spi_slave, slave);
}

void spi_init(void)
{
}

int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
	/* MXS SPI: 4 ports and 3 chip selects maximum */
	if (!mxs_ssp_bus_id_valid(bus) || cs > 2)
		return 0;
	else
		return 1;
}

struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
				  unsigned int max_hz, unsigned int mode)
{
	struct mxs_spi_slave *mxs_slave;
	struct mxs_ssp_regs *ssp_regs;
	int reg;

	if (!spi_cs_is_valid(bus, cs)) {
		printf("mxs_spi: invalid bus %d / chip select %d\n", bus, cs);
		return NULL;
	}

	mxs_slave = spi_alloc_slave(struct mxs_spi_slave, bus, cs);
	if (!mxs_slave)
		return NULL;

	if (mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + bus))
		goto err_init;

	mxs_slave->max_khz = max_hz / 1000;
	mxs_slave->mode = mode;
	mxs_slave->regs = mxs_ssp_regs_by_bus(bus);
	ssp_regs = mxs_slave->regs;

	reg = readl(&ssp_regs->hw_ssp_ctrl0);
	reg &= ~(MXS_SSP_CHIPSELECT_MASK);
	reg |= cs << MXS_SSP_CHIPSELECT_SHIFT;

	writel(reg, &ssp_regs->hw_ssp_ctrl0);
	return &mxs_slave->slave;

err_init:
	free(mxs_slave);
	return NULL;
}

void spi_free_slave(struct spi_slave *slave)
{
	struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
	free(mxs_slave);
}

int spi_claim_bus(struct spi_slave *slave)
{
	struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
	struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
	uint32_t reg = 0;

	mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);

	writel(SSP_CTRL0_BUS_WIDTH_ONE_BIT, &ssp_regs->hw_ssp_ctrl0);

	reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS;
	reg |= (mxs_slave->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0;
	reg |= (mxs_slave->mode & SPI_CPHA) ? SSP_CTRL1_PHASE : 0;
	writel(reg, &ssp_regs->hw_ssp_ctrl1);

	writel(0, &ssp_regs->hw_ssp_cmd0);

	mxs_set_ssp_busclock(slave->bus, mxs_slave->max_khz);

	return 0;
}

void spi_release_bus(struct spi_slave *slave)
{
}

static void mxs_spi_start_xfer(struct mxs_ssp_regs *ssp_regs)
{
	writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_set);
	writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_clr);
}

static void mxs_spi_end_xfer(struct mxs_ssp_regs *ssp_regs)
{
	writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_clr);
	writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_set);
}

static int mxs_spi_xfer_pio(struct mxs_spi_slave *slave,
			char *data, int length, int write, unsigned long flags)
{
	struct mxs_ssp_regs *ssp_regs = slave->regs;

	if (flags & SPI_XFER_BEGIN)
		mxs_spi_start_xfer(ssp_regs);

	while (length--) {
		/* We transfer 1 byte */
#if defined(CONFIG_MX23)
		writel(SSP_CTRL0_XFER_COUNT_MASK, &ssp_regs->hw_ssp_ctrl0_clr);
		writel(1, &ssp_regs->hw_ssp_ctrl0_set);
#elif defined(CONFIG_MX28)
		writel(1, &ssp_regs->hw_ssp_xfer_size);
#endif

		if ((flags & SPI_XFER_END) && !length)
			mxs_spi_end_xfer(ssp_regs);

		if (write)
			writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_clr);
		else
			writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_set);

		writel(SSP_CTRL0_RUN, &ssp_regs->hw_ssp_ctrl0_set);

		if (mxs_wait_mask_set(&ssp_regs->hw_ssp_ctrl0_reg,
			SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
			printf("MXS SPI: Timeout waiting for start\n");
			return -ETIMEDOUT;
		}

		if (write)
			writel(*data++, &ssp_regs->hw_ssp_data);

		writel(SSP_CTRL0_DATA_XFER, &ssp_regs->hw_ssp_ctrl0_set);

		if (!write) {
			if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_status_reg,
				SSP_STATUS_FIFO_EMPTY, MXS_SPI_MAX_TIMEOUT)) {
				printf("MXS SPI: Timeout waiting for data\n");
				return -ETIMEDOUT;
			}

			*data = readl(&ssp_regs->hw_ssp_data);
			data++;
		}

		if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_ctrl0_reg,
			SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
			printf("MXS SPI: Timeout waiting for finish\n");
			return -ETIMEDOUT;
		}
	}

	return 0;
}

static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
			char *data, int length, int write, unsigned long flags)
{
	const int xfer_max_sz = 0xff00;
	const int desc_count = DIV_ROUND_UP(length, xfer_max_sz) + 1;
	struct mxs_ssp_regs *ssp_regs = slave->regs;
	struct mxs_dma_desc *dp;
	uint32_t ctrl0;
	uint32_t cache_data_count;
	const uint32_t dstart = (uint32_t)data;
	int dmach;
	int tl;
	int ret = 0;

#if defined(CONFIG_MX23)
	const int mxs_spi_pio_words = 1;
#elif defined(CONFIG_MX28)
	const int mxs_spi_pio_words = 4;
#endif

	ALLOC_CACHE_ALIGN_BUFFER(struct mxs_dma_desc, desc, desc_count);

	memset(desc, 0, sizeof(struct mxs_dma_desc) * desc_count);

	ctrl0 = readl(&ssp_regs->hw_ssp_ctrl0);
	ctrl0 |= SSP_CTRL0_DATA_XFER;

	if (flags & SPI_XFER_BEGIN)
		ctrl0 |= SSP_CTRL0_LOCK_CS;
	if (!write)
		ctrl0 |= SSP_CTRL0_READ;

	if (length % ARCH_DMA_MINALIGN)
		cache_data_count = roundup(length, ARCH_DMA_MINALIGN);
	else
		cache_data_count = length;

	/* Flush data to DRAM so DMA can pick them up */
	if (write)
		flush_dcache_range(dstart, dstart + cache_data_count);

	/* Invalidate the area, so no writeback into the RAM races with DMA */
	invalidate_dcache_range(dstart, dstart + cache_data_count);

	dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + slave->slave.bus;

	dp = desc;
	while (length) {
		dp->address = (dma_addr_t)dp;
		dp->cmd.address = (dma_addr_t)data;

		/*
		 * This is correct, even though it does indeed look insane.
		 * I hereby have to, wholeheartedly, thank Freescale Inc.,
		 * for always inventing insane hardware and keeping me busy
		 * and employed ;-)
		 */
		if (write)
			dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
		else
			dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;

		/*
		 * The DMA controller can transfer large chunks (64kB) at
		 * time by setting the transfer length to 0. Setting tl to
		 * 0x10000 will overflow below and make .data contain 0.
		 * Otherwise, 0xff00 is the transfer maximum.
		 */
		if (length >= 0x10000)
			tl = 0x10000;
		else
			tl = min(length, xfer_max_sz);

		dp->cmd.data |=
			((tl & 0xffff) << MXS_DMA_DESC_BYTES_OFFSET) |
			(mxs_spi_pio_words << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
			MXS_DMA_DESC_HALT_ON_TERMINATE |
			MXS_DMA_DESC_TERMINATE_FLUSH;

		data += tl;
		length -= tl;

		if (!length) {
			dp->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM;

			if (flags & SPI_XFER_END) {
				ctrl0 &= ~SSP_CTRL0_LOCK_CS;
				ctrl0 |= SSP_CTRL0_IGNORE_CRC;
			}
		}

		/*
		 * Write CTRL0, CMD0, CMD1 and XFER_SIZE registers in
		 * case of MX28, write only CTRL0 in case of MX23 due
		 * to the difference in register layout. It is utterly
		 * essential that the XFER_SIZE register is written on
		 * a per-descriptor basis with the same size as is the
		 * descriptor!
		 */
		dp->cmd.pio_words[0] = ctrl0;
#ifdef CONFIG_MX28
		dp->cmd.pio_words[1] = 0;
		dp->cmd.pio_words[2] = 0;
		dp->cmd.pio_words[3] = tl;
#endif

		mxs_dma_desc_append(dmach, dp);

		dp++;
	}

	if (mxs_dma_go(dmach))
		ret = -EINVAL;

	/* The data arrived into DRAM, invalidate cache over them */
	if (!write)
		invalidate_dcache_range(dstart, dstart + cache_data_count);

	return ret;
}

int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
		const void *dout, void *din, unsigned long flags)
{
	struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
	struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
	int len = bitlen / 8;
	char dummy;
	int write = 0;
	char *data = NULL;
	int dma = 1;

	if (bitlen == 0) {
		if (flags & SPI_XFER_END) {
			din = (void *)&dummy;
			len = 1;
		} else
			return 0;
	}

	/* Half-duplex only */
	if (din && dout)
		return -EINVAL;
	/* No data */
	if (!din && !dout)
		return 0;

	if (dout) {
		data = (char *)dout;
		write = 1;
	} else if (din) {
		data = (char *)din;
		write = 0;
	}

	/*
	 * Check for alignment, if the buffer is aligned, do DMA transfer,
	 * PIO otherwise. This is a temporary workaround until proper bounce
	 * buffer is in place.
	 */
	if (dma) {
		if (((uint32_t)data) & (ARCH_DMA_MINALIGN - 1))
			dma = 0;
		if (((uint32_t)len) & (ARCH_DMA_MINALIGN - 1))
			dma = 0;
	}

	if (!dma || (len < MXSSSP_SMALL_TRANSFER)) {
		writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
		return mxs_spi_xfer_pio(mxs_slave, data, len, write, flags);
	} else {
		writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
		return mxs_spi_xfer_dma(mxs_slave, data, len, write, flags);
	}
}
Commit	Line	Data
ec33de3d MV	1	/*
	2	* Freescale i.MX28 SPI driver
	3	*
	4	* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
	5	* on behalf of DENX Software Engineering GmbH
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
ec33de3d MV	8	*
	9	* NOTE: This driver only supports the SPI-controller chipselects,
	10	* GPIO driven chipselects are not supported.
	11	*/
	12
	13	#include <common.h>
	14	#include <malloc.h>
	15	#include <spi.h>
	16	#include <asm/errno.h>
	17	#include <asm/io.h>
	18	#include <asm/arch/clock.h>
	19	#include <asm/arch/imx-regs.h>
	20	#include <asm/arch/sys_proto.h>
0499218d	21	#include <asm/imx-common/dma.h>
ec33de3d MV	22
	23	#define MXS_SPI_MAX_TIMEOUT 1000000
	24	#define MXS_SPI_PORT_OFFSET 0x2000
148ca64f FE	25	#define MXS_SSP_CHIPSELECT_MASK 0x00300000
148ca64f FE	26	#define MXS_SSP_CHIPSELECT_SHIFT 20
ec33de3d	27
7c5e6f7a MV	28	#define MXSSSP_SMALL_TRANSFER 512
7c5e6f7a MV	29
ec33de3d MV	30	struct mxs_spi_slave {
	31	struct spi_slave slave;
	32	uint32_t max_khz;
	33	uint32_t mode;
9c471142	34	struct mxs_ssp_regs *regs;
ec33de3d MV	35	};
	36
	37	static inline struct mxs_spi_slave to_mxs_slave(struct spi_slave slave)
	38	{
	39	return container_of(slave, struct mxs_spi_slave, slave);
	40	}
	41
	42	void spi_init(void)
	43	{
	44	}
	45
79cb14ab FE	46	int spi_cs_is_valid(unsigned int bus, unsigned int cs)
	47	{
	48	/* MXS SPI: 4 ports and 3 chip selects maximum */
3430e0bd	49	if (!mxs_ssp_bus_id_valid(bus) \|\| cs > 2)
79cb14ab FE	50	return 0;
	51	else
	52	return 1;
	53	}
	54
ec33de3d MV	55	struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
	56	unsigned int max_hz, unsigned int mode)
	57	{
	58	struct mxs_spi_slave *mxs_slave;
9c471142	59	struct mxs_ssp_regs *ssp_regs;
148ca64f	60	int reg;
ec33de3d	61
79cb14ab FE	62	if (!spi_cs_is_valid(bus, cs)) {
79cb14ab FE	63	printf("mxs_spi: invalid bus %d / chip select %d\n", bus, cs);
ec33de3d MV	64	return NULL;
	65	}
	66
d3504fee	67	mxs_slave = spi_alloc_slave(struct mxs_spi_slave, bus, cs);
ec33de3d MV	68	if (!mxs_slave)
	69	return NULL;
	70
3430e0bd	71	if (mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + bus))
7c5e6f7a MV	72	goto err_init;
7c5e6f7a MV	73
ec33de3d MV	74	mxs_slave->max_khz = max_hz / 1000;
ec33de3d MV	75	mxs_slave->mode = mode;
14e26bcf	76	mxs_slave->regs = mxs_ssp_regs_by_bus(bus);
148ca64f	77	ssp_regs = mxs_slave->regs;
ec33de3d	78
148ca64f FE	79	reg = readl(&ssp_regs->hw_ssp_ctrl0);
	80	reg &= ~(MXS_SSP_CHIPSELECT_MASK);
	81	reg \|= cs << MXS_SSP_CHIPSELECT_SHIFT;
	82
	83	writel(reg, &ssp_regs->hw_ssp_ctrl0);
ec33de3d	84	return &mxs_slave->slave;
7c5e6f7a MV	85
7c5e6f7a MV	86	err_init:
7c5e6f7a MV	87	free(mxs_slave);
7c5e6f7a MV	88	return NULL;
ec33de3d MV	89	}
	90
	91	void spi_free_slave(struct spi_slave *slave)
	92	{
	93	struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
	94	free(mxs_slave);
	95	}
	96
	97	int spi_claim_bus(struct spi_slave *slave)
	98	{
	99	struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
9c471142	100	struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
ec33de3d MV	101	uint32_t reg = 0;
ec33de3d MV	102
fa7a51cb	103	mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
ec33de3d MV	104
	105	writel(SSP_CTRL0_BUS_WIDTH_ONE_BIT, &ssp_regs->hw_ssp_ctrl0);
	106
	107	reg = SSP_CTRL1_SSP_MODE_SPI \| SSP_CTRL1_WORD_LENGTH_EIGHT_BITS;
	108	reg \|= (mxs_slave->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0;
	109	reg \|= (mxs_slave->mode & SPI_CPHA) ? SSP_CTRL1_PHASE : 0;
	110	writel(reg, &ssp_regs->hw_ssp_ctrl1);
	111
	112	writel(0, &ssp_regs->hw_ssp_cmd0);
	113
bf48fcb6	114	mxs_set_ssp_busclock(slave->bus, mxs_slave->max_khz);
ec33de3d MV	115
	116	return 0;
	117	}
	118
	119	void spi_release_bus(struct spi_slave *slave)
	120	{
	121	}
	122
9c471142	123	static void mxs_spi_start_xfer(struct mxs_ssp_regs *ssp_regs)
ec33de3d MV	124	{
	125	writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_set);
	126	writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_clr);
	127	}
	128
9c471142	129	static void mxs_spi_end_xfer(struct mxs_ssp_regs *ssp_regs)
ec33de3d MV	130	{
	131	writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_clr);
	132	writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_set);
	133	}
	134
ccd4d5a0 MV	135	static int mxs_spi_xfer_pio(struct mxs_spi_slave *slave,
ccd4d5a0 MV	136	char *data, int length, int write, unsigned long flags)
ec33de3d	137	{
9c471142	138	struct mxs_ssp_regs *ssp_regs = slave->regs;
c7065fa8	139
ec33de3d MV	140	if (flags & SPI_XFER_BEGIN)
	141	mxs_spi_start_xfer(ssp_regs);
	142
ccd4d5a0	143	while (length--) {
ec33de3d	144	/* We transfer 1 byte */
c96e78cc MV	145	#if defined(CONFIG_MX23)
	146	writel(SSP_CTRL0_XFER_COUNT_MASK, &ssp_regs->hw_ssp_ctrl0_clr);
	147	writel(1, &ssp_regs->hw_ssp_ctrl0_set);
	148	#elif defined(CONFIG_MX28)
ec33de3d	149	writel(1, &ssp_regs->hw_ssp_xfer_size);
c96e78cc	150	#endif
ec33de3d	151
ccd4d5a0	152	if ((flags & SPI_XFER_END) && !length)
ec33de3d MV	153	mxs_spi_end_xfer(ssp_regs);
ec33de3d MV	154
c7065fa8	155	if (write)
ec33de3d MV	156	writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_clr);
	157	else
	158	writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_set);
	159
	160	writel(SSP_CTRL0_RUN, &ssp_regs->hw_ssp_ctrl0_set);
	161
fa7a51cb	162	if (mxs_wait_mask_set(&ssp_regs->hw_ssp_ctrl0_reg,
ec33de3d MV	163	SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
ec33de3d MV	164	printf("MXS SPI: Timeout waiting for start\n");
d9fb6a4c	165	return -ETIMEDOUT;
ec33de3d MV	166	}
ec33de3d MV	167
c7065fa8 MV	168	if (write)
c7065fa8 MV	169	writel(*data++, &ssp_regs->hw_ssp_data);
ec33de3d MV	170
	171	writel(SSP_CTRL0_DATA_XFER, &ssp_regs->hw_ssp_ctrl0_set);
	172
c7065fa8	173	if (!write) {
fa7a51cb	174	if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_status_reg,
ec33de3d MV	175	SSP_STATUS_FIFO_EMPTY, MXS_SPI_MAX_TIMEOUT)) {
ec33de3d MV	176	printf("MXS SPI: Timeout waiting for data\n");
d9fb6a4c	177	return -ETIMEDOUT;
ec33de3d MV	178	}
ec33de3d MV	179
c7065fa8 MV	180	*data = readl(&ssp_regs->hw_ssp_data);
c7065fa8 MV	181	data++;
ec33de3d MV	182	}
ec33de3d MV	183
fa7a51cb	184	if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_ctrl0_reg,
ec33de3d MV	185	SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
ec33de3d MV	186	printf("MXS SPI: Timeout waiting for finish\n");
d9fb6a4c	187	return -ETIMEDOUT;
ec33de3d MV	188	}
	189	}
	190
	191	return 0;
ccd4d5a0 MV	192	}
ccd4d5a0 MV	193
7c5e6f7a MV	194	static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
	195	char *data, int length, int write, unsigned long flags)
	196	{
2c432144 MV	197	const int xfer_max_sz = 0xff00;
2c432144 MV	198	const int desc_count = DIV_ROUND_UP(length, xfer_max_sz) + 1;
9c471142	199	struct mxs_ssp_regs *ssp_regs = slave->regs;
2c432144 MV	200	struct mxs_dma_desc *dp;
2c432144 MV	201	uint32_t ctrl0;
7c5e6f7a	202	uint32_t cache_data_count;
88d15559	203	const uint32_t dstart = (uint32_t)data;
7c5e6f7a	204	int dmach;
2c432144	205	int tl;
e9f7eafd	206	int ret = 0;
2c432144	207
c96e78cc MV	208	#if defined(CONFIG_MX23)
	209	const int mxs_spi_pio_words = 1;
	210	#elif defined(CONFIG_MX28)
	211	const int mxs_spi_pio_words = 4;
	212	#endif
	213
2c432144 MV	214	ALLOC_CACHE_ALIGN_BUFFER(struct mxs_dma_desc, desc, desc_count);
	215
	216	memset(desc, 0, sizeof(struct mxs_dma_desc) * desc_count);
7c5e6f7a	217
2c432144 MV	218	ctrl0 = readl(&ssp_regs->hw_ssp_ctrl0);
2c432144 MV	219	ctrl0 \|= SSP_CTRL0_DATA_XFER;
7c5e6f7a MV	220
	221	if (flags & SPI_XFER_BEGIN)
	222	ctrl0 \|= SSP_CTRL0_LOCK_CS;
7c5e6f7a MV	223	if (!write)
	224	ctrl0 \|= SSP_CTRL0_READ;
	225
7c5e6f7a MV	226	if (length % ARCH_DMA_MINALIGN)
	227	cache_data_count = roundup(length, ARCH_DMA_MINALIGN);
	228	else
	229	cache_data_count = length;
	230
88d15559	231	/* Flush data to DRAM so DMA can pick them up */
2c432144	232	if (write)
88d15559 MV	233	flush_dcache_range(dstart, dstart + cache_data_count);
	234
	235	/* Invalidate the area, so no writeback into the RAM races with DMA */
	236	invalidate_dcache_range(dstart, dstart + cache_data_count);
7c5e6f7a	237
2c432144 MV	238	dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + slave->slave.bus;
	239
	240	dp = desc;
	241	while (length) {
	242	dp->address = (dma_addr_t)dp;
	243	dp->cmd.address = (dma_addr_t)data;
	244
	245	/*
	246	* This is correct, even though it does indeed look insane.
	247	* I hereby have to, wholeheartedly, thank Freescale Inc.,
	248	* for always inventing insane hardware and keeping me busy
	249	* and employed ;-)
	250	*/
	251	if (write)
	252	dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
	253	else
	254	dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
	255
	256	/*
	257	* The DMA controller can transfer large chunks (64kB) at
	258	* time by setting the transfer length to 0. Setting tl to
	259	* 0x10000 will overflow below and make .data contain 0.
	260	* Otherwise, 0xff00 is the transfer maximum.
	261	*/
	262	if (length >= 0x10000)
	263	tl = 0x10000;
	264	else
	265	tl = min(length, xfer_max_sz);
	266
	267	dp->cmd.data \|=
e9f7eafd	268	((tl & 0xffff) << MXS_DMA_DESC_BYTES_OFFSET) \|
c96e78cc	269	(mxs_spi_pio_words << MXS_DMA_DESC_PIO_WORDS_OFFSET) \|
2c432144 MV	270	MXS_DMA_DESC_HALT_ON_TERMINATE \|
2c432144 MV	271	MXS_DMA_DESC_TERMINATE_FLUSH;
7c5e6f7a	272
2c432144 MV	273	data += tl;
	274	length -= tl;
	275
e9f7eafd MV	276	if (!length) {
	277	dp->cmd.data \|= MXS_DMA_DESC_IRQ \| MXS_DMA_DESC_DEC_SEM;
	278
	279	if (flags & SPI_XFER_END) {
	280	ctrl0 &= ~SSP_CTRL0_LOCK_CS;
	281	ctrl0 \|= SSP_CTRL0_IGNORE_CRC;
	282	}
	283	}
	284
	285	/*
c96e78cc MV	286	* Write CTRL0, CMD0, CMD1 and XFER_SIZE registers in
	287	* case of MX28, write only CTRL0 in case of MX23 due
	288	* to the difference in register layout. It is utterly
e9f7eafd MV	289	* essential that the XFER_SIZE register is written on
	290	* a per-descriptor basis with the same size as is the
	291	* descriptor!
	292	*/
	293	dp->cmd.pio_words[0] = ctrl0;
c96e78cc	294	#ifdef CONFIG_MX28
e9f7eafd MV	295	dp->cmd.pio_words[1] = 0;
	296	dp->cmd.pio_words[2] = 0;
	297	dp->cmd.pio_words[3] = tl;
c96e78cc	298	#endif
e9f7eafd	299
2c432144 MV	300	mxs_dma_desc_append(dmach, dp);
	301
	302	dp++;
	303	}
	304
7c5e6f7a	305	if (mxs_dma_go(dmach))
e9f7eafd	306	ret = -EINVAL;
7c5e6f7a MV	307
7c5e6f7a MV	308	/* The data arrived into DRAM, invalidate cache over them */
88d15559 MV	309	if (!write)
88d15559 MV	310	invalidate_dcache_range(dstart, dstart + cache_data_count);
7c5e6f7a	311
e9f7eafd	312	return ret;
7c5e6f7a MV	313	}
7c5e6f7a MV	314
ccd4d5a0 MV	315	int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
	316	const void dout, void din, unsigned long flags)
	317	{
	318	struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
9c471142	319	struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
ccd4d5a0 MV	320	int len = bitlen / 8;
	321	char dummy;
	322	int write = 0;
	323	char *data = NULL;
7c5e6f7a	324	int dma = 1;
7c5e6f7a	325
ccd4d5a0 MV	326	if (bitlen == 0) {
	327	if (flags & SPI_XFER_END) {
	328	din = (void *)&dummy;
	329	len = 1;
	330	} else
	331	return 0;
	332	}
	333
	334	/* Half-duplex only */
	335	if (din && dout)
	336	return -EINVAL;
	337	/* No data */
	338	if (!din && !dout)
	339	return 0;
	340
	341	if (dout) {
	342	data = (char *)dout;
	343	write = 1;
	344	} else if (din) {
	345	data = (char *)din;
	346	write = 0;
	347	}
	348
7c5e6f7a MV	349	/*
	350	* Check for alignment, if the buffer is aligned, do DMA transfer,
	351	* PIO otherwise. This is a temporary workaround until proper bounce
	352	* buffer is in place.
	353	*/
	354	if (dma) {
	355	if (((uint32_t)data) & (ARCH_DMA_MINALIGN - 1))
	356	dma = 0;
	357	if (((uint32_t)len) & (ARCH_DMA_MINALIGN - 1))
	358	dma = 0;
	359	}
	360
	361	if (!dma \|\| (len < MXSSSP_SMALL_TRANSFER)) {
	362	writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
	363	return mxs_spi_xfer_pio(mxs_slave, data, len, write, flags);
	364	} else {
	365	writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
	366	return mxs_spi_xfer_dma(mxs_slave, data, len, write, flags);
	367	}
ec33de3d	368	}