[people/ms/u-boot.git] / drivers / spi / mxs_spi.c

/*
 * Freescale i.MX28 SPI driver
 *
 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
 * on behalf of DENX Software Engineering GmbH
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 * NOTE: This driver only supports the SPI-controller chipselects,
 *       GPIO driven chipselects are not supported.
 */

#include <common.h>
#include <malloc.h>
#include <spi.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>

#define	MXS_SPI_MAX_TIMEOUT	1000000
#define	MXS_SPI_PORT_OFFSET	0x2000
#define MXS_SSP_CHIPSELECT_MASK		0x00300000
#define MXS_SSP_CHIPSELECT_SHIFT	20

struct mxs_spi_slave {
	struct spi_slave	slave;
	uint32_t		max_khz;
	uint32_t		mode;
	struct mx28_ssp_regs	*regs;
};

static inline struct mxs_spi_slave *to_mxs_slave(struct spi_slave *slave)
{
	return container_of(slave, struct mxs_spi_slave, slave);
}

void spi_init(void)
{
}

int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
	/* MXS SPI: 4 ports and 3 chip selects maximum */
	if (bus > 3 || cs > 2)
		return 0;
	else
		return 1;
}

struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
				  unsigned int max_hz, unsigned int mode)
{
	struct mxs_spi_slave *mxs_slave;
	uint32_t addr;
	struct mx28_ssp_regs *ssp_regs;
	int reg;

	if (!spi_cs_is_valid(bus, cs)) {
		printf("mxs_spi: invalid bus %d / chip select %d\n", bus, cs);
		return NULL;
	}

	mxs_slave = malloc(sizeof(struct mxs_spi_slave));
	if (!mxs_slave)
		return NULL;

	addr = MXS_SSP0_BASE + (bus * MXS_SPI_PORT_OFFSET);

	mxs_slave->slave.bus = bus;
	mxs_slave->slave.cs = cs;
	mxs_slave->max_khz = max_hz / 1000;
	mxs_slave->mode = mode;
	mxs_slave->regs = (struct mx28_ssp_regs *)addr;
	ssp_regs = mxs_slave->regs;

	reg = readl(&ssp_regs->hw_ssp_ctrl0);
	reg &= ~(MXS_SSP_CHIPSELECT_MASK);
	reg |= cs << MXS_SSP_CHIPSELECT_SHIFT;

	writel(reg, &ssp_regs->hw_ssp_ctrl0);
	return &mxs_slave->slave;
}

void spi_free_slave(struct spi_slave *slave)
{
	struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
	free(mxs_slave);
}

int spi_claim_bus(struct spi_slave *slave)
{
	struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
	struct mx28_ssp_regs *ssp_regs = mxs_slave->regs;
	uint32_t reg = 0;

	mx28_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);

	writel(SSP_CTRL0_BUS_WIDTH_ONE_BIT, &ssp_regs->hw_ssp_ctrl0);

	reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS;
	reg |= (mxs_slave->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0;
	reg |= (mxs_slave->mode & SPI_CPHA) ? SSP_CTRL1_PHASE : 0;
	writel(reg, &ssp_regs->hw_ssp_ctrl1);

	writel(0, &ssp_regs->hw_ssp_cmd0);

	mx28_set_ssp_busclock(slave->bus, mxs_slave->max_khz);

	return 0;
}

void spi_release_bus(struct spi_slave *slave)
{
}

static void mxs_spi_start_xfer(struct mx28_ssp_regs *ssp_regs)
{
	writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_set);
	writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_clr);
}

static void mxs_spi_end_xfer(struct mx28_ssp_regs *ssp_regs)
{
	writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_clr);
	writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_set);
}

int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
		const void *dout, void *din, unsigned long flags)
{
	struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
	struct mx28_ssp_regs *ssp_regs = mxs_slave->regs;
	int len = bitlen / 8;
	char dummy;
	int write = 0;
	char *data = NULL;

	if (bitlen == 0) {
		if (flags & SPI_XFER_END) {
			din = (void *)&dummy;
			len = 1;
		} else
			return 0;
	}

	/* Half-duplex only */
	if (din && dout)
		return -EINVAL;
	/* No data */
	if (!din && !dout)
		return 0;

	if (dout) {
		data = (char *)dout;
		write = 1;
	} else if (din) {
		data = (char *)din;
		write = 0;
	}

	if (flags & SPI_XFER_BEGIN)
		mxs_spi_start_xfer(ssp_regs);

	while (len--) {
		/* We transfer 1 byte */
		writel(1, &ssp_regs->hw_ssp_xfer_size);

		if ((flags & SPI_XFER_END) && !len)
			mxs_spi_end_xfer(ssp_regs);

		if (write)
			writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_clr);
		else
			writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_set);

		writel(SSP_CTRL0_RUN, &ssp_regs->hw_ssp_ctrl0_set);

		if (mx28_wait_mask_set(&ssp_regs->hw_ssp_ctrl0_reg,
			SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
			printf("MXS SPI: Timeout waiting for start\n");
			return -ETIMEDOUT;
		}

		if (write)
			writel(*data++, &ssp_regs->hw_ssp_data);

		writel(SSP_CTRL0_DATA_XFER, &ssp_regs->hw_ssp_ctrl0_set);

		if (!write) {
			if (mx28_wait_mask_clr(&ssp_regs->hw_ssp_status_reg,
				SSP_STATUS_FIFO_EMPTY, MXS_SPI_MAX_TIMEOUT)) {
				printf("MXS SPI: Timeout waiting for data\n");
				return -ETIMEDOUT;
			}

			*data = readl(&ssp_regs->hw_ssp_data);
			data++;
		}

		if (mx28_wait_mask_clr(&ssp_regs->hw_ssp_ctrl0_reg,
			SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
			printf("MXS SPI: Timeout waiting for finish\n");
			return -ETIMEDOUT;
		}
	}

	return 0;
}
Commit	Line	Data
ec33de3d MV	1	/*
	2	* Freescale i.MX28 SPI driver
	3	*
	4	* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
	5	* on behalf of DENX Software Engineering GmbH
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*
	22	* NOTE: This driver only supports the SPI-controller chipselects,
	23	* GPIO driven chipselects are not supported.
	24	*/
	25
	26	#include <common.h>
	27	#include <malloc.h>
	28	#include <spi.h>
	29	#include <asm/errno.h>
	30	#include <asm/io.h>
	31	#include <asm/arch/clock.h>
	32	#include <asm/arch/imx-regs.h>
	33	#include <asm/arch/sys_proto.h>
	34
	35	#define MXS_SPI_MAX_TIMEOUT 1000000
	36	#define MXS_SPI_PORT_OFFSET 0x2000
148ca64f FE	37	#define MXS_SSP_CHIPSELECT_MASK 0x00300000
148ca64f FE	38	#define MXS_SSP_CHIPSELECT_SHIFT 20
ec33de3d MV	39
	40	struct mxs_spi_slave {
	41	struct spi_slave slave;
	42	uint32_t max_khz;
	43	uint32_t mode;
	44	struct mx28_ssp_regs *regs;
	45	};
	46
	47	static inline struct mxs_spi_slave to_mxs_slave(struct spi_slave slave)
	48	{
	49	return container_of(slave, struct mxs_spi_slave, slave);
	50	}
	51
	52	void spi_init(void)
	53	{
	54	}
	55
79cb14ab FE	56	int spi_cs_is_valid(unsigned int bus, unsigned int cs)
	57	{
	58	/* MXS SPI: 4 ports and 3 chip selects maximum */
	59	if (bus > 3 \|\| cs > 2)
	60	return 0;
	61	else
	62	return 1;
	63	}
	64
ec33de3d MV	65	struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
	66	unsigned int max_hz, unsigned int mode)
	67	{
	68	struct mxs_spi_slave *mxs_slave;
	69	uint32_t addr;
148ca64f FE	70	struct mx28_ssp_regs *ssp_regs;
148ca64f FE	71	int reg;
ec33de3d	72
79cb14ab FE	73	if (!spi_cs_is_valid(bus, cs)) {
79cb14ab FE	74	printf("mxs_spi: invalid bus %d / chip select %d\n", bus, cs);
ec33de3d MV	75	return NULL;
	76	}
	77
	78	mxs_slave = malloc(sizeof(struct mxs_spi_slave));
	79	if (!mxs_slave)
	80	return NULL;
	81
	82	addr = MXS_SSP0_BASE + (bus * MXS_SPI_PORT_OFFSET);
	83
	84	mxs_slave->slave.bus = bus;
	85	mxs_slave->slave.cs = cs;
	86	mxs_slave->max_khz = max_hz / 1000;
	87	mxs_slave->mode = mode;
	88	mxs_slave->regs = (struct mx28_ssp_regs *)addr;
148ca64f	89	ssp_regs = mxs_slave->regs;
ec33de3d	90
148ca64f FE	91	reg = readl(&ssp_regs->hw_ssp_ctrl0);
	92	reg &= ~(MXS_SSP_CHIPSELECT_MASK);
	93	reg \|= cs << MXS_SSP_CHIPSELECT_SHIFT;
	94
	95	writel(reg, &ssp_regs->hw_ssp_ctrl0);
ec33de3d MV	96	return &mxs_slave->slave;
	97	}
	98
	99	void spi_free_slave(struct spi_slave *slave)
	100	{
	101	struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
	102	free(mxs_slave);
	103	}
	104
	105	int spi_claim_bus(struct spi_slave *slave)
	106	{
	107	struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
	108	struct mx28_ssp_regs *ssp_regs = mxs_slave->regs;
	109	uint32_t reg = 0;
	110
	111	mx28_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
	112
	113	writel(SSP_CTRL0_BUS_WIDTH_ONE_BIT, &ssp_regs->hw_ssp_ctrl0);
	114
	115	reg = SSP_CTRL1_SSP_MODE_SPI \| SSP_CTRL1_WORD_LENGTH_EIGHT_BITS;
	116	reg \|= (mxs_slave->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0;
	117	reg \|= (mxs_slave->mode & SPI_CPHA) ? SSP_CTRL1_PHASE : 0;
	118	writel(reg, &ssp_regs->hw_ssp_ctrl1);
	119
	120	writel(0, &ssp_regs->hw_ssp_cmd0);
	121
	122	mx28_set_ssp_busclock(slave->bus, mxs_slave->max_khz);
	123
	124	return 0;
	125	}
	126
	127	void spi_release_bus(struct spi_slave *slave)
	128	{
	129	}
	130
	131	static void mxs_spi_start_xfer(struct mx28_ssp_regs *ssp_regs)
	132	{
	133	writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_set);
	134	writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_clr);
	135	}
	136
	137	static void mxs_spi_end_xfer(struct mx28_ssp_regs *ssp_regs)
	138	{
	139	writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_clr);
	140	writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_set);
	141	}
	142
	143	int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
	144	const void dout, void din, unsigned long flags)
	145	{
	146	struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
	147	struct mx28_ssp_regs *ssp_regs = mxs_slave->regs;
	148	int len = bitlen / 8;
2638b50b	149	char dummy;
c7065fa8 MV	150	int write = 0;
c7065fa8 MV	151	char *data = NULL;
2638b50b MF	152
	153	if (bitlen == 0) {
	154	if (flags & SPI_XFER_END) {
c7065fa8	155	din = (void *)&dummy;
2638b50b MF	156	len = 1;
	157	} else
	158	return 0;
	159	}
ec33de3d	160
c7065fa8 MV	161	/* Half-duplex only */
	162	if (din && dout)
	163	return -EINVAL;
	164	/* No data */
	165	if (!din && !dout)
ec33de3d MV	166	return 0;
ec33de3d MV	167
c7065fa8 MV	168	if (dout) {
	169	data = (char *)dout;
	170	write = 1;
	171	} else if (din) {
	172	data = (char *)din;
	173	write = 0;
	174	}
	175
ec33de3d MV	176	if (flags & SPI_XFER_BEGIN)
	177	mxs_spi_start_xfer(ssp_regs);
	178
	179	while (len--) {
	180	/* We transfer 1 byte */
	181	writel(1, &ssp_regs->hw_ssp_xfer_size);
	182
	183	if ((flags & SPI_XFER_END) && !len)
	184	mxs_spi_end_xfer(ssp_regs);
	185
c7065fa8	186	if (write)
ec33de3d MV	187	writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_clr);
	188	else
	189	writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_set);
	190
	191	writel(SSP_CTRL0_RUN, &ssp_regs->hw_ssp_ctrl0_set);
	192
	193	if (mx28_wait_mask_set(&ssp_regs->hw_ssp_ctrl0_reg,
	194	SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
	195	printf("MXS SPI: Timeout waiting for start\n");
d9fb6a4c	196	return -ETIMEDOUT;
ec33de3d MV	197	}
ec33de3d MV	198
c7065fa8 MV	199	if (write)
c7065fa8 MV	200	writel(*data++, &ssp_regs->hw_ssp_data);
ec33de3d MV	201
	202	writel(SSP_CTRL0_DATA_XFER, &ssp_regs->hw_ssp_ctrl0_set);
	203
c7065fa8	204	if (!write) {
ec33de3d MV	205	if (mx28_wait_mask_clr(&ssp_regs->hw_ssp_status_reg,
	206	SSP_STATUS_FIFO_EMPTY, MXS_SPI_MAX_TIMEOUT)) {
	207	printf("MXS SPI: Timeout waiting for data\n");
d9fb6a4c	208	return -ETIMEDOUT;
ec33de3d MV	209	}
ec33de3d MV	210
c7065fa8 MV	211	*data = readl(&ssp_regs->hw_ssp_data);
c7065fa8 MV	212	data++;
ec33de3d MV	213	}
	214
	215	if (mx28_wait_mask_clr(&ssp_regs->hw_ssp_ctrl0_reg,
	216	SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
	217	printf("MXS SPI: Timeout waiting for finish\n");
d9fb6a4c	218	return -ETIMEDOUT;
ec33de3d MV	219	}
	220	}
	221
	222	return 0;
	223	}