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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
754ce4f2 HS |
2 | /* |
3 | * Driver for Atmel AT32 and AT91 SPI Controllers | |
4 | * | |
5 | * Copyright (C) 2006 Atmel Corporation | |
754ce4f2 HS |
6 | */ |
7 | ||
8 | #include <linux/kernel.h> | |
754ce4f2 HS |
9 | #include <linux/clk.h> |
10 | #include <linux/module.h> | |
11 | #include <linux/platform_device.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/dma-mapping.h> | |
1ccc404a | 14 | #include <linux/dmaengine.h> |
754ce4f2 HS |
15 | #include <linux/err.h> |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/spi/spi.h> | |
5a0e3ad6 | 18 | #include <linux/slab.h> |
1ccc404a | 19 | #include <linux/platform_data/dma-atmel.h> |
850a5b67 | 20 | #include <linux/of.h> |
754ce4f2 | 21 | |
d4820b74 | 22 | #include <linux/io.h> |
efc92fbb | 23 | #include <linux/gpio/consumer.h> |
5bdfd491 | 24 | #include <linux/pinctrl/consumer.h> |
ce0c4caf | 25 | #include <linux/pm_runtime.h> |
3c0448d5 | 26 | #include <trace/events/spi.h> |
bb2d1c36 | 27 | |
ca632f55 GL |
28 | /* SPI register offsets */ |
29 | #define SPI_CR 0x0000 | |
30 | #define SPI_MR 0x0004 | |
31 | #define SPI_RDR 0x0008 | |
32 | #define SPI_TDR 0x000c | |
33 | #define SPI_SR 0x0010 | |
34 | #define SPI_IER 0x0014 | |
35 | #define SPI_IDR 0x0018 | |
36 | #define SPI_IMR 0x001c | |
37 | #define SPI_CSR0 0x0030 | |
38 | #define SPI_CSR1 0x0034 | |
39 | #define SPI_CSR2 0x0038 | |
40 | #define SPI_CSR3 0x003c | |
11f2764f CP |
41 | #define SPI_FMR 0x0040 |
42 | #define SPI_FLR 0x0044 | |
d4820b74 | 43 | #define SPI_VERSION 0x00fc |
ca632f55 GL |
44 | #define SPI_RPR 0x0100 |
45 | #define SPI_RCR 0x0104 | |
46 | #define SPI_TPR 0x0108 | |
47 | #define SPI_TCR 0x010c | |
48 | #define SPI_RNPR 0x0110 | |
49 | #define SPI_RNCR 0x0114 | |
50 | #define SPI_TNPR 0x0118 | |
51 | #define SPI_TNCR 0x011c | |
52 | #define SPI_PTCR 0x0120 | |
53 | #define SPI_PTSR 0x0124 | |
54 | ||
55 | /* Bitfields in CR */ | |
56 | #define SPI_SPIEN_OFFSET 0 | |
57 | #define SPI_SPIEN_SIZE 1 | |
58 | #define SPI_SPIDIS_OFFSET 1 | |
59 | #define SPI_SPIDIS_SIZE 1 | |
60 | #define SPI_SWRST_OFFSET 7 | |
61 | #define SPI_SWRST_SIZE 1 | |
62 | #define SPI_LASTXFER_OFFSET 24 | |
63 | #define SPI_LASTXFER_SIZE 1 | |
11f2764f CP |
64 | #define SPI_TXFCLR_OFFSET 16 |
65 | #define SPI_TXFCLR_SIZE 1 | |
66 | #define SPI_RXFCLR_OFFSET 17 | |
67 | #define SPI_RXFCLR_SIZE 1 | |
68 | #define SPI_FIFOEN_OFFSET 30 | |
69 | #define SPI_FIFOEN_SIZE 1 | |
70 | #define SPI_FIFODIS_OFFSET 31 | |
71 | #define SPI_FIFODIS_SIZE 1 | |
ca632f55 GL |
72 | |
73 | /* Bitfields in MR */ | |
74 | #define SPI_MSTR_OFFSET 0 | |
75 | #define SPI_MSTR_SIZE 1 | |
76 | #define SPI_PS_OFFSET 1 | |
77 | #define SPI_PS_SIZE 1 | |
78 | #define SPI_PCSDEC_OFFSET 2 | |
79 | #define SPI_PCSDEC_SIZE 1 | |
80 | #define SPI_FDIV_OFFSET 3 | |
81 | #define SPI_FDIV_SIZE 1 | |
82 | #define SPI_MODFDIS_OFFSET 4 | |
83 | #define SPI_MODFDIS_SIZE 1 | |
d4820b74 WY |
84 | #define SPI_WDRBT_OFFSET 5 |
85 | #define SPI_WDRBT_SIZE 1 | |
ca632f55 GL |
86 | #define SPI_LLB_OFFSET 7 |
87 | #define SPI_LLB_SIZE 1 | |
88 | #define SPI_PCS_OFFSET 16 | |
89 | #define SPI_PCS_SIZE 4 | |
90 | #define SPI_DLYBCS_OFFSET 24 | |
91 | #define SPI_DLYBCS_SIZE 8 | |
92 | ||
93 | /* Bitfields in RDR */ | |
94 | #define SPI_RD_OFFSET 0 | |
95 | #define SPI_RD_SIZE 16 | |
96 | ||
97 | /* Bitfields in TDR */ | |
98 | #define SPI_TD_OFFSET 0 | |
99 | #define SPI_TD_SIZE 16 | |
100 | ||
101 | /* Bitfields in SR */ | |
102 | #define SPI_RDRF_OFFSET 0 | |
103 | #define SPI_RDRF_SIZE 1 | |
104 | #define SPI_TDRE_OFFSET 1 | |
105 | #define SPI_TDRE_SIZE 1 | |
106 | #define SPI_MODF_OFFSET 2 | |
107 | #define SPI_MODF_SIZE 1 | |
108 | #define SPI_OVRES_OFFSET 3 | |
109 | #define SPI_OVRES_SIZE 1 | |
110 | #define SPI_ENDRX_OFFSET 4 | |
111 | #define SPI_ENDRX_SIZE 1 | |
112 | #define SPI_ENDTX_OFFSET 5 | |
113 | #define SPI_ENDTX_SIZE 1 | |
114 | #define SPI_RXBUFF_OFFSET 6 | |
115 | #define SPI_RXBUFF_SIZE 1 | |
116 | #define SPI_TXBUFE_OFFSET 7 | |
117 | #define SPI_TXBUFE_SIZE 1 | |
118 | #define SPI_NSSR_OFFSET 8 | |
119 | #define SPI_NSSR_SIZE 1 | |
120 | #define SPI_TXEMPTY_OFFSET 9 | |
121 | #define SPI_TXEMPTY_SIZE 1 | |
122 | #define SPI_SPIENS_OFFSET 16 | |
123 | #define SPI_SPIENS_SIZE 1 | |
11f2764f CP |
124 | #define SPI_TXFEF_OFFSET 24 |
125 | #define SPI_TXFEF_SIZE 1 | |
126 | #define SPI_TXFFF_OFFSET 25 | |
127 | #define SPI_TXFFF_SIZE 1 | |
128 | #define SPI_TXFTHF_OFFSET 26 | |
129 | #define SPI_TXFTHF_SIZE 1 | |
130 | #define SPI_RXFEF_OFFSET 27 | |
131 | #define SPI_RXFEF_SIZE 1 | |
132 | #define SPI_RXFFF_OFFSET 28 | |
133 | #define SPI_RXFFF_SIZE 1 | |
134 | #define SPI_RXFTHF_OFFSET 29 | |
135 | #define SPI_RXFTHF_SIZE 1 | |
136 | #define SPI_TXFPTEF_OFFSET 30 | |
137 | #define SPI_TXFPTEF_SIZE 1 | |
138 | #define SPI_RXFPTEF_OFFSET 31 | |
139 | #define SPI_RXFPTEF_SIZE 1 | |
ca632f55 GL |
140 | |
141 | /* Bitfields in CSR0 */ | |
142 | #define SPI_CPOL_OFFSET 0 | |
143 | #define SPI_CPOL_SIZE 1 | |
144 | #define SPI_NCPHA_OFFSET 1 | |
145 | #define SPI_NCPHA_SIZE 1 | |
146 | #define SPI_CSAAT_OFFSET 3 | |
147 | #define SPI_CSAAT_SIZE 1 | |
148 | #define SPI_BITS_OFFSET 4 | |
149 | #define SPI_BITS_SIZE 4 | |
150 | #define SPI_SCBR_OFFSET 8 | |
151 | #define SPI_SCBR_SIZE 8 | |
152 | #define SPI_DLYBS_OFFSET 16 | |
153 | #define SPI_DLYBS_SIZE 8 | |
154 | #define SPI_DLYBCT_OFFSET 24 | |
155 | #define SPI_DLYBCT_SIZE 8 | |
156 | ||
157 | /* Bitfields in RCR */ | |
158 | #define SPI_RXCTR_OFFSET 0 | |
159 | #define SPI_RXCTR_SIZE 16 | |
160 | ||
161 | /* Bitfields in TCR */ | |
162 | #define SPI_TXCTR_OFFSET 0 | |
163 | #define SPI_TXCTR_SIZE 16 | |
164 | ||
165 | /* Bitfields in RNCR */ | |
166 | #define SPI_RXNCR_OFFSET 0 | |
167 | #define SPI_RXNCR_SIZE 16 | |
168 | ||
169 | /* Bitfields in TNCR */ | |
170 | #define SPI_TXNCR_OFFSET 0 | |
171 | #define SPI_TXNCR_SIZE 16 | |
172 | ||
173 | /* Bitfields in PTCR */ | |
174 | #define SPI_RXTEN_OFFSET 0 | |
175 | #define SPI_RXTEN_SIZE 1 | |
176 | #define SPI_RXTDIS_OFFSET 1 | |
177 | #define SPI_RXTDIS_SIZE 1 | |
178 | #define SPI_TXTEN_OFFSET 8 | |
179 | #define SPI_TXTEN_SIZE 1 | |
180 | #define SPI_TXTDIS_OFFSET 9 | |
181 | #define SPI_TXTDIS_SIZE 1 | |
182 | ||
11f2764f CP |
183 | /* Bitfields in FMR */ |
184 | #define SPI_TXRDYM_OFFSET 0 | |
185 | #define SPI_TXRDYM_SIZE 2 | |
186 | #define SPI_RXRDYM_OFFSET 4 | |
187 | #define SPI_RXRDYM_SIZE 2 | |
188 | #define SPI_TXFTHRES_OFFSET 16 | |
189 | #define SPI_TXFTHRES_SIZE 6 | |
190 | #define SPI_RXFTHRES_OFFSET 24 | |
191 | #define SPI_RXFTHRES_SIZE 6 | |
192 | ||
193 | /* Bitfields in FLR */ | |
194 | #define SPI_TXFL_OFFSET 0 | |
195 | #define SPI_TXFL_SIZE 6 | |
196 | #define SPI_RXFL_OFFSET 16 | |
197 | #define SPI_RXFL_SIZE 6 | |
198 | ||
ca632f55 GL |
199 | /* Constants for BITS */ |
200 | #define SPI_BITS_8_BPT 0 | |
201 | #define SPI_BITS_9_BPT 1 | |
202 | #define SPI_BITS_10_BPT 2 | |
203 | #define SPI_BITS_11_BPT 3 | |
204 | #define SPI_BITS_12_BPT 4 | |
205 | #define SPI_BITS_13_BPT 5 | |
206 | #define SPI_BITS_14_BPT 6 | |
207 | #define SPI_BITS_15_BPT 7 | |
208 | #define SPI_BITS_16_BPT 8 | |
11f2764f CP |
209 | #define SPI_ONE_DATA 0 |
210 | #define SPI_TWO_DATA 1 | |
211 | #define SPI_FOUR_DATA 2 | |
ca632f55 GL |
212 | |
213 | /* Bit manipulation macros */ | |
214 | #define SPI_BIT(name) \ | |
215 | (1 << SPI_##name##_OFFSET) | |
a536d765 | 216 | #define SPI_BF(name, value) \ |
ca632f55 | 217 | (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET) |
a536d765 | 218 | #define SPI_BFEXT(name, value) \ |
ca632f55 | 219 | (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1)) |
a536d765 SK |
220 | #define SPI_BFINS(name, value, old) \ |
221 | (((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \ | |
222 | | SPI_BF(name, value)) | |
ca632f55 GL |
223 | |
224 | /* Register access macros */ | |
ea467326 BD |
225 | #define spi_readl(port, reg) \ |
226 | readl_relaxed((port)->regs + SPI_##reg) | |
227 | #define spi_writel(port, reg, value) \ | |
228 | writel_relaxed((value), (port)->regs + SPI_##reg) | |
11f2764f CP |
229 | #define spi_writew(port, reg, value) \ |
230 | writew_relaxed((value), (port)->regs + SPI_##reg) | |
231 | ||
1ccc404a NF |
232 | /* use PIO for small transfers, avoiding DMA setup/teardown overhead and |
233 | * cache operations; better heuristics consider wordsize and bitrate. | |
234 | */ | |
235 | #define DMA_MIN_BYTES 16 | |
236 | ||
8090d6d1 WY |
237 | #define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000)) |
238 | ||
ce0c4caf WY |
239 | #define AUTOSUSPEND_TIMEOUT 2000 |
240 | ||
d4820b74 WY |
241 | struct atmel_spi_caps { |
242 | bool is_spi2; | |
243 | bool has_wdrbt; | |
244 | bool has_dma_support; | |
7094576c | 245 | bool has_pdc_support; |
d4820b74 | 246 | }; |
754ce4f2 HS |
247 | |
248 | /* | |
249 | * The core SPI transfer engine just talks to a register bank to set up | |
250 | * DMA transfers; transfer queue progress is driven by IRQs. The clock | |
251 | * framework provides the base clock, subdivided for each spi_device. | |
754ce4f2 HS |
252 | */ |
253 | struct atmel_spi { | |
254 | spinlock_t lock; | |
8aad7924 | 255 | unsigned long flags; |
754ce4f2 | 256 | |
dfab30ee | 257 | phys_addr_t phybase; |
754ce4f2 HS |
258 | void __iomem *regs; |
259 | int irq; | |
260 | struct clk *clk; | |
261 | struct platform_device *pdev; | |
39fe33f9 | 262 | unsigned long spi_clk; |
754ce4f2 | 263 | |
754ce4f2 | 264 | struct spi_transfer *current_transfer; |
0c3b9748 | 265 | int current_remaining_bytes; |
823cd045 | 266 | int done_status; |
a9889ed6 RP |
267 | dma_addr_t dma_addr_rx_bbuf; |
268 | dma_addr_t dma_addr_tx_bbuf; | |
269 | void *addr_rx_bbuf; | |
270 | void *addr_tx_bbuf; | |
754ce4f2 | 271 | |
8090d6d1 WY |
272 | struct completion xfer_completion; |
273 | ||
d4820b74 | 274 | struct atmel_spi_caps caps; |
1ccc404a NF |
275 | |
276 | bool use_dma; | |
277 | bool use_pdc; | |
8090d6d1 WY |
278 | |
279 | bool keep_cs; | |
11f2764f CP |
280 | |
281 | u32 fifo_size; | |
57e31377 GC |
282 | u8 native_cs_free; |
283 | u8 native_cs_for_gpio; | |
754ce4f2 HS |
284 | }; |
285 | ||
5ee36c98 HS |
286 | /* Controller-specific per-slave state */ |
287 | struct atmel_spi_device { | |
5ee36c98 HS |
288 | u32 csr; |
289 | }; | |
290 | ||
7910d9af | 291 | #define SPI_MAX_DMA_XFER 65535 /* true for both PDC and DMA */ |
754ce4f2 HS |
292 | #define INVALID_DMA_ADDRESS 0xffffffff |
293 | ||
5bfa26ca HS |
294 | /* |
295 | * Version 2 of the SPI controller has | |
296 | * - CR.LASTXFER | |
297 | * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero) | |
298 | * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs) | |
299 | * - SPI_CSRx.CSAAT | |
300 | * - SPI_CSRx.SBCR allows faster clocking | |
5bfa26ca | 301 | */ |
d4820b74 | 302 | static bool atmel_spi_is_v2(struct atmel_spi *as) |
5bfa26ca | 303 | { |
d4820b74 | 304 | return as->caps.is_spi2; |
5bfa26ca HS |
305 | } |
306 | ||
754ce4f2 HS |
307 | /* |
308 | * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby | |
309 | * they assume that spi slave device state will not change on deselect, so | |
defbd3b4 DB |
310 | * that automagic deselection is OK. ("NPCSx rises if no data is to be |
311 | * transmitted") Not so! Workaround uses nCSx pins as GPIOs; or newer | |
312 | * controllers have CSAAT and friends. | |
754ce4f2 | 313 | * |
4d8672d1 GC |
314 | * Even controller newer than ar91rm9200, using GPIOs can make sens as |
315 | * it lets us support active-high chipselects despite the controller's | |
316 | * belief that only active-low devices/systems exists. | |
defbd3b4 DB |
317 | * |
318 | * However, at91rm9200 has a second erratum whereby nCS0 doesn't work | |
319 | * right when driven with GPIO. ("Mode Fault does not allow more than one | |
320 | * Master on Chip Select 0.") No workaround exists for that ... so for | |
321 | * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH, | |
322 | * and (c) will trigger that first erratum in some cases. | |
754ce4f2 HS |
323 | */ |
324 | ||
defbd3b4 | 325 | static void cs_activate(struct atmel_spi *as, struct spi_device *spi) |
754ce4f2 | 326 | { |
5ee36c98 | 327 | struct atmel_spi_device *asd = spi->controller_state; |
57e31377 | 328 | int chip_select; |
defbd3b4 DB |
329 | u32 mr; |
330 | ||
57e31377 GC |
331 | if (spi->cs_gpiod) |
332 | chip_select = as->native_cs_for_gpio; | |
333 | else | |
334 | chip_select = spi->chip_select; | |
335 | ||
d4820b74 | 336 | if (atmel_spi_is_v2(as)) { |
57e31377 | 337 | spi_writel(as, CSR0 + 4 * chip_select, asd->csr); |
97ed465b WY |
338 | /* For the low SPI version, there is a issue that PDC transfer |
339 | * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS | |
5ee36c98 HS |
340 | */ |
341 | spi_writel(as, CSR0, asd->csr); | |
d4820b74 | 342 | if (as->caps.has_wdrbt) { |
97ed465b | 343 | spi_writel(as, MR, |
57e31377 | 344 | SPI_BF(PCS, ~(0x01 << chip_select)) |
97ed465b WY |
345 | | SPI_BIT(WDRBT) |
346 | | SPI_BIT(MODFDIS) | |
347 | | SPI_BIT(MSTR)); | |
d4820b74 | 348 | } else { |
97ed465b | 349 | spi_writel(as, MR, |
57e31377 | 350 | SPI_BF(PCS, ~(0x01 << chip_select)) |
97ed465b WY |
351 | | SPI_BIT(MODFDIS) |
352 | | SPI_BIT(MSTR)); | |
d4820b74 | 353 | } |
1ccc404a | 354 | |
5ee36c98 | 355 | mr = spi_readl(as, MR); |
60086e23 GC |
356 | if (spi->cs_gpiod) |
357 | gpiod_set_value(spi->cs_gpiod, 1); | |
5ee36c98 HS |
358 | } else { |
359 | u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0; | |
360 | int i; | |
361 | u32 csr; | |
362 | ||
363 | /* Make sure clock polarity is correct */ | |
364 | for (i = 0; i < spi->master->num_chipselect; i++) { | |
365 | csr = spi_readl(as, CSR0 + 4 * i); | |
366 | if ((csr ^ cpol) & SPI_BIT(CPOL)) | |
367 | spi_writel(as, CSR0 + 4 * i, | |
368 | csr ^ SPI_BIT(CPOL)); | |
369 | } | |
370 | ||
371 | mr = spi_readl(as, MR); | |
57e31377 | 372 | mr = SPI_BFINS(PCS, ~(1 << chip_select), mr); |
9c86f12a | 373 | if (spi->cs_gpiod) |
60086e23 | 374 | gpiod_set_value(spi->cs_gpiod, 1); |
5ee36c98 HS |
375 | spi_writel(as, MR, mr); |
376 | } | |
defbd3b4 | 377 | |
efc92fbb | 378 | dev_dbg(&spi->dev, "activate NPCS, mr %08x\n", mr); |
754ce4f2 HS |
379 | } |
380 | ||
defbd3b4 | 381 | static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi) |
754ce4f2 | 382 | { |
57e31377 | 383 | int chip_select; |
defbd3b4 DB |
384 | u32 mr; |
385 | ||
57e31377 GC |
386 | if (spi->cs_gpiod) |
387 | chip_select = as->native_cs_for_gpio; | |
388 | else | |
389 | chip_select = spi->chip_select; | |
390 | ||
defbd3b4 DB |
391 | /* only deactivate *this* device; sometimes transfers to |
392 | * another device may be active when this routine is called. | |
393 | */ | |
394 | mr = spi_readl(as, MR); | |
57e31377 | 395 | if (~SPI_BFEXT(PCS, mr) & (1 << chip_select)) { |
defbd3b4 DB |
396 | mr = SPI_BFINS(PCS, 0xf, mr); |
397 | spi_writel(as, MR, mr); | |
398 | } | |
754ce4f2 | 399 | |
efc92fbb | 400 | dev_dbg(&spi->dev, "DEactivate NPCS, mr %08x\n", mr); |
defbd3b4 | 401 | |
60086e23 | 402 | if (!spi->cs_gpiod) |
48203034 | 403 | spi_writel(as, CR, SPI_BIT(LASTXFER)); |
9c86f12a | 404 | else |
60086e23 | 405 | gpiod_set_value(spi->cs_gpiod, 0); |
754ce4f2 HS |
406 | } |
407 | ||
6c07ef29 | 408 | static void atmel_spi_lock(struct atmel_spi *as) __acquires(&as->lock) |
8aad7924 NF |
409 | { |
410 | spin_lock_irqsave(&as->lock, as->flags); | |
411 | } | |
412 | ||
6c07ef29 | 413 | static void atmel_spi_unlock(struct atmel_spi *as) __releases(&as->lock) |
8aad7924 NF |
414 | { |
415 | spin_unlock_irqrestore(&as->lock, as->flags); | |
416 | } | |
417 | ||
a9889ed6 RP |
418 | static inline bool atmel_spi_is_vmalloc_xfer(struct spi_transfer *xfer) |
419 | { | |
420 | return is_vmalloc_addr(xfer->tx_buf) || is_vmalloc_addr(xfer->rx_buf); | |
421 | } | |
422 | ||
1ccc404a NF |
423 | static inline bool atmel_spi_use_dma(struct atmel_spi *as, |
424 | struct spi_transfer *xfer) | |
425 | { | |
426 | return as->use_dma && xfer->len >= DMA_MIN_BYTES; | |
427 | } | |
428 | ||
04242ca4 CP |
429 | static bool atmel_spi_can_dma(struct spi_master *master, |
430 | struct spi_device *spi, | |
431 | struct spi_transfer *xfer) | |
432 | { | |
433 | struct atmel_spi *as = spi_master_get_devdata(master); | |
434 | ||
a9889ed6 RP |
435 | if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) |
436 | return atmel_spi_use_dma(as, xfer) && | |
437 | !atmel_spi_is_vmalloc_xfer(xfer); | |
438 | else | |
439 | return atmel_spi_use_dma(as, xfer); | |
440 | ||
04242ca4 CP |
441 | } |
442 | ||
1ccc404a NF |
443 | static int atmel_spi_dma_slave_config(struct atmel_spi *as, |
444 | struct dma_slave_config *slave_config, | |
445 | u8 bits_per_word) | |
446 | { | |
768f3d9d | 447 | struct spi_master *master = platform_get_drvdata(as->pdev); |
1ccc404a NF |
448 | int err = 0; |
449 | ||
450 | if (bits_per_word > 8) { | |
451 | slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
452 | slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
453 | } else { | |
454 | slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
455 | slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
456 | } | |
457 | ||
458 | slave_config->dst_addr = (dma_addr_t)as->phybase + SPI_TDR; | |
459 | slave_config->src_addr = (dma_addr_t)as->phybase + SPI_RDR; | |
460 | slave_config->src_maxburst = 1; | |
461 | slave_config->dst_maxburst = 1; | |
462 | slave_config->device_fc = false; | |
463 | ||
11f2764f CP |
464 | /* |
465 | * This driver uses fixed peripheral select mode (PS bit set to '0' in | |
466 | * the Mode Register). | |
467 | * So according to the datasheet, when FIFOs are available (and | |
468 | * enabled), the Transmit FIFO operates in Multiple Data Mode. | |
469 | * In this mode, up to 2 data, not 4, can be written into the Transmit | |
470 | * Data Register in a single access. | |
471 | * However, the first data has to be written into the lowest 16 bits and | |
472 | * the second data into the highest 16 bits of the Transmit | |
473 | * Data Register. For 8bit data (the most frequent case), it would | |
474 | * require to rework tx_buf so each data would actualy fit 16 bits. | |
475 | * So we'd rather write only one data at the time. Hence the transmit | |
476 | * path works the same whether FIFOs are available (and enabled) or not. | |
477 | */ | |
1ccc404a | 478 | slave_config->direction = DMA_MEM_TO_DEV; |
768f3d9d | 479 | if (dmaengine_slave_config(master->dma_tx, slave_config)) { |
1ccc404a NF |
480 | dev_err(&as->pdev->dev, |
481 | "failed to configure tx dma channel\n"); | |
482 | err = -EINVAL; | |
483 | } | |
484 | ||
11f2764f CP |
485 | /* |
486 | * This driver configures the spi controller for master mode (MSTR bit | |
487 | * set to '1' in the Mode Register). | |
488 | * So according to the datasheet, when FIFOs are available (and | |
489 | * enabled), the Receive FIFO operates in Single Data Mode. | |
490 | * So the receive path works the same whether FIFOs are available (and | |
491 | * enabled) or not. | |
492 | */ | |
1ccc404a | 493 | slave_config->direction = DMA_DEV_TO_MEM; |
768f3d9d | 494 | if (dmaengine_slave_config(master->dma_rx, slave_config)) { |
1ccc404a NF |
495 | dev_err(&as->pdev->dev, |
496 | "failed to configure rx dma channel\n"); | |
497 | err = -EINVAL; | |
498 | } | |
499 | ||
500 | return err; | |
501 | } | |
502 | ||
768f3d9d NF |
503 | static int atmel_spi_configure_dma(struct spi_master *master, |
504 | struct atmel_spi *as) | |
1ccc404a | 505 | { |
1ccc404a | 506 | struct dma_slave_config slave_config; |
2f767a9f | 507 | struct device *dev = &as->pdev->dev; |
1ccc404a NF |
508 | int err; |
509 | ||
2f767a9f RG |
510 | dma_cap_mask_t mask; |
511 | dma_cap_zero(mask); | |
512 | dma_cap_set(DMA_SLAVE, mask); | |
1ccc404a | 513 | |
bef1e0c8 | 514 | master->dma_tx = dma_request_chan(dev, "tx"); |
768f3d9d NF |
515 | if (IS_ERR(master->dma_tx)) { |
516 | err = PTR_ERR(master->dma_tx); | |
d947c9d2 PU |
517 | if (err != -EPROBE_DEFER) |
518 | dev_err(dev, "No TX DMA channel, DMA is disabled\n"); | |
768f3d9d | 519 | goto error_clear; |
1ccc404a | 520 | } |
2f767a9f | 521 | |
d947c9d2 PU |
522 | master->dma_rx = dma_request_chan(dev, "rx"); |
523 | if (IS_ERR(master->dma_rx)) { | |
524 | err = PTR_ERR(master->dma_rx); | |
525 | /* | |
526 | * No reason to check EPROBE_DEFER here since we have already | |
527 | * requested tx channel. | |
528 | */ | |
529 | dev_err(dev, "No RX DMA channel, DMA is disabled\n"); | |
1ccc404a NF |
530 | goto error; |
531 | } | |
532 | ||
533 | err = atmel_spi_dma_slave_config(as, &slave_config, 8); | |
534 | if (err) | |
535 | goto error; | |
536 | ||
537 | dev_info(&as->pdev->dev, | |
538 | "Using %s (tx) and %s (rx) for DMA transfers\n", | |
768f3d9d NF |
539 | dma_chan_name(master->dma_tx), |
540 | dma_chan_name(master->dma_rx)); | |
541 | ||
1ccc404a NF |
542 | return 0; |
543 | error: | |
d947c9d2 | 544 | if (!IS_ERR(master->dma_rx)) |
768f3d9d NF |
545 | dma_release_channel(master->dma_rx); |
546 | if (!IS_ERR(master->dma_tx)) | |
547 | dma_release_channel(master->dma_tx); | |
548 | error_clear: | |
549 | master->dma_tx = master->dma_rx = NULL; | |
1ccc404a NF |
550 | return err; |
551 | } | |
552 | ||
768f3d9d | 553 | static void atmel_spi_stop_dma(struct spi_master *master) |
1ccc404a | 554 | { |
768f3d9d NF |
555 | if (master->dma_rx) |
556 | dmaengine_terminate_all(master->dma_rx); | |
557 | if (master->dma_tx) | |
558 | dmaengine_terminate_all(master->dma_tx); | |
1ccc404a NF |
559 | } |
560 | ||
768f3d9d | 561 | static void atmel_spi_release_dma(struct spi_master *master) |
1ccc404a | 562 | { |
768f3d9d NF |
563 | if (master->dma_rx) { |
564 | dma_release_channel(master->dma_rx); | |
565 | master->dma_rx = NULL; | |
566 | } | |
567 | if (master->dma_tx) { | |
568 | dma_release_channel(master->dma_tx); | |
569 | master->dma_tx = NULL; | |
570 | } | |
1ccc404a NF |
571 | } |
572 | ||
573 | /* This function is called by the DMA driver from tasklet context */ | |
574 | static void dma_callback(void *data) | |
575 | { | |
576 | struct spi_master *master = data; | |
577 | struct atmel_spi *as = spi_master_get_devdata(master); | |
578 | ||
a9889ed6 RP |
579 | if (is_vmalloc_addr(as->current_transfer->rx_buf) && |
580 | IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) { | |
581 | memcpy(as->current_transfer->rx_buf, as->addr_rx_bbuf, | |
582 | as->current_transfer->len); | |
583 | } | |
8090d6d1 | 584 | complete(&as->xfer_completion); |
1ccc404a NF |
585 | } |
586 | ||
587 | /* | |
11f2764f | 588 | * Next transfer using PIO without FIFO. |
1ccc404a | 589 | */ |
11f2764f CP |
590 | static void atmel_spi_next_xfer_single(struct spi_master *master, |
591 | struct spi_transfer *xfer) | |
1ccc404a NF |
592 | { |
593 | struct atmel_spi *as = spi_master_get_devdata(master); | |
8090d6d1 | 594 | unsigned long xfer_pos = xfer->len - as->current_remaining_bytes; |
1ccc404a NF |
595 | |
596 | dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_pio\n"); | |
597 | ||
1ccc404a NF |
598 | /* Make sure data is not remaining in RDR */ |
599 | spi_readl(as, RDR); | |
600 | while (spi_readl(as, SR) & SPI_BIT(RDRF)) { | |
601 | spi_readl(as, RDR); | |
602 | cpu_relax(); | |
603 | } | |
604 | ||
7910d9af NF |
605 | if (xfer->bits_per_word > 8) |
606 | spi_writel(as, TDR, *(u16 *)(xfer->tx_buf + xfer_pos)); | |
607 | else | |
608 | spi_writel(as, TDR, *(u8 *)(xfer->tx_buf + xfer_pos)); | |
1ccc404a NF |
609 | |
610 | dev_dbg(master->dev.parent, | |
f557c98b RG |
611 | " start pio xfer %p: len %u tx %p rx %p bitpw %d\n", |
612 | xfer, xfer->len, xfer->tx_buf, xfer->rx_buf, | |
613 | xfer->bits_per_word); | |
1ccc404a NF |
614 | |
615 | /* Enable relevant interrupts */ | |
616 | spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES)); | |
617 | } | |
618 | ||
11f2764f CP |
619 | /* |
620 | * Next transfer using PIO with FIFO. | |
621 | */ | |
622 | static void atmel_spi_next_xfer_fifo(struct spi_master *master, | |
623 | struct spi_transfer *xfer) | |
624 | { | |
625 | struct atmel_spi *as = spi_master_get_devdata(master); | |
626 | u32 current_remaining_data, num_data; | |
627 | u32 offset = xfer->len - as->current_remaining_bytes; | |
628 | const u16 *words = (const u16 *)((u8 *)xfer->tx_buf + offset); | |
629 | const u8 *bytes = (const u8 *)((u8 *)xfer->tx_buf + offset); | |
630 | u16 td0, td1; | |
631 | u32 fifomr; | |
632 | ||
633 | dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_fifo\n"); | |
634 | ||
635 | /* Compute the number of data to transfer in the current iteration */ | |
636 | current_remaining_data = ((xfer->bits_per_word > 8) ? | |
637 | ((u32)as->current_remaining_bytes >> 1) : | |
638 | (u32)as->current_remaining_bytes); | |
639 | num_data = min(current_remaining_data, as->fifo_size); | |
640 | ||
641 | /* Flush RX and TX FIFOs */ | |
642 | spi_writel(as, CR, SPI_BIT(RXFCLR) | SPI_BIT(TXFCLR)); | |
643 | while (spi_readl(as, FLR)) | |
644 | cpu_relax(); | |
645 | ||
646 | /* Set RX FIFO Threshold to the number of data to transfer */ | |
647 | fifomr = spi_readl(as, FMR); | |
648 | spi_writel(as, FMR, SPI_BFINS(RXFTHRES, num_data, fifomr)); | |
649 | ||
650 | /* Clear FIFO flags in the Status Register, especially RXFTHF */ | |
651 | (void)spi_readl(as, SR); | |
652 | ||
653 | /* Fill TX FIFO */ | |
654 | while (num_data >= 2) { | |
7910d9af NF |
655 | if (xfer->bits_per_word > 8) { |
656 | td0 = *words++; | |
657 | td1 = *words++; | |
11f2764f | 658 | } else { |
7910d9af NF |
659 | td0 = *bytes++; |
660 | td1 = *bytes++; | |
11f2764f CP |
661 | } |
662 | ||
663 | spi_writel(as, TDR, (td1 << 16) | td0); | |
664 | num_data -= 2; | |
665 | } | |
666 | ||
667 | if (num_data) { | |
7910d9af NF |
668 | if (xfer->bits_per_word > 8) |
669 | td0 = *words++; | |
670 | else | |
671 | td0 = *bytes++; | |
11f2764f CP |
672 | |
673 | spi_writew(as, TDR, td0); | |
674 | num_data--; | |
675 | } | |
676 | ||
677 | dev_dbg(master->dev.parent, | |
678 | " start fifo xfer %p: len %u tx %p rx %p bitpw %d\n", | |
679 | xfer, xfer->len, xfer->tx_buf, xfer->rx_buf, | |
680 | xfer->bits_per_word); | |
681 | ||
682 | /* | |
683 | * Enable RX FIFO Threshold Flag interrupt to be notified about | |
684 | * transfer completion. | |
685 | */ | |
686 | spi_writel(as, IER, SPI_BIT(RXFTHF) | SPI_BIT(OVRES)); | |
687 | } | |
688 | ||
689 | /* | |
690 | * Next transfer using PIO. | |
691 | */ | |
692 | static void atmel_spi_next_xfer_pio(struct spi_master *master, | |
693 | struct spi_transfer *xfer) | |
694 | { | |
695 | struct atmel_spi *as = spi_master_get_devdata(master); | |
696 | ||
697 | if (as->fifo_size) | |
698 | atmel_spi_next_xfer_fifo(master, xfer); | |
699 | else | |
700 | atmel_spi_next_xfer_single(master, xfer); | |
701 | } | |
702 | ||
1ccc404a NF |
703 | /* |
704 | * Submit next transfer for DMA. | |
1ccc404a NF |
705 | */ |
706 | static int atmel_spi_next_xfer_dma_submit(struct spi_master *master, | |
707 | struct spi_transfer *xfer, | |
708 | u32 *plen) | |
b68527df | 709 | __must_hold(&as->lock) |
1ccc404a NF |
710 | { |
711 | struct atmel_spi *as = spi_master_get_devdata(master); | |
768f3d9d NF |
712 | struct dma_chan *rxchan = master->dma_rx; |
713 | struct dma_chan *txchan = master->dma_tx; | |
1ccc404a NF |
714 | struct dma_async_tx_descriptor *rxdesc; |
715 | struct dma_async_tx_descriptor *txdesc; | |
716 | struct dma_slave_config slave_config; | |
717 | dma_cookie_t cookie; | |
1ccc404a NF |
718 | |
719 | dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_dma_submit\n"); | |
720 | ||
721 | /* Check that the channels are available */ | |
722 | if (!rxchan || !txchan) | |
723 | return -ENODEV; | |
724 | ||
725 | /* release lock for DMA operations */ | |
726 | atmel_spi_unlock(as); | |
727 | ||
04242ca4 | 728 | *plen = xfer->len; |
1ccc404a | 729 | |
06515f83 DMT |
730 | if (atmel_spi_dma_slave_config(as, &slave_config, |
731 | xfer->bits_per_word)) | |
1ccc404a NF |
732 | goto err_exit; |
733 | ||
734 | /* Send both scatterlists */ | |
a9889ed6 RP |
735 | if (atmel_spi_is_vmalloc_xfer(xfer) && |
736 | IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) { | |
737 | rxdesc = dmaengine_prep_slave_single(rxchan, | |
738 | as->dma_addr_rx_bbuf, | |
739 | xfer->len, | |
35732576 | 740 | DMA_DEV_TO_MEM, |
a9889ed6 RP |
741 | DMA_PREP_INTERRUPT | |
742 | DMA_CTRL_ACK); | |
743 | } else { | |
744 | rxdesc = dmaengine_prep_slave_sg(rxchan, | |
745 | xfer->rx_sg.sgl, | |
746 | xfer->rx_sg.nents, | |
35732576 | 747 | DMA_DEV_TO_MEM, |
a9889ed6 RP |
748 | DMA_PREP_INTERRUPT | |
749 | DMA_CTRL_ACK); | |
750 | } | |
1ccc404a NF |
751 | if (!rxdesc) |
752 | goto err_dma; | |
753 | ||
a9889ed6 RP |
754 | if (atmel_spi_is_vmalloc_xfer(xfer) && |
755 | IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) { | |
756 | memcpy(as->addr_tx_bbuf, xfer->tx_buf, xfer->len); | |
757 | txdesc = dmaengine_prep_slave_single(txchan, | |
758 | as->dma_addr_tx_bbuf, | |
35732576 | 759 | xfer->len, DMA_MEM_TO_DEV, |
a9889ed6 RP |
760 | DMA_PREP_INTERRUPT | |
761 | DMA_CTRL_ACK); | |
762 | } else { | |
763 | txdesc = dmaengine_prep_slave_sg(txchan, | |
764 | xfer->tx_sg.sgl, | |
765 | xfer->tx_sg.nents, | |
35732576 | 766 | DMA_MEM_TO_DEV, |
a9889ed6 RP |
767 | DMA_PREP_INTERRUPT | |
768 | DMA_CTRL_ACK); | |
769 | } | |
1ccc404a NF |
770 | if (!txdesc) |
771 | goto err_dma; | |
772 | ||
773 | dev_dbg(master->dev.parent, | |
2de024b7 EG |
774 | " start dma xfer %p: len %u tx %p/%08llx rx %p/%08llx\n", |
775 | xfer, xfer->len, xfer->tx_buf, (unsigned long long)xfer->tx_dma, | |
776 | xfer->rx_buf, (unsigned long long)xfer->rx_dma); | |
1ccc404a NF |
777 | |
778 | /* Enable relevant interrupts */ | |
779 | spi_writel(as, IER, SPI_BIT(OVRES)); | |
780 | ||
781 | /* Put the callback on the RX transfer only, that should finish last */ | |
782 | rxdesc->callback = dma_callback; | |
783 | rxdesc->callback_param = master; | |
784 | ||
785 | /* Submit and fire RX and TX with TX last so we're ready to read! */ | |
786 | cookie = rxdesc->tx_submit(rxdesc); | |
787 | if (dma_submit_error(cookie)) | |
788 | goto err_dma; | |
789 | cookie = txdesc->tx_submit(txdesc); | |
790 | if (dma_submit_error(cookie)) | |
791 | goto err_dma; | |
792 | rxchan->device->device_issue_pending(rxchan); | |
793 | txchan->device->device_issue_pending(txchan); | |
794 | ||
795 | /* take back lock */ | |
796 | atmel_spi_lock(as); | |
797 | return 0; | |
798 | ||
799 | err_dma: | |
800 | spi_writel(as, IDR, SPI_BIT(OVRES)); | |
768f3d9d | 801 | atmel_spi_stop_dma(master); |
1ccc404a NF |
802 | err_exit: |
803 | atmel_spi_lock(as); | |
804 | return -ENOMEM; | |
805 | } | |
806 | ||
154443c7 SE |
807 | static void atmel_spi_next_xfer_data(struct spi_master *master, |
808 | struct spi_transfer *xfer, | |
809 | dma_addr_t *tx_dma, | |
810 | dma_addr_t *rx_dma, | |
811 | u32 *plen) | |
812 | { | |
7910d9af NF |
813 | *rx_dma = xfer->rx_dma + xfer->len - *plen; |
814 | *tx_dma = xfer->tx_dma + xfer->len - *plen; | |
04242ca4 CP |
815 | if (*plen > master->max_dma_len) |
816 | *plen = master->max_dma_len; | |
154443c7 SE |
817 | } |
818 | ||
d3b72c7e RG |
819 | static int atmel_spi_set_xfer_speed(struct atmel_spi *as, |
820 | struct spi_device *spi, | |
821 | struct spi_transfer *xfer) | |
822 | { | |
823 | u32 scbr, csr; | |
824 | unsigned long bus_hz; | |
57e31377 GC |
825 | int chip_select; |
826 | ||
827 | if (spi->cs_gpiod) | |
828 | chip_select = as->native_cs_for_gpio; | |
829 | else | |
830 | chip_select = spi->chip_select; | |
d3b72c7e RG |
831 | |
832 | /* v1 chips start out at half the peripheral bus speed. */ | |
39fe33f9 | 833 | bus_hz = as->spi_clk; |
d3b72c7e RG |
834 | if (!atmel_spi_is_v2(as)) |
835 | bus_hz /= 2; | |
836 | ||
837 | /* | |
838 | * Calculate the lowest divider that satisfies the | |
839 | * constraint, assuming div32/fdiv/mbz == 0. | |
840 | */ | |
e8646580 | 841 | scbr = DIV_ROUND_UP(bus_hz, xfer->speed_hz); |
d3b72c7e RG |
842 | |
843 | /* | |
844 | * If the resulting divider doesn't fit into the | |
845 | * register bitfield, we can't satisfy the constraint. | |
846 | */ | |
847 | if (scbr >= (1 << SPI_SCBR_SIZE)) { | |
848 | dev_err(&spi->dev, | |
849 | "setup: %d Hz too slow, scbr %u; min %ld Hz\n", | |
850 | xfer->speed_hz, scbr, bus_hz/255); | |
851 | return -EINVAL; | |
852 | } | |
853 | if (scbr == 0) { | |
854 | dev_err(&spi->dev, | |
855 | "setup: %d Hz too high, scbr %u; max %ld Hz\n", | |
856 | xfer->speed_hz, scbr, bus_hz); | |
857 | return -EINVAL; | |
858 | } | |
57e31377 | 859 | csr = spi_readl(as, CSR0 + 4 * chip_select); |
d3b72c7e | 860 | csr = SPI_BFINS(SCBR, scbr, csr); |
57e31377 | 861 | spi_writel(as, CSR0 + 4 * chip_select, csr); |
d3b72c7e RG |
862 | |
863 | return 0; | |
864 | } | |
865 | ||
754ce4f2 | 866 | /* |
1ccc404a | 867 | * Submit next transfer for PDC. |
754ce4f2 HS |
868 | * lock is held, spi irq is blocked |
869 | */ | |
1ccc404a | 870 | static void atmel_spi_pdc_next_xfer(struct spi_master *master, |
8090d6d1 WY |
871 | struct spi_message *msg, |
872 | struct spi_transfer *xfer) | |
754ce4f2 HS |
873 | { |
874 | struct atmel_spi *as = spi_master_get_devdata(master); | |
8090d6d1 | 875 | u32 len; |
754ce4f2 HS |
876 | dma_addr_t tx_dma, rx_dma; |
877 | ||
8090d6d1 | 878 | spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); |
754ce4f2 | 879 | |
8090d6d1 WY |
880 | len = as->current_remaining_bytes; |
881 | atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len); | |
882 | as->current_remaining_bytes -= len; | |
754ce4f2 | 883 | |
8090d6d1 WY |
884 | spi_writel(as, RPR, rx_dma); |
885 | spi_writel(as, TPR, tx_dma); | |
754ce4f2 | 886 | |
8090d6d1 WY |
887 | if (msg->spi->bits_per_word > 8) |
888 | len >>= 1; | |
889 | spi_writel(as, RCR, len); | |
890 | spi_writel(as, TCR, len); | |
754ce4f2 | 891 | |
8090d6d1 WY |
892 | dev_dbg(&msg->spi->dev, |
893 | " start xfer %p: len %u tx %p/%08llx rx %p/%08llx\n", | |
894 | xfer, xfer->len, xfer->tx_buf, | |
895 | (unsigned long long)xfer->tx_dma, xfer->rx_buf, | |
896 | (unsigned long long)xfer->rx_dma); | |
dc329442 | 897 | |
8090d6d1 WY |
898 | if (as->current_remaining_bytes) { |
899 | len = as->current_remaining_bytes; | |
154443c7 | 900 | atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len); |
8090d6d1 | 901 | as->current_remaining_bytes -= len; |
754ce4f2 | 902 | |
154443c7 SE |
903 | spi_writel(as, RNPR, rx_dma); |
904 | spi_writel(as, TNPR, tx_dma); | |
754ce4f2 | 905 | |
154443c7 SE |
906 | if (msg->spi->bits_per_word > 8) |
907 | len >>= 1; | |
908 | spi_writel(as, RNCR, len); | |
909 | spi_writel(as, TNCR, len); | |
8bacb219 HS |
910 | |
911 | dev_dbg(&msg->spi->dev, | |
2de024b7 EG |
912 | " next xfer %p: len %u tx %p/%08llx rx %p/%08llx\n", |
913 | xfer, xfer->len, xfer->tx_buf, | |
914 | (unsigned long long)xfer->tx_dma, xfer->rx_buf, | |
915 | (unsigned long long)xfer->rx_dma); | |
154443c7 SE |
916 | } |
917 | ||
76e1d14b | 918 | /* REVISIT: We're waiting for RXBUFF before we start the next |
754ce4f2 | 919 | * transfer because we need to handle some difficult timing |
76e1d14b TF |
920 | * issues otherwise. If we wait for TXBUFE in one transfer and |
921 | * then starts waiting for RXBUFF in the next, it's difficult | |
922 | * to tell the difference between the RXBUFF interrupt we're | |
923 | * actually waiting for and the RXBUFF interrupt of the | |
754ce4f2 HS |
924 | * previous transfer. |
925 | * | |
926 | * It should be doable, though. Just not now... | |
927 | */ | |
76e1d14b | 928 | spi_writel(as, IER, SPI_BIT(RXBUFF) | SPI_BIT(OVRES)); |
754ce4f2 HS |
929 | spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN)); |
930 | } | |
931 | ||
8da0859a DB |
932 | /* |
933 | * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma: | |
934 | * - The buffer is either valid for CPU access, else NULL | |
b595076a | 935 | * - If the buffer is valid, so is its DMA address |
8da0859a | 936 | * |
b595076a | 937 | * This driver manages the dma address unless message->is_dma_mapped. |
8da0859a DB |
938 | */ |
939 | static int | |
754ce4f2 HS |
940 | atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer) |
941 | { | |
8da0859a DB |
942 | struct device *dev = &as->pdev->dev; |
943 | ||
754ce4f2 | 944 | xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS; |
8da0859a | 945 | if (xfer->tx_buf) { |
214b574a JCPV |
946 | /* tx_buf is a const void* where we need a void * for the dma |
947 | * mapping */ | |
948 | void *nonconst_tx = (void *)xfer->tx_buf; | |
949 | ||
8da0859a | 950 | xfer->tx_dma = dma_map_single(dev, |
214b574a | 951 | nonconst_tx, xfer->len, |
754ce4f2 | 952 | DMA_TO_DEVICE); |
8d8bb39b | 953 | if (dma_mapping_error(dev, xfer->tx_dma)) |
8da0859a DB |
954 | return -ENOMEM; |
955 | } | |
956 | if (xfer->rx_buf) { | |
957 | xfer->rx_dma = dma_map_single(dev, | |
754ce4f2 HS |
958 | xfer->rx_buf, xfer->len, |
959 | DMA_FROM_DEVICE); | |
8d8bb39b | 960 | if (dma_mapping_error(dev, xfer->rx_dma)) { |
8da0859a DB |
961 | if (xfer->tx_buf) |
962 | dma_unmap_single(dev, | |
963 | xfer->tx_dma, xfer->len, | |
964 | DMA_TO_DEVICE); | |
965 | return -ENOMEM; | |
966 | } | |
967 | } | |
968 | return 0; | |
754ce4f2 HS |
969 | } |
970 | ||
971 | static void atmel_spi_dma_unmap_xfer(struct spi_master *master, | |
972 | struct spi_transfer *xfer) | |
973 | { | |
974 | if (xfer->tx_dma != INVALID_DMA_ADDRESS) | |
49dce689 | 975 | dma_unmap_single(master->dev.parent, xfer->tx_dma, |
754ce4f2 HS |
976 | xfer->len, DMA_TO_DEVICE); |
977 | if (xfer->rx_dma != INVALID_DMA_ADDRESS) | |
49dce689 | 978 | dma_unmap_single(master->dev.parent, xfer->rx_dma, |
754ce4f2 HS |
979 | xfer->len, DMA_FROM_DEVICE); |
980 | } | |
981 | ||
1ccc404a NF |
982 | static void atmel_spi_disable_pdc_transfer(struct atmel_spi *as) |
983 | { | |
984 | spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); | |
985 | } | |
986 | ||
1ccc404a | 987 | static void |
11f2764f | 988 | atmel_spi_pump_single_data(struct atmel_spi *as, struct spi_transfer *xfer) |
1ccc404a | 989 | { |
1ccc404a | 990 | u8 *rxp; |
f557c98b | 991 | u16 *rxp16; |
1ccc404a NF |
992 | unsigned long xfer_pos = xfer->len - as->current_remaining_bytes; |
993 | ||
7910d9af NF |
994 | if (xfer->bits_per_word > 8) { |
995 | rxp16 = (u16 *)(((u8 *)xfer->rx_buf) + xfer_pos); | |
996 | *rxp16 = spi_readl(as, RDR); | |
1ccc404a | 997 | } else { |
7910d9af NF |
998 | rxp = ((u8 *)xfer->rx_buf) + xfer_pos; |
999 | *rxp = spi_readl(as, RDR); | |
1ccc404a | 1000 | } |
f557c98b | 1001 | if (xfer->bits_per_word > 8) { |
b112f058 AB |
1002 | if (as->current_remaining_bytes > 2) |
1003 | as->current_remaining_bytes -= 2; | |
1004 | else | |
f557c98b RG |
1005 | as->current_remaining_bytes = 0; |
1006 | } else { | |
1007 | as->current_remaining_bytes--; | |
1008 | } | |
1ccc404a NF |
1009 | } |
1010 | ||
11f2764f CP |
1011 | static void |
1012 | atmel_spi_pump_fifo_data(struct atmel_spi *as, struct spi_transfer *xfer) | |
1013 | { | |
1014 | u32 fifolr = spi_readl(as, FLR); | |
1015 | u32 num_bytes, num_data = SPI_BFEXT(RXFL, fifolr); | |
1016 | u32 offset = xfer->len - as->current_remaining_bytes; | |
1017 | u16 *words = (u16 *)((u8 *)xfer->rx_buf + offset); | |
1018 | u8 *bytes = (u8 *)((u8 *)xfer->rx_buf + offset); | |
1019 | u16 rd; /* RD field is the lowest 16 bits of RDR */ | |
1020 | ||
1021 | /* Update the number of remaining bytes to transfer */ | |
1022 | num_bytes = ((xfer->bits_per_word > 8) ? | |
1023 | (num_data << 1) : | |
1024 | num_data); | |
1025 | ||
1026 | if (as->current_remaining_bytes > num_bytes) | |
1027 | as->current_remaining_bytes -= num_bytes; | |
1028 | else | |
1029 | as->current_remaining_bytes = 0; | |
1030 | ||
1031 | /* Handle odd number of bytes when data are more than 8bit width */ | |
1032 | if (xfer->bits_per_word > 8) | |
1033 | as->current_remaining_bytes &= ~0x1; | |
1034 | ||
1035 | /* Read data */ | |
1036 | while (num_data) { | |
1037 | rd = spi_readl(as, RDR); | |
7910d9af NF |
1038 | if (xfer->bits_per_word > 8) |
1039 | *words++ = rd; | |
1040 | else | |
1041 | *bytes++ = rd; | |
11f2764f CP |
1042 | num_data--; |
1043 | } | |
1044 | } | |
1045 | ||
1046 | /* Called from IRQ | |
1047 | * | |
1048 | * Must update "current_remaining_bytes" to keep track of data | |
1049 | * to transfer. | |
1050 | */ | |
1051 | static void | |
1052 | atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer) | |
1053 | { | |
1054 | if (as->fifo_size) | |
1055 | atmel_spi_pump_fifo_data(as, xfer); | |
1056 | else | |
1057 | atmel_spi_pump_single_data(as, xfer); | |
1058 | } | |
1059 | ||
1ccc404a NF |
1060 | /* Interrupt |
1061 | * | |
1062 | * No need for locking in this Interrupt handler: done_status is the | |
8090d6d1 | 1063 | * only information modified. |
1ccc404a NF |
1064 | */ |
1065 | static irqreturn_t | |
1066 | atmel_spi_pio_interrupt(int irq, void *dev_id) | |
1067 | { | |
1068 | struct spi_master *master = dev_id; | |
1069 | struct atmel_spi *as = spi_master_get_devdata(master); | |
1070 | u32 status, pending, imr; | |
1071 | struct spi_transfer *xfer; | |
1072 | int ret = IRQ_NONE; | |
1073 | ||
1074 | imr = spi_readl(as, IMR); | |
1075 | status = spi_readl(as, SR); | |
1076 | pending = status & imr; | |
1077 | ||
1078 | if (pending & SPI_BIT(OVRES)) { | |
1079 | ret = IRQ_HANDLED; | |
1080 | spi_writel(as, IDR, SPI_BIT(OVRES)); | |
1081 | dev_warn(master->dev.parent, "overrun\n"); | |
1082 | ||
1083 | /* | |
1084 | * When we get an overrun, we disregard the current | |
1085 | * transfer. Data will not be copied back from any | |
1086 | * bounce buffer and msg->actual_len will not be | |
1087 | * updated with the last xfer. | |
1088 | * | |
1089 | * We will also not process any remaning transfers in | |
1090 | * the message. | |
1ccc404a NF |
1091 | */ |
1092 | as->done_status = -EIO; | |
1093 | smp_wmb(); | |
1094 | ||
1095 | /* Clear any overrun happening while cleaning up */ | |
1096 | spi_readl(as, SR); | |
1097 | ||
8090d6d1 | 1098 | complete(&as->xfer_completion); |
1ccc404a | 1099 | |
11f2764f | 1100 | } else if (pending & (SPI_BIT(RDRF) | SPI_BIT(RXFTHF))) { |
1ccc404a NF |
1101 | atmel_spi_lock(as); |
1102 | ||
1103 | if (as->current_remaining_bytes) { | |
1104 | ret = IRQ_HANDLED; | |
1105 | xfer = as->current_transfer; | |
1106 | atmel_spi_pump_pio_data(as, xfer); | |
8090d6d1 | 1107 | if (!as->current_remaining_bytes) |
1ccc404a | 1108 | spi_writel(as, IDR, pending); |
8090d6d1 WY |
1109 | |
1110 | complete(&as->xfer_completion); | |
1ccc404a NF |
1111 | } |
1112 | ||
1113 | atmel_spi_unlock(as); | |
1114 | } else { | |
1115 | WARN_ONCE(pending, "IRQ not handled, pending = %x\n", pending); | |
1116 | ret = IRQ_HANDLED; | |
1117 | spi_writel(as, IDR, pending); | |
1118 | } | |
1119 | ||
1120 | return ret; | |
754ce4f2 HS |
1121 | } |
1122 | ||
1123 | static irqreturn_t | |
1ccc404a | 1124 | atmel_spi_pdc_interrupt(int irq, void *dev_id) |
754ce4f2 HS |
1125 | { |
1126 | struct spi_master *master = dev_id; | |
1127 | struct atmel_spi *as = spi_master_get_devdata(master); | |
754ce4f2 HS |
1128 | u32 status, pending, imr; |
1129 | int ret = IRQ_NONE; | |
1130 | ||
754ce4f2 HS |
1131 | imr = spi_readl(as, IMR); |
1132 | status = spi_readl(as, SR); | |
1133 | pending = status & imr; | |
1134 | ||
1135 | if (pending & SPI_BIT(OVRES)) { | |
754ce4f2 HS |
1136 | |
1137 | ret = IRQ_HANDLED; | |
1138 | ||
dc329442 | 1139 | spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX) |
754ce4f2 HS |
1140 | | SPI_BIT(OVRES))); |
1141 | ||
754ce4f2 HS |
1142 | /* Clear any overrun happening while cleaning up */ |
1143 | spi_readl(as, SR); | |
1144 | ||
823cd045 | 1145 | as->done_status = -EIO; |
8090d6d1 WY |
1146 | |
1147 | complete(&as->xfer_completion); | |
1148 | ||
dc329442 | 1149 | } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) { |
754ce4f2 HS |
1150 | ret = IRQ_HANDLED; |
1151 | ||
1152 | spi_writel(as, IDR, pending); | |
1153 | ||
8090d6d1 | 1154 | complete(&as->xfer_completion); |
754ce4f2 HS |
1155 | } |
1156 | ||
754ce4f2 HS |
1157 | return ret; |
1158 | } | |
1159 | ||
6c613f68 AA |
1160 | static int atmel_word_delay_csr(struct spi_device *spi, struct atmel_spi *as) |
1161 | { | |
1162 | struct spi_delay *delay = &spi->word_delay; | |
1163 | u32 value = delay->value; | |
1164 | ||
1165 | switch (delay->unit) { | |
1166 | case SPI_DELAY_UNIT_NSECS: | |
1167 | value /= 1000; | |
1168 | break; | |
1169 | case SPI_DELAY_UNIT_USECS: | |
1170 | break; | |
1171 | default: | |
1172 | return -EINVAL; | |
1173 | } | |
1174 | ||
1175 | return (as->spi_clk / 1000000 * value) >> 5; | |
1176 | } | |
1177 | ||
57e31377 GC |
1178 | static void initialize_native_cs_for_gpio(struct atmel_spi *as) |
1179 | { | |
1180 | int i; | |
1181 | struct spi_master *master = platform_get_drvdata(as->pdev); | |
1182 | ||
1183 | if (!as->native_cs_free) | |
1184 | return; /* already initialized */ | |
1185 | ||
1186 | if (!master->cs_gpiods) | |
1187 | return; /* No CS GPIO */ | |
1188 | ||
9c86f12a GC |
1189 | /* |
1190 | * On the first version of the controller (AT91RM9200), CS0 | |
1191 | * can't be used associated with GPIO | |
1192 | */ | |
1193 | if (atmel_spi_is_v2(as)) | |
1194 | i = 0; | |
1195 | else | |
1196 | i = 1; | |
1197 | ||
1198 | for (; i < 4; i++) | |
57e31377 GC |
1199 | if (master->cs_gpiods[i]) |
1200 | as->native_cs_free |= BIT(i); | |
1201 | ||
1202 | if (as->native_cs_free) | |
1203 | as->native_cs_for_gpio = ffs(as->native_cs_free); | |
1204 | } | |
1205 | ||
754ce4f2 HS |
1206 | static int atmel_spi_setup(struct spi_device *spi) |
1207 | { | |
1208 | struct atmel_spi *as; | |
5ee36c98 | 1209 | struct atmel_spi_device *asd; |
d3b72c7e | 1210 | u32 csr; |
754ce4f2 | 1211 | unsigned int bits = spi->bits_per_word; |
57e31377 | 1212 | int chip_select; |
6c613f68 | 1213 | int word_delay_csr; |
754ce4f2 HS |
1214 | |
1215 | as = spi_master_get_devdata(spi->master); | |
1216 | ||
defbd3b4 | 1217 | /* see notes above re chipselect */ |
585d18f7 | 1218 | if (!spi->cs_gpiod && (spi->mode & SPI_CS_HIGH)) { |
7cbb16b2 | 1219 | dev_warn(&spi->dev, "setup: non GPIO CS can't be active-high\n"); |
defbd3b4 DB |
1220 | return -EINVAL; |
1221 | } | |
1222 | ||
57e31377 GC |
1223 | /* Setup() is called during spi_register_controller(aka |
1224 | * spi_register_master) but after all membmers of the cs_gpiod | |
1225 | * array have been filled, so we can looked for which native | |
1226 | * CS will be free for using with GPIO | |
1227 | */ | |
1228 | initialize_native_cs_for_gpio(as); | |
1229 | ||
1230 | if (spi->cs_gpiod && as->native_cs_free) { | |
1231 | dev_err(&spi->dev, | |
1232 | "No native CS available to support this GPIO CS\n"); | |
1233 | return -EBUSY; | |
1234 | } | |
1235 | ||
1236 | if (spi->cs_gpiod) | |
1237 | chip_select = as->native_cs_for_gpio; | |
1238 | else | |
1239 | chip_select = spi->chip_select; | |
1240 | ||
d3b72c7e | 1241 | csr = SPI_BF(BITS, bits - 8); |
754ce4f2 HS |
1242 | if (spi->mode & SPI_CPOL) |
1243 | csr |= SPI_BIT(CPOL); | |
1244 | if (!(spi->mode & SPI_CPHA)) | |
1245 | csr |= SPI_BIT(NCPHA); | |
1246 | ||
585d18f7 GC |
1247 | if (!spi->cs_gpiod) |
1248 | csr |= SPI_BIT(CSAAT); | |
1eed29df | 1249 | csr |= SPI_BF(DLYBS, 0); |
473a78a7 | 1250 | |
6c613f68 AA |
1251 | word_delay_csr = atmel_word_delay_csr(spi, as); |
1252 | if (word_delay_csr < 0) | |
1253 | return word_delay_csr; | |
1254 | ||
473a78a7 JB |
1255 | /* DLYBCT adds delays between words. This is useful for slow devices |
1256 | * that need a bit of time to setup the next transfer. | |
1257 | */ | |
6c613f68 | 1258 | csr |= SPI_BF(DLYBCT, word_delay_csr); |
754ce4f2 | 1259 | |
5ee36c98 HS |
1260 | asd = spi->controller_state; |
1261 | if (!asd) { | |
1262 | asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL); | |
1263 | if (!asd) | |
1264 | return -ENOMEM; | |
1265 | ||
5ee36c98 | 1266 | spi->controller_state = asd; |
754ce4f2 HS |
1267 | } |
1268 | ||
5ee36c98 HS |
1269 | asd->csr = csr; |
1270 | ||
754ce4f2 | 1271 | dev_dbg(&spi->dev, |
d3b72c7e RG |
1272 | "setup: bpw %u mode 0x%x -> csr%d %08x\n", |
1273 | bits, spi->mode, spi->chip_select, csr); | |
754ce4f2 | 1274 | |
d4820b74 | 1275 | if (!atmel_spi_is_v2(as)) |
57e31377 | 1276 | spi_writel(as, CSR0 + 4 * chip_select, csr); |
754ce4f2 HS |
1277 | |
1278 | return 0; | |
1279 | } | |
1280 | ||
8090d6d1 WY |
1281 | static int atmel_spi_one_transfer(struct spi_master *master, |
1282 | struct spi_message *msg, | |
1283 | struct spi_transfer *xfer) | |
754ce4f2 HS |
1284 | { |
1285 | struct atmel_spi *as; | |
8090d6d1 | 1286 | struct spi_device *spi = msg->spi; |
b9d228f9 | 1287 | u8 bits; |
8090d6d1 | 1288 | u32 len; |
b9d228f9 | 1289 | struct atmel_spi_device *asd; |
8090d6d1 WY |
1290 | int timeout; |
1291 | int ret; | |
1369dea6 | 1292 | unsigned long dma_timeout; |
754ce4f2 | 1293 | |
8090d6d1 | 1294 | as = spi_master_get_devdata(master); |
754ce4f2 | 1295 | |
8090d6d1 WY |
1296 | if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) { |
1297 | dev_dbg(&spi->dev, "missing rx or tx buf\n"); | |
754ce4f2 | 1298 | return -EINVAL; |
8090d6d1 | 1299 | } |
754ce4f2 | 1300 | |
e8646580 JN |
1301 | asd = spi->controller_state; |
1302 | bits = (asd->csr >> 4) & 0xf; | |
1303 | if (bits != xfer->bits_per_word - 8) { | |
1304 | dev_dbg(&spi->dev, | |
8090d6d1 | 1305 | "you can't yet change bits_per_word in transfers\n"); |
e8646580 | 1306 | return -ENOPROTOOPT; |
8090d6d1 | 1307 | } |
754ce4f2 | 1308 | |
8090d6d1 WY |
1309 | /* |
1310 | * DMA map early, for performance (empties dcache ASAP) and | |
1311 | * better fault reporting. | |
1312 | */ | |
1313 | if ((!msg->is_dma_mapped) | |
04242ca4 | 1314 | && as->use_pdc) { |
8090d6d1 WY |
1315 | if (atmel_spi_dma_map_xfer(as, xfer) < 0) |
1316 | return -ENOMEM; | |
1317 | } | |
1318 | ||
1319 | atmel_spi_set_xfer_speed(as, msg->spi, xfer); | |
754ce4f2 | 1320 | |
8090d6d1 WY |
1321 | as->done_status = 0; |
1322 | as->current_transfer = xfer; | |
1323 | as->current_remaining_bytes = xfer->len; | |
1324 | while (as->current_remaining_bytes) { | |
1325 | reinit_completion(&as->xfer_completion); | |
1326 | ||
1327 | if (as->use_pdc) { | |
1328 | atmel_spi_pdc_next_xfer(master, msg, xfer); | |
1329 | } else if (atmel_spi_use_dma(as, xfer)) { | |
1330 | len = as->current_remaining_bytes; | |
1331 | ret = atmel_spi_next_xfer_dma_submit(master, | |
1332 | xfer, &len); | |
1333 | if (ret) { | |
1334 | dev_err(&spi->dev, | |
1335 | "unable to use DMA, fallback to PIO\n"); | |
1336 | atmel_spi_next_xfer_pio(master, xfer); | |
1337 | } else { | |
1338 | as->current_remaining_bytes -= len; | |
0c3b9748 AL |
1339 | if (as->current_remaining_bytes < 0) |
1340 | as->current_remaining_bytes = 0; | |
b9d228f9 | 1341 | } |
8090d6d1 WY |
1342 | } else { |
1343 | atmel_spi_next_xfer_pio(master, xfer); | |
b9d228f9 MB |
1344 | } |
1345 | ||
1676014e AS |
1346 | /* interrupts are disabled, so free the lock for schedule */ |
1347 | atmel_spi_unlock(as); | |
1369dea6 NMG |
1348 | dma_timeout = wait_for_completion_timeout(&as->xfer_completion, |
1349 | SPI_DMA_TIMEOUT); | |
1676014e | 1350 | atmel_spi_lock(as); |
1369dea6 NMG |
1351 | if (WARN_ON(dma_timeout == 0)) { |
1352 | dev_err(&spi->dev, "spi transfer timeout\n"); | |
8090d6d1 | 1353 | as->done_status = -EIO; |
f557c98b RG |
1354 | } |
1355 | ||
8090d6d1 WY |
1356 | if (as->done_status) |
1357 | break; | |
1358 | } | |
1359 | ||
1360 | if (as->done_status) { | |
1361 | if (as->use_pdc) { | |
1362 | dev_warn(master->dev.parent, | |
1363 | "overrun (%u/%u remaining)\n", | |
1364 | spi_readl(as, TCR), spi_readl(as, RCR)); | |
1365 | ||
1366 | /* | |
1367 | * Clean up DMA registers and make sure the data | |
1368 | * registers are empty. | |
1369 | */ | |
1370 | spi_writel(as, RNCR, 0); | |
1371 | spi_writel(as, TNCR, 0); | |
1372 | spi_writel(as, RCR, 0); | |
1373 | spi_writel(as, TCR, 0); | |
1374 | for (timeout = 1000; timeout; timeout--) | |
1375 | if (spi_readl(as, SR) & SPI_BIT(TXEMPTY)) | |
1376 | break; | |
1377 | if (!timeout) | |
1378 | dev_warn(master->dev.parent, | |
1379 | "timeout waiting for TXEMPTY"); | |
1380 | while (spi_readl(as, SR) & SPI_BIT(RDRF)) | |
1381 | spi_readl(as, RDR); | |
1382 | ||
1383 | /* Clear any overrun happening while cleaning up */ | |
1384 | spi_readl(as, SR); | |
1385 | ||
1386 | } else if (atmel_spi_use_dma(as, xfer)) { | |
768f3d9d | 1387 | atmel_spi_stop_dma(master); |
8090d6d1 WY |
1388 | } |
1389 | ||
1390 | if (!msg->is_dma_mapped | |
04242ca4 | 1391 | && as->use_pdc) |
8090d6d1 WY |
1392 | atmel_spi_dma_unmap_xfer(master, xfer); |
1393 | ||
1394 | return 0; | |
1395 | ||
1396 | } else { | |
1397 | /* only update length if no error */ | |
1398 | msg->actual_length += xfer->len; | |
1399 | } | |
1400 | ||
1401 | if (!msg->is_dma_mapped | |
04242ca4 | 1402 | && as->use_pdc) |
8090d6d1 WY |
1403 | atmel_spi_dma_unmap_xfer(master, xfer); |
1404 | ||
e74dc5c7 | 1405 | spi_transfer_delay_exec(xfer); |
8090d6d1 WY |
1406 | |
1407 | if (xfer->cs_change) { | |
1408 | if (list_is_last(&xfer->transfer_list, | |
1409 | &msg->transfers)) { | |
1410 | as->keep_cs = true; | |
1411 | } else { | |
fed8d8c7 MR |
1412 | cs_deactivate(as, msg->spi); |
1413 | udelay(10); | |
1414 | cs_activate(as, msg->spi); | |
8da0859a | 1415 | } |
754ce4f2 HS |
1416 | } |
1417 | ||
8090d6d1 WY |
1418 | return 0; |
1419 | } | |
1420 | ||
1421 | static int atmel_spi_transfer_one_message(struct spi_master *master, | |
1422 | struct spi_message *msg) | |
1423 | { | |
1424 | struct atmel_spi *as; | |
1425 | struct spi_transfer *xfer; | |
1426 | struct spi_device *spi = msg->spi; | |
1427 | int ret = 0; | |
1428 | ||
1429 | as = spi_master_get_devdata(master); | |
1430 | ||
1431 | dev_dbg(&spi->dev, "new message %p submitted for %s\n", | |
1432 | msg, dev_name(&spi->dev)); | |
1433 | ||
8090d6d1 WY |
1434 | atmel_spi_lock(as); |
1435 | cs_activate(as, spi); | |
1436 | ||
8090d6d1 WY |
1437 | as->keep_cs = false; |
1438 | ||
1439 | msg->status = 0; | |
1440 | msg->actual_length = 0; | |
1441 | ||
1442 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { | |
3c0448d5 UKK |
1443 | trace_spi_transfer_start(msg, xfer); |
1444 | ||
8090d6d1 WY |
1445 | ret = atmel_spi_one_transfer(master, msg, xfer); |
1446 | if (ret) | |
1447 | goto msg_done; | |
3c0448d5 UKK |
1448 | |
1449 | trace_spi_transfer_stop(msg, xfer); | |
8090d6d1 WY |
1450 | } |
1451 | ||
1452 | if (as->use_pdc) | |
1453 | atmel_spi_disable_pdc_transfer(as); | |
1454 | ||
754ce4f2 | 1455 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { |
8090d6d1 | 1456 | dev_dbg(&spi->dev, |
54f4c51c | 1457 | " xfer %p: len %u tx %p/%pad rx %p/%pad\n", |
754ce4f2 | 1458 | xfer, xfer->len, |
54f4c51c RD |
1459 | xfer->tx_buf, &xfer->tx_dma, |
1460 | xfer->rx_buf, &xfer->rx_dma); | |
754ce4f2 HS |
1461 | } |
1462 | ||
8090d6d1 WY |
1463 | msg_done: |
1464 | if (!as->keep_cs) | |
1465 | cs_deactivate(as, msg->spi); | |
754ce4f2 | 1466 | |
8aad7924 | 1467 | atmel_spi_unlock(as); |
754ce4f2 | 1468 | |
8090d6d1 WY |
1469 | msg->status = as->done_status; |
1470 | spi_finalize_current_message(spi->master); | |
1471 | ||
1472 | return ret; | |
754ce4f2 HS |
1473 | } |
1474 | ||
bb2d1c36 | 1475 | static void atmel_spi_cleanup(struct spi_device *spi) |
754ce4f2 | 1476 | { |
5ee36c98 | 1477 | struct atmel_spi_device *asd = spi->controller_state; |
defbd3b4 | 1478 | |
5ee36c98 | 1479 | if (!asd) |
defbd3b4 DB |
1480 | return; |
1481 | ||
5ee36c98 | 1482 | spi->controller_state = NULL; |
5ee36c98 | 1483 | kfree(asd); |
754ce4f2 HS |
1484 | } |
1485 | ||
d4820b74 WY |
1486 | static inline unsigned int atmel_get_version(struct atmel_spi *as) |
1487 | { | |
1488 | return spi_readl(as, VERSION) & 0x00000fff; | |
1489 | } | |
1490 | ||
1491 | static void atmel_get_caps(struct atmel_spi *as) | |
1492 | { | |
1493 | unsigned int version; | |
1494 | ||
1495 | version = atmel_get_version(as); | |
d4820b74 WY |
1496 | |
1497 | as->caps.is_spi2 = version > 0x121; | |
1498 | as->caps.has_wdrbt = version >= 0x210; | |
1499 | as->caps.has_dma_support = version >= 0x212; | |
7094576c | 1500 | as->caps.has_pdc_support = version < 0x212; |
d4820b74 WY |
1501 | } |
1502 | ||
05514c86 QS |
1503 | static void atmel_spi_init(struct atmel_spi *as) |
1504 | { | |
1505 | spi_writel(as, CR, SPI_BIT(SWRST)); | |
1506 | spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ | |
9581329e EH |
1507 | |
1508 | /* It is recommended to enable FIFOs first thing after reset */ | |
1509 | if (as->fifo_size) | |
1510 | spi_writel(as, CR, SPI_BIT(FIFOEN)); | |
1511 | ||
05514c86 QS |
1512 | if (as->caps.has_wdrbt) { |
1513 | spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS) | |
1514 | | SPI_BIT(MSTR)); | |
1515 | } else { | |
1516 | spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS)); | |
1517 | } | |
1518 | ||
1519 | if (as->use_pdc) | |
1520 | spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); | |
1521 | spi_writel(as, CR, SPI_BIT(SPIEN)); | |
05514c86 QS |
1522 | } |
1523 | ||
fd4a319b | 1524 | static int atmel_spi_probe(struct platform_device *pdev) |
754ce4f2 HS |
1525 | { |
1526 | struct resource *regs; | |
1527 | int irq; | |
1528 | struct clk *clk; | |
1529 | int ret; | |
1530 | struct spi_master *master; | |
1531 | struct atmel_spi *as; | |
1532 | ||
5bdfd491 WY |
1533 | /* Select default pin state */ |
1534 | pinctrl_pm_select_default_state(&pdev->dev); | |
1535 | ||
754ce4f2 HS |
1536 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1537 | if (!regs) | |
1538 | return -ENXIO; | |
1539 | ||
1540 | irq = platform_get_irq(pdev, 0); | |
1541 | if (irq < 0) | |
1542 | return irq; | |
1543 | ||
9f87d6f2 | 1544 | clk = devm_clk_get(&pdev->dev, "spi_clk"); |
754ce4f2 HS |
1545 | if (IS_ERR(clk)) |
1546 | return PTR_ERR(clk); | |
1547 | ||
1548 | /* setup spi core then atmel-specific driver state */ | |
1549 | ret = -ENOMEM; | |
a536d765 | 1550 | master = spi_alloc_master(&pdev->dev, sizeof(*as)); |
754ce4f2 HS |
1551 | if (!master) |
1552 | goto out_free; | |
1553 | ||
e7db06b5 | 1554 | /* the spi->mode bits understood by this driver: */ |
efc92fbb | 1555 | master->use_gpio_descriptors = true; |
e7db06b5 | 1556 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; |
24778be2 | 1557 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16); |
850a5b67 | 1558 | master->dev.of_node = pdev->dev.of_node; |
754ce4f2 | 1559 | master->bus_num = pdev->id; |
1cb84b02 | 1560 | master->num_chipselect = 4; |
754ce4f2 | 1561 | master->setup = atmel_spi_setup; |
7910d9af | 1562 | master->flags = (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX); |
8090d6d1 | 1563 | master->transfer_one_message = atmel_spi_transfer_one_message; |
754ce4f2 | 1564 | master->cleanup = atmel_spi_cleanup; |
ce0c4caf | 1565 | master->auto_runtime_pm = true; |
7910d9af | 1566 | master->max_dma_len = SPI_MAX_DMA_XFER; |
04242ca4 | 1567 | master->can_dma = atmel_spi_can_dma; |
754ce4f2 HS |
1568 | platform_set_drvdata(pdev, master); |
1569 | ||
1570 | as = spi_master_get_devdata(master); | |
1571 | ||
754ce4f2 | 1572 | spin_lock_init(&as->lock); |
1ccc404a | 1573 | |
754ce4f2 | 1574 | as->pdev = pdev; |
31407478 | 1575 | as->regs = devm_ioremap_resource(&pdev->dev, regs); |
543c954d WY |
1576 | if (IS_ERR(as->regs)) { |
1577 | ret = PTR_ERR(as->regs); | |
7910d9af | 1578 | goto out_unmap_regs; |
543c954d | 1579 | } |
dfab30ee | 1580 | as->phybase = regs->start; |
754ce4f2 HS |
1581 | as->irq = irq; |
1582 | as->clk = clk; | |
754ce4f2 | 1583 | |
8090d6d1 WY |
1584 | init_completion(&as->xfer_completion); |
1585 | ||
d4820b74 WY |
1586 | atmel_get_caps(as); |
1587 | ||
1ccc404a NF |
1588 | as->use_dma = false; |
1589 | as->use_pdc = false; | |
1590 | if (as->caps.has_dma_support) { | |
768f3d9d | 1591 | ret = atmel_spi_configure_dma(master, as); |
04242ca4 | 1592 | if (ret == 0) { |
1ccc404a | 1593 | as->use_dma = true; |
04242ca4 | 1594 | } else if (ret == -EPROBE_DEFER) { |
5e9af37e | 1595 | return ret; |
04242ca4 | 1596 | } |
7094576c | 1597 | } else if (as->caps.has_pdc_support) { |
1ccc404a NF |
1598 | as->use_pdc = true; |
1599 | } | |
1600 | ||
a9889ed6 RP |
1601 | if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) { |
1602 | as->addr_rx_bbuf = dma_alloc_coherent(&pdev->dev, | |
1603 | SPI_MAX_DMA_XFER, | |
1604 | &as->dma_addr_rx_bbuf, | |
1605 | GFP_KERNEL | GFP_DMA); | |
1606 | if (!as->addr_rx_bbuf) { | |
1607 | as->use_dma = false; | |
1608 | } else { | |
1609 | as->addr_tx_bbuf = dma_alloc_coherent(&pdev->dev, | |
1610 | SPI_MAX_DMA_XFER, | |
1611 | &as->dma_addr_tx_bbuf, | |
1612 | GFP_KERNEL | GFP_DMA); | |
1613 | if (!as->addr_tx_bbuf) { | |
1614 | as->use_dma = false; | |
1615 | dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER, | |
1616 | as->addr_rx_bbuf, | |
1617 | as->dma_addr_rx_bbuf); | |
1618 | } | |
1619 | } | |
1620 | if (!as->use_dma) | |
1621 | dev_info(master->dev.parent, | |
1622 | " can not allocate dma coherent memory\n"); | |
1623 | } | |
1624 | ||
1ccc404a NF |
1625 | if (as->caps.has_dma_support && !as->use_dma) |
1626 | dev_info(&pdev->dev, "Atmel SPI Controller using PIO only\n"); | |
1627 | ||
1628 | if (as->use_pdc) { | |
9f87d6f2 JH |
1629 | ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pdc_interrupt, |
1630 | 0, dev_name(&pdev->dev), master); | |
1ccc404a | 1631 | } else { |
9f87d6f2 JH |
1632 | ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pio_interrupt, |
1633 | 0, dev_name(&pdev->dev), master); | |
1ccc404a | 1634 | } |
754ce4f2 HS |
1635 | if (ret) |
1636 | goto out_unmap_regs; | |
1637 | ||
1638 | /* Initialize the hardware */ | |
dfec4a6e BB |
1639 | ret = clk_prepare_enable(clk); |
1640 | if (ret) | |
de8cc234 | 1641 | goto out_free_irq; |
39fe33f9 BW |
1642 | |
1643 | as->spi_clk = clk_get_rate(clk); | |
1644 | ||
11f2764f CP |
1645 | as->fifo_size = 0; |
1646 | if (!of_property_read_u32(pdev->dev.of_node, "atmel,fifo-size", | |
1647 | &as->fifo_size)) { | |
1648 | dev_info(&pdev->dev, "Using FIFO (%u data)\n", as->fifo_size); | |
11f2764f CP |
1649 | } |
1650 | ||
05514c86 QS |
1651 | atmel_spi_init(as); |
1652 | ||
ce0c4caf WY |
1653 | pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT); |
1654 | pm_runtime_use_autosuspend(&pdev->dev); | |
1655 | pm_runtime_set_active(&pdev->dev); | |
1656 | pm_runtime_enable(&pdev->dev); | |
1657 | ||
9f87d6f2 | 1658 | ret = devm_spi_register_master(&pdev->dev, master); |
754ce4f2 | 1659 | if (ret) |
1ccc404a | 1660 | goto out_free_dma; |
754ce4f2 | 1661 | |
ce24a513 | 1662 | /* go! */ |
6aba9c65 BS |
1663 | dev_info(&pdev->dev, "Atmel SPI Controller version 0x%x at 0x%08lx (irq %d)\n", |
1664 | atmel_get_version(as), (unsigned long)regs->start, | |
1665 | irq); | |
ce24a513 | 1666 | |
754ce4f2 HS |
1667 | return 0; |
1668 | ||
1ccc404a | 1669 | out_free_dma: |
ce0c4caf WY |
1670 | pm_runtime_disable(&pdev->dev); |
1671 | pm_runtime_set_suspended(&pdev->dev); | |
1672 | ||
1ccc404a | 1673 | if (as->use_dma) |
768f3d9d | 1674 | atmel_spi_release_dma(master); |
1ccc404a | 1675 | |
754ce4f2 | 1676 | spi_writel(as, CR, SPI_BIT(SWRST)); |
50d7d5bf | 1677 | spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ |
dfec4a6e | 1678 | clk_disable_unprepare(clk); |
de8cc234 | 1679 | out_free_irq: |
754ce4f2 | 1680 | out_unmap_regs: |
754ce4f2 | 1681 | out_free: |
754ce4f2 HS |
1682 | spi_master_put(master); |
1683 | return ret; | |
1684 | } | |
1685 | ||
fd4a319b | 1686 | static int atmel_spi_remove(struct platform_device *pdev) |
754ce4f2 HS |
1687 | { |
1688 | struct spi_master *master = platform_get_drvdata(pdev); | |
1689 | struct atmel_spi *as = spi_master_get_devdata(master); | |
754ce4f2 | 1690 | |
ce0c4caf WY |
1691 | pm_runtime_get_sync(&pdev->dev); |
1692 | ||
754ce4f2 | 1693 | /* reset the hardware and block queue progress */ |
1ccc404a | 1694 | if (as->use_dma) { |
768f3d9d NF |
1695 | atmel_spi_stop_dma(master); |
1696 | atmel_spi_release_dma(master); | |
a9889ed6 RP |
1697 | if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) { |
1698 | dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER, | |
1699 | as->addr_tx_bbuf, | |
1700 | as->dma_addr_tx_bbuf); | |
1701 | dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER, | |
1702 | as->addr_rx_bbuf, | |
1703 | as->dma_addr_rx_bbuf); | |
1704 | } | |
1ccc404a NF |
1705 | } |
1706 | ||
66e900a3 | 1707 | spin_lock_irq(&as->lock); |
754ce4f2 | 1708 | spi_writel(as, CR, SPI_BIT(SWRST)); |
50d7d5bf | 1709 | spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ |
754ce4f2 HS |
1710 | spi_readl(as, SR); |
1711 | spin_unlock_irq(&as->lock); | |
1712 | ||
dfec4a6e | 1713 | clk_disable_unprepare(as->clk); |
754ce4f2 | 1714 | |
ce0c4caf WY |
1715 | pm_runtime_put_noidle(&pdev->dev); |
1716 | pm_runtime_disable(&pdev->dev); | |
1717 | ||
754ce4f2 HS |
1718 | return 0; |
1719 | } | |
1720 | ||
ce0c4caf | 1721 | #ifdef CONFIG_PM |
c1ee8f3f WY |
1722 | static int atmel_spi_runtime_suspend(struct device *dev) |
1723 | { | |
1724 | struct spi_master *master = dev_get_drvdata(dev); | |
1725 | struct atmel_spi *as = spi_master_get_devdata(master); | |
1726 | ||
1727 | clk_disable_unprepare(as->clk); | |
1728 | pinctrl_pm_select_sleep_state(dev); | |
1729 | ||
1730 | return 0; | |
1731 | } | |
1732 | ||
1733 | static int atmel_spi_runtime_resume(struct device *dev) | |
1734 | { | |
1735 | struct spi_master *master = dev_get_drvdata(dev); | |
1736 | struct atmel_spi *as = spi_master_get_devdata(master); | |
1737 | ||
1738 | pinctrl_pm_select_default_state(dev); | |
1739 | ||
1740 | return clk_prepare_enable(as->clk); | |
1741 | } | |
1742 | ||
d630526d | 1743 | #ifdef CONFIG_PM_SLEEP |
ec60dd37 | 1744 | static int atmel_spi_suspend(struct device *dev) |
754ce4f2 | 1745 | { |
c1ee8f3f | 1746 | struct spi_master *master = dev_get_drvdata(dev); |
ba938f3a WY |
1747 | int ret; |
1748 | ||
1749 | /* Stop the queue running */ | |
1750 | ret = spi_master_suspend(master); | |
7c5d8a24 | 1751 | if (ret) |
ba938f3a | 1752 | return ret; |
754ce4f2 | 1753 | |
c1ee8f3f WY |
1754 | if (!pm_runtime_suspended(dev)) |
1755 | atmel_spi_runtime_suspend(dev); | |
5bdfd491 | 1756 | |
754ce4f2 HS |
1757 | return 0; |
1758 | } | |
1759 | ||
ec60dd37 | 1760 | static int atmel_spi_resume(struct device *dev) |
754ce4f2 | 1761 | { |
c1ee8f3f | 1762 | struct spi_master *master = dev_get_drvdata(dev); |
e5380078 | 1763 | struct atmel_spi *as = spi_master_get_devdata(master); |
ba938f3a | 1764 | int ret; |
754ce4f2 | 1765 | |
e5380078 QS |
1766 | ret = clk_prepare_enable(as->clk); |
1767 | if (ret) | |
1768 | return ret; | |
1769 | ||
1770 | atmel_spi_init(as); | |
1771 | ||
1772 | clk_disable_unprepare(as->clk); | |
1773 | ||
ce0c4caf | 1774 | if (!pm_runtime_suspended(dev)) { |
c1ee8f3f | 1775 | ret = atmel_spi_runtime_resume(dev); |
ce0c4caf WY |
1776 | if (ret) |
1777 | return ret; | |
1778 | } | |
ba938f3a WY |
1779 | |
1780 | /* Start the queue running */ | |
7c5d8a24 | 1781 | return spi_master_resume(master); |
754ce4f2 | 1782 | } |
d630526d | 1783 | #endif |
ce0c4caf WY |
1784 | |
1785 | static const struct dev_pm_ops atmel_spi_pm_ops = { | |
1786 | SET_SYSTEM_SLEEP_PM_OPS(atmel_spi_suspend, atmel_spi_resume) | |
1787 | SET_RUNTIME_PM_OPS(atmel_spi_runtime_suspend, | |
1788 | atmel_spi_runtime_resume, NULL) | |
1789 | }; | |
ec60dd37 | 1790 | #define ATMEL_SPI_PM_OPS (&atmel_spi_pm_ops) |
754ce4f2 | 1791 | #else |
ec60dd37 | 1792 | #define ATMEL_SPI_PM_OPS NULL |
754ce4f2 HS |
1793 | #endif |
1794 | ||
850a5b67 JCPV |
1795 | static const struct of_device_id atmel_spi_dt_ids[] = { |
1796 | { .compatible = "atmel,at91rm9200-spi" }, | |
1797 | { /* sentinel */ } | |
1798 | }; | |
1799 | ||
1800 | MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids); | |
754ce4f2 HS |
1801 | |
1802 | static struct platform_driver atmel_spi_driver = { | |
1803 | .driver = { | |
1804 | .name = "atmel_spi", | |
ec60dd37 | 1805 | .pm = ATMEL_SPI_PM_OPS, |
1cb84b02 | 1806 | .of_match_table = atmel_spi_dt_ids, |
754ce4f2 | 1807 | }, |
1cb201af | 1808 | .probe = atmel_spi_probe, |
2deff8d6 | 1809 | .remove = atmel_spi_remove, |
754ce4f2 | 1810 | }; |
940ab889 | 1811 | module_platform_driver(atmel_spi_driver); |
754ce4f2 HS |
1812 | |
1813 | MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver"); | |
e05503ef | 1814 | MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); |
754ce4f2 | 1815 | MODULE_LICENSE("GPL"); |
7e38c3c4 | 1816 | MODULE_ALIAS("platform:atmel_spi"); |