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c942fddf | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
f8043872 CB |
2 | /* |
3 | * Driver for Broadcom BCM2835 SPI Controllers | |
4 | * | |
5 | * Copyright (C) 2012 Chris Boot | |
6 | * Copyright (C) 2013 Stephen Warren | |
e34ff011 | 7 | * Copyright (C) 2015 Martin Sperl |
f8043872 CB |
8 | * |
9 | * This driver is inspired by: | |
10 | * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org> | |
11 | * spi-atmel.c, Copyright (C) 2006 Atmel Corporation | |
f8043872 CB |
12 | */ |
13 | ||
14 | #include <linux/clk.h> | |
15 | #include <linux/completion.h> | |
154f7da5 | 16 | #include <linux/debugfs.h> |
f8043872 | 17 | #include <linux/delay.h> |
3ecd37ed MS |
18 | #include <linux/dma-mapping.h> |
19 | #include <linux/dmaengine.h> | |
f8043872 CB |
20 | #include <linux/err.h> |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/io.h> | |
23 | #include <linux/kernel.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/of.h> | |
3ecd37ed | 26 | #include <linux/of_address.h> |
f8043872 | 27 | #include <linux/of_device.h> |
3bd158c5 LW |
28 | #include <linux/gpio/consumer.h> |
29 | #include <linux/gpio/machine.h> /* FIXME: using chip internals */ | |
30 | #include <linux/gpio/driver.h> /* FIXME: using chip internals */ | |
3ecd37ed | 31 | #include <linux/of_irq.h> |
f8043872 CB |
32 | #include <linux/spi/spi.h> |
33 | ||
34 | /* SPI register offsets */ | |
35 | #define BCM2835_SPI_CS 0x00 | |
36 | #define BCM2835_SPI_FIFO 0x04 | |
37 | #define BCM2835_SPI_CLK 0x08 | |
38 | #define BCM2835_SPI_DLEN 0x0c | |
39 | #define BCM2835_SPI_LTOH 0x10 | |
40 | #define BCM2835_SPI_DC 0x14 | |
41 | ||
42 | /* Bitfields in CS */ | |
43 | #define BCM2835_SPI_CS_LEN_LONG 0x02000000 | |
44 | #define BCM2835_SPI_CS_DMA_LEN 0x01000000 | |
45 | #define BCM2835_SPI_CS_CSPOL2 0x00800000 | |
46 | #define BCM2835_SPI_CS_CSPOL1 0x00400000 | |
47 | #define BCM2835_SPI_CS_CSPOL0 0x00200000 | |
48 | #define BCM2835_SPI_CS_RXF 0x00100000 | |
49 | #define BCM2835_SPI_CS_RXR 0x00080000 | |
50 | #define BCM2835_SPI_CS_TXD 0x00040000 | |
51 | #define BCM2835_SPI_CS_RXD 0x00020000 | |
52 | #define BCM2835_SPI_CS_DONE 0x00010000 | |
53 | #define BCM2835_SPI_CS_LEN 0x00002000 | |
54 | #define BCM2835_SPI_CS_REN 0x00001000 | |
55 | #define BCM2835_SPI_CS_ADCS 0x00000800 | |
56 | #define BCM2835_SPI_CS_INTR 0x00000400 | |
57 | #define BCM2835_SPI_CS_INTD 0x00000200 | |
58 | #define BCM2835_SPI_CS_DMAEN 0x00000100 | |
59 | #define BCM2835_SPI_CS_TA 0x00000080 | |
60 | #define BCM2835_SPI_CS_CSPOL 0x00000040 | |
61 | #define BCM2835_SPI_CS_CLEAR_RX 0x00000020 | |
62 | #define BCM2835_SPI_CS_CLEAR_TX 0x00000010 | |
63 | #define BCM2835_SPI_CS_CPOL 0x00000008 | |
64 | #define BCM2835_SPI_CS_CPHA 0x00000004 | |
65 | #define BCM2835_SPI_CS_CS_10 0x00000002 | |
66 | #define BCM2835_SPI_CS_CS_01 0x00000001 | |
67 | ||
2e0733bc LW |
68 | #define BCM2835_SPI_FIFO_SIZE 64 |
69 | #define BCM2835_SPI_FIFO_SIZE_3_4 48 | |
3ecd37ed | 70 | #define BCM2835_SPI_DMA_MIN_LENGTH 96 |
603e92ff | 71 | #define BCM2835_SPI_NUM_CS 4 /* raise as necessary */ |
6935224d MS |
72 | #define BCM2835_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \ |
73 | | SPI_NO_CS | SPI_3WIRE) | |
f8043872 CB |
74 | |
75 | #define DRV_NAME "spi-bcm2835" | |
76 | ||
ff245d90 MS |
77 | /* define polling limits */ |
78 | unsigned int polling_limit_us = 30; | |
79 | module_param(polling_limit_us, uint, 0664); | |
80 | MODULE_PARM_DESC(polling_limit_us, | |
81 | "time in us to run a transfer in polling mode\n"); | |
82 | ||
acf0f856 LW |
83 | /** |
84 | * struct bcm2835_spi - BCM2835 SPI controller | |
85 | * @regs: base address of register map | |
86 | * @clk: core clock, divided to calculate serial clock | |
87 | * @irq: interrupt, signals TX FIFO empty or RX FIFO ¾ full | |
3bd7f658 | 88 | * @tfr: SPI transfer currently processed |
acf0f856 LW |
89 | * @tx_buf: pointer whence next transmitted byte is read |
90 | * @rx_buf: pointer where next received byte is written | |
91 | * @tx_len: remaining bytes to transmit | |
92 | * @rx_len: remaining bytes to receive | |
3bd7f658 LW |
93 | * @tx_prologue: bytes transmitted without DMA if first TX sglist entry's |
94 | * length is not a multiple of 4 (to overcome hardware limitation) | |
95 | * @rx_prologue: bytes received without DMA if first RX sglist entry's | |
96 | * length is not a multiple of 4 (to overcome hardware limitation) | |
97 | * @tx_spillover: whether @tx_prologue spills over to second TX sglist entry | |
571e31fa LW |
98 | * @prepare_cs: precalculated CS register value for ->prepare_message() |
99 | * (uses slave-specific clock polarity and phase settings) | |
154f7da5 MS |
100 | * @debugfs_dir: the debugfs directory - neede to remove debugfs when |
101 | * unloading the module | |
102 | * @count_transfer_polling: count of how often polling mode is used | |
103 | * @count_transfer_irq: count of how often interrupt mode is used | |
104 | * @count_transfer_irq_after_polling: count of how often we fall back to | |
105 | * interrupt mode after starting in polling mode. | |
106 | * These are counted as well in @count_transfer_polling and | |
107 | * @count_transfer_irq | |
108 | * @count_transfer_dma: count how often dma mode is used | |
8259bf66 LW |
109 | * @chip_select: SPI slave currently selected |
110 | * (used by bcm2835_spi_dma_tx_done() to write @clear_rx_cs) | |
111 | * @tx_dma_active: whether a TX DMA descriptor is in progress | |
112 | * @rx_dma_active: whether a RX DMA descriptor is in progress | |
113 | * (used by bcm2835_spi_dma_tx_done() to handle a race) | |
2b8279ae LW |
114 | * @fill_tx_desc: preallocated TX DMA descriptor used for RX-only transfers |
115 | * (cyclically copies from zero page to TX FIFO) | |
116 | * @fill_tx_addr: bus address of zero page | |
8259bf66 LW |
117 | * @clear_rx_desc: preallocated RX DMA descriptor used for TX-only transfers |
118 | * (cyclically clears RX FIFO by writing @clear_rx_cs to CS register) | |
119 | * @clear_rx_addr: bus address of @clear_rx_cs | |
120 | * @clear_rx_cs: precalculated CS register value to clear RX FIFO | |
121 | * (uses slave-specific clock polarity and phase settings) | |
acf0f856 | 122 | */ |
f8043872 CB |
123 | struct bcm2835_spi { |
124 | void __iomem *regs; | |
125 | struct clk *clk; | |
126 | int irq; | |
3bd7f658 | 127 | struct spi_transfer *tfr; |
f8043872 CB |
128 | const u8 *tx_buf; |
129 | u8 *rx_buf; | |
e34ff011 MS |
130 | int tx_len; |
131 | int rx_len; | |
3bd7f658 LW |
132 | int tx_prologue; |
133 | int rx_prologue; | |
b31a9299 | 134 | unsigned int tx_spillover; |
571e31fa | 135 | u32 prepare_cs[BCM2835_SPI_NUM_CS]; |
154f7da5 MS |
136 | |
137 | struct dentry *debugfs_dir; | |
138 | u64 count_transfer_polling; | |
139 | u64 count_transfer_irq; | |
140 | u64 count_transfer_irq_after_polling; | |
141 | u64 count_transfer_dma; | |
8259bf66 LW |
142 | |
143 | u8 chip_select; | |
144 | unsigned int tx_dma_active; | |
145 | unsigned int rx_dma_active; | |
2b8279ae LW |
146 | struct dma_async_tx_descriptor *fill_tx_desc; |
147 | dma_addr_t fill_tx_addr; | |
8259bf66 LW |
148 | struct dma_async_tx_descriptor *clear_rx_desc[BCM2835_SPI_NUM_CS]; |
149 | dma_addr_t clear_rx_addr; | |
150 | u32 clear_rx_cs[BCM2835_SPI_NUM_CS] ____cacheline_aligned; | |
f8043872 CB |
151 | }; |
152 | ||
154f7da5 MS |
153 | #if defined(CONFIG_DEBUG_FS) |
154 | static void bcm2835_debugfs_create(struct bcm2835_spi *bs, | |
155 | const char *dname) | |
156 | { | |
157 | char name[64]; | |
158 | struct dentry *dir; | |
159 | ||
160 | /* get full name */ | |
161 | snprintf(name, sizeof(name), "spi-bcm2835-%s", dname); | |
162 | ||
163 | /* the base directory */ | |
164 | dir = debugfs_create_dir(name, NULL); | |
165 | bs->debugfs_dir = dir; | |
166 | ||
167 | /* the counters */ | |
168 | debugfs_create_u64("count_transfer_polling", 0444, dir, | |
169 | &bs->count_transfer_polling); | |
170 | debugfs_create_u64("count_transfer_irq", 0444, dir, | |
171 | &bs->count_transfer_irq); | |
172 | debugfs_create_u64("count_transfer_irq_after_polling", 0444, dir, | |
173 | &bs->count_transfer_irq_after_polling); | |
174 | debugfs_create_u64("count_transfer_dma", 0444, dir, | |
175 | &bs->count_transfer_dma); | |
176 | } | |
177 | ||
178 | static void bcm2835_debugfs_remove(struct bcm2835_spi *bs) | |
179 | { | |
180 | debugfs_remove_recursive(bs->debugfs_dir); | |
181 | bs->debugfs_dir = NULL; | |
182 | } | |
183 | #else | |
184 | static void bcm2835_debugfs_create(struct bcm2835_spi *bs, | |
185 | const char *dname) | |
186 | { | |
187 | } | |
188 | ||
189 | static void bcm2835_debugfs_remove(struct bcm2835_spi *bs) | |
190 | { | |
191 | } | |
192 | #endif /* CONFIG_DEBUG_FS */ | |
193 | ||
e37687c9 | 194 | static inline u32 bcm2835_rd(struct bcm2835_spi *bs, unsigned int reg) |
f8043872 CB |
195 | { |
196 | return readl(bs->regs + reg); | |
197 | } | |
198 | ||
e37687c9 | 199 | static inline void bcm2835_wr(struct bcm2835_spi *bs, unsigned int reg, u32 val) |
f8043872 CB |
200 | { |
201 | writel(val, bs->regs + reg); | |
202 | } | |
203 | ||
4adf3129 | 204 | static inline void bcm2835_rd_fifo(struct bcm2835_spi *bs) |
f8043872 CB |
205 | { |
206 | u8 byte; | |
207 | ||
e34ff011 MS |
208 | while ((bs->rx_len) && |
209 | (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_RXD)) { | |
f8043872 CB |
210 | byte = bcm2835_rd(bs, BCM2835_SPI_FIFO); |
211 | if (bs->rx_buf) | |
212 | *bs->rx_buf++ = byte; | |
e34ff011 | 213 | bs->rx_len--; |
f8043872 CB |
214 | } |
215 | } | |
216 | ||
4adf3129 | 217 | static inline void bcm2835_wr_fifo(struct bcm2835_spi *bs) |
f8043872 CB |
218 | { |
219 | u8 byte; | |
220 | ||
e34ff011 | 221 | while ((bs->tx_len) && |
4adf3129 | 222 | (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_TXD)) { |
f8043872 CB |
223 | byte = bs->tx_buf ? *bs->tx_buf++ : 0; |
224 | bcm2835_wr(bs, BCM2835_SPI_FIFO, byte); | |
e34ff011 | 225 | bs->tx_len--; |
f8043872 CB |
226 | } |
227 | } | |
228 | ||
3bd7f658 LW |
229 | /** |
230 | * bcm2835_rd_fifo_count() - blindly read exactly @count bytes from RX FIFO | |
231 | * @bs: BCM2835 SPI controller | |
232 | * @count: bytes to read from RX FIFO | |
233 | * | |
234 | * The caller must ensure that @bs->rx_len is greater than or equal to @count, | |
235 | * that the RX FIFO contains at least @count bytes and that the DMA Enable flag | |
236 | * in the CS register is set (such that a read from the FIFO register receives | |
b31a9299 | 237 | * 32-bit instead of just 8-bit). Moreover @bs->rx_buf must not be %NULL. |
3bd7f658 LW |
238 | */ |
239 | static inline void bcm2835_rd_fifo_count(struct bcm2835_spi *bs, int count) | |
240 | { | |
241 | u32 val; | |
b31a9299 | 242 | int len; |
3bd7f658 LW |
243 | |
244 | bs->rx_len -= count; | |
245 | ||
246 | while (count > 0) { | |
247 | val = bcm2835_rd(bs, BCM2835_SPI_FIFO); | |
b31a9299 LW |
248 | len = min(count, 4); |
249 | memcpy(bs->rx_buf, &val, len); | |
250 | bs->rx_buf += len; | |
3bd7f658 LW |
251 | count -= 4; |
252 | } | |
253 | } | |
254 | ||
255 | /** | |
256 | * bcm2835_wr_fifo_count() - blindly write exactly @count bytes to TX FIFO | |
257 | * @bs: BCM2835 SPI controller | |
258 | * @count: bytes to write to TX FIFO | |
259 | * | |
260 | * The caller must ensure that @bs->tx_len is greater than or equal to @count, | |
261 | * that the TX FIFO can accommodate @count bytes and that the DMA Enable flag | |
262 | * in the CS register is set (such that a write to the FIFO register transmits | |
263 | * 32-bit instead of just 8-bit). | |
264 | */ | |
265 | static inline void bcm2835_wr_fifo_count(struct bcm2835_spi *bs, int count) | |
266 | { | |
267 | u32 val; | |
b31a9299 | 268 | int len; |
3bd7f658 LW |
269 | |
270 | bs->tx_len -= count; | |
271 | ||
272 | while (count > 0) { | |
273 | if (bs->tx_buf) { | |
b31a9299 | 274 | len = min(count, 4); |
3bd7f658 LW |
275 | memcpy(&val, bs->tx_buf, len); |
276 | bs->tx_buf += len; | |
277 | } else { | |
278 | val = 0; | |
279 | } | |
280 | bcm2835_wr(bs, BCM2835_SPI_FIFO, val); | |
281 | count -= 4; | |
282 | } | |
283 | } | |
284 | ||
285 | /** | |
286 | * bcm2835_wait_tx_fifo_empty() - busy-wait for TX FIFO to empty | |
287 | * @bs: BCM2835 SPI controller | |
b31a9299 LW |
288 | * |
289 | * The caller must ensure that the RX FIFO can accommodate as many bytes | |
290 | * as have been written to the TX FIFO: Transmission is halted once the | |
291 | * RX FIFO is full, causing this function to spin forever. | |
3bd7f658 LW |
292 | */ |
293 | static inline void bcm2835_wait_tx_fifo_empty(struct bcm2835_spi *bs) | |
294 | { | |
295 | while (!(bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_DONE)) | |
296 | cpu_relax(); | |
297 | } | |
298 | ||
2e0733bc LW |
299 | /** |
300 | * bcm2835_rd_fifo_blind() - blindly read up to @count bytes from RX FIFO | |
301 | * @bs: BCM2835 SPI controller | |
302 | * @count: bytes available for reading in RX FIFO | |
303 | */ | |
304 | static inline void bcm2835_rd_fifo_blind(struct bcm2835_spi *bs, int count) | |
305 | { | |
306 | u8 val; | |
307 | ||
308 | count = min(count, bs->rx_len); | |
309 | bs->rx_len -= count; | |
310 | ||
311 | while (count) { | |
312 | val = bcm2835_rd(bs, BCM2835_SPI_FIFO); | |
313 | if (bs->rx_buf) | |
314 | *bs->rx_buf++ = val; | |
315 | count--; | |
316 | } | |
317 | } | |
318 | ||
319 | /** | |
320 | * bcm2835_wr_fifo_blind() - blindly write up to @count bytes to TX FIFO | |
321 | * @bs: BCM2835 SPI controller | |
322 | * @count: bytes available for writing in TX FIFO | |
323 | */ | |
324 | static inline void bcm2835_wr_fifo_blind(struct bcm2835_spi *bs, int count) | |
325 | { | |
326 | u8 val; | |
327 | ||
328 | count = min(count, bs->tx_len); | |
329 | bs->tx_len -= count; | |
330 | ||
331 | while (count) { | |
332 | val = bs->tx_buf ? *bs->tx_buf++ : 0; | |
333 | bcm2835_wr(bs, BCM2835_SPI_FIFO, val); | |
334 | count--; | |
335 | } | |
336 | } | |
337 | ||
5f336ea5 | 338 | static void bcm2835_spi_reset_hw(struct spi_controller *ctlr) |
e34ff011 | 339 | { |
5f336ea5 | 340 | struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr); |
e34ff011 MS |
341 | u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS); |
342 | ||
343 | /* Disable SPI interrupts and transfer */ | |
344 | cs &= ~(BCM2835_SPI_CS_INTR | | |
345 | BCM2835_SPI_CS_INTD | | |
3ecd37ed | 346 | BCM2835_SPI_CS_DMAEN | |
e34ff011 | 347 | BCM2835_SPI_CS_TA); |
4c524191 LW |
348 | /* |
349 | * Transmission sometimes breaks unless the DONE bit is written at the | |
350 | * end of every transfer. The spec says it's a RO bit. Either the | |
351 | * spec is wrong and the bit is actually of type RW1C, or it's a | |
352 | * hardware erratum. | |
353 | */ | |
354 | cs |= BCM2835_SPI_CS_DONE; | |
e34ff011 MS |
355 | /* and reset RX/TX FIFOS */ |
356 | cs |= BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX; | |
357 | ||
358 | /* and reset the SPI_HW */ | |
359 | bcm2835_wr(bs, BCM2835_SPI_CS, cs); | |
3ecd37ed MS |
360 | /* as well as DLEN */ |
361 | bcm2835_wr(bs, BCM2835_SPI_DLEN, 0); | |
e34ff011 MS |
362 | } |
363 | ||
f8043872 CB |
364 | static irqreturn_t bcm2835_spi_interrupt(int irq, void *dev_id) |
365 | { | |
5f336ea5 LW |
366 | struct spi_controller *ctlr = dev_id; |
367 | struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr); | |
2e0733bc LW |
368 | u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS); |
369 | ||
370 | /* | |
371 | * An interrupt is signaled either if DONE is set (TX FIFO empty) | |
372 | * or if RXR is set (RX FIFO >= ¾ full). | |
373 | */ | |
374 | if (cs & BCM2835_SPI_CS_RXF) | |
375 | bcm2835_rd_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE); | |
376 | else if (cs & BCM2835_SPI_CS_RXR) | |
377 | bcm2835_rd_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE_3_4); | |
378 | ||
379 | if (bs->tx_len && cs & BCM2835_SPI_CS_DONE) | |
380 | bcm2835_wr_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE); | |
f8043872 | 381 | |
4adf3129 MS |
382 | /* Read as many bytes as possible from FIFO */ |
383 | bcm2835_rd_fifo(bs); | |
e34ff011 MS |
384 | /* Write as many bytes as possible to FIFO */ |
385 | bcm2835_wr_fifo(bs); | |
386 | ||
56c17234 | 387 | if (!bs->rx_len) { |
e34ff011 | 388 | /* Transfer complete - reset SPI HW */ |
5f336ea5 | 389 | bcm2835_spi_reset_hw(ctlr); |
e34ff011 | 390 | /* wake up the framework */ |
5f336ea5 | 391 | complete(&ctlr->xfer_completion); |
f8043872 CB |
392 | } |
393 | ||
4adf3129 | 394 | return IRQ_HANDLED; |
f8043872 CB |
395 | } |
396 | ||
5f336ea5 | 397 | static int bcm2835_spi_transfer_one_irq(struct spi_controller *ctlr, |
704f32d4 MS |
398 | struct spi_device *spi, |
399 | struct spi_transfer *tfr, | |
2e0733bc | 400 | u32 cs, bool fifo_empty) |
704f32d4 | 401 | { |
5f336ea5 | 402 | struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr); |
704f32d4 | 403 | |
154f7da5 MS |
404 | /* update usage statistics */ |
405 | bs->count_transfer_irq++; | |
406 | ||
704f32d4 | 407 | /* |
5c09e42f LW |
408 | * Enable HW block, but with interrupts still disabled. |
409 | * Otherwise the empty TX FIFO would immediately trigger an interrupt. | |
704f32d4 | 410 | */ |
5c09e42f LW |
411 | bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA); |
412 | ||
413 | /* fill TX FIFO as much as possible */ | |
2e0733bc LW |
414 | if (fifo_empty) |
415 | bcm2835_wr_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE); | |
5c09e42f LW |
416 | bcm2835_wr_fifo(bs); |
417 | ||
418 | /* enable interrupts */ | |
704f32d4 MS |
419 | cs |= BCM2835_SPI_CS_INTR | BCM2835_SPI_CS_INTD | BCM2835_SPI_CS_TA; |
420 | bcm2835_wr(bs, BCM2835_SPI_CS, cs); | |
421 | ||
422 | /* signal that we need to wait for completion */ | |
423 | return 1; | |
424 | } | |
425 | ||
3bd7f658 LW |
426 | /** |
427 | * bcm2835_spi_transfer_prologue() - transfer first few bytes without DMA | |
5f336ea5 | 428 | * @ctlr: SPI master controller |
3bd7f658 LW |
429 | * @tfr: SPI transfer |
430 | * @bs: BCM2835 SPI controller | |
431 | * @cs: CS register | |
432 | * | |
433 | * A limitation in DMA mode is that the FIFO must be accessed in 4 byte chunks. | |
434 | * Only the final write access is permitted to transmit less than 4 bytes, the | |
435 | * SPI controller deduces its intended size from the DLEN register. | |
436 | * | |
437 | * If a TX or RX sglist contains multiple entries, one per page, and the first | |
438 | * entry starts in the middle of a page, that first entry's length may not be | |
439 | * a multiple of 4. Subsequent entries are fine because they span an entire | |
440 | * page, hence do have a length that's a multiple of 4. | |
441 | * | |
442 | * This cannot happen with kmalloc'ed buffers (which is what most clients use) | |
443 | * because they are contiguous in physical memory and therefore not split on | |
444 | * page boundaries by spi_map_buf(). But it *can* happen with vmalloc'ed | |
445 | * buffers. | |
446 | * | |
447 | * The DMA engine is incapable of combining sglist entries into a continuous | |
448 | * stream of 4 byte chunks, it treats every entry separately: A TX entry is | |
449 | * rounded up a to a multiple of 4 bytes by transmitting surplus bytes, an RX | |
450 | * entry is rounded up by throwing away received bytes. | |
451 | * | |
452 | * Overcome this limitation by transferring the first few bytes without DMA: | |
453 | * E.g. if the first TX sglist entry's length is 23 and the first RX's is 42, | |
454 | * write 3 bytes to the TX FIFO but read only 2 bytes from the RX FIFO. | |
455 | * The residue of 1 byte in the RX FIFO is picked up by DMA. Together with | |
456 | * the rest of the first RX sglist entry it makes up a multiple of 4 bytes. | |
457 | * | |
458 | * Should the RX prologue be larger, say, 3 vis-à-vis a TX prologue of 1, | |
459 | * write 1 + 4 = 5 bytes to the TX FIFO and read 3 bytes from the RX FIFO. | |
460 | * Caution, the additional 4 bytes spill over to the second TX sglist entry | |
461 | * if the length of the first is *exactly* 1. | |
462 | * | |
463 | * At most 6 bytes are written and at most 3 bytes read. Do we know the | |
464 | * transfer has this many bytes? Yes, see BCM2835_SPI_DMA_MIN_LENGTH. | |
465 | * | |
466 | * The FIFO is normally accessed with 8-bit width by the CPU and 32-bit width | |
467 | * by the DMA engine. Toggling the DMA Enable flag in the CS register switches | |
468 | * the width but also garbles the FIFO's contents. The prologue must therefore | |
469 | * be transmitted in 32-bit width to ensure that the following DMA transfer can | |
470 | * pick up the residue in the RX FIFO in ungarbled form. | |
471 | */ | |
5f336ea5 | 472 | static void bcm2835_spi_transfer_prologue(struct spi_controller *ctlr, |
3bd7f658 LW |
473 | struct spi_transfer *tfr, |
474 | struct bcm2835_spi *bs, | |
475 | u32 cs) | |
476 | { | |
477 | int tx_remaining; | |
478 | ||
479 | bs->tfr = tfr; | |
480 | bs->tx_prologue = 0; | |
481 | bs->rx_prologue = 0; | |
482 | bs->tx_spillover = false; | |
483 | ||
2b8279ae | 484 | if (bs->tx_buf && !sg_is_last(&tfr->tx_sg.sgl[0])) |
3bd7f658 LW |
485 | bs->tx_prologue = sg_dma_len(&tfr->tx_sg.sgl[0]) & 3; |
486 | ||
8259bf66 | 487 | if (bs->rx_buf && !sg_is_last(&tfr->rx_sg.sgl[0])) { |
3bd7f658 LW |
488 | bs->rx_prologue = sg_dma_len(&tfr->rx_sg.sgl[0]) & 3; |
489 | ||
490 | if (bs->rx_prologue > bs->tx_prologue) { | |
2b8279ae | 491 | if (!bs->tx_buf || sg_is_last(&tfr->tx_sg.sgl[0])) { |
3bd7f658 LW |
492 | bs->tx_prologue = bs->rx_prologue; |
493 | } else { | |
494 | bs->tx_prologue += 4; | |
495 | bs->tx_spillover = | |
496 | !(sg_dma_len(&tfr->tx_sg.sgl[0]) & ~3); | |
497 | } | |
498 | } | |
499 | } | |
500 | ||
501 | /* rx_prologue > 0 implies tx_prologue > 0, so check only the latter */ | |
502 | if (!bs->tx_prologue) | |
503 | return; | |
504 | ||
505 | /* Write and read RX prologue. Adjust first entry in RX sglist. */ | |
506 | if (bs->rx_prologue) { | |
507 | bcm2835_wr(bs, BCM2835_SPI_DLEN, bs->rx_prologue); | |
508 | bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA | |
509 | | BCM2835_SPI_CS_DMAEN); | |
510 | bcm2835_wr_fifo_count(bs, bs->rx_prologue); | |
511 | bcm2835_wait_tx_fifo_empty(bs); | |
512 | bcm2835_rd_fifo_count(bs, bs->rx_prologue); | |
4c524191 LW |
513 | bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_CLEAR_RX |
514 | | BCM2835_SPI_CS_CLEAR_TX | |
515 | | BCM2835_SPI_CS_DONE); | |
3bd7f658 | 516 | |
5f336ea5 | 517 | dma_sync_single_for_device(ctlr->dma_rx->device->dev, |
b31a9299 LW |
518 | sg_dma_address(&tfr->rx_sg.sgl[0]), |
519 | bs->rx_prologue, DMA_FROM_DEVICE); | |
3bd7f658 | 520 | |
b31a9299 LW |
521 | sg_dma_address(&tfr->rx_sg.sgl[0]) += bs->rx_prologue; |
522 | sg_dma_len(&tfr->rx_sg.sgl[0]) -= bs->rx_prologue; | |
3bd7f658 LW |
523 | } |
524 | ||
2b8279ae LW |
525 | if (!bs->tx_buf) |
526 | return; | |
527 | ||
3bd7f658 LW |
528 | /* |
529 | * Write remaining TX prologue. Adjust first entry in TX sglist. | |
530 | * Also adjust second entry if prologue spills over to it. | |
531 | */ | |
532 | tx_remaining = bs->tx_prologue - bs->rx_prologue; | |
533 | if (tx_remaining) { | |
534 | bcm2835_wr(bs, BCM2835_SPI_DLEN, tx_remaining); | |
535 | bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA | |
536 | | BCM2835_SPI_CS_DMAEN); | |
537 | bcm2835_wr_fifo_count(bs, tx_remaining); | |
538 | bcm2835_wait_tx_fifo_empty(bs); | |
4c524191 LW |
539 | bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_CLEAR_TX |
540 | | BCM2835_SPI_CS_DONE); | |
3bd7f658 LW |
541 | } |
542 | ||
543 | if (likely(!bs->tx_spillover)) { | |
b31a9299 LW |
544 | sg_dma_address(&tfr->tx_sg.sgl[0]) += bs->tx_prologue; |
545 | sg_dma_len(&tfr->tx_sg.sgl[0]) -= bs->tx_prologue; | |
3bd7f658 | 546 | } else { |
b31a9299 LW |
547 | sg_dma_len(&tfr->tx_sg.sgl[0]) = 0; |
548 | sg_dma_address(&tfr->tx_sg.sgl[1]) += 4; | |
549 | sg_dma_len(&tfr->tx_sg.sgl[1]) -= 4; | |
3bd7f658 LW |
550 | } |
551 | } | |
552 | ||
553 | /** | |
554 | * bcm2835_spi_undo_prologue() - reconstruct original sglist state | |
555 | * @bs: BCM2835 SPI controller | |
556 | * | |
557 | * Undo changes which were made to an SPI transfer's sglist when transmitting | |
558 | * the prologue. This is necessary to ensure the same memory ranges are | |
559 | * unmapped that were originally mapped. | |
560 | */ | |
561 | static void bcm2835_spi_undo_prologue(struct bcm2835_spi *bs) | |
562 | { | |
563 | struct spi_transfer *tfr = bs->tfr; | |
564 | ||
565 | if (!bs->tx_prologue) | |
566 | return; | |
567 | ||
568 | if (bs->rx_prologue) { | |
b31a9299 LW |
569 | sg_dma_address(&tfr->rx_sg.sgl[0]) -= bs->rx_prologue; |
570 | sg_dma_len(&tfr->rx_sg.sgl[0]) += bs->rx_prologue; | |
3bd7f658 LW |
571 | } |
572 | ||
2b8279ae LW |
573 | if (!bs->tx_buf) |
574 | goto out; | |
575 | ||
3bd7f658 | 576 | if (likely(!bs->tx_spillover)) { |
b31a9299 LW |
577 | sg_dma_address(&tfr->tx_sg.sgl[0]) -= bs->tx_prologue; |
578 | sg_dma_len(&tfr->tx_sg.sgl[0]) += bs->tx_prologue; | |
3bd7f658 | 579 | } else { |
b31a9299 LW |
580 | sg_dma_len(&tfr->tx_sg.sgl[0]) = bs->tx_prologue - 4; |
581 | sg_dma_address(&tfr->tx_sg.sgl[1]) -= 4; | |
582 | sg_dma_len(&tfr->tx_sg.sgl[1]) += 4; | |
3bd7f658 | 583 | } |
2b8279ae | 584 | out: |
1513ceee | 585 | bs->tx_prologue = 0; |
3bd7f658 LW |
586 | } |
587 | ||
8259bf66 LW |
588 | /** |
589 | * bcm2835_spi_dma_rx_done() - callback for DMA RX channel | |
590 | * @data: SPI master controller | |
591 | * | |
592 | * Used for bidirectional and RX-only transfers. | |
593 | */ | |
594 | static void bcm2835_spi_dma_rx_done(void *data) | |
3ecd37ed | 595 | { |
5f336ea5 LW |
596 | struct spi_controller *ctlr = data; |
597 | struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr); | |
3ecd37ed | 598 | |
2b8279ae | 599 | /* terminate tx-dma as we do not have an irq for it |
3ecd37ed MS |
600 | * because when the rx dma will terminate and this callback |
601 | * is called the tx-dma must have finished - can't get to this | |
602 | * situation otherwise... | |
603 | */ | |
1513ceee | 604 | dmaengine_terminate_async(ctlr->dma_tx); |
8259bf66 LW |
605 | bs->tx_dma_active = false; |
606 | bs->rx_dma_active = false; | |
1513ceee | 607 | bcm2835_spi_undo_prologue(bs); |
3ecd37ed | 608 | |
2b8279ae LW |
609 | /* reset fifo and HW */ |
610 | bcm2835_spi_reset_hw(ctlr); | |
3ecd37ed MS |
611 | |
612 | /* and mark as completed */; | |
5f336ea5 | 613 | complete(&ctlr->xfer_completion); |
3ecd37ed MS |
614 | } |
615 | ||
8259bf66 LW |
616 | /** |
617 | * bcm2835_spi_dma_tx_done() - callback for DMA TX channel | |
618 | * @data: SPI master controller | |
619 | * | |
620 | * Used for TX-only transfers. | |
621 | */ | |
622 | static void bcm2835_spi_dma_tx_done(void *data) | |
623 | { | |
624 | struct spi_controller *ctlr = data; | |
625 | struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr); | |
626 | ||
627 | /* busy-wait for TX FIFO to empty */ | |
628 | while (!(bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_DONE)) | |
629 | bcm2835_wr(bs, BCM2835_SPI_CS, | |
630 | bs->clear_rx_cs[bs->chip_select]); | |
631 | ||
632 | bs->tx_dma_active = false; | |
633 | smp_wmb(); | |
634 | ||
635 | /* | |
636 | * In case of a very short transfer, RX DMA may not have been | |
637 | * issued yet. The onus is then on bcm2835_spi_transfer_one_dma() | |
638 | * to terminate it immediately after issuing. | |
639 | */ | |
640 | if (cmpxchg(&bs->rx_dma_active, true, false)) | |
641 | dmaengine_terminate_async(ctlr->dma_rx); | |
642 | ||
643 | bcm2835_spi_undo_prologue(bs); | |
644 | bcm2835_spi_reset_hw(ctlr); | |
645 | complete(&ctlr->xfer_completion); | |
646 | } | |
647 | ||
648 | /** | |
649 | * bcm2835_spi_prepare_sg() - prepare and submit DMA descriptor for sglist | |
650 | * @ctlr: SPI master controller | |
651 | * @spi: SPI slave | |
652 | * @tfr: SPI transfer | |
653 | * @bs: BCM2835 SPI controller | |
654 | * @is_tx: whether to submit DMA descriptor for TX or RX sglist | |
655 | * | |
656 | * Prepare and submit a DMA descriptor for the TX or RX sglist of @tfr. | |
657 | * Return 0 on success or a negative error number. | |
658 | */ | |
5f336ea5 | 659 | static int bcm2835_spi_prepare_sg(struct spi_controller *ctlr, |
8259bf66 | 660 | struct spi_device *spi, |
3ecd37ed | 661 | struct spi_transfer *tfr, |
8259bf66 | 662 | struct bcm2835_spi *bs, |
3ecd37ed MS |
663 | bool is_tx) |
664 | { | |
665 | struct dma_chan *chan; | |
666 | struct scatterlist *sgl; | |
667 | unsigned int nents; | |
668 | enum dma_transfer_direction dir; | |
669 | unsigned long flags; | |
670 | ||
671 | struct dma_async_tx_descriptor *desc; | |
672 | dma_cookie_t cookie; | |
673 | ||
674 | if (is_tx) { | |
675 | dir = DMA_MEM_TO_DEV; | |
5f336ea5 | 676 | chan = ctlr->dma_tx; |
3ecd37ed MS |
677 | nents = tfr->tx_sg.nents; |
678 | sgl = tfr->tx_sg.sgl; | |
8259bf66 | 679 | flags = tfr->rx_buf ? 0 : DMA_PREP_INTERRUPT; |
3ecd37ed MS |
680 | } else { |
681 | dir = DMA_DEV_TO_MEM; | |
5f336ea5 | 682 | chan = ctlr->dma_rx; |
3ecd37ed MS |
683 | nents = tfr->rx_sg.nents; |
684 | sgl = tfr->rx_sg.sgl; | |
685 | flags = DMA_PREP_INTERRUPT; | |
686 | } | |
687 | /* prepare the channel */ | |
688 | desc = dmaengine_prep_slave_sg(chan, sgl, nents, dir, flags); | |
689 | if (!desc) | |
690 | return -EINVAL; | |
691 | ||
8259bf66 LW |
692 | /* |
693 | * Completion is signaled by the RX channel for bidirectional and | |
694 | * RX-only transfers; else by the TX channel for TX-only transfers. | |
695 | */ | |
3ecd37ed | 696 | if (!is_tx) { |
8259bf66 | 697 | desc->callback = bcm2835_spi_dma_rx_done; |
5f336ea5 | 698 | desc->callback_param = ctlr; |
8259bf66 LW |
699 | } else if (!tfr->rx_buf) { |
700 | desc->callback = bcm2835_spi_dma_tx_done; | |
5f336ea5 | 701 | desc->callback_param = ctlr; |
8259bf66 | 702 | bs->chip_select = spi->chip_select; |
3ecd37ed MS |
703 | } |
704 | ||
705 | /* submit it to DMA-engine */ | |
706 | cookie = dmaengine_submit(desc); | |
707 | ||
708 | return dma_submit_error(cookie); | |
709 | } | |
710 | ||
8259bf66 LW |
711 | /** |
712 | * bcm2835_spi_transfer_one_dma() - perform SPI transfer using DMA engine | |
713 | * @ctlr: SPI master controller | |
714 | * @spi: SPI slave | |
715 | * @tfr: SPI transfer | |
716 | * @cs: CS register | |
717 | * | |
718 | * For *bidirectional* transfers (both tx_buf and rx_buf are non-%NULL), set up | |
719 | * the TX and RX DMA channel to copy between memory and FIFO register. | |
720 | * | |
721 | * For *TX-only* transfers (rx_buf is %NULL), copying the RX FIFO's contents to | |
722 | * memory is pointless. However not reading the RX FIFO isn't an option either | |
723 | * because transmission is halted once it's full. As a workaround, cyclically | |
724 | * clear the RX FIFO by setting the CLEAR_RX bit in the CS register. | |
725 | * | |
726 | * The CS register value is precalculated in bcm2835_spi_setup(). Normally | |
727 | * this is called only once, on slave registration. A DMA descriptor to write | |
728 | * this value is preallocated in bcm2835_dma_init(). All that's left to do | |
729 | * when performing a TX-only transfer is to submit this descriptor to the RX | |
730 | * DMA channel. Latency is thereby minimized. The descriptor does not | |
731 | * generate any interrupts while running. It must be terminated once the | |
732 | * TX DMA channel is done. | |
733 | * | |
734 | * Clearing the RX FIFO is paced by the DREQ signal. The signal is asserted | |
735 | * when the RX FIFO becomes half full, i.e. 32 bytes. (Tuneable with the DC | |
736 | * register.) Reading 32 bytes from the RX FIFO would normally require 8 bus | |
737 | * accesses, whereas clearing it requires only 1 bus access. So an 8-fold | |
738 | * reduction in bus traffic and thus energy consumption is achieved. | |
2b8279ae LW |
739 | * |
740 | * For *RX-only* transfers (tx_buf is %NULL), fill the TX FIFO by cyclically | |
741 | * copying from the zero page. The DMA descriptor to do this is preallocated | |
742 | * in bcm2835_dma_init(). It must be terminated once the RX DMA channel is | |
743 | * done and can then be reused. | |
744 | * | |
745 | * The BCM2835 DMA driver autodetects when a transaction copies from the zero | |
746 | * page and utilizes the DMA controller's ability to synthesize zeroes instead | |
747 | * of copying them from memory. This reduces traffic on the memory bus. The | |
748 | * feature is not available on so-called "lite" channels, but normally TX DMA | |
749 | * is backed by a full-featured channel. | |
750 | * | |
751 | * Zero-filling the TX FIFO is paced by the DREQ signal. Unfortunately the | |
752 | * BCM2835 SPI controller continues to assert DREQ even after the DLEN register | |
753 | * has been counted down to zero (hardware erratum). Thus, when the transfer | |
754 | * has finished, the DMA engine zero-fills the TX FIFO until it is half full. | |
755 | * (Tuneable with the DC register.) So up to 9 gratuitous bus accesses are | |
756 | * performed at the end of an RX-only transfer. | |
8259bf66 | 757 | */ |
5f336ea5 | 758 | static int bcm2835_spi_transfer_one_dma(struct spi_controller *ctlr, |
3ecd37ed MS |
759 | struct spi_device *spi, |
760 | struct spi_transfer *tfr, | |
761 | u32 cs) | |
762 | { | |
5f336ea5 | 763 | struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr); |
8259bf66 | 764 | dma_cookie_t cookie; |
3ecd37ed MS |
765 | int ret; |
766 | ||
154f7da5 MS |
767 | /* update usage statistics */ |
768 | bs->count_transfer_dma++; | |
769 | ||
3bd7f658 LW |
770 | /* |
771 | * Transfer first few bytes without DMA if length of first TX or RX | |
772 | * sglist entry is not a multiple of 4 bytes (hardware limitation). | |
773 | */ | |
5f336ea5 | 774 | bcm2835_spi_transfer_prologue(ctlr, tfr, bs, cs); |
3ecd37ed MS |
775 | |
776 | /* setup tx-DMA */ | |
2b8279ae LW |
777 | if (bs->tx_buf) { |
778 | ret = bcm2835_spi_prepare_sg(ctlr, spi, tfr, bs, true); | |
779 | } else { | |
780 | cookie = dmaengine_submit(bs->fill_tx_desc); | |
781 | ret = dma_submit_error(cookie); | |
782 | } | |
3ecd37ed | 783 | if (ret) |
3bd7f658 | 784 | goto err_reset_hw; |
3ecd37ed | 785 | |
3ecd37ed | 786 | /* set the DMA length */ |
3bd7f658 | 787 | bcm2835_wr(bs, BCM2835_SPI_DLEN, bs->tx_len); |
3ecd37ed MS |
788 | |
789 | /* start the HW */ | |
790 | bcm2835_wr(bs, BCM2835_SPI_CS, | |
791 | cs | BCM2835_SPI_CS_TA | BCM2835_SPI_CS_DMAEN); | |
792 | ||
8259bf66 LW |
793 | bs->tx_dma_active = true; |
794 | smp_wmb(); | |
795 | ||
796 | /* start TX early */ | |
797 | dma_async_issue_pending(ctlr->dma_tx); | |
798 | ||
3ecd37ed MS |
799 | /* setup rx-DMA late - to run transfers while |
800 | * mapping of the rx buffers still takes place | |
801 | * this saves 10us or more. | |
802 | */ | |
8259bf66 LW |
803 | if (bs->rx_buf) { |
804 | ret = bcm2835_spi_prepare_sg(ctlr, spi, tfr, bs, false); | |
805 | } else { | |
806 | cookie = dmaengine_submit(bs->clear_rx_desc[spi->chip_select]); | |
807 | ret = dma_submit_error(cookie); | |
808 | } | |
3ecd37ed MS |
809 | if (ret) { |
810 | /* need to reset on errors */ | |
5f336ea5 | 811 | dmaengine_terminate_sync(ctlr->dma_tx); |
8259bf66 | 812 | bs->tx_dma_active = false; |
3bd7f658 | 813 | goto err_reset_hw; |
3ecd37ed MS |
814 | } |
815 | ||
816 | /* start rx dma late */ | |
5f336ea5 | 817 | dma_async_issue_pending(ctlr->dma_rx); |
8259bf66 LW |
818 | bs->rx_dma_active = true; |
819 | smp_mb(); | |
820 | ||
821 | /* | |
822 | * In case of a very short TX-only transfer, bcm2835_spi_dma_tx_done() | |
823 | * may run before RX DMA is issued. Terminate RX DMA if so. | |
824 | */ | |
825 | if (!bs->rx_buf && !bs->tx_dma_active && | |
826 | cmpxchg(&bs->rx_dma_active, true, false)) { | |
827 | dmaengine_terminate_async(ctlr->dma_rx); | |
828 | bcm2835_spi_reset_hw(ctlr); | |
829 | } | |
3ecd37ed MS |
830 | |
831 | /* wait for wakeup in framework */ | |
832 | return 1; | |
3bd7f658 LW |
833 | |
834 | err_reset_hw: | |
5f336ea5 | 835 | bcm2835_spi_reset_hw(ctlr); |
3bd7f658 LW |
836 | bcm2835_spi_undo_prologue(bs); |
837 | return ret; | |
3ecd37ed MS |
838 | } |
839 | ||
5f336ea5 | 840 | static bool bcm2835_spi_can_dma(struct spi_controller *ctlr, |
3ecd37ed MS |
841 | struct spi_device *spi, |
842 | struct spi_transfer *tfr) | |
843 | { | |
3ecd37ed MS |
844 | /* we start DMA efforts only on bigger transfers */ |
845 | if (tfr->len < BCM2835_SPI_DMA_MIN_LENGTH) | |
846 | return false; | |
847 | ||
3ecd37ed MS |
848 | /* return OK */ |
849 | return true; | |
850 | } | |
851 | ||
8259bf66 LW |
852 | static void bcm2835_dma_release(struct spi_controller *ctlr, |
853 | struct bcm2835_spi *bs) | |
3ecd37ed | 854 | { |
8259bf66 LW |
855 | int i; |
856 | ||
5f336ea5 LW |
857 | if (ctlr->dma_tx) { |
858 | dmaengine_terminate_sync(ctlr->dma_tx); | |
2b8279ae LW |
859 | |
860 | if (bs->fill_tx_desc) | |
861 | dmaengine_desc_free(bs->fill_tx_desc); | |
862 | ||
863 | if (bs->fill_tx_addr) | |
864 | dma_unmap_page_attrs(ctlr->dma_tx->device->dev, | |
865 | bs->fill_tx_addr, sizeof(u32), | |
866 | DMA_TO_DEVICE, | |
867 | DMA_ATTR_SKIP_CPU_SYNC); | |
868 | ||
5f336ea5 LW |
869 | dma_release_channel(ctlr->dma_tx); |
870 | ctlr->dma_tx = NULL; | |
3ecd37ed | 871 | } |
8259bf66 | 872 | |
5f336ea5 LW |
873 | if (ctlr->dma_rx) { |
874 | dmaengine_terminate_sync(ctlr->dma_rx); | |
8259bf66 LW |
875 | |
876 | for (i = 0; i < BCM2835_SPI_NUM_CS; i++) | |
877 | if (bs->clear_rx_desc[i]) | |
878 | dmaengine_desc_free(bs->clear_rx_desc[i]); | |
879 | ||
880 | if (bs->clear_rx_addr) | |
881 | dma_unmap_single(ctlr->dma_rx->device->dev, | |
882 | bs->clear_rx_addr, | |
883 | sizeof(bs->clear_rx_cs), | |
884 | DMA_TO_DEVICE); | |
885 | ||
5f336ea5 LW |
886 | dma_release_channel(ctlr->dma_rx); |
887 | ctlr->dma_rx = NULL; | |
3ecd37ed MS |
888 | } |
889 | } | |
890 | ||
6133fed0 PU |
891 | static int bcm2835_dma_init(struct spi_controller *ctlr, struct device *dev, |
892 | struct bcm2835_spi *bs) | |
3ecd37ed MS |
893 | { |
894 | struct dma_slave_config slave_config; | |
895 | const __be32 *addr; | |
896 | dma_addr_t dma_reg_base; | |
8259bf66 | 897 | int ret, i; |
3ecd37ed MS |
898 | |
899 | /* base address in dma-space */ | |
5f336ea5 | 900 | addr = of_get_address(ctlr->dev.of_node, 0, NULL, NULL); |
3ecd37ed MS |
901 | if (!addr) { |
902 | dev_err(dev, "could not get DMA-register address - not using dma mode\n"); | |
6133fed0 PU |
903 | /* Fall back to interrupt mode */ |
904 | return 0; | |
3ecd37ed MS |
905 | } |
906 | dma_reg_base = be32_to_cpup(addr); | |
907 | ||
908 | /* get tx/rx dma */ | |
6133fed0 PU |
909 | ctlr->dma_tx = dma_request_chan(dev, "tx"); |
910 | if (IS_ERR(ctlr->dma_tx)) { | |
3ecd37ed | 911 | dev_err(dev, "no tx-dma configuration found - not using dma mode\n"); |
6133fed0 PU |
912 | ret = PTR_ERR(ctlr->dma_tx); |
913 | ctlr->dma_tx = NULL; | |
3ecd37ed MS |
914 | goto err; |
915 | } | |
6133fed0 PU |
916 | ctlr->dma_rx = dma_request_chan(dev, "rx"); |
917 | if (IS_ERR(ctlr->dma_rx)) { | |
3ecd37ed | 918 | dev_err(dev, "no rx-dma configuration found - not using dma mode\n"); |
6133fed0 PU |
919 | ret = PTR_ERR(ctlr->dma_rx); |
920 | ctlr->dma_rx = NULL; | |
3ecd37ed MS |
921 | goto err_release; |
922 | } | |
923 | ||
2b8279ae LW |
924 | /* |
925 | * The TX DMA channel either copies a transfer's TX buffer to the FIFO | |
926 | * or, in case of an RX-only transfer, cyclically copies from the zero | |
927 | * page to the FIFO using a preallocated, reusable descriptor. | |
928 | */ | |
3ecd37ed MS |
929 | slave_config.dst_addr = (u32)(dma_reg_base + BCM2835_SPI_FIFO); |
930 | slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
931 | ||
5f336ea5 | 932 | ret = dmaengine_slave_config(ctlr->dma_tx, &slave_config); |
3ecd37ed MS |
933 | if (ret) |
934 | goto err_config; | |
935 | ||
2b8279ae LW |
936 | bs->fill_tx_addr = dma_map_page_attrs(ctlr->dma_tx->device->dev, |
937 | ZERO_PAGE(0), 0, sizeof(u32), | |
938 | DMA_TO_DEVICE, | |
939 | DMA_ATTR_SKIP_CPU_SYNC); | |
940 | if (dma_mapping_error(ctlr->dma_tx->device->dev, bs->fill_tx_addr)) { | |
941 | dev_err(dev, "cannot map zero page - not using DMA mode\n"); | |
942 | bs->fill_tx_addr = 0; | |
dd4441ab | 943 | ret = -ENOMEM; |
2b8279ae LW |
944 | goto err_release; |
945 | } | |
946 | ||
947 | bs->fill_tx_desc = dmaengine_prep_dma_cyclic(ctlr->dma_tx, | |
948 | bs->fill_tx_addr, | |
949 | sizeof(u32), 0, | |
950 | DMA_MEM_TO_DEV, 0); | |
951 | if (!bs->fill_tx_desc) { | |
952 | dev_err(dev, "cannot prepare fill_tx_desc - not using DMA mode\n"); | |
dd4441ab | 953 | ret = -ENOMEM; |
2b8279ae LW |
954 | goto err_release; |
955 | } | |
956 | ||
957 | ret = dmaengine_desc_set_reuse(bs->fill_tx_desc); | |
958 | if (ret) { | |
959 | dev_err(dev, "cannot reuse fill_tx_desc - not using DMA mode\n"); | |
960 | goto err_release; | |
961 | } | |
962 | ||
8259bf66 LW |
963 | /* |
964 | * The RX DMA channel is used bidirectionally: It either reads the | |
965 | * RX FIFO or, in case of a TX-only transfer, cyclically writes a | |
966 | * precalculated value to the CS register to clear the RX FIFO. | |
967 | */ | |
3ecd37ed MS |
968 | slave_config.src_addr = (u32)(dma_reg_base + BCM2835_SPI_FIFO); |
969 | slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
8259bf66 LW |
970 | slave_config.dst_addr = (u32)(dma_reg_base + BCM2835_SPI_CS); |
971 | slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
3ecd37ed | 972 | |
5f336ea5 | 973 | ret = dmaengine_slave_config(ctlr->dma_rx, &slave_config); |
3ecd37ed MS |
974 | if (ret) |
975 | goto err_config; | |
976 | ||
8259bf66 LW |
977 | bs->clear_rx_addr = dma_map_single(ctlr->dma_rx->device->dev, |
978 | bs->clear_rx_cs, | |
979 | sizeof(bs->clear_rx_cs), | |
980 | DMA_TO_DEVICE); | |
981 | if (dma_mapping_error(ctlr->dma_rx->device->dev, bs->clear_rx_addr)) { | |
982 | dev_err(dev, "cannot map clear_rx_cs - not using DMA mode\n"); | |
983 | bs->clear_rx_addr = 0; | |
dd4441ab | 984 | ret = -ENOMEM; |
8259bf66 LW |
985 | goto err_release; |
986 | } | |
987 | ||
988 | for (i = 0; i < BCM2835_SPI_NUM_CS; i++) { | |
989 | bs->clear_rx_desc[i] = dmaengine_prep_dma_cyclic(ctlr->dma_rx, | |
990 | bs->clear_rx_addr + i * sizeof(u32), | |
991 | sizeof(u32), 0, | |
992 | DMA_MEM_TO_DEV, 0); | |
993 | if (!bs->clear_rx_desc[i]) { | |
994 | dev_err(dev, "cannot prepare clear_rx_desc - not using DMA mode\n"); | |
dd4441ab | 995 | ret = -ENOMEM; |
8259bf66 LW |
996 | goto err_release; |
997 | } | |
998 | ||
999 | ret = dmaengine_desc_set_reuse(bs->clear_rx_desc[i]); | |
1000 | if (ret) { | |
1001 | dev_err(dev, "cannot reuse clear_rx_desc - not using DMA mode\n"); | |
1002 | goto err_release; | |
1003 | } | |
1004 | } | |
1005 | ||
3ecd37ed | 1006 | /* all went well, so set can_dma */ |
5f336ea5 | 1007 | ctlr->can_dma = bcm2835_spi_can_dma; |
3ecd37ed | 1008 | |
6133fed0 | 1009 | return 0; |
3ecd37ed MS |
1010 | |
1011 | err_config: | |
1012 | dev_err(dev, "issue configuring dma: %d - not using DMA mode\n", | |
1013 | ret); | |
1014 | err_release: | |
8259bf66 | 1015 | bcm2835_dma_release(ctlr, bs); |
3ecd37ed | 1016 | err: |
6133fed0 PU |
1017 | /* |
1018 | * Only report error for deferred probing, otherwise fall back to | |
1019 | * interrupt mode | |
1020 | */ | |
1021 | if (ret != -EPROBE_DEFER) | |
1022 | ret = 0; | |
1023 | ||
1024 | return ret; | |
3ecd37ed MS |
1025 | } |
1026 | ||
5f336ea5 | 1027 | static int bcm2835_spi_transfer_one_poll(struct spi_controller *ctlr, |
a750b124 MS |
1028 | struct spi_device *spi, |
1029 | struct spi_transfer *tfr, | |
9ac3f90d | 1030 | u32 cs) |
a750b124 | 1031 | { |
5f336ea5 | 1032 | struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr); |
a750b124 MS |
1033 | unsigned long timeout; |
1034 | ||
154f7da5 MS |
1035 | /* update usage statistics */ |
1036 | bs->count_transfer_polling++; | |
1037 | ||
a750b124 MS |
1038 | /* enable HW block without interrupts */ |
1039 | bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA); | |
1040 | ||
1041 | /* fill in the fifo before timeout calculations | |
1042 | * if we are interrupted here, then the data is | |
1043 | * getting transferred by the HW while we are interrupted | |
1044 | */ | |
2e0733bc | 1045 | bcm2835_wr_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE); |
a750b124 | 1046 | |
ff245d90 MS |
1047 | /* set the timeout to at least 2 jiffies */ |
1048 | timeout = jiffies + 2 + HZ * polling_limit_us / 1000000; | |
a750b124 MS |
1049 | |
1050 | /* loop until finished the transfer */ | |
1051 | while (bs->rx_len) { | |
1052 | /* fill in tx fifo with remaining data */ | |
1053 | bcm2835_wr_fifo(bs); | |
1054 | ||
1055 | /* read from fifo as much as possible */ | |
1056 | bcm2835_rd_fifo(bs); | |
1057 | ||
1058 | /* if there is still data pending to read | |
1059 | * then check the timeout | |
1060 | */ | |
1061 | if (bs->rx_len && time_after(jiffies, timeout)) { | |
1062 | dev_dbg_ratelimited(&spi->dev, | |
1063 | "timeout period reached: jiffies: %lu remaining tx/rx: %d/%d - falling back to interrupt mode\n", | |
1064 | jiffies - timeout, | |
1065 | bs->tx_len, bs->rx_len); | |
1066 | /* fall back to interrupt mode */ | |
154f7da5 MS |
1067 | |
1068 | /* update usage statistics */ | |
1069 | bs->count_transfer_irq_after_polling++; | |
1070 | ||
5f336ea5 | 1071 | return bcm2835_spi_transfer_one_irq(ctlr, spi, |
2e0733bc | 1072 | tfr, cs, false); |
a750b124 MS |
1073 | } |
1074 | } | |
1075 | ||
1076 | /* Transfer complete - reset SPI HW */ | |
5f336ea5 | 1077 | bcm2835_spi_reset_hw(ctlr); |
a750b124 MS |
1078 | /* and return without waiting for completion */ |
1079 | return 0; | |
1080 | } | |
1081 | ||
5f336ea5 | 1082 | static int bcm2835_spi_transfer_one(struct spi_controller *ctlr, |
e34ff011 MS |
1083 | struct spi_device *spi, |
1084 | struct spi_transfer *tfr) | |
f8043872 | 1085 | { |
5f336ea5 | 1086 | struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr); |
ff245d90 MS |
1087 | unsigned long spi_hz, clk_hz, cdiv, spi_used_hz; |
1088 | unsigned long hz_per_byte, byte_limit; | |
571e31fa | 1089 | u32 cs = bs->prepare_cs[spi->chip_select]; |
f8043872 | 1090 | |
e34ff011 | 1091 | /* set clock */ |
f8043872 CB |
1092 | spi_hz = tfr->speed_hz; |
1093 | clk_hz = clk_get_rate(bs->clk); | |
1094 | ||
1095 | if (spi_hz >= clk_hz / 2) { | |
1096 | cdiv = 2; /* clk_hz/2 is the fastest we can go */ | |
1097 | } else if (spi_hz) { | |
210b4923 MS |
1098 | /* CDIV must be a multiple of two */ |
1099 | cdiv = DIV_ROUND_UP(clk_hz, spi_hz); | |
1100 | cdiv += (cdiv % 2); | |
f8043872 CB |
1101 | |
1102 | if (cdiv >= 65536) | |
1103 | cdiv = 0; /* 0 is the slowest we can go */ | |
342f948a | 1104 | } else { |
f8043872 | 1105 | cdiv = 0; /* 0 is the slowest we can go */ |
342f948a | 1106 | } |
704f32d4 | 1107 | spi_used_hz = cdiv ? (clk_hz / cdiv) : (clk_hz / 65536); |
e34ff011 | 1108 | bcm2835_wr(bs, BCM2835_SPI_CLK, cdiv); |
f8043872 | 1109 | |
acace73d | 1110 | /* handle all the 3-wire mode */ |
8259bf66 | 1111 | if (spi->mode & SPI_3WIRE && tfr->rx_buf) |
6935224d | 1112 | cs |= BCM2835_SPI_CS_REN; |
f8043872 | 1113 | |
e34ff011 | 1114 | /* set transmit buffers and length */ |
f8043872 CB |
1115 | bs->tx_buf = tfr->tx_buf; |
1116 | bs->rx_buf = tfr->rx_buf; | |
e34ff011 MS |
1117 | bs->tx_len = tfr->len; |
1118 | bs->rx_len = tfr->len; | |
f8043872 | 1119 | |
7f1922eb MS |
1120 | /* Calculate the estimated time in us the transfer runs. Note that |
1121 | * there is 1 idle clocks cycles after each byte getting transferred | |
1122 | * so we have 9 cycles/byte. This is used to find the number of Hz | |
1123 | * per byte per polling limit. E.g., we can transfer 1 byte in 30 us | |
1124 | * per 300,000 Hz of bus clock. | |
1125 | */ | |
ff245d90 MS |
1126 | hz_per_byte = polling_limit_us ? (9 * 1000000) / polling_limit_us : 0; |
1127 | byte_limit = hz_per_byte ? spi_used_hz / hz_per_byte : 1; | |
1128 | ||
7f1922eb | 1129 | /* run in polling mode for short transfers */ |
ff245d90 | 1130 | if (tfr->len < byte_limit) |
5f336ea5 | 1131 | return bcm2835_spi_transfer_one_poll(ctlr, spi, tfr, cs); |
f8043872 | 1132 | |
c41d62b0 MS |
1133 | /* run in dma mode if conditions are right |
1134 | * Note that unlike poll or interrupt mode DMA mode does not have | |
1135 | * this 1 idle clock cycle pattern but runs the spi clock without gaps | |
1136 | */ | |
5f336ea5 LW |
1137 | if (ctlr->can_dma && bcm2835_spi_can_dma(ctlr, spi, tfr)) |
1138 | return bcm2835_spi_transfer_one_dma(ctlr, spi, tfr, cs); | |
3ecd37ed MS |
1139 | |
1140 | /* run in interrupt-mode */ | |
5f336ea5 | 1141 | return bcm2835_spi_transfer_one_irq(ctlr, spi, tfr, cs, true); |
f8043872 CB |
1142 | } |
1143 | ||
5f336ea5 | 1144 | static int bcm2835_spi_prepare_message(struct spi_controller *ctlr, |
acace73d MS |
1145 | struct spi_message *msg) |
1146 | { | |
1147 | struct spi_device *spi = msg->spi; | |
5f336ea5 | 1148 | struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr); |
8b7bd10e MM |
1149 | int ret; |
1150 | ||
5f336ea5 | 1151 | if (ctlr->can_dma) { |
3393f7d9 NSJ |
1152 | /* |
1153 | * DMA transfers are limited to 16 bit (0 to 65535 bytes) by | |
1154 | * the SPI HW due to DLEN. Split up transfers (32-bit FIFO | |
1155 | * aligned) if the limit is exceeded. | |
1156 | */ | |
5f336ea5 | 1157 | ret = spi_split_transfers_maxsize(ctlr, msg, 65532, |
3393f7d9 NSJ |
1158 | GFP_KERNEL | GFP_DMA); |
1159 | if (ret) | |
1160 | return ret; | |
1161 | } | |
acace73d | 1162 | |
571e31fa LW |
1163 | /* |
1164 | * Set up clock polarity before spi_transfer_one_message() asserts | |
1165 | * chip select to avoid a gratuitous clock signal edge. | |
1166 | */ | |
1167 | bcm2835_wr(bs, BCM2835_SPI_CS, bs->prepare_cs[spi->chip_select]); | |
acace73d MS |
1168 | |
1169 | return 0; | |
1170 | } | |
1171 | ||
5f336ea5 | 1172 | static void bcm2835_spi_handle_err(struct spi_controller *ctlr, |
e34ff011 | 1173 | struct spi_message *msg) |
f8043872 | 1174 | { |
5f336ea5 | 1175 | struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr); |
3ecd37ed MS |
1176 | |
1177 | /* if an error occurred and we have an active dma, then terminate */ | |
1513ceee | 1178 | dmaengine_terminate_sync(ctlr->dma_tx); |
8259bf66 | 1179 | bs->tx_dma_active = false; |
1513ceee | 1180 | dmaengine_terminate_sync(ctlr->dma_rx); |
8259bf66 | 1181 | bs->rx_dma_active = false; |
1513ceee LW |
1182 | bcm2835_spi_undo_prologue(bs); |
1183 | ||
3ecd37ed | 1184 | /* and reset */ |
5f336ea5 | 1185 | bcm2835_spi_reset_hw(ctlr); |
f8043872 CB |
1186 | } |
1187 | ||
a30a555d MS |
1188 | static int chip_match_name(struct gpio_chip *chip, void *data) |
1189 | { | |
1190 | return !strcmp(chip->label, data); | |
1191 | } | |
1192 | ||
e34ff011 MS |
1193 | static int bcm2835_spi_setup(struct spi_device *spi) |
1194 | { | |
8259bf66 LW |
1195 | struct spi_controller *ctlr = spi->controller; |
1196 | struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr); | |
a30a555d | 1197 | struct gpio_chip *chip; |
3bd158c5 | 1198 | enum gpio_lookup_flags lflags; |
571e31fa LW |
1199 | u32 cs; |
1200 | ||
1201 | /* | |
1202 | * Precalculate SPI slave's CS register value for ->prepare_message(): | |
1203 | * The driver always uses software-controlled GPIO chip select, hence | |
1204 | * set the hardware-controlled native chip select to an invalid value | |
1205 | * to prevent it from interfering. | |
1206 | */ | |
1207 | cs = BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01; | |
1208 | if (spi->mode & SPI_CPOL) | |
1209 | cs |= BCM2835_SPI_CS_CPOL; | |
1210 | if (spi->mode & SPI_CPHA) | |
1211 | cs |= BCM2835_SPI_CS_CPHA; | |
1212 | bs->prepare_cs[spi->chip_select] = cs; | |
3bd158c5 | 1213 | |
8259bf66 LW |
1214 | /* |
1215 | * Precalculate SPI slave's CS register value to clear RX FIFO | |
1216 | * in case of a TX-only DMA transfer. | |
1217 | */ | |
1218 | if (ctlr->dma_rx) { | |
1219 | bs->clear_rx_cs[spi->chip_select] = cs | | |
1220 | BCM2835_SPI_CS_TA | | |
1221 | BCM2835_SPI_CS_DMAEN | | |
1222 | BCM2835_SPI_CS_CLEAR_RX; | |
1223 | dma_sync_single_for_device(ctlr->dma_rx->device->dev, | |
1224 | bs->clear_rx_addr, | |
1225 | sizeof(bs->clear_rx_cs), | |
1226 | DMA_TO_DEVICE); | |
1227 | } | |
1228 | ||
e34ff011 MS |
1229 | /* |
1230 | * sanity checking the native-chipselects | |
1231 | */ | |
1232 | if (spi->mode & SPI_NO_CS) | |
1233 | return 0; | |
3bd158c5 LW |
1234 | /* |
1235 | * The SPI core has successfully requested the CS GPIO line from the | |
1236 | * device tree, so we are done. | |
1237 | */ | |
1238 | if (spi->cs_gpiod) | |
e34ff011 | 1239 | return 0; |
a30a555d MS |
1240 | if (spi->chip_select > 1) { |
1241 | /* error in the case of native CS requested with CS > 1 | |
1242 | * officially there is a CS2, but it is not documented | |
1243 | * which GPIO is connected with that... | |
1244 | */ | |
1245 | dev_err(&spi->dev, | |
1246 | "setup: only two native chip-selects are supported\n"); | |
1247 | return -EINVAL; | |
1248 | } | |
3bd158c5 LW |
1249 | |
1250 | /* | |
1251 | * Translate native CS to GPIO | |
1252 | * | |
1253 | * FIXME: poking around in the gpiolib internals like this is | |
1254 | * not very good practice. Find a way to locate the real problem | |
1255 | * and fix it. Why is the GPIO descriptor in spi->cs_gpiod | |
1256 | * sometimes not assigned correctly? Erroneous device trees? | |
1257 | */ | |
a30a555d MS |
1258 | |
1259 | /* get the gpio chip for the base */ | |
1260 | chip = gpiochip_find("pinctrl-bcm2835", chip_match_name); | |
1261 | if (!chip) | |
e34ff011 MS |
1262 | return 0; |
1263 | ||
3bd158c5 LW |
1264 | /* |
1265 | * Retrieve the corresponding GPIO line used for CS. | |
1266 | * The inversion semantics will be handled by the GPIO core | |
c2f102f1 | 1267 | * code, so we pass GPIOD_OUT_LOW for "unasserted" and |
3bd158c5 LW |
1268 | * the correct flag for inversion semantics. The SPI_CS_HIGH |
1269 | * on spi->mode cannot be checked for polarity in this case | |
1270 | * as the flag use_gpio_descriptors enforces SPI_CS_HIGH. | |
1271 | */ | |
1272 | if (of_property_read_bool(spi->dev.of_node, "spi-cs-high")) | |
1273 | lflags = GPIO_ACTIVE_HIGH; | |
1274 | else | |
1275 | lflags = GPIO_ACTIVE_LOW; | |
1276 | spi->cs_gpiod = gpiochip_request_own_desc(chip, 8 - spi->chip_select, | |
1277 | DRV_NAME, | |
1278 | lflags, | |
1279 | GPIOD_OUT_LOW); | |
1280 | if (IS_ERR(spi->cs_gpiod)) | |
1281 | return PTR_ERR(spi->cs_gpiod); | |
a30a555d MS |
1282 | |
1283 | /* and set up the "mode" and level */ | |
3bd158c5 LW |
1284 | dev_info(&spi->dev, "setting up native-CS%i to use GPIO\n", |
1285 | spi->chip_select); | |
a30a555d MS |
1286 | |
1287 | return 0; | |
f8043872 CB |
1288 | } |
1289 | ||
1290 | static int bcm2835_spi_probe(struct platform_device *pdev) | |
1291 | { | |
5f336ea5 | 1292 | struct spi_controller *ctlr; |
f8043872 | 1293 | struct bcm2835_spi *bs; |
f8043872 CB |
1294 | int err; |
1295 | ||
8259bf66 LW |
1296 | ctlr = spi_alloc_master(&pdev->dev, ALIGN(sizeof(*bs), |
1297 | dma_get_cache_alignment())); | |
5f336ea5 | 1298 | if (!ctlr) |
f8043872 | 1299 | return -ENOMEM; |
f8043872 | 1300 | |
5f336ea5 | 1301 | platform_set_drvdata(pdev, ctlr); |
f8043872 | 1302 | |
3bd158c5 | 1303 | ctlr->use_gpio_descriptors = true; |
5f336ea5 LW |
1304 | ctlr->mode_bits = BCM2835_SPI_MODE_BITS; |
1305 | ctlr->bits_per_word_mask = SPI_BPW_MASK(8); | |
571e31fa | 1306 | ctlr->num_chipselect = BCM2835_SPI_NUM_CS; |
5f336ea5 LW |
1307 | ctlr->setup = bcm2835_spi_setup; |
1308 | ctlr->transfer_one = bcm2835_spi_transfer_one; | |
1309 | ctlr->handle_err = bcm2835_spi_handle_err; | |
1310 | ctlr->prepare_message = bcm2835_spi_prepare_message; | |
1311 | ctlr->dev.of_node = pdev->dev.of_node; | |
f8043872 | 1312 | |
5f336ea5 | 1313 | bs = spi_controller_get_devdata(ctlr); |
f8043872 | 1314 | |
6ba794df | 1315 | bs->regs = devm_platform_ioremap_resource(pdev, 0); |
2d6e75e8 LN |
1316 | if (IS_ERR(bs->regs)) { |
1317 | err = PTR_ERR(bs->regs); | |
5f336ea5 | 1318 | goto out_controller_put; |
f8043872 CB |
1319 | } |
1320 | ||
1321 | bs->clk = devm_clk_get(&pdev->dev, NULL); | |
1322 | if (IS_ERR(bs->clk)) { | |
1323 | err = PTR_ERR(bs->clk); | |
f4dc4abd JQ |
1324 | if (err == -EPROBE_DEFER) |
1325 | dev_dbg(&pdev->dev, "could not get clk: %d\n", err); | |
1326 | else | |
1327 | dev_err(&pdev->dev, "could not get clk: %d\n", err); | |
5f336ea5 | 1328 | goto out_controller_put; |
f8043872 CB |
1329 | } |
1330 | ||
ddf0e1c2 | 1331 | bs->irq = platform_get_irq(pdev, 0); |
f8043872 | 1332 | if (bs->irq <= 0) { |
f8043872 | 1333 | err = bs->irq ? bs->irq : -ENODEV; |
5f336ea5 | 1334 | goto out_controller_put; |
f8043872 CB |
1335 | } |
1336 | ||
1337 | clk_prepare_enable(bs->clk); | |
1338 | ||
6133fed0 PU |
1339 | err = bcm2835_dma_init(ctlr, &pdev->dev, bs); |
1340 | if (err) | |
1341 | goto out_clk_disable; | |
ddf0e1c2 MS |
1342 | |
1343 | /* initialise the hardware with the default polarities */ | |
1344 | bcm2835_wr(bs, BCM2835_SPI_CS, | |
1345 | BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX); | |
1346 | ||
d62069c2 MB |
1347 | err = devm_request_irq(&pdev->dev, bs->irq, bcm2835_spi_interrupt, 0, |
1348 | dev_name(&pdev->dev), ctlr); | |
f8043872 CB |
1349 | if (err) { |
1350 | dev_err(&pdev->dev, "could not request IRQ: %d\n", err); | |
666224b4 | 1351 | goto out_dma_release; |
f8043872 CB |
1352 | } |
1353 | ||
9dd277ff | 1354 | err = spi_register_controller(ctlr); |
f8043872 | 1355 | if (err) { |
5f336ea5 LW |
1356 | dev_err(&pdev->dev, "could not register SPI controller: %d\n", |
1357 | err); | |
666224b4 | 1358 | goto out_dma_release; |
f8043872 CB |
1359 | } |
1360 | ||
154f7da5 MS |
1361 | bcm2835_debugfs_create(bs, dev_name(&pdev->dev)); |
1362 | ||
f8043872 CB |
1363 | return 0; |
1364 | ||
666224b4 PU |
1365 | out_dma_release: |
1366 | bcm2835_dma_release(ctlr, bs); | |
f8043872 CB |
1367 | out_clk_disable: |
1368 | clk_disable_unprepare(bs->clk); | |
5f336ea5 LW |
1369 | out_controller_put: |
1370 | spi_controller_put(ctlr); | |
f8043872 CB |
1371 | return err; |
1372 | } | |
1373 | ||
1374 | static int bcm2835_spi_remove(struct platform_device *pdev) | |
1375 | { | |
5f336ea5 LW |
1376 | struct spi_controller *ctlr = platform_get_drvdata(pdev); |
1377 | struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr); | |
f8043872 | 1378 | |
154f7da5 MS |
1379 | bcm2835_debugfs_remove(bs); |
1380 | ||
9dd277ff LW |
1381 | spi_unregister_controller(ctlr); |
1382 | ||
05897c71 LW |
1383 | bcm2835_dma_release(ctlr, bs); |
1384 | ||
f8043872 CB |
1385 | /* Clear FIFOs, and disable the HW block */ |
1386 | bcm2835_wr(bs, BCM2835_SPI_CS, | |
1387 | BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX); | |
1388 | ||
1389 | clk_disable_unprepare(bs->clk); | |
f8043872 CB |
1390 | |
1391 | return 0; | |
1392 | } | |
1393 | ||
118eb0e5 FF |
1394 | static void bcm2835_spi_shutdown(struct platform_device *pdev) |
1395 | { | |
1396 | int ret; | |
1397 | ||
1398 | ret = bcm2835_spi_remove(pdev); | |
1399 | if (ret) | |
1400 | dev_err(&pdev->dev, "failed to shutdown\n"); | |
1401 | } | |
1402 | ||
f8043872 CB |
1403 | static const struct of_device_id bcm2835_spi_match[] = { |
1404 | { .compatible = "brcm,bcm2835-spi", }, | |
1405 | {} | |
1406 | }; | |
1407 | MODULE_DEVICE_TABLE(of, bcm2835_spi_match); | |
1408 | ||
1409 | static struct platform_driver bcm2835_spi_driver = { | |
1410 | .driver = { | |
1411 | .name = DRV_NAME, | |
f8043872 CB |
1412 | .of_match_table = bcm2835_spi_match, |
1413 | }, | |
1414 | .probe = bcm2835_spi_probe, | |
1415 | .remove = bcm2835_spi_remove, | |
118eb0e5 | 1416 | .shutdown = bcm2835_spi_shutdown, |
f8043872 CB |
1417 | }; |
1418 | module_platform_driver(bcm2835_spi_driver); | |
1419 | ||
1420 | MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835"); | |
1421 | MODULE_AUTHOR("Chris Boot <bootc@bootc.net>"); | |
22bf6cd2 | 1422 | MODULE_LICENSE("GPL"); |