[thirdparty/kernel/linux.git] / drivers / spi / spi-bitbang.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Polling/bitbanging SPI host controller controller driver utilities
 */

#include <linux/spinlock.h>
#include <linux/workqueue.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/time64.h>

#include <linux/spi/spi.h>
#include <linux/spi/spi_bitbang.h>

#define SPI_BITBANG_CS_DELAY	100


/*----------------------------------------------------------------------*/

/*
 * FIRST PART (OPTIONAL):  word-at-a-time spi_transfer support.
 * Use this for GPIO or shift-register level hardware APIs.
 *
 * spi_bitbang_cs is in spi_device->controller_state, which is unavailable
 * to glue code.  These bitbang setup() and cleanup() routines are always
 * used, though maybe they're called from controller-aware code.
 *
 * chipselect() and friends may use spi_device->controller_data and
 * controller registers as appropriate.
 *
 *
 * NOTE:  SPI controller pins can often be used as GPIO pins instead,
 * which means you could use a bitbang driver either to get hardware
 * working quickly, or testing for differences that aren't speed related.
 */

struct spi_bitbang_cs {
	unsigned	nsecs;	/* (clock cycle time)/2 */
	u32		(*txrx_word)(struct spi_device *spi, unsigned nsecs,
					u32 word, u8 bits, unsigned flags);
	unsigned	(*txrx_bufs)(struct spi_device *,
					u32 (*txrx_word)(
						struct spi_device *spi,
						unsigned nsecs,
						u32 word, u8 bits,
						unsigned flags),
					unsigned, struct spi_transfer *,
					unsigned);
};

static unsigned bitbang_txrx_8(
	struct spi_device	*spi,
	u32			(*txrx_word)(struct spi_device *spi,
					unsigned nsecs,
					u32 word, u8 bits,
					unsigned flags),
	unsigned		ns,
	struct spi_transfer	*t,
	unsigned flags
)
{
	unsigned		bits = t->bits_per_word;
	unsigned		count = t->len;
	const u8		*tx = t->tx_buf;
	u8			*rx = t->rx_buf;

	while (likely(count > 0)) {
		u8		word = 0;

		if (tx)
			word = *tx++;
		word = txrx_word(spi, ns, word, bits, flags);
		if (rx)
			*rx++ = word;
		count -= 1;
	}
	return t->len - count;
}

static unsigned bitbang_txrx_16(
	struct spi_device	*spi,
	u32			(*txrx_word)(struct spi_device *spi,
					unsigned nsecs,
					u32 word, u8 bits,
					unsigned flags),
	unsigned		ns,
	struct spi_transfer	*t,
	unsigned flags
)
{
	unsigned		bits = t->bits_per_word;
	unsigned		count = t->len;
	const u16		*tx = t->tx_buf;
	u16			*rx = t->rx_buf;

	while (likely(count > 1)) {
		u16		word = 0;

		if (tx)
			word = *tx++;
		word = txrx_word(spi, ns, word, bits, flags);
		if (rx)
			*rx++ = word;
		count -= 2;
	}
	return t->len - count;
}

static unsigned bitbang_txrx_32(
	struct spi_device	*spi,
	u32			(*txrx_word)(struct spi_device *spi,
					unsigned nsecs,
					u32 word, u8 bits,
					unsigned flags),
	unsigned		ns,
	struct spi_transfer	*t,
	unsigned flags
)
{
	unsigned		bits = t->bits_per_word;
	unsigned		count = t->len;
	const u32		*tx = t->tx_buf;
	u32			*rx = t->rx_buf;

	while (likely(count > 3)) {
		u32		word = 0;

		if (tx)
			word = *tx++;
		word = txrx_word(spi, ns, word, bits, flags);
		if (rx)
			*rx++ = word;
		count -= 4;
	}
	return t->len - count;
}

int spi_bitbang_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
{
	struct spi_bitbang_cs	*cs = spi->controller_state;
	u8			bits_per_word;
	u32			hz;

	if (t) {
		bits_per_word = t->bits_per_word;
		hz = t->speed_hz;
	} else {
		bits_per_word = 0;
		hz = 0;
	}

	/* spi_transfer level calls that work per-word */
	if (!bits_per_word)
		bits_per_word = spi->bits_per_word;
	if (bits_per_word <= 8)
		cs->txrx_bufs = bitbang_txrx_8;
	else if (bits_per_word <= 16)
		cs->txrx_bufs = bitbang_txrx_16;
	else if (bits_per_word <= 32)
		cs->txrx_bufs = bitbang_txrx_32;
	else
		return -EINVAL;

	/* nsecs = (clock period)/2 */
	if (!hz)
		hz = spi->max_speed_hz;
	if (hz) {
		cs->nsecs = (NSEC_PER_SEC / 2) / hz;
		if (cs->nsecs > (MAX_UDELAY_MS * NSEC_PER_MSEC))
			return -EINVAL;
	}

	return 0;
}
EXPORT_SYMBOL_GPL(spi_bitbang_setup_transfer);

/*
 * spi_bitbang_setup - default setup for per-word I/O loops
 */
int spi_bitbang_setup(struct spi_device *spi)
{
	struct spi_bitbang_cs	*cs = spi->controller_state;
	struct spi_bitbang	*bitbang;
	bool			initial_setup = false;
	int			retval;

	bitbang = spi_controller_get_devdata(spi->controller);

	if (!cs) {
		cs = kzalloc(sizeof(*cs), GFP_KERNEL);
		if (!cs)
			return -ENOMEM;
		spi->controller_state = cs;
		initial_setup = true;
	}

	/* per-word shift register access, in hardware or bitbanging */
	cs->txrx_word = bitbang->txrx_word[spi->mode & (SPI_CPOL|SPI_CPHA)];
	if (!cs->txrx_word) {
		retval = -EINVAL;
		goto err_free;
	}

	if (bitbang->setup_transfer) {
		retval = bitbang->setup_transfer(spi, NULL);
		if (retval < 0)
			goto err_free;
	}

	dev_dbg(&spi->dev, "%s, %u nsec/bit\n", __func__, 2 * cs->nsecs);

	return 0;

err_free:
	if (initial_setup)
		kfree(cs);
	return retval;
}
EXPORT_SYMBOL_GPL(spi_bitbang_setup);

/*
 * spi_bitbang_cleanup - default cleanup for per-word I/O loops
 */
void spi_bitbang_cleanup(struct spi_device *spi)
{
	kfree(spi->controller_state);
}
EXPORT_SYMBOL_GPL(spi_bitbang_cleanup);

static int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t)
{
	struct spi_bitbang_cs	*cs = spi->controller_state;
	unsigned		nsecs = cs->nsecs;
	struct spi_bitbang	*bitbang;

	bitbang = spi_controller_get_devdata(spi->controller);
	if (bitbang->set_line_direction) {
		int err;

		err = bitbang->set_line_direction(spi, !!(t->tx_buf));
		if (err < 0)
			return err;
	}

	if (spi->mode & SPI_3WIRE) {
		unsigned flags;

		flags = t->tx_buf ? SPI_CONTROLLER_NO_RX : SPI_CONTROLLER_NO_TX;
		return cs->txrx_bufs(spi, cs->txrx_word, nsecs, t, flags);
	}
	return cs->txrx_bufs(spi, cs->txrx_word, nsecs, t, 0);
}

/*----------------------------------------------------------------------*/

/*
 * SECOND PART ... simple transfer queue runner.
 *
 * This costs a task context per controller, running the queue by
 * performing each transfer in sequence.  Smarter hardware can queue
 * several DMA transfers at once, and process several controller queues
 * in parallel; this driver doesn't match such hardware very well.
 *
 * Drivers can provide word-at-a-time i/o primitives, or provide
 * transfer-at-a-time ones to leverage dma or fifo hardware.
 */

static int spi_bitbang_prepare_hardware(struct spi_controller *spi)
{
	struct spi_bitbang	*bitbang;

	bitbang = spi_controller_get_devdata(spi);

	mutex_lock(&bitbang->lock);
	bitbang->busy = 1;
	mutex_unlock(&bitbang->lock);

	return 0;
}

static int spi_bitbang_transfer_one(struct spi_controller *ctlr,
				    struct spi_device *spi,
				    struct spi_transfer *transfer)
{
	struct spi_bitbang *bitbang = spi_controller_get_devdata(ctlr);
	int status = 0;

	if (bitbang->setup_transfer) {
		status = bitbang->setup_transfer(spi, transfer);
		if (status < 0)
			goto out;
	}

	if (transfer->len)
		status = bitbang->txrx_bufs(spi, transfer);

	if (status == transfer->len)
		status = 0;
	else if (status >= 0)
		status = -EREMOTEIO;

out:
	spi_finalize_current_transfer(ctlr);

	return status;
}

static int spi_bitbang_unprepare_hardware(struct spi_controller *spi)
{
	struct spi_bitbang	*bitbang;

	bitbang = spi_controller_get_devdata(spi);

	mutex_lock(&bitbang->lock);
	bitbang->busy = 0;
	mutex_unlock(&bitbang->lock);

	return 0;
}

static void spi_bitbang_set_cs(struct spi_device *spi, bool enable)
{
	struct spi_bitbang *bitbang = spi_controller_get_devdata(spi->controller);

	/* SPI core provides CS high / low, but bitbang driver
	 * expects CS active
	 * spi device driver takes care of handling SPI_CS_HIGH
	 */
	enable = (!!(spi->mode & SPI_CS_HIGH) == enable);

	ndelay(SPI_BITBANG_CS_DELAY);
	bitbang->chipselect(spi, enable ? BITBANG_CS_ACTIVE :
			    BITBANG_CS_INACTIVE);
	ndelay(SPI_BITBANG_CS_DELAY);
}

/*----------------------------------------------------------------------*/

int spi_bitbang_init(struct spi_bitbang *bitbang)
{
	struct spi_controller *ctlr = bitbang->ctlr;
	bool custom_cs;

	if (!ctlr)
		return -EINVAL;
	/*
	 * We only need the chipselect callback if we are actually using it.
	 * If we just use GPIO descriptors, it is surplus. If the
	 * SPI_CONTROLLER_GPIO_SS flag is set, we always need to call the
	 * driver-specific chipselect routine.
	 */
	custom_cs = (!ctlr->use_gpio_descriptors ||
		     (ctlr->flags & SPI_CONTROLLER_GPIO_SS));

	if (custom_cs && !bitbang->chipselect)
		return -EINVAL;

	mutex_init(&bitbang->lock);

	if (!ctlr->mode_bits)
		ctlr->mode_bits = SPI_CPOL | SPI_CPHA | bitbang->flags;

	if (ctlr->transfer || ctlr->transfer_one_message)
		return -EINVAL;

	ctlr->prepare_transfer_hardware = spi_bitbang_prepare_hardware;
	ctlr->unprepare_transfer_hardware = spi_bitbang_unprepare_hardware;
	ctlr->transfer_one = spi_bitbang_transfer_one;
	/*
	 * When using GPIO descriptors, the ->set_cs() callback doesn't even
	 * get called unless SPI_CONTROLLER_GPIO_SS is set.
	 */
	if (custom_cs)
		ctlr->set_cs = spi_bitbang_set_cs;

	if (!bitbang->txrx_bufs) {
		bitbang->use_dma = 0;
		bitbang->txrx_bufs = spi_bitbang_bufs;
		if (!ctlr->setup) {
			if (!bitbang->setup_transfer)
				bitbang->setup_transfer =
					 spi_bitbang_setup_transfer;
			ctlr->setup = spi_bitbang_setup;
			ctlr->cleanup = spi_bitbang_cleanup;
		}
	}

	return 0;
}
EXPORT_SYMBOL_GPL(spi_bitbang_init);

/**
 * spi_bitbang_start - start up a polled/bitbanging SPI host controller driver
 * @bitbang: driver handle
 *
 * Caller should have zero-initialized all parts of the structure, and then
 * provided callbacks for chip selection and I/O loops.  If the host controller has
 * a transfer method, its final step should call spi_bitbang_transfer(); or,
 * that's the default if the transfer routine is not initialized.  It should
 * also set up the bus number and number of chipselects.
 *
 * For i/o loops, provide callbacks either per-word (for bitbanging, or for
 * hardware that basically exposes a shift register) or per-spi_transfer
 * (which takes better advantage of hardware like fifos or DMA engines).
 *
 * Drivers using per-word I/O loops should use (or call) spi_bitbang_setup(),
 * spi_bitbang_cleanup() and spi_bitbang_setup_transfer() to handle those SPI
 * host controller methods.  Those methods are the defaults if the bitbang->txrx_bufs
 * routine isn't initialized.
 *
 * This routine registers the spi_controller, which will process requests in a
 * dedicated task, keeping IRQs unblocked most of the time.  To stop
 * processing those requests, call spi_bitbang_stop().
 *
 * On success, this routine will take a reference to the controller. The caller
 * is responsible for calling spi_bitbang_stop() to decrement the reference and
 * spi_controller_put() as counterpart of spi_alloc_host() to prevent a memory
 * leak.
 */
int spi_bitbang_start(struct spi_bitbang *bitbang)
{
	struct spi_controller *ctlr = bitbang->ctlr;
	int ret;

	ret = spi_bitbang_init(bitbang);
	if (ret)
		return ret;

	/* driver may get busy before register() returns, especially
	 * if someone registered boardinfo for devices
	 */
	ret = spi_register_controller(spi_controller_get(ctlr));
	if (ret)
		spi_controller_put(ctlr);

	return ret;
}
EXPORT_SYMBOL_GPL(spi_bitbang_start);

/*
 * spi_bitbang_stop - stops the task providing spi communication
 */
void spi_bitbang_stop(struct spi_bitbang *bitbang)
{
	spi_unregister_controller(bitbang->ctlr);
}
EXPORT_SYMBOL_GPL(spi_bitbang_stop);

MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Utilities for Bitbanging SPI host controllers");
Commit	Line	Data
c942fddf	1	// SPDX-License-Identifier: GPL-2.0-or-later
9904f22a	2	/*
8ee46db1	3	* Polling/bitbanging SPI host controller controller driver utilities
9904f22a DB	4	*/
9904f22a DB	5
9904f22a DB	6	#include <linux/spinlock.h>
	7	#include <linux/workqueue.h>
	8	#include <linux/interrupt.h>
d7614de4	9	#include <linux/module.h>
9904f22a DB	10	#include <linux/delay.h>
	11	#include <linux/errno.h>
	12	#include <linux/platform_device.h>
5a0e3ad6	13	#include <linux/slab.h>
645094b4	14	#include <linux/time64.h>
9904f22a DB	15
	16	#include <linux/spi/spi.h>
	17	#include <linux/spi/spi_bitbang.h>
	18
00376865 HK	19	#define SPI_BITBANG_CS_DELAY 100
00376865 HK	20
9904f22a DB	21
	22	/----------------------------------------------------------------------/
	23
	24	/*
	25	* FIRST PART (OPTIONAL): word-at-a-time spi_transfer support.
	26	* Use this for GPIO or shift-register level hardware APIs.
	27	*
	28	* spi_bitbang_cs is in spi_device->controller_state, which is unavailable
	29	* to glue code. These bitbang setup() and cleanup() routines are always
	30	* used, though maybe they're called from controller-aware code.
	31	*
03ddcbc5	32	* chipselect() and friends may use spi_device->controller_data and
9904f22a DB	33	* controller registers as appropriate.
	34	*
	35	*
	36	* NOTE: SPI controller pins can often be used as GPIO pins instead,
	37	* which means you could use a bitbang driver either to get hardware
	38	* working quickly, or testing for differences that aren't speed related.
	39	*/
	40
	41	struct spi_bitbang_cs {
	42	unsigned nsecs; /* (clock cycle time)/2 */
	43	u32 (txrx_word)(struct spi_device spi, unsigned nsecs,
304d3436	44	u32 word, u8 bits, unsigned flags);
9904f22a DB	45	unsigned (txrx_bufs)(struct spi_device ,
	46	u32 (*txrx_word)(
	47	struct spi_device *spi,
	48	unsigned nsecs,
304d3436 LB	49	u32 word, u8 bits,
	50	unsigned flags),
	51	unsigned, struct spi_transfer *,
	52	unsigned);
9904f22a DB	53	};
	54
	55	static unsigned bitbang_txrx_8(
	56	struct spi_device *spi,
	57	u32 (txrx_word)(struct spi_device spi,
	58	unsigned nsecs,
304d3436 LB	59	u32 word, u8 bits,
304d3436 LB	60	unsigned flags),
9904f22a	61	unsigned ns,
304d3436 LB	62	struct spi_transfer *t,
304d3436 LB	63	unsigned flags
f96c19fa JF	64	)
f96c19fa JF	65	{
766ed704	66	unsigned bits = t->bits_per_word;
9904f22a DB	67	unsigned count = t->len;
	68	const u8 *tx = t->tx_buf;
	69	u8 *rx = t->rx_buf;
	70
	71	while (likely(count > 0)) {
	72	u8 word = 0;
	73
	74	if (tx)
	75	word = *tx++;
304d3436	76	word = txrx_word(spi, ns, word, bits, flags);
9904f22a DB	77	if (rx)
	78	*rx++ = word;
	79	count -= 1;
	80	}
	81	return t->len - count;
	82	}
	83
	84	static unsigned bitbang_txrx_16(
	85	struct spi_device *spi,
	86	u32 (txrx_word)(struct spi_device spi,
	87	unsigned nsecs,
304d3436 LB	88	u32 word, u8 bits,
304d3436 LB	89	unsigned flags),
9904f22a	90	unsigned ns,
304d3436 LB	91	struct spi_transfer *t,
304d3436 LB	92	unsigned flags
f96c19fa JF	93	)
f96c19fa JF	94	{
766ed704	95	unsigned bits = t->bits_per_word;
9904f22a DB	96	unsigned count = t->len;
	97	const u16 *tx = t->tx_buf;
	98	u16 *rx = t->rx_buf;
	99
	100	while (likely(count > 1)) {
	101	u16 word = 0;
	102
	103	if (tx)
	104	word = *tx++;
304d3436	105	word = txrx_word(spi, ns, word, bits, flags);
9904f22a DB	106	if (rx)
	107	*rx++ = word;
	108	count -= 2;
	109	}
	110	return t->len - count;
	111	}
	112
	113	static unsigned bitbang_txrx_32(
	114	struct spi_device *spi,
	115	u32 (txrx_word)(struct spi_device spi,
	116	unsigned nsecs,
304d3436 LB	117	u32 word, u8 bits,
304d3436 LB	118	unsigned flags),
9904f22a	119	unsigned ns,
304d3436 LB	120	struct spi_transfer *t,
304d3436 LB	121	unsigned flags
f96c19fa JF	122	)
f96c19fa JF	123	{
766ed704	124	unsigned bits = t->bits_per_word;
9904f22a DB	125	unsigned count = t->len;
	126	const u32 *tx = t->tx_buf;
	127	u32 *rx = t->rx_buf;
	128
	129	while (likely(count > 3)) {
	130	u32 word = 0;
	131
	132	if (tx)
	133	word = *tx++;
304d3436	134	word = txrx_word(spi, ns, word, bits, flags);
9904f22a DB	135	if (rx)
	136	*rx++ = word;
	137	count -= 4;
	138	}
	139	return t->len - count;
	140	}
	141
ff9f4771	142	int spi_bitbang_setup_transfer(struct spi_device spi, struct spi_transfer t)
4cff33f9 ID	143	{
	144	struct spi_bitbang_cs *cs = spi->controller_state;
	145	u8 bits_per_word;
	146	u32 hz;
	147
	148	if (t) {
	149	bits_per_word = t->bits_per_word;
	150	hz = t->speed_hz;
	151	} else {
	152	bits_per_word = 0;
	153	hz = 0;
	154	}
	155
	156	/* spi_transfer level calls that work per-word */
	157	if (!bits_per_word)
	158	bits_per_word = spi->bits_per_word;
	159	if (bits_per_word <= 8)
	160	cs->txrx_bufs = bitbang_txrx_8;
	161	else if (bits_per_word <= 16)
	162	cs->txrx_bufs = bitbang_txrx_16;
	163	else if (bits_per_word <= 32)
	164	cs->txrx_bufs = bitbang_txrx_32;
	165	else
	166	return -EINVAL;
	167
	168	/* nsecs = (clock period)/2 */
	169	if (!hz)
	170	hz = spi->max_speed_hz;
1e316d75	171	if (hz) {
645094b4 AS	172	cs->nsecs = (NSEC_PER_SEC / 2) / hz;
645094b4 AS	173	if (cs->nsecs > (MAX_UDELAY_MS * NSEC_PER_MSEC))
1e316d75 DB	174	return -EINVAL;
1e316d75 DB	175	}
4cff33f9 ID	176
	177	return 0;
	178	}
ff9f4771	179	EXPORT_SYMBOL_GPL(spi_bitbang_setup_transfer);
4cff33f9	180
c13b5044	181	/*
9904f22a DB	182	* spi_bitbang_setup - default setup for per-word I/O loops
	183	*/
	184	int spi_bitbang_setup(struct spi_device *spi)
	185	{
	186	struct spi_bitbang_cs *cs = spi->controller_state;
	187	struct spi_bitbang *bitbang;
2ec6f20b LW	188	bool initial_setup = false;
2ec6f20b LW	189	int retval;
9904f22a	190
22592331	191	bitbang = spi_controller_get_devdata(spi->controller);
ccf77cc4	192
9904f22a	193	if (!cs) {
cff93c58	194	cs = kzalloc(sizeof(*cs), GFP_KERNEL);
9904f22a DB	195	if (!cs)
	196	return -ENOMEM;
	197	spi->controller_state = cs;
2ec6f20b	198	initial_setup = true;
9904f22a	199	}
9904f22a	200
9904f22a DB	201	/* per-word shift register access, in hardware or bitbanging */
9904f22a DB	202	cs->txrx_word = bitbang->txrx_word[spi->mode & (SPI_CPOL\|SPI_CPHA)];
2ec6f20b LW	203	if (!cs->txrx_word) {
	204	retval = -EINVAL;
	205	goto err_free;
	206	}
9904f22a	207
7d0ec8b6	208	if (bitbang->setup_transfer) {
2ec6f20b	209	retval = bitbang->setup_transfer(spi, NULL);
7d0ec8b6	210	if (retval < 0)
2ec6f20b	211	goto err_free;
7d0ec8b6	212	}
9904f22a	213
7d077197	214	dev_dbg(&spi->dev, "%s, %u nsec/bit\n", __func__, 2 * cs->nsecs);
9904f22a	215
9904f22a	216	return 0;
2ec6f20b LW	217
	218	err_free:
	219	if (initial_setup)
	220	kfree(cs);
	221	return retval;
9904f22a DB	222	}
	223	EXPORT_SYMBOL_GPL(spi_bitbang_setup);
	224
c13b5044	225	/*
9904f22a DB	226	* spi_bitbang_cleanup - default cleanup for per-word I/O loops
9904f22a DB	227	*/
0ffa0285	228	void spi_bitbang_cleanup(struct spi_device *spi)
9904f22a DB	229	{
	230	kfree(spi->controller_state);
	231	}
	232	EXPORT_SYMBOL_GPL(spi_bitbang_cleanup);
	233
	234	static int spi_bitbang_bufs(struct spi_device spi, struct spi_transfer t)
	235	{
	236	struct spi_bitbang_cs *cs = spi->controller_state;
	237	unsigned nsecs = cs->nsecs;
4b859db2 LB	238	struct spi_bitbang *bitbang;
4b859db2 LB	239
22592331	240	bitbang = spi_controller_get_devdata(spi->controller);
4b859db2 LB	241	if (bitbang->set_line_direction) {
4b859db2 LB	242	int err;
9904f22a	243
4b859db2 LB	244	err = bitbang->set_line_direction(spi, !!(t->tx_buf));
	245	if (err < 0)
	246	return err;
	247	}
	248
	249	if (spi->mode & SPI_3WIRE) {
	250	unsigned flags;
	251
c397f09e	252	flags = t->tx_buf ? SPI_CONTROLLER_NO_RX : SPI_CONTROLLER_NO_TX;
4b859db2 LB	253	return cs->txrx_bufs(spi, cs->txrx_word, nsecs, t, flags);
4b859db2 LB	254	}
304d3436	255	return cs->txrx_bufs(spi, cs->txrx_word, nsecs, t, 0);
9904f22a DB	256	}
	257
	258	/----------------------------------------------------------------------/
	259
	260	/*
	261	* SECOND PART ... simple transfer queue runner.
	262	*
	263	* This costs a task context per controller, running the queue by
	264	* performing each transfer in sequence. Smarter hardware can queue
	265	* several DMA transfers at once, and process several controller queues
	266	* in parallel; this driver doesn't match such hardware very well.
	267	*
	268	* Drivers can provide word-at-a-time i/o primitives, or provide
	269	* transfer-at-a-time ones to leverage dma or fifo hardware.
	270	*/
2025172e	271
22592331	272	static int spi_bitbang_prepare_hardware(struct spi_controller *spi)
2025172e	273	{
cff93c58	274	struct spi_bitbang *bitbang;
2025172e	275
22592331	276	bitbang = spi_controller_get_devdata(spi);
2025172e	277
c15f6ed3	278	mutex_lock(&bitbang->lock);
2025172e	279	bitbang->busy = 1;
c15f6ed3	280	mutex_unlock(&bitbang->lock);
2025172e MB	281
	282	return 0;
	283	}
	284
22592331	285	static int spi_bitbang_transfer_one(struct spi_controller *ctlr,
00376865 HK	286	struct spi_device *spi,
00376865 HK	287	struct spi_transfer *transfer)
9904f22a	288	{
22592331	289	struct spi_bitbang *bitbang = spi_controller_get_devdata(ctlr);
00376865	290	int status = 0;
91b30858	291
00376865 HK	292	if (bitbang->setup_transfer) {
	293	status = bitbang->setup_transfer(spi, transfer);
	294	if (status < 0)
	295	goto out;
91b30858 MB	296	}
91b30858 MB	297
00376865 HK	298	if (transfer->len)
00376865 HK	299	status = bitbang->txrx_bufs(spi, transfer);
91b30858	300
00376865 HK	301	if (status == transfer->len)
	302	status = 0;
	303	else if (status >= 0)
	304	status = -EREMOTEIO;
91b30858	305
00376865	306	out:
22592331	307	spi_finalize_current_transfer(ctlr);
9904f22a	308
2025172e	309	return status;
9904f22a DB	310	}
9904f22a DB	311
22592331	312	static int spi_bitbang_unprepare_hardware(struct spi_controller *spi)
9904f22a	313	{
cff93c58	314	struct spi_bitbang *bitbang;
9904f22a	315
22592331	316	bitbang = spi_controller_get_devdata(spi);
9904f22a	317
c15f6ed3	318	mutex_lock(&bitbang->lock);
2025172e	319	bitbang->busy = 0;
c15f6ed3	320	mutex_unlock(&bitbang->lock);
9904f22a	321
2025172e	322	return 0;
9904f22a	323	}
9904f22a	324
00376865 HK	325	static void spi_bitbang_set_cs(struct spi_device *spi, bool enable)
00376865 HK	326	{
22592331	327	struct spi_bitbang *bitbang = spi_controller_get_devdata(spi->controller);
00376865 HK	328
	329	/* SPI core provides CS high / low, but bitbang driver
	330	* expects CS active
	331	* spi device driver takes care of handling SPI_CS_HIGH
	332	*/
	333	enable = (!!(spi->mode & SPI_CS_HIGH) == enable);
	334
	335	ndelay(SPI_BITBANG_CS_DELAY);
	336	bitbang->chipselect(spi, enable ? BITBANG_CS_ACTIVE :
	337	BITBANG_CS_INACTIVE);
	338	ndelay(SPI_BITBANG_CS_DELAY);
	339	}
	340
9904f22a DB	341	/----------------------------------------------------------------------/
9904f22a DB	342
45beec35 AS	343	int spi_bitbang_init(struct spi_bitbang *bitbang)
45beec35 AS	344	{
22592331	345	struct spi_controller *ctlr = bitbang->ctlr;
4a07b8bc	346	bool custom_cs;
45beec35	347
22592331	348	if (!ctlr)
4a07b8bc LW	349	return -EINVAL;
	350	/*
	351	* We only need the chipselect callback if we are actually using it.
	352	* If we just use GPIO descriptors, it is surplus. If the
82238d2c	353	* SPI_CONTROLLER_GPIO_SS flag is set, we always need to call the
4a07b8bc LW	354	* driver-specific chipselect routine.
4a07b8bc LW	355	*/
22592331 UKK	356	custom_cs = (!ctlr->use_gpio_descriptors \|\|
22592331 UKK	357	(ctlr->flags & SPI_CONTROLLER_GPIO_SS));
4a07b8bc LW	358
4a07b8bc LW	359	if (custom_cs && !bitbang->chipselect)
45beec35 AS	360	return -EINVAL;
	361
	362	mutex_init(&bitbang->lock);
	363
22592331 UKK	364	if (!ctlr->mode_bits)
22592331 UKK	365	ctlr->mode_bits = SPI_CPOL \| SPI_CPHA \| bitbang->flags;
45beec35	366
22592331	367	if (ctlr->transfer \|\| ctlr->transfer_one_message)
45beec35 AS	368	return -EINVAL;
45beec35 AS	369
22592331 UKK	370	ctlr->prepare_transfer_hardware = spi_bitbang_prepare_hardware;
	371	ctlr->unprepare_transfer_hardware = spi_bitbang_unprepare_hardware;
	372	ctlr->transfer_one = spi_bitbang_transfer_one;
4a07b8bc LW	373	/*
4a07b8bc LW	374	* When using GPIO descriptors, the ->set_cs() callback doesn't even
82238d2c	375	* get called unless SPI_CONTROLLER_GPIO_SS is set.
4a07b8bc LW	376	*/
4a07b8bc LW	377	if (custom_cs)
22592331	378	ctlr->set_cs = spi_bitbang_set_cs;
45beec35 AS	379
	380	if (!bitbang->txrx_bufs) {
	381	bitbang->use_dma = 0;
	382	bitbang->txrx_bufs = spi_bitbang_bufs;
22592331	383	if (!ctlr->setup) {
45beec35 AS	384	if (!bitbang->setup_transfer)
	385	bitbang->setup_transfer =
	386	spi_bitbang_setup_transfer;
22592331 UKK	387	ctlr->setup = spi_bitbang_setup;
22592331 UKK	388	ctlr->cleanup = spi_bitbang_cleanup;
45beec35 AS	389	}
	390	}
	391
	392	return 0;
	393	}
	394	EXPORT_SYMBOL_GPL(spi_bitbang_init);
	395
9904f22a	396	/**
8ee46db1	397	* spi_bitbang_start - start up a polled/bitbanging SPI host controller driver
9904f22a DB	398	* @bitbang: driver handle
	399	*
	400	* Caller should have zero-initialized all parts of the structure, and then
8ee46db1 AS	401	* provided callbacks for chip selection and I/O loops. If the host controller has
8ee46db1 AS	402	* a transfer method, its final step should call spi_bitbang_transfer(); or,
9904f22a DB	403	* that's the default if the transfer routine is not initialized. It should
	404	* also set up the bus number and number of chipselects.
	405	*
	406	* For i/o loops, provide callbacks either per-word (for bitbanging, or for
	407	* hardware that basically exposes a shift register) or per-spi_transfer
	408	* (which takes better advantage of hardware like fifos or DMA engines).
	409	*
8ee46db1 AS	410	* Drivers using per-word I/O loops should use (or call) spi_bitbang_setup(),
	411	* spi_bitbang_cleanup() and spi_bitbang_setup_transfer() to handle those SPI
	412	* host controller methods. Those methods are the defaults if the bitbang->txrx_bufs
7f8c7619	413	* routine isn't initialized.
9904f22a	414	*
22592331	415	* This routine registers the spi_controller, which will process requests in a
9904f22a DB	416	* dedicated task, keeping IRQs unblocked most of the time. To stop
9904f22a DB	417	* processing those requests, call spi_bitbang_stop().
702a4879	418	*
22592331 UKK	419	* On success, this routine will take a reference to the controller. The caller
22592331 UKK	420	* is responsible for calling spi_bitbang_stop() to decrement the reference and
8ee46db1	421	* spi_controller_put() as counterpart of spi_alloc_host() to prevent a memory
702a4879	422	* leak.
9904f22a DB	423	*/
	424	int spi_bitbang_start(struct spi_bitbang *bitbang)
	425	{
22592331	426	struct spi_controller *ctlr = bitbang->ctlr;
702a4879	427	int ret;
9904f22a	428
45beec35 AS	429	ret = spi_bitbang_init(bitbang);
	430	if (ret)
	431	return ret;
9904f22a DB	432
	433	/* driver may get busy before register() returns, especially
	434	* if someone registered boardinfo for devices
	435	*/
22592331	436	ret = spi_register_controller(spi_controller_get(ctlr));
702a4879	437	if (ret)
22592331	438	spi_controller_put(ctlr);
702a4879	439
5caaf29a	440	return ret;
9904f22a DB	441	}
	442	EXPORT_SYMBOL_GPL(spi_bitbang_start);
	443
c13b5044	444	/*
9904f22a DB	445	* spi_bitbang_stop - stops the task providing spi communication
9904f22a DB	446	*/
d9721ae1	447	void spi_bitbang_stop(struct spi_bitbang *bitbang)
9904f22a	448	{
22592331	449	spi_unregister_controller(bitbang->ctlr);
9904f22a DB	450	}
	451	EXPORT_SYMBOL_GPL(spi_bitbang_stop);
	452
	453	MODULE_LICENSE("GPL");
8ee46db1	454	MODULE_DESCRIPTION("Utilities for Bitbanging SPI host controllers");