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c942fddf | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
34b8c661 SK |
2 | /* |
3 | * Freescale/Motorola Coldfire Queued SPI driver | |
4 | * | |
5 | * Copyright 2010 Steven King <sfking@fdwdc.com> | |
34b8c661 SK |
6 | */ |
7 | ||
8 | #include <linux/kernel.h> | |
9 | #include <linux/module.h> | |
10 | #include <linux/interrupt.h> | |
11 | #include <linux/errno.h> | |
12 | #include <linux/platform_device.h> | |
5e1c5335 | 13 | #include <linux/sched.h> |
34b8c661 SK |
14 | #include <linux/delay.h> |
15 | #include <linux/io.h> | |
16 | #include <linux/clk.h> | |
17 | #include <linux/err.h> | |
18 | #include <linux/spi/spi.h> | |
bc98d13f | 19 | #include <linux/pm_runtime.h> |
34b8c661 SK |
20 | |
21 | #include <asm/coldfire.h> | |
0b4bf782 | 22 | #include <asm/mcfsim.h> |
34b8c661 SK |
23 | #include <asm/mcfqspi.h> |
24 | ||
25 | #define DRIVER_NAME "mcfqspi" | |
26 | ||
27 | #define MCFQSPI_BUSCLK (MCF_BUSCLK / 2) | |
28 | ||
29 | #define MCFQSPI_QMR 0x00 | |
30 | #define MCFQSPI_QMR_MSTR 0x8000 | |
31 | #define MCFQSPI_QMR_CPOL 0x0200 | |
32 | #define MCFQSPI_QMR_CPHA 0x0100 | |
33 | #define MCFQSPI_QDLYR 0x04 | |
34 | #define MCFQSPI_QDLYR_SPE 0x8000 | |
35 | #define MCFQSPI_QWR 0x08 | |
36 | #define MCFQSPI_QWR_HALT 0x8000 | |
37 | #define MCFQSPI_QWR_WREN 0x4000 | |
38 | #define MCFQSPI_QWR_CSIV 0x1000 | |
39 | #define MCFQSPI_QIR 0x0C | |
40 | #define MCFQSPI_QIR_WCEFB 0x8000 | |
41 | #define MCFQSPI_QIR_ABRTB 0x4000 | |
42 | #define MCFQSPI_QIR_ABRTL 0x1000 | |
43 | #define MCFQSPI_QIR_WCEFE 0x0800 | |
44 | #define MCFQSPI_QIR_ABRTE 0x0400 | |
45 | #define MCFQSPI_QIR_SPIFE 0x0100 | |
46 | #define MCFQSPI_QIR_WCEF 0x0008 | |
47 | #define MCFQSPI_QIR_ABRT 0x0004 | |
48 | #define MCFQSPI_QIR_SPIF 0x0001 | |
49 | #define MCFQSPI_QAR 0x010 | |
50 | #define MCFQSPI_QAR_TXBUF 0x00 | |
51 | #define MCFQSPI_QAR_RXBUF 0x10 | |
52 | #define MCFQSPI_QAR_CMDBUF 0x20 | |
53 | #define MCFQSPI_QDR 0x014 | |
54 | #define MCFQSPI_QCR 0x014 | |
55 | #define MCFQSPI_QCR_CONT 0x8000 | |
56 | #define MCFQSPI_QCR_BITSE 0x4000 | |
57 | #define MCFQSPI_QCR_DT 0x2000 | |
58 | ||
59 | struct mcfqspi { | |
60 | void __iomem *iobase; | |
61 | int irq; | |
62 | struct clk *clk; | |
63 | struct mcfqspi_cs_control *cs_control; | |
64 | ||
65 | wait_queue_head_t waitq; | |
34b8c661 SK |
66 | }; |
67 | ||
68 | static void mcfqspi_wr_qmr(struct mcfqspi *mcfqspi, u16 val) | |
69 | { | |
70 | writew(val, mcfqspi->iobase + MCFQSPI_QMR); | |
71 | } | |
72 | ||
73 | static void mcfqspi_wr_qdlyr(struct mcfqspi *mcfqspi, u16 val) | |
74 | { | |
75 | writew(val, mcfqspi->iobase + MCFQSPI_QDLYR); | |
76 | } | |
77 | ||
78 | static u16 mcfqspi_rd_qdlyr(struct mcfqspi *mcfqspi) | |
79 | { | |
80 | return readw(mcfqspi->iobase + MCFQSPI_QDLYR); | |
81 | } | |
82 | ||
83 | static void mcfqspi_wr_qwr(struct mcfqspi *mcfqspi, u16 val) | |
84 | { | |
85 | writew(val, mcfqspi->iobase + MCFQSPI_QWR); | |
86 | } | |
87 | ||
88 | static void mcfqspi_wr_qir(struct mcfqspi *mcfqspi, u16 val) | |
89 | { | |
90 | writew(val, mcfqspi->iobase + MCFQSPI_QIR); | |
91 | } | |
92 | ||
93 | static void mcfqspi_wr_qar(struct mcfqspi *mcfqspi, u16 val) | |
94 | { | |
95 | writew(val, mcfqspi->iobase + MCFQSPI_QAR); | |
96 | } | |
97 | ||
98 | static void mcfqspi_wr_qdr(struct mcfqspi *mcfqspi, u16 val) | |
99 | { | |
100 | writew(val, mcfqspi->iobase + MCFQSPI_QDR); | |
101 | } | |
102 | ||
103 | static u16 mcfqspi_rd_qdr(struct mcfqspi *mcfqspi) | |
104 | { | |
105 | return readw(mcfqspi->iobase + MCFQSPI_QDR); | |
106 | } | |
107 | ||
108 | static void mcfqspi_cs_select(struct mcfqspi *mcfqspi, u8 chip_select, | |
109 | bool cs_high) | |
110 | { | |
111 | mcfqspi->cs_control->select(mcfqspi->cs_control, chip_select, cs_high); | |
112 | } | |
113 | ||
114 | static void mcfqspi_cs_deselect(struct mcfqspi *mcfqspi, u8 chip_select, | |
115 | bool cs_high) | |
116 | { | |
117 | mcfqspi->cs_control->deselect(mcfqspi->cs_control, chip_select, cs_high); | |
118 | } | |
119 | ||
120 | static int mcfqspi_cs_setup(struct mcfqspi *mcfqspi) | |
121 | { | |
2271cf12 | 122 | return (mcfqspi->cs_control->setup) ? |
34b8c661 SK |
123 | mcfqspi->cs_control->setup(mcfqspi->cs_control) : 0; |
124 | } | |
125 | ||
126 | static void mcfqspi_cs_teardown(struct mcfqspi *mcfqspi) | |
127 | { | |
2271cf12 | 128 | if (mcfqspi->cs_control->teardown) |
34b8c661 SK |
129 | mcfqspi->cs_control->teardown(mcfqspi->cs_control); |
130 | } | |
131 | ||
132 | static u8 mcfqspi_qmr_baud(u32 speed_hz) | |
133 | { | |
134 | return clamp((MCFQSPI_BUSCLK + speed_hz - 1) / speed_hz, 2u, 255u); | |
135 | } | |
136 | ||
137 | static bool mcfqspi_qdlyr_spe(struct mcfqspi *mcfqspi) | |
138 | { | |
139 | return mcfqspi_rd_qdlyr(mcfqspi) & MCFQSPI_QDLYR_SPE; | |
140 | } | |
141 | ||
142 | static irqreturn_t mcfqspi_irq_handler(int this_irq, void *dev_id) | |
143 | { | |
144 | struct mcfqspi *mcfqspi = dev_id; | |
145 | ||
146 | /* clear interrupt */ | |
147 | mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE | MCFQSPI_QIR_SPIF); | |
148 | wake_up(&mcfqspi->waitq); | |
149 | ||
150 | return IRQ_HANDLED; | |
151 | } | |
152 | ||
153 | static void mcfqspi_transfer_msg8(struct mcfqspi *mcfqspi, unsigned count, | |
154 | const u8 *txbuf, u8 *rxbuf) | |
155 | { | |
156 | unsigned i, n, offset = 0; | |
157 | ||
158 | n = min(count, 16u); | |
159 | ||
160 | mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_CMDBUF); | |
161 | for (i = 0; i < n; ++i) | |
162 | mcfqspi_wr_qdr(mcfqspi, MCFQSPI_QCR_BITSE); | |
163 | ||
164 | mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_TXBUF); | |
165 | if (txbuf) | |
166 | for (i = 0; i < n; ++i) | |
167 | mcfqspi_wr_qdr(mcfqspi, *txbuf++); | |
168 | else | |
169 | for (i = 0; i < count; ++i) | |
170 | mcfqspi_wr_qdr(mcfqspi, 0); | |
171 | ||
172 | count -= n; | |
173 | if (count) { | |
174 | u16 qwr = 0xf08; | |
175 | mcfqspi_wr_qwr(mcfqspi, 0x700); | |
176 | mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE); | |
177 | ||
178 | do { | |
179 | wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi)); | |
180 | mcfqspi_wr_qwr(mcfqspi, qwr); | |
181 | mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE); | |
182 | if (rxbuf) { | |
183 | mcfqspi_wr_qar(mcfqspi, | |
184 | MCFQSPI_QAR_RXBUF + offset); | |
185 | for (i = 0; i < 8; ++i) | |
186 | *rxbuf++ = mcfqspi_rd_qdr(mcfqspi); | |
187 | } | |
188 | n = min(count, 8u); | |
189 | if (txbuf) { | |
190 | mcfqspi_wr_qar(mcfqspi, | |
191 | MCFQSPI_QAR_TXBUF + offset); | |
192 | for (i = 0; i < n; ++i) | |
193 | mcfqspi_wr_qdr(mcfqspi, *txbuf++); | |
194 | } | |
195 | qwr = (offset ? 0x808 : 0) + ((n - 1) << 8); | |
196 | offset ^= 8; | |
197 | count -= n; | |
198 | } while (count); | |
199 | wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi)); | |
200 | mcfqspi_wr_qwr(mcfqspi, qwr); | |
201 | mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE); | |
202 | if (rxbuf) { | |
203 | mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset); | |
204 | for (i = 0; i < 8; ++i) | |
205 | *rxbuf++ = mcfqspi_rd_qdr(mcfqspi); | |
206 | offset ^= 8; | |
207 | } | |
208 | } else { | |
209 | mcfqspi_wr_qwr(mcfqspi, (n - 1) << 8); | |
210 | mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE); | |
211 | } | |
212 | wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi)); | |
213 | if (rxbuf) { | |
214 | mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset); | |
215 | for (i = 0; i < n; ++i) | |
216 | *rxbuf++ = mcfqspi_rd_qdr(mcfqspi); | |
217 | } | |
218 | } | |
219 | ||
220 | static void mcfqspi_transfer_msg16(struct mcfqspi *mcfqspi, unsigned count, | |
221 | const u16 *txbuf, u16 *rxbuf) | |
222 | { | |
223 | unsigned i, n, offset = 0; | |
224 | ||
225 | n = min(count, 16u); | |
226 | ||
227 | mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_CMDBUF); | |
228 | for (i = 0; i < n; ++i) | |
229 | mcfqspi_wr_qdr(mcfqspi, MCFQSPI_QCR_BITSE); | |
230 | ||
231 | mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_TXBUF); | |
232 | if (txbuf) | |
233 | for (i = 0; i < n; ++i) | |
234 | mcfqspi_wr_qdr(mcfqspi, *txbuf++); | |
235 | else | |
236 | for (i = 0; i < count; ++i) | |
237 | mcfqspi_wr_qdr(mcfqspi, 0); | |
238 | ||
239 | count -= n; | |
240 | if (count) { | |
241 | u16 qwr = 0xf08; | |
242 | mcfqspi_wr_qwr(mcfqspi, 0x700); | |
243 | mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE); | |
244 | ||
245 | do { | |
246 | wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi)); | |
247 | mcfqspi_wr_qwr(mcfqspi, qwr); | |
248 | mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE); | |
249 | if (rxbuf) { | |
250 | mcfqspi_wr_qar(mcfqspi, | |
251 | MCFQSPI_QAR_RXBUF + offset); | |
252 | for (i = 0; i < 8; ++i) | |
253 | *rxbuf++ = mcfqspi_rd_qdr(mcfqspi); | |
254 | } | |
255 | n = min(count, 8u); | |
256 | if (txbuf) { | |
257 | mcfqspi_wr_qar(mcfqspi, | |
258 | MCFQSPI_QAR_TXBUF + offset); | |
259 | for (i = 0; i < n; ++i) | |
260 | mcfqspi_wr_qdr(mcfqspi, *txbuf++); | |
261 | } | |
262 | qwr = (offset ? 0x808 : 0x000) + ((n - 1) << 8); | |
263 | offset ^= 8; | |
264 | count -= n; | |
265 | } while (count); | |
266 | wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi)); | |
267 | mcfqspi_wr_qwr(mcfqspi, qwr); | |
268 | mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE); | |
269 | if (rxbuf) { | |
270 | mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset); | |
271 | for (i = 0; i < 8; ++i) | |
272 | *rxbuf++ = mcfqspi_rd_qdr(mcfqspi); | |
273 | offset ^= 8; | |
274 | } | |
275 | } else { | |
276 | mcfqspi_wr_qwr(mcfqspi, (n - 1) << 8); | |
277 | mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE); | |
278 | } | |
279 | wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi)); | |
280 | if (rxbuf) { | |
281 | mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset); | |
282 | for (i = 0; i < n; ++i) | |
283 | *rxbuf++ = mcfqspi_rd_qdr(mcfqspi); | |
284 | } | |
285 | } | |
286 | ||
3531b717 | 287 | static void mcfqspi_set_cs(struct spi_device *spi, bool enable) |
34b8c661 | 288 | { |
3531b717 AL |
289 | struct mcfqspi *mcfqspi = spi_master_get_devdata(spi->master); |
290 | bool cs_high = spi->mode & SPI_CS_HIGH; | |
bc98d13f | 291 | |
3531b717 | 292 | if (enable) |
bc98d13f | 293 | mcfqspi_cs_select(mcfqspi, spi->chip_select, cs_high); |
3531b717 AL |
294 | else |
295 | mcfqspi_cs_deselect(mcfqspi, spi->chip_select, cs_high); | |
296 | } | |
bc98d13f | 297 | |
3531b717 AL |
298 | static int mcfqspi_transfer_one(struct spi_master *master, |
299 | struct spi_device *spi, | |
300 | struct spi_transfer *t) | |
301 | { | |
302 | struct mcfqspi *mcfqspi = spi_master_get_devdata(master); | |
303 | u16 qmr = MCFQSPI_QMR_MSTR; | |
304 | ||
305 | qmr |= t->bits_per_word << 10; | |
306 | if (spi->mode & SPI_CPHA) | |
307 | qmr |= MCFQSPI_QMR_CPHA; | |
308 | if (spi->mode & SPI_CPOL) | |
309 | qmr |= MCFQSPI_QMR_CPOL; | |
8023d384 | 310 | qmr |= mcfqspi_qmr_baud(t->speed_hz); |
3531b717 | 311 | mcfqspi_wr_qmr(mcfqspi, qmr); |
bc98d13f | 312 | |
3531b717 AL |
313 | mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE); |
314 | if (t->bits_per_word == 8) | |
315 | mcfqspi_transfer_msg8(mcfqspi, t->len, t->tx_buf, t->rx_buf); | |
316 | else | |
317 | mcfqspi_transfer_msg16(mcfqspi, t->len / 2, t->tx_buf, | |
318 | t->rx_buf); | |
319 | mcfqspi_wr_qir(mcfqspi, 0); | |
bc98d13f | 320 | |
3531b717 | 321 | return 0; |
34b8c661 SK |
322 | } |
323 | ||
34b8c661 SK |
324 | static int mcfqspi_setup(struct spi_device *spi) |
325 | { | |
34b8c661 SK |
326 | mcfqspi_cs_deselect(spi_master_get_devdata(spi->master), |
327 | spi->chip_select, spi->mode & SPI_CS_HIGH); | |
328 | ||
329 | dev_dbg(&spi->dev, | |
330 | "bits per word %d, chip select %d, speed %d KHz\n", | |
331 | spi->bits_per_word, spi->chip_select, | |
332 | (MCFQSPI_BUSCLK / mcfqspi_qmr_baud(spi->max_speed_hz)) | |
333 | / 1000); | |
334 | ||
335 | return 0; | |
336 | } | |
337 | ||
fd4a319b | 338 | static int mcfqspi_probe(struct platform_device *pdev) |
34b8c661 SK |
339 | { |
340 | struct spi_master *master; | |
341 | struct mcfqspi *mcfqspi; | |
342 | struct resource *res; | |
343 | struct mcfqspi_platform_data *pdata; | |
344 | int status; | |
345 | ||
8074cf06 | 346 | pdata = dev_get_platdata(&pdev->dev); |
4a577f52 WY |
347 | if (!pdata) { |
348 | dev_dbg(&pdev->dev, "platform data is missing\n"); | |
349 | return -ENOENT; | |
350 | } | |
351 | ||
2271cf12 AL |
352 | if (!pdata->cs_control) { |
353 | dev_dbg(&pdev->dev, "pdata->cs_control is NULL\n"); | |
354 | return -EINVAL; | |
355 | } | |
356 | ||
34b8c661 SK |
357 | master = spi_alloc_master(&pdev->dev, sizeof(*mcfqspi)); |
358 | if (master == NULL) { | |
359 | dev_dbg(&pdev->dev, "spi_alloc_master failed\n"); | |
360 | return -ENOMEM; | |
361 | } | |
362 | ||
363 | mcfqspi = spi_master_get_devdata(master); | |
364 | ||
365 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
9a3ced19 JH |
366 | mcfqspi->iobase = devm_ioremap_resource(&pdev->dev, res); |
367 | if (IS_ERR(mcfqspi->iobase)) { | |
368 | status = PTR_ERR(mcfqspi->iobase); | |
34b8c661 SK |
369 | goto fail0; |
370 | } | |
371 | ||
34b8c661 SK |
372 | mcfqspi->irq = platform_get_irq(pdev, 0); |
373 | if (mcfqspi->irq < 0) { | |
374 | dev_dbg(&pdev->dev, "platform_get_irq failed\n"); | |
375 | status = -ENXIO; | |
9a3ced19 | 376 | goto fail0; |
34b8c661 SK |
377 | } |
378 | ||
9a3ced19 JH |
379 | status = devm_request_irq(&pdev->dev, mcfqspi->irq, mcfqspi_irq_handler, |
380 | 0, pdev->name, mcfqspi); | |
34b8c661 SK |
381 | if (status) { |
382 | dev_dbg(&pdev->dev, "request_irq failed\n"); | |
9a3ced19 | 383 | goto fail0; |
34b8c661 SK |
384 | } |
385 | ||
9a3ced19 | 386 | mcfqspi->clk = devm_clk_get(&pdev->dev, "qspi_clk"); |
34b8c661 SK |
387 | if (IS_ERR(mcfqspi->clk)) { |
388 | dev_dbg(&pdev->dev, "clk_get failed\n"); | |
389 | status = PTR_ERR(mcfqspi->clk); | |
9a3ced19 | 390 | goto fail0; |
34b8c661 SK |
391 | } |
392 | clk_enable(mcfqspi->clk); | |
393 | ||
34b8c661 SK |
394 | master->bus_num = pdata->bus_num; |
395 | master->num_chipselect = pdata->num_chipselect; | |
396 | ||
397 | mcfqspi->cs_control = pdata->cs_control; | |
398 | status = mcfqspi_cs_setup(mcfqspi); | |
399 | if (status) { | |
400 | dev_dbg(&pdev->dev, "error initializing cs_control\n"); | |
9a3ced19 | 401 | goto fail1; |
34b8c661 SK |
402 | } |
403 | ||
bc98d13f | 404 | init_waitqueue_head(&mcfqspi->waitq); |
bc98d13f | 405 | |
34b8c661 | 406 | master->mode_bits = SPI_CS_HIGH | SPI_CPOL | SPI_CPHA; |
24778be2 | 407 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16); |
34b8c661 | 408 | master->setup = mcfqspi_setup; |
3531b717 AL |
409 | master->set_cs = mcfqspi_set_cs; |
410 | master->transfer_one = mcfqspi_transfer_one; | |
3f36e80a | 411 | master->auto_runtime_pm = true; |
34b8c661 SK |
412 | |
413 | platform_set_drvdata(pdev, master); | |
f9b841af | 414 | pm_runtime_enable(&pdev->dev); |
34b8c661 | 415 | |
9a3ced19 | 416 | status = devm_spi_register_master(&pdev->dev, master); |
34b8c661 SK |
417 | if (status) { |
418 | dev_dbg(&pdev->dev, "spi_register_master failed\n"); | |
9a3ced19 | 419 | goto fail2; |
34b8c661 | 420 | } |
bc98d13f | 421 | |
34b8c661 SK |
422 | dev_info(&pdev->dev, "Coldfire QSPI bus driver\n"); |
423 | ||
424 | return 0; | |
425 | ||
34b8c661 | 426 | fail2: |
f9b841af | 427 | pm_runtime_disable(&pdev->dev); |
9a3ced19 | 428 | mcfqspi_cs_teardown(mcfqspi); |
34b8c661 | 429 | fail1: |
9a3ced19 | 430 | clk_disable(mcfqspi->clk); |
34b8c661 SK |
431 | fail0: |
432 | spi_master_put(master); | |
433 | ||
434 | dev_dbg(&pdev->dev, "Coldfire QSPI probe failed\n"); | |
435 | ||
436 | return status; | |
437 | } | |
438 | ||
fd4a319b | 439 | static int mcfqspi_remove(struct platform_device *pdev) |
34b8c661 SK |
440 | { |
441 | struct spi_master *master = platform_get_drvdata(pdev); | |
442 | struct mcfqspi *mcfqspi = spi_master_get_devdata(master); | |
34b8c661 | 443 | |
8bd31345 | 444 | pm_runtime_disable(&pdev->dev); |
34b8c661 SK |
445 | /* disable the hardware (set the baud rate to 0) */ |
446 | mcfqspi_wr_qmr(mcfqspi, MCFQSPI_QMR_MSTR); | |
447 | ||
34b8c661 | 448 | mcfqspi_cs_teardown(mcfqspi); |
34b8c661 | 449 | clk_disable(mcfqspi->clk); |
34b8c661 SK |
450 | |
451 | return 0; | |
452 | } | |
453 | ||
bc98d13f | 454 | #ifdef CONFIG_PM_SLEEP |
34b8c661 SK |
455 | static int mcfqspi_suspend(struct device *dev) |
456 | { | |
af361079 | 457 | struct spi_master *master = dev_get_drvdata(dev); |
bc98d13f | 458 | struct mcfqspi *mcfqspi = spi_master_get_devdata(master); |
2aa237f4 | 459 | int ret; |
bc98d13f | 460 | |
2aa237f4 AL |
461 | ret = spi_master_suspend(master); |
462 | if (ret) | |
463 | return ret; | |
34b8c661 SK |
464 | |
465 | clk_disable(mcfqspi->clk); | |
466 | ||
467 | return 0; | |
468 | } | |
469 | ||
470 | static int mcfqspi_resume(struct device *dev) | |
471 | { | |
af361079 | 472 | struct spi_master *master = dev_get_drvdata(dev); |
bc98d13f SK |
473 | struct mcfqspi *mcfqspi = spi_master_get_devdata(master); |
474 | ||
34b8c661 SK |
475 | clk_enable(mcfqspi->clk); |
476 | ||
2aa237f4 | 477 | return spi_master_resume(master); |
34b8c661 | 478 | } |
bc98d13f | 479 | #endif |
34b8c661 | 480 | |
ec833050 | 481 | #ifdef CONFIG_PM |
bc98d13f SK |
482 | static int mcfqspi_runtime_suspend(struct device *dev) |
483 | { | |
ee73b4c6 AL |
484 | struct spi_master *master = dev_get_drvdata(dev); |
485 | struct mcfqspi *mcfqspi = spi_master_get_devdata(master); | |
34b8c661 | 486 | |
bc98d13f SK |
487 | clk_disable(mcfqspi->clk); |
488 | ||
489 | return 0; | |
490 | } | |
491 | ||
492 | static int mcfqspi_runtime_resume(struct device *dev) | |
493 | { | |
ee73b4c6 AL |
494 | struct spi_master *master = dev_get_drvdata(dev); |
495 | struct mcfqspi *mcfqspi = spi_master_get_devdata(master); | |
bc98d13f SK |
496 | |
497 | clk_enable(mcfqspi->clk); | |
498 | ||
499 | return 0; | |
500 | } | |
34b8c661 SK |
501 | #endif |
502 | ||
bc98d13f SK |
503 | static const struct dev_pm_ops mcfqspi_pm = { |
504 | SET_SYSTEM_SLEEP_PM_OPS(mcfqspi_suspend, mcfqspi_resume) | |
505 | SET_RUNTIME_PM_OPS(mcfqspi_runtime_suspend, mcfqspi_runtime_resume, | |
506 | NULL) | |
507 | }; | |
508 | ||
34b8c661 SK |
509 | static struct platform_driver mcfqspi_driver = { |
510 | .driver.name = DRIVER_NAME, | |
511 | .driver.owner = THIS_MODULE, | |
bc98d13f | 512 | .driver.pm = &mcfqspi_pm, |
940ab889 | 513 | .probe = mcfqspi_probe, |
fd4a319b | 514 | .remove = mcfqspi_remove, |
34b8c661 | 515 | }; |
940ab889 | 516 | module_platform_driver(mcfqspi_driver); |
34b8c661 SK |
517 | |
518 | MODULE_AUTHOR("Steven King <sfking@fdwdc.com>"); | |
519 | MODULE_DESCRIPTION("Coldfire QSPI Controller Driver"); | |
520 | MODULE_LICENSE("GPL"); | |
521 | MODULE_ALIAS("platform:" DRIVER_NAME); |