[thirdparty/linux.git] / drivers / spi / spi-dw-mmio.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Memory-mapped interface driver for DW SPI Core
 *
 * Copyright (c) 2010, Octasic semiconductor.
 */

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include <linux/spi/spi.h>
#include <linux/scatterlist.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/acpi.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/reset.h>

#include "spi-dw.h"

#define DRIVER_NAME "dw_spi_mmio"

struct dw_spi_mmio {
	struct dw_spi  dws;
	struct clk     *clk;
	struct clk     *pclk;
	void           *priv;
	struct reset_control *rstc;
};

#define MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL	0x24
#define OCELOT_IF_SI_OWNER_OFFSET		4
#define JAGUAR2_IF_SI_OWNER_OFFSET		6
#define MSCC_IF_SI_OWNER_MASK			GENMASK(1, 0)
#define MSCC_IF_SI_OWNER_SISL			0
#define MSCC_IF_SI_OWNER_SIBM			1
#define MSCC_IF_SI_OWNER_SIMC			2

#define MSCC_SPI_MST_SW_MODE			0x14
#define MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE	BIT(13)
#define MSCC_SPI_MST_SW_MODE_SW_SPI_CS(x)	(x << 5)

/*
 * For Keem Bay, CTRLR0[31] is used to select controller mode.
 * 0: SSI is slave
 * 1: SSI is master
 */
#define KEEMBAY_CTRLR0_SSIC_IS_MST		BIT(31)

struct dw_spi_mscc {
	struct regmap       *syscon;
	void __iomem        *spi_mst;
};

/*
 * The Designware SPI controller (referred to as master in the documentation)
 * automatically deasserts chip select when the tx fifo is empty. The chip
 * selects then needs to be either driven as GPIOs or, for the first 4 using the
 * the SPI boot controller registers. the final chip select is an OR gate
 * between the Designware SPI controller and the SPI boot controller.
 */
static void dw_spi_mscc_set_cs(struct spi_device *spi, bool enable)
{
	struct dw_spi *dws = spi_master_get_devdata(spi->master);
	struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws);
	struct dw_spi_mscc *dwsmscc = dwsmmio->priv;
	u32 cs = spi->chip_select;

	if (cs < 4) {
		u32 sw_mode = MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE;

		if (!enable)
			sw_mode |= MSCC_SPI_MST_SW_MODE_SW_SPI_CS(BIT(cs));

		writel(sw_mode, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);
	}

	dw_spi_set_cs(spi, enable);
}

static int dw_spi_mscc_init(struct platform_device *pdev,
			    struct dw_spi_mmio *dwsmmio,
			    const char *cpu_syscon, u32 if_si_owner_offset)
{
	struct dw_spi_mscc *dwsmscc;

	dwsmscc = devm_kzalloc(&pdev->dev, sizeof(*dwsmscc), GFP_KERNEL);
	if (!dwsmscc)
		return -ENOMEM;

	dwsmscc->spi_mst = devm_platform_ioremap_resource(pdev, 1);
	if (IS_ERR(dwsmscc->spi_mst)) {
		dev_err(&pdev->dev, "SPI_MST region map failed\n");
		return PTR_ERR(dwsmscc->spi_mst);
	}

	dwsmscc->syscon = syscon_regmap_lookup_by_compatible(cpu_syscon);
	if (IS_ERR(dwsmscc->syscon))
		return PTR_ERR(dwsmscc->syscon);

	/* Deassert all CS */
	writel(0, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);

	/* Select the owner of the SI interface */
	regmap_update_bits(dwsmscc->syscon, MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL,
			   MSCC_IF_SI_OWNER_MASK << if_si_owner_offset,
			   MSCC_IF_SI_OWNER_SIMC << if_si_owner_offset);

	dwsmmio->dws.set_cs = dw_spi_mscc_set_cs;
	dwsmmio->priv = dwsmscc;

	/* Register hook to configure CTRLR0 */
	dwsmmio->dws.update_cr0 = dw_spi_update_cr0;

	return 0;
}

static int dw_spi_mscc_ocelot_init(struct platform_device *pdev,
				   struct dw_spi_mmio *dwsmmio)
{
	return dw_spi_mscc_init(pdev, dwsmmio, "mscc,ocelot-cpu-syscon",
				OCELOT_IF_SI_OWNER_OFFSET);
}

static int dw_spi_mscc_jaguar2_init(struct platform_device *pdev,
				    struct dw_spi_mmio *dwsmmio)
{
	return dw_spi_mscc_init(pdev, dwsmmio, "mscc,jaguar2-cpu-syscon",
				JAGUAR2_IF_SI_OWNER_OFFSET);
}

static int dw_spi_alpine_init(struct platform_device *pdev,
			      struct dw_spi_mmio *dwsmmio)
{
	dwsmmio->dws.cs_override = 1;

	/* Register hook to configure CTRLR0 */
	dwsmmio->dws.update_cr0 = dw_spi_update_cr0;

	return 0;
}

static int dw_spi_dw_apb_init(struct platform_device *pdev,
			      struct dw_spi_mmio *dwsmmio)
{
	/* Register hook to configure CTRLR0 */
	dwsmmio->dws.update_cr0 = dw_spi_update_cr0;

	dw_spi_dma_setup_generic(&dwsmmio->dws);

	return 0;
}

static int dw_spi_dwc_ssi_init(struct platform_device *pdev,
			       struct dw_spi_mmio *dwsmmio)
{
	/* Register hook to configure CTRLR0 */
	dwsmmio->dws.update_cr0 = dw_spi_update_cr0_v1_01a;

	dw_spi_dma_setup_generic(&dwsmmio->dws);

	return 0;
}

static u32 dw_spi_update_cr0_keembay(struct spi_controller *master,
				     struct spi_device *spi,
				     struct spi_transfer *transfer)
{
	u32 cr0 = dw_spi_update_cr0_v1_01a(master, spi, transfer);

	return cr0 | KEEMBAY_CTRLR0_SSIC_IS_MST;
}

static int dw_spi_keembay_init(struct platform_device *pdev,
			       struct dw_spi_mmio *dwsmmio)
{
	/* Register hook to configure CTRLR0 */
	dwsmmio->dws.update_cr0 = dw_spi_update_cr0_keembay;

	return 0;
}

static int dw_spi_mmio_probe(struct platform_device *pdev)
{
	int (*init_func)(struct platform_device *pdev,
			 struct dw_spi_mmio *dwsmmio);
	struct dw_spi_mmio *dwsmmio;
	struct resource *mem;
	struct dw_spi *dws;
	int ret;
	int num_cs;

	dwsmmio = devm_kzalloc(&pdev->dev, sizeof(struct dw_spi_mmio),
			GFP_KERNEL);
	if (!dwsmmio)
		return -ENOMEM;

	dws = &dwsmmio->dws;

	/* Get basic io resource and map it */
	dws->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
	if (IS_ERR(dws->regs))
		return PTR_ERR(dws->regs);

	dws->paddr = mem->start;

	dws->irq = platform_get_irq(pdev, 0);
	if (dws->irq < 0)
		return dws->irq; /* -ENXIO */

	dwsmmio->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(dwsmmio->clk))
		return PTR_ERR(dwsmmio->clk);
	ret = clk_prepare_enable(dwsmmio->clk);
	if (ret)
		return ret;

	/* Optional clock needed to access the registers */
	dwsmmio->pclk = devm_clk_get_optional(&pdev->dev, "pclk");
	if (IS_ERR(dwsmmio->pclk)) {
		ret = PTR_ERR(dwsmmio->pclk);
		goto out_clk;
	}
	ret = clk_prepare_enable(dwsmmio->pclk);
	if (ret)
		goto out_clk;

	/* find an optional reset controller */
	dwsmmio->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, "spi");
	if (IS_ERR(dwsmmio->rstc)) {
		ret = PTR_ERR(dwsmmio->rstc);
		goto out_clk;
	}
	reset_control_deassert(dwsmmio->rstc);

	dws->bus_num = pdev->id;

	dws->max_freq = clk_get_rate(dwsmmio->clk);

	device_property_read_u32(&pdev->dev, "reg-io-width", &dws->reg_io_width);

	num_cs = 4;

	device_property_read_u32(&pdev->dev, "num-cs", &num_cs);

	dws->num_cs = num_cs;

	init_func = device_get_match_data(&pdev->dev);
	if (init_func) {
		ret = init_func(pdev, dwsmmio);
		if (ret)
			goto out;
	}

	pm_runtime_enable(&pdev->dev);

	ret = dw_spi_add_host(&pdev->dev, dws);
	if (ret)
		goto out;

	platform_set_drvdata(pdev, dwsmmio);
	return 0;

out:
	pm_runtime_disable(&pdev->dev);
	clk_disable_unprepare(dwsmmio->pclk);
out_clk:
	clk_disable_unprepare(dwsmmio->clk);
	reset_control_assert(dwsmmio->rstc);

	return ret;
}

static int dw_spi_mmio_remove(struct platform_device *pdev)
{
	struct dw_spi_mmio *dwsmmio = platform_get_drvdata(pdev);

	dw_spi_remove_host(&dwsmmio->dws);
	pm_runtime_disable(&pdev->dev);
	clk_disable_unprepare(dwsmmio->pclk);
	clk_disable_unprepare(dwsmmio->clk);
	reset_control_assert(dwsmmio->rstc);

	return 0;
}

static const struct of_device_id dw_spi_mmio_of_match[] = {
	{ .compatible = "snps,dw-apb-ssi", .data = dw_spi_dw_apb_init},
	{ .compatible = "mscc,ocelot-spi", .data = dw_spi_mscc_ocelot_init},
	{ .compatible = "mscc,jaguar2-spi", .data = dw_spi_mscc_jaguar2_init},
	{ .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init},
	{ .compatible = "renesas,rzn1-spi", .data = dw_spi_dw_apb_init},
	{ .compatible = "snps,dwc-ssi-1.01a", .data = dw_spi_dwc_ssi_init},
	{ .compatible = "intel,keembay-ssi", .data = dw_spi_keembay_init},
	{ /* end of table */}
};
MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match);

#ifdef CONFIG_ACPI
static const struct acpi_device_id dw_spi_mmio_acpi_match[] = {
	{"HISI0173", (kernel_ulong_t)dw_spi_dw_apb_init},
	{},
};
MODULE_DEVICE_TABLE(acpi, dw_spi_mmio_acpi_match);
#endif

static struct platform_driver dw_spi_mmio_driver = {
	.probe		= dw_spi_mmio_probe,
	.remove		= dw_spi_mmio_remove,
	.driver		= {
		.name	= DRIVER_NAME,
		.of_match_table = dw_spi_mmio_of_match,
		.acpi_match_table = ACPI_PTR(dw_spi_mmio_acpi_match),
	},
};
module_platform_driver(dw_spi_mmio_driver);

MODULE_AUTHOR("Jean-Hugues Deschenes <jean-hugues.deschenes@octasic.com>");
MODULE_DESCRIPTION("Memory-mapped I/O interface driver for DW SPI Core");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
75a6faf6	1	// SPDX-License-Identifier: GPL-2.0-only
f7b6fd6d	2	/*
ca632f55	3	* Memory-mapped interface driver for DW SPI Core
f7b6fd6d JHD	4	*
f7b6fd6d JHD	5	* Copyright (c) 2010, Octasic semiconductor.
f7b6fd6d JHD	6	*/
	7
	8	#include <linux/clk.h>
50c01fc3	9	#include <linux/err.h>
f7b6fd6d	10	#include <linux/platform_device.h>
b9fc2d20	11	#include <linux/pm_runtime.h>
5a0e3ad6	12	#include <linux/slab.h>
f7b6fd6d	13	#include <linux/spi/spi.h>
568a60ed	14	#include <linux/scatterlist.h>
c2c25cc3	15	#include <linux/mfd/syscon.h>
d7614de4	16	#include <linux/module.h>
22dae17e	17	#include <linux/of.h>
22dae17e	18	#include <linux/of_platform.h>
32215a6c	19	#include <linux/acpi.h>
9899995e	20	#include <linux/property.h>
c2c25cc3	21	#include <linux/regmap.h>
7830c0ef	22	#include <linux/reset.h>
568a60ed	23
ca632f55	24	#include "spi-dw.h"
f7b6fd6d JHD	25
	26	#define DRIVER_NAME "dw_spi_mmio"
	27
	28	struct dw_spi_mmio {
0a4c1d7d JHD	29	struct dw_spi dws;
0a4c1d7d JHD	30	struct clk *clk;
560ee7e9	31	struct clk *pclk;
c2c25cc3	32	void *priv;
7830c0ef	33	struct reset_control *rstc;
f7b6fd6d JHD	34	};
f7b6fd6d JHD	35
c2c25cc3	36	#define MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL 0x24
c2c25cc3	37	#define OCELOT_IF_SI_OWNER_OFFSET 4
be17ee0d	38	#define JAGUAR2_IF_SI_OWNER_OFFSET 6
c1d8b082	39	#define MSCC_IF_SI_OWNER_MASK GENMASK(1, 0)
c2c25cc3 AB	40	#define MSCC_IF_SI_OWNER_SISL 0
	41	#define MSCC_IF_SI_OWNER_SIBM 1
	42	#define MSCC_IF_SI_OWNER_SIMC 2
	43
	44	#define MSCC_SPI_MST_SW_MODE 0x14
	45	#define MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE BIT(13)
	46	#define MSCC_SPI_MST_SW_MODE_SW_SPI_CS(x) (x << 5)
	47
f4237791 WAZ	48	/*
	49	* For Keem Bay, CTRLR0[31] is used to select controller mode.
	50	* 0: SSI is slave
	51	* 1: SSI is master
	52	*/
	53	#define KEEMBAY_CTRLR0_SSIC_IS_MST BIT(31)
	54
c2c25cc3 AB	55	struct dw_spi_mscc {
	56	struct regmap *syscon;
	57	void __iomem *spi_mst;
	58	};
	59
	60	/*
	61	* The Designware SPI controller (referred to as master in the documentation)
	62	* automatically deasserts chip select when the tx fifo is empty. The chip
	63	* selects then needs to be either driven as GPIOs or, for the first 4 using the
	64	* the SPI boot controller registers. the final chip select is an OR gate
	65	* between the Designware SPI controller and the SPI boot controller.
	66	*/
	67	static void dw_spi_mscc_set_cs(struct spi_device *spi, bool enable)
	68	{
	69	struct dw_spi *dws = spi_master_get_devdata(spi->master);
	70	struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws);
	71	struct dw_spi_mscc *dwsmscc = dwsmmio->priv;
	72	u32 cs = spi->chip_select;
	73
	74	if (cs < 4) {
	75	u32 sw_mode = MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE;
	76
	77	if (!enable)
	78	sw_mode \|= MSCC_SPI_MST_SW_MODE_SW_SPI_CS(BIT(cs));
	79
	80	writel(sw_mode, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);
	81	}
	82
	83	dw_spi_set_cs(spi, enable);
	84	}
	85
	86	static int dw_spi_mscc_init(struct platform_device *pdev,
be17ee0d AB	87	struct dw_spi_mmio *dwsmmio,
be17ee0d AB	88	const char *cpu_syscon, u32 if_si_owner_offset)
c2c25cc3 AB	89	{
c2c25cc3 AB	90	struct dw_spi_mscc *dwsmscc;
c2c25cc3 AB	91
	92	dwsmscc = devm_kzalloc(&pdev->dev, sizeof(*dwsmscc), GFP_KERNEL);
	93	if (!dwsmscc)
	94	return -ENOMEM;
	95
5cc6fdcc	96	dwsmscc->spi_mst = devm_platform_ioremap_resource(pdev, 1);
c2c25cc3 AB	97	if (IS_ERR(dwsmscc->spi_mst)) {
	98	dev_err(&pdev->dev, "SPI_MST region map failed\n");
	99	return PTR_ERR(dwsmscc->spi_mst);
	100	}
	101
be17ee0d	102	dwsmscc->syscon = syscon_regmap_lookup_by_compatible(cpu_syscon);
c2c25cc3 AB	103	if (IS_ERR(dwsmscc->syscon))
	104	return PTR_ERR(dwsmscc->syscon);
	105
	106	/* Deassert all CS */
	107	writel(0, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);
	108
	109	/* Select the owner of the SI interface */
	110	regmap_update_bits(dwsmscc->syscon, MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL,
c1d8b082	111	MSCC_IF_SI_OWNER_MASK << if_si_owner_offset,
be17ee0d	112	MSCC_IF_SI_OWNER_SIMC << if_si_owner_offset);
c2c25cc3 AB	113
	114	dwsmmio->dws.set_cs = dw_spi_mscc_set_cs;
	115	dwsmmio->priv = dwsmscc;
	116
c4eadee2 WAZ	117	/* Register hook to configure CTRLR0 */
	118	dwsmmio->dws.update_cr0 = dw_spi_update_cr0;
	119
c2c25cc3 AB	120	return 0;
	121	}
	122
be17ee0d AB	123	static int dw_spi_mscc_ocelot_init(struct platform_device *pdev,
	124	struct dw_spi_mmio *dwsmmio)
	125	{
	126	return dw_spi_mscc_init(pdev, dwsmmio, "mscc,ocelot-cpu-syscon",
	127	OCELOT_IF_SI_OWNER_OFFSET);
	128	}
	129
	130	static int dw_spi_mscc_jaguar2_init(struct platform_device *pdev,
	131	struct dw_spi_mmio *dwsmmio)
	132	{
	133	return dw_spi_mscc_init(pdev, dwsmmio, "mscc,jaguar2-cpu-syscon",
	134	JAGUAR2_IF_SI_OWNER_OFFSET);
	135	}
	136
f2d70479 TS	137	static int dw_spi_alpine_init(struct platform_device *pdev,
	138	struct dw_spi_mmio *dwsmmio)
	139	{
	140	dwsmmio->dws.cs_override = 1;
	141
c4eadee2 WAZ	142	/* Register hook to configure CTRLR0 */
	143	dwsmmio->dws.update_cr0 = dw_spi_update_cr0;
	144
	145	return 0;
	146	}
	147
	148	static int dw_spi_dw_apb_init(struct platform_device *pdev,
	149	struct dw_spi_mmio *dwsmmio)
	150	{
	151	/* Register hook to configure CTRLR0 */
	152	dwsmmio->dws.update_cr0 = dw_spi_update_cr0;
	153
0fdad596 SS	154	dw_spi_dma_setup_generic(&dwsmmio->dws);
0fdad596 SS	155
f2d70479 TS	156	return 0;
	157	}
	158
e539f435 WAZ	159	static int dw_spi_dwc_ssi_init(struct platform_device *pdev,
	160	struct dw_spi_mmio *dwsmmio)
	161	{
	162	/* Register hook to configure CTRLR0 */
	163	dwsmmio->dws.update_cr0 = dw_spi_update_cr0_v1_01a;
	164
0fdad596 SS	165	dw_spi_dma_setup_generic(&dwsmmio->dws);
0fdad596 SS	166
e539f435 WAZ	167	return 0;
	168	}
	169
f4237791 WAZ	170	static u32 dw_spi_update_cr0_keembay(struct spi_controller *master,
	171	struct spi_device *spi,
	172	struct spi_transfer *transfer)
	173	{
	174	u32 cr0 = dw_spi_update_cr0_v1_01a(master, spi, transfer);
	175
	176	return cr0 \| KEEMBAY_CTRLR0_SSIC_IS_MST;
	177	}
	178
	179	static int dw_spi_keembay_init(struct platform_device *pdev,
	180	struct dw_spi_mmio *dwsmmio)
	181	{
	182	/* Register hook to configure CTRLR0 */
	183	dwsmmio->dws.update_cr0 = dw_spi_update_cr0_keembay;
	184
	185	return 0;
	186	}
	187
fd4a319b	188	static int dw_spi_mmio_probe(struct platform_device *pdev)
f7b6fd6d	189	{
c2c25cc3 AB	190	int (init_func)(struct platform_device pdev,
c2c25cc3 AB	191	struct dw_spi_mmio *dwsmmio);
f7b6fd6d	192	struct dw_spi_mmio *dwsmmio;
77810d48	193	struct resource *mem;
f7b6fd6d	194	struct dw_spi *dws;
f7b6fd6d	195	int ret;
22dae17e	196	int num_cs;
f7b6fd6d	197
04f421e7 BS	198	dwsmmio = devm_kzalloc(&pdev->dev, sizeof(struct dw_spi_mmio),
	199	GFP_KERNEL);
	200	if (!dwsmmio)
	201	return -ENOMEM;
f7b6fd6d JHD	202
	203	dws = &dwsmmio->dws;
	204
	205	/* Get basic io resource and map it */
77810d48	206	dws->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
afb7f565	207	if (IS_ERR(dws->regs))
04f421e7	208	return PTR_ERR(dws->regs);
f7b6fd6d	209
77810d48 SS	210	dws->paddr = mem->start;
77810d48 SS	211
f7b6fd6d	212	dws->irq = platform_get_irq(pdev, 0);
6b8ac10e	213	if (dws->irq < 0)
04f421e7	214	return dws->irq; /* -ENXIO */
f7b6fd6d	215
04f421e7 BS	216	dwsmmio->clk = devm_clk_get(&pdev->dev, NULL);
	217	if (IS_ERR(dwsmmio->clk))
	218	return PTR_ERR(dwsmmio->clk);
020fe3fe	219	ret = clk_prepare_enable(dwsmmio->clk);
04f421e7 BS	220	if (ret)
04f421e7 BS	221	return ret;
f7b6fd6d	222
560ee7e9 PE	223	/* Optional clock needed to access the registers */
560ee7e9 PE	224	dwsmmio->pclk = devm_clk_get_optional(&pdev->dev, "pclk");
3da9834d AS	225	if (IS_ERR(dwsmmio->pclk)) {
	226	ret = PTR_ERR(dwsmmio->pclk);
	227	goto out_clk;
	228	}
560ee7e9 PE	229	ret = clk_prepare_enable(dwsmmio->pclk);
	230	if (ret)
	231	goto out_clk;
	232
7830c0ef DN	233	/* find an optional reset controller */
	234	dwsmmio->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, "spi");
	235	if (IS_ERR(dwsmmio->rstc)) {
	236	ret = PTR_ERR(dwsmmio->rstc);
	237	goto out_clk;
	238	}
	239	reset_control_deassert(dwsmmio->rstc);
	240
2418991e	241	dws->bus_num = pdev->id;
22dae17e	242
f7b6fd6d JHD	243	dws->max_freq = clk_get_rate(dwsmmio->clk);
f7b6fd6d JHD	244
9899995e	245	device_property_read_u32(&pdev->dev, "reg-io-width", &dws->reg_io_width);
c4fe57f7	246
22dae17e ST	247	num_cs = 4;
22dae17e ST	248
9899995e	249	device_property_read_u32(&pdev->dev, "num-cs", &num_cs);
22dae17e ST	250
	251	dws->num_cs = num_cs;
	252
c2c25cc3 AB	253	init_func = device_get_match_data(&pdev->dev);
	254	if (init_func) {
	255	ret = init_func(pdev, dwsmmio);
	256	if (ret)
	257	goto out;
	258	}
	259
b9fc2d20 JN	260	pm_runtime_enable(&pdev->dev);
b9fc2d20 JN	261
04f421e7	262	ret = dw_spi_add_host(&pdev->dev, dws);
f7b6fd6d	263	if (ret)
04f421e7	264	goto out;
f7b6fd6d JHD	265
	266	platform_set_drvdata(pdev, dwsmmio);
	267	return 0;
	268
04f421e7	269	out:
b9fc2d20	270	pm_runtime_disable(&pdev->dev);
560ee7e9 PE	271	clk_disable_unprepare(dwsmmio->pclk);
560ee7e9 PE	272	out_clk:
020fe3fe	273	clk_disable_unprepare(dwsmmio->clk);
7830c0ef DN	274	reset_control_assert(dwsmmio->rstc);
7830c0ef DN	275
f7b6fd6d JHD	276	return ret;
	277	}
	278
fd4a319b	279	static int dw_spi_mmio_remove(struct platform_device *pdev)
f7b6fd6d JHD	280	{
f7b6fd6d JHD	281	struct dw_spi_mmio *dwsmmio = platform_get_drvdata(pdev);
f7b6fd6d	282
f7b6fd6d	283	dw_spi_remove_host(&dwsmmio->dws);
b9fc2d20	284	pm_runtime_disable(&pdev->dev);
560ee7e9	285	clk_disable_unprepare(dwsmmio->pclk);
400c18e3	286	clk_disable_unprepare(dwsmmio->clk);
7830c0ef	287	reset_control_assert(dwsmmio->rstc);
f7b6fd6d	288
f7b6fd6d JHD	289	return 0;
	290	}
	291
22dae17e	292	static const struct of_device_id dw_spi_mmio_of_match[] = {
c4eadee2	293	{ .compatible = "snps,dw-apb-ssi", .data = dw_spi_dw_apb_init},
be17ee0d AB	294	{ .compatible = "mscc,ocelot-spi", .data = dw_spi_mscc_ocelot_init},
be17ee0d AB	295	{ .compatible = "mscc,jaguar2-spi", .data = dw_spi_mscc_jaguar2_init},
f2d70479	296	{ .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init},
c4eadee2	297	{ .compatible = "renesas,rzn1-spi", .data = dw_spi_dw_apb_init},
e539f435	298	{ .compatible = "snps,dwc-ssi-1.01a", .data = dw_spi_dwc_ssi_init},
f4237791	299	{ .compatible = "intel,keembay-ssi", .data = dw_spi_keembay_init},
22dae17e ST	300	{ /* end of table */}
	301	};
	302	MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match);
	303
4dd227a5	304	#ifdef CONFIG_ACPI
32215a6c	305	static const struct acpi_device_id dw_spi_mmio_acpi_match[] = {
c4eadee2	306	{"HISI0173", (kernel_ulong_t)dw_spi_dw_apb_init},
32215a6c JF	307	{},
	308	};
	309	MODULE_DEVICE_TABLE(acpi, dw_spi_mmio_acpi_match);
4dd227a5	310	#endif
32215a6c	311
f7b6fd6d	312	static struct platform_driver dw_spi_mmio_driver = {
940ab889	313	.probe = dw_spi_mmio_probe,
fd4a319b	314	.remove = dw_spi_mmio_remove,
f7b6fd6d JHD	315	.driver = {
f7b6fd6d JHD	316	.name = DRIVER_NAME,
22dae17e	317	.of_match_table = dw_spi_mmio_of_match,
32215a6c	318	.acpi_match_table = ACPI_PTR(dw_spi_mmio_acpi_match),
f7b6fd6d JHD	319	},
f7b6fd6d JHD	320	};
940ab889	321	module_platform_driver(dw_spi_mmio_driver);
f7b6fd6d JHD	322
	323	MODULE_AUTHOR("Jean-Hugues Deschenes <jean-hugues.deschenes@octasic.com>");
	324	MODULE_DESCRIPTION("Memory-mapped I/O interface driver for DW SPI Core");
	325	MODULE_LICENSE("GPL v2");