[thirdparty/kernel/stable.git] / drivers / spi / spi-dw-mmio.c

/*
 * Memory-mapped interface driver for DW SPI Core
 *
 * Copyright (c) 2010, Octasic semiconductor.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 */

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/spi/spi.h>
#include <linux/scatterlist.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/acpi.h>
#include <linux/property.h>
#include <linux/regmap.h>

#include "spi-dw.h"

#define DRIVER_NAME "dw_spi_mmio"

struct dw_spi_mmio {
	struct dw_spi  dws;
	struct clk     *clk;
	void           *priv;
};

#define MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL	0x24
#define OCELOT_IF_SI_OWNER_OFFSET		4
#define JAGUAR2_IF_SI_OWNER_OFFSET		6
#define MSCC_IF_SI_OWNER_MASK			GENMASK(1, 0)
#define MSCC_IF_SI_OWNER_SISL			0
#define MSCC_IF_SI_OWNER_SIBM			1
#define MSCC_IF_SI_OWNER_SIMC			2

#define MSCC_SPI_MST_SW_MODE			0x14
#define MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE	BIT(13)
#define MSCC_SPI_MST_SW_MODE_SW_SPI_CS(x)	(x << 5)

struct dw_spi_mscc {
	struct regmap       *syscon;
	void __iomem        *spi_mst;
};

/*
 * The Designware SPI controller (referred to as master in the documentation)
 * automatically deasserts chip select when the tx fifo is empty. The chip
 * selects then needs to be either driven as GPIOs or, for the first 4 using the
 * the SPI boot controller registers. the final chip select is an OR gate
 * between the Designware SPI controller and the SPI boot controller.
 */
static void dw_spi_mscc_set_cs(struct spi_device *spi, bool enable)
{
	struct dw_spi *dws = spi_master_get_devdata(spi->master);
	struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws);
	struct dw_spi_mscc *dwsmscc = dwsmmio->priv;
	u32 cs = spi->chip_select;

	if (cs < 4) {
		u32 sw_mode = MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE;

		if (!enable)
			sw_mode |= MSCC_SPI_MST_SW_MODE_SW_SPI_CS(BIT(cs));

		writel(sw_mode, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);
	}

	dw_spi_set_cs(spi, enable);
}

static int dw_spi_mscc_init(struct platform_device *pdev,
			    struct dw_spi_mmio *dwsmmio,
			    const char *cpu_syscon, u32 if_si_owner_offset)
{
	struct dw_spi_mscc *dwsmscc;
	struct resource *res;

	dwsmscc = devm_kzalloc(&pdev->dev, sizeof(*dwsmscc), GFP_KERNEL);
	if (!dwsmscc)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	dwsmscc->spi_mst = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(dwsmscc->spi_mst)) {
		dev_err(&pdev->dev, "SPI_MST region map failed\n");
		return PTR_ERR(dwsmscc->spi_mst);
	}

	dwsmscc->syscon = syscon_regmap_lookup_by_compatible(cpu_syscon);
	if (IS_ERR(dwsmscc->syscon))
		return PTR_ERR(dwsmscc->syscon);

	/* Deassert all CS */
	writel(0, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);

	/* Select the owner of the SI interface */
	regmap_update_bits(dwsmscc->syscon, MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL,
			   MSCC_IF_SI_OWNER_MASK << if_si_owner_offset,
			   MSCC_IF_SI_OWNER_SIMC << if_si_owner_offset);

	dwsmmio->dws.set_cs = dw_spi_mscc_set_cs;
	dwsmmio->priv = dwsmscc;

	return 0;
}

static int dw_spi_mscc_ocelot_init(struct platform_device *pdev,
				   struct dw_spi_mmio *dwsmmio)
{
	return dw_spi_mscc_init(pdev, dwsmmio, "mscc,ocelot-cpu-syscon",
				OCELOT_IF_SI_OWNER_OFFSET);
}

static int dw_spi_mscc_jaguar2_init(struct platform_device *pdev,
				    struct dw_spi_mmio *dwsmmio)
{
	return dw_spi_mscc_init(pdev, dwsmmio, "mscc,jaguar2-cpu-syscon",
				JAGUAR2_IF_SI_OWNER_OFFSET);
}

static int dw_spi_alpine_init(struct platform_device *pdev,
			      struct dw_spi_mmio *dwsmmio)
{
	dwsmmio->dws.cs_override = 1;

	return 0;
}

static int dw_spi_mmio_probe(struct platform_device *pdev)
{
	int (*init_func)(struct platform_device *pdev,
			 struct dw_spi_mmio *dwsmmio);
	struct dw_spi_mmio *dwsmmio;
	struct dw_spi *dws;
	struct resource *mem;
	int ret;
	int num_cs;

	dwsmmio = devm_kzalloc(&pdev->dev, sizeof(struct dw_spi_mmio),
			GFP_KERNEL);
	if (!dwsmmio)
		return -ENOMEM;

	dws = &dwsmmio->dws;

	/* Get basic io resource and map it */
	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	dws->regs = devm_ioremap_resource(&pdev->dev, mem);
	if (IS_ERR(dws->regs)) {
		dev_err(&pdev->dev, "SPI region map failed\n");
		return PTR_ERR(dws->regs);
	}

	dws->irq = platform_get_irq(pdev, 0);
	if (dws->irq < 0) {
		dev_err(&pdev->dev, "no irq resource?\n");
		return dws->irq; /* -ENXIO */
	}

	dwsmmio->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(dwsmmio->clk))
		return PTR_ERR(dwsmmio->clk);
	ret = clk_prepare_enable(dwsmmio->clk);
	if (ret)
		return ret;

	dws->bus_num = pdev->id;

	dws->max_freq = clk_get_rate(dwsmmio->clk);

	device_property_read_u32(&pdev->dev, "reg-io-width", &dws->reg_io_width);

	num_cs = 4;

	device_property_read_u32(&pdev->dev, "num-cs", &num_cs);

	dws->num_cs = num_cs;

	init_func = device_get_match_data(&pdev->dev);
	if (init_func) {
		ret = init_func(pdev, dwsmmio);
		if (ret)
			goto out;
	}

	ret = dw_spi_add_host(&pdev->dev, dws);
	if (ret)
		goto out;

	platform_set_drvdata(pdev, dwsmmio);
	return 0;

out:
	clk_disable_unprepare(dwsmmio->clk);
	return ret;
}

static int dw_spi_mmio_remove(struct platform_device *pdev)
{
	struct dw_spi_mmio *dwsmmio = platform_get_drvdata(pdev);

	dw_spi_remove_host(&dwsmmio->dws);
	clk_disable_unprepare(dwsmmio->clk);

	return 0;
}

static const struct of_device_id dw_spi_mmio_of_match[] = {
	{ .compatible = "snps,dw-apb-ssi", },
	{ .compatible = "mscc,ocelot-spi", .data = dw_spi_mscc_ocelot_init},
	{ .compatible = "mscc,jaguar2-spi", .data = dw_spi_mscc_jaguar2_init},
	{ .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init},
	{ /* end of table */}
};
MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match);

static const struct acpi_device_id dw_spi_mmio_acpi_match[] = {
	{"HISI0173", 0},
	{},
};
MODULE_DEVICE_TABLE(acpi, dw_spi_mmio_acpi_match);

static struct platform_driver dw_spi_mmio_driver = {
	.probe		= dw_spi_mmio_probe,
	.remove		= dw_spi_mmio_remove,
	.driver		= {
		.name	= DRIVER_NAME,
		.of_match_table = dw_spi_mmio_of_match,
		.acpi_match_table = ACPI_PTR(dw_spi_mmio_acpi_match),
	},
};
module_platform_driver(dw_spi_mmio_driver);

MODULE_AUTHOR("Jean-Hugues Deschenes <jean-hugues.deschenes@octasic.com>");
MODULE_DESCRIPTION("Memory-mapped I/O interface driver for DW SPI Core");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
f7b6fd6d	1	/*
ca632f55	2	* Memory-mapped interface driver for DW SPI Core
f7b6fd6d JHD	3	*
	4	* Copyright (c) 2010, Octasic semiconductor.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms and conditions of the GNU General Public License,
	8	* version 2, as published by the Free Software Foundation.
	9	*/
	10
	11	#include <linux/clk.h>
50c01fc3	12	#include <linux/err.h>
f7b6fd6d JHD	13	#include <linux/interrupt.h>
f7b6fd6d JHD	14	#include <linux/platform_device.h>
5a0e3ad6	15	#include <linux/slab.h>
f7b6fd6d	16	#include <linux/spi/spi.h>
568a60ed	17	#include <linux/scatterlist.h>
c2c25cc3	18	#include <linux/mfd/syscon.h>
d7614de4	19	#include <linux/module.h>
22dae17e	20	#include <linux/of.h>
22dae17e	21	#include <linux/of_platform.h>
32215a6c	22	#include <linux/acpi.h>
9899995e	23	#include <linux/property.h>
c2c25cc3	24	#include <linux/regmap.h>
568a60ed	25
ca632f55	26	#include "spi-dw.h"
f7b6fd6d JHD	27
	28	#define DRIVER_NAME "dw_spi_mmio"
	29
	30	struct dw_spi_mmio {
0a4c1d7d JHD	31	struct dw_spi dws;
0a4c1d7d JHD	32	struct clk *clk;
c2c25cc3	33	void *priv;
f7b6fd6d JHD	34	};
f7b6fd6d JHD	35
c2c25cc3	36	#define MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL 0x24
c2c25cc3	37	#define OCELOT_IF_SI_OWNER_OFFSET 4
be17ee0d	38	#define JAGUAR2_IF_SI_OWNER_OFFSET 6
c1d8b082	39	#define MSCC_IF_SI_OWNER_MASK GENMASK(1, 0)
c2c25cc3 AB	40	#define MSCC_IF_SI_OWNER_SISL 0
	41	#define MSCC_IF_SI_OWNER_SIBM 1
	42	#define MSCC_IF_SI_OWNER_SIMC 2
	43
	44	#define MSCC_SPI_MST_SW_MODE 0x14
	45	#define MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE BIT(13)
	46	#define MSCC_SPI_MST_SW_MODE_SW_SPI_CS(x) (x << 5)
	47
	48	struct dw_spi_mscc {
	49	struct regmap *syscon;
	50	void __iomem *spi_mst;
	51	};
	52
	53	/*
	54	* The Designware SPI controller (referred to as master in the documentation)
	55	* automatically deasserts chip select when the tx fifo is empty. The chip
	56	* selects then needs to be either driven as GPIOs or, for the first 4 using the
	57	* the SPI boot controller registers. the final chip select is an OR gate
	58	* between the Designware SPI controller and the SPI boot controller.
	59	*/
	60	static void dw_spi_mscc_set_cs(struct spi_device *spi, bool enable)
	61	{
	62	struct dw_spi *dws = spi_master_get_devdata(spi->master);
	63	struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws);
	64	struct dw_spi_mscc *dwsmscc = dwsmmio->priv;
	65	u32 cs = spi->chip_select;
	66
	67	if (cs < 4) {
	68	u32 sw_mode = MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE;
	69
	70	if (!enable)
	71	sw_mode \|= MSCC_SPI_MST_SW_MODE_SW_SPI_CS(BIT(cs));
	72
	73	writel(sw_mode, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);
	74	}
	75
	76	dw_spi_set_cs(spi, enable);
	77	}
	78
	79	static int dw_spi_mscc_init(struct platform_device *pdev,
be17ee0d AB	80	struct dw_spi_mmio *dwsmmio,
be17ee0d AB	81	const char *cpu_syscon, u32 if_si_owner_offset)
c2c25cc3 AB	82	{
	83	struct dw_spi_mscc *dwsmscc;
	84	struct resource *res;
	85
	86	dwsmscc = devm_kzalloc(&pdev->dev, sizeof(*dwsmscc), GFP_KERNEL);
	87	if (!dwsmscc)
	88	return -ENOMEM;
	89
	90	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	91	dwsmscc->spi_mst = devm_ioremap_resource(&pdev->dev, res);
	92	if (IS_ERR(dwsmscc->spi_mst)) {
	93	dev_err(&pdev->dev, "SPI_MST region map failed\n");
	94	return PTR_ERR(dwsmscc->spi_mst);
	95	}
	96
be17ee0d	97	dwsmscc->syscon = syscon_regmap_lookup_by_compatible(cpu_syscon);
c2c25cc3 AB	98	if (IS_ERR(dwsmscc->syscon))
	99	return PTR_ERR(dwsmscc->syscon);
	100
	101	/* Deassert all CS */
	102	writel(0, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);
	103
	104	/* Select the owner of the SI interface */
	105	regmap_update_bits(dwsmscc->syscon, MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL,
c1d8b082	106	MSCC_IF_SI_OWNER_MASK << if_si_owner_offset,
be17ee0d	107	MSCC_IF_SI_OWNER_SIMC << if_si_owner_offset);
c2c25cc3 AB	108
	109	dwsmmio->dws.set_cs = dw_spi_mscc_set_cs;
	110	dwsmmio->priv = dwsmscc;
	111
	112	return 0;
	113	}
	114
be17ee0d AB	115	static int dw_spi_mscc_ocelot_init(struct platform_device *pdev,
	116	struct dw_spi_mmio *dwsmmio)
	117	{
	118	return dw_spi_mscc_init(pdev, dwsmmio, "mscc,ocelot-cpu-syscon",
	119	OCELOT_IF_SI_OWNER_OFFSET);
	120	}
	121
	122	static int dw_spi_mscc_jaguar2_init(struct platform_device *pdev,
	123	struct dw_spi_mmio *dwsmmio)
	124	{
	125	return dw_spi_mscc_init(pdev, dwsmmio, "mscc,jaguar2-cpu-syscon",
	126	JAGUAR2_IF_SI_OWNER_OFFSET);
	127	}
	128
f2d70479 TS	129	static int dw_spi_alpine_init(struct platform_device *pdev,
	130	struct dw_spi_mmio *dwsmmio)
	131	{
	132	dwsmmio->dws.cs_override = 1;
	133
	134	return 0;
	135	}
	136
fd4a319b	137	static int dw_spi_mmio_probe(struct platform_device *pdev)
f7b6fd6d	138	{
c2c25cc3 AB	139	int (init_func)(struct platform_device pdev,
c2c25cc3 AB	140	struct dw_spi_mmio *dwsmmio);
f7b6fd6d JHD	141	struct dw_spi_mmio *dwsmmio;
f7b6fd6d JHD	142	struct dw_spi *dws;
04f421e7	143	struct resource *mem;
f7b6fd6d	144	int ret;
22dae17e	145	int num_cs;
f7b6fd6d	146
04f421e7 BS	147	dwsmmio = devm_kzalloc(&pdev->dev, sizeof(struct dw_spi_mmio),
	148	GFP_KERNEL);
	149	if (!dwsmmio)
	150	return -ENOMEM;
f7b6fd6d JHD	151
	152	dws = &dwsmmio->dws;
	153
	154	/* Get basic io resource and map it */
	155	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
04f421e7 BS	156	dws->regs = devm_ioremap_resource(&pdev->dev, mem);
	157	if (IS_ERR(dws->regs)) {
	158	dev_err(&pdev->dev, "SPI region map failed\n");
	159	return PTR_ERR(dws->regs);
f7b6fd6d JHD	160	}
	161
	162	dws->irq = platform_get_irq(pdev, 0);
	163	if (dws->irq < 0) {
	164	dev_err(&pdev->dev, "no irq resource?\n");
04f421e7	165	return dws->irq; /* -ENXIO */
f7b6fd6d JHD	166	}
f7b6fd6d JHD	167
04f421e7 BS	168	dwsmmio->clk = devm_clk_get(&pdev->dev, NULL);
	169	if (IS_ERR(dwsmmio->clk))
	170	return PTR_ERR(dwsmmio->clk);
020fe3fe	171	ret = clk_prepare_enable(dwsmmio->clk);
04f421e7 BS	172	if (ret)
04f421e7 BS	173	return ret;
f7b6fd6d	174
2418991e	175	dws->bus_num = pdev->id;
22dae17e	176
f7b6fd6d JHD	177	dws->max_freq = clk_get_rate(dwsmmio->clk);
f7b6fd6d JHD	178
9899995e	179	device_property_read_u32(&pdev->dev, "reg-io-width", &dws->reg_io_width);
c4fe57f7	180
22dae17e ST	181	num_cs = 4;
22dae17e ST	182
9899995e	183	device_property_read_u32(&pdev->dev, "num-cs", &num_cs);
22dae17e ST	184
	185	dws->num_cs = num_cs;
	186
c2c25cc3 AB	187	init_func = device_get_match_data(&pdev->dev);
	188	if (init_func) {
	189	ret = init_func(pdev, dwsmmio);
	190	if (ret)
	191	goto out;
	192	}
	193
04f421e7	194	ret = dw_spi_add_host(&pdev->dev, dws);
f7b6fd6d	195	if (ret)
04f421e7	196	goto out;
f7b6fd6d JHD	197
	198	platform_set_drvdata(pdev, dwsmmio);
	199	return 0;
	200
04f421e7	201	out:
020fe3fe	202	clk_disable_unprepare(dwsmmio->clk);
f7b6fd6d JHD	203	return ret;
	204	}
	205
fd4a319b	206	static int dw_spi_mmio_remove(struct platform_device *pdev)
f7b6fd6d JHD	207	{
f7b6fd6d JHD	208	struct dw_spi_mmio *dwsmmio = platform_get_drvdata(pdev);
f7b6fd6d	209
f7b6fd6d	210	dw_spi_remove_host(&dwsmmio->dws);
400c18e3	211	clk_disable_unprepare(dwsmmio->clk);
f7b6fd6d	212
f7b6fd6d JHD	213	return 0;
	214	}
	215
22dae17e ST	216	static const struct of_device_id dw_spi_mmio_of_match[] = {
22dae17e ST	217	{ .compatible = "snps,dw-apb-ssi", },
be17ee0d AB	218	{ .compatible = "mscc,ocelot-spi", .data = dw_spi_mscc_ocelot_init},
be17ee0d AB	219	{ .compatible = "mscc,jaguar2-spi", .data = dw_spi_mscc_jaguar2_init},
f2d70479	220	{ .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init},
22dae17e ST	221	{ /* end of table */}
	222	};
	223	MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match);
	224
32215a6c JF	225	static const struct acpi_device_id dw_spi_mmio_acpi_match[] = {
	226	{"HISI0173", 0},
	227	{},
	228	};
	229	MODULE_DEVICE_TABLE(acpi, dw_spi_mmio_acpi_match);
	230
f7b6fd6d	231	static struct platform_driver dw_spi_mmio_driver = {
940ab889	232	.probe = dw_spi_mmio_probe,
fd4a319b	233	.remove = dw_spi_mmio_remove,
f7b6fd6d JHD	234	.driver = {
f7b6fd6d JHD	235	.name = DRIVER_NAME,
22dae17e	236	.of_match_table = dw_spi_mmio_of_match,
32215a6c	237	.acpi_match_table = ACPI_PTR(dw_spi_mmio_acpi_match),
f7b6fd6d JHD	238	},
f7b6fd6d JHD	239	};
940ab889	240	module_platform_driver(dw_spi_mmio_driver);
f7b6fd6d JHD	241
	242	MODULE_AUTHOR("Jean-Hugues Deschenes <jean-hugues.deschenes@octasic.com>");
	243	MODULE_DESCRIPTION("Memory-mapped I/O interface driver for DW SPI Core");
	244	MODULE_LICENSE("GPL v2");