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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
ccf06998 | 2 | /* |
b36ece83 | 3 | * Freescale SPI controller driver. |
ccf06998 KG |
4 | * |
5 | * Maintainer: Kumar Gala | |
6 | * | |
7 | * Copyright (C) 2006 Polycom, Inc. | |
b36ece83 | 8 | * Copyright 2010 Freescale Semiconductor, Inc. |
ccf06998 | 9 | * |
4c1fba44 AV |
10 | * CPM SPI and QE buffer descriptors mode support: |
11 | * Copyright (c) 2009 MontaVista Software, Inc. | |
12 | * Author: Anton Vorontsov <avorontsov@ru.mvista.com> | |
13 | * | |
447b0c7b AL |
14 | * GRLIB support: |
15 | * Copyright (c) 2012 Aeroflex Gaisler AB. | |
16 | * Author: Andreas Larsson <andreas@gaisler.com> | |
ccf06998 | 17 | */ |
ccf06998 | 18 | #include <linux/delay.h> |
4c1fba44 | 19 | #include <linux/dma-mapping.h> |
a3108360 | 20 | #include <linux/fsl_devices.h> |
0f0581b2 | 21 | #include <linux/gpio/consumer.h> |
a3108360 XL |
22 | #include <linux/interrupt.h> |
23 | #include <linux/irq.h> | |
24 | #include <linux/kernel.h> | |
4c1fba44 | 25 | #include <linux/mm.h> |
a3108360 | 26 | #include <linux/module.h> |
4c1fba44 | 27 | #include <linux/mutex.h> |
35b4b3c0 | 28 | #include <linux/of.h> |
e8beacbb AL |
29 | #include <linux/of_address.h> |
30 | #include <linux/of_irq.h> | |
a3108360 XL |
31 | #include <linux/of_platform.h> |
32 | #include <linux/platform_device.h> | |
33 | #include <linux/spi/spi.h> | |
34 | #include <linux/spi/spi_bitbang.h> | |
35 | #include <linux/types.h> | |
ccf06998 | 36 | |
69b921ac RV |
37 | #ifdef CONFIG_FSL_SOC |
38 | #include <sysdev/fsl_soc.h> | |
39 | #endif | |
40 | ||
41 | /* Specific to the MPC8306/MPC8309 */ | |
42 | #define IMMR_SPI_CS_OFFSET 0x14c | |
43 | #define SPI_BOOT_SEL_BIT 0x80000000 | |
44 | ||
ca632f55 | 45 | #include "spi-fsl-lib.h" |
e8beacbb AL |
46 | #include "spi-fsl-cpm.h" |
47 | #include "spi-fsl-spi.h" | |
ccf06998 | 48 | |
c3f3e771 | 49 | #define TYPE_FSL 0 |
447b0c7b | 50 | #define TYPE_GRLIB 1 |
c3f3e771 AL |
51 | |
52 | struct fsl_spi_match_data { | |
53 | int type; | |
54 | }; | |
55 | ||
56 | static struct fsl_spi_match_data of_fsl_spi_fsl_config = { | |
57 | .type = TYPE_FSL, | |
58 | }; | |
59 | ||
447b0c7b AL |
60 | static struct fsl_spi_match_data of_fsl_spi_grlib_config = { |
61 | .type = TYPE_GRLIB, | |
62 | }; | |
63 | ||
3aea901d | 64 | static const struct of_device_id of_fsl_spi_match[] = { |
c3f3e771 AL |
65 | { |
66 | .compatible = "fsl,spi", | |
67 | .data = &of_fsl_spi_fsl_config, | |
68 | }, | |
447b0c7b AL |
69 | { |
70 | .compatible = "aeroflexgaisler,spictrl", | |
71 | .data = &of_fsl_spi_grlib_config, | |
72 | }, | |
c3f3e771 AL |
73 | {} |
74 | }; | |
75 | MODULE_DEVICE_TABLE(of, of_fsl_spi_match); | |
76 | ||
77 | static int fsl_spi_get_type(struct device *dev) | |
78 | { | |
79 | const struct of_device_id *match; | |
80 | ||
81 | if (dev->of_node) { | |
82 | match = of_match_node(of_fsl_spi_match, dev->of_node); | |
83 | if (match && match->data) | |
84 | return ((struct fsl_spi_match_data *)match->data)->type; | |
85 | } | |
86 | return TYPE_FSL; | |
87 | } | |
88 | ||
b36ece83 | 89 | static void fsl_spi_change_mode(struct spi_device *spi) |
a35c1710 | 90 | { |
d32382ca | 91 | struct mpc8xxx_spi *mspi = spi_controller_get_devdata(spi->controller); |
a35c1710 | 92 | struct spi_mpc8xxx_cs *cs = spi->controller_state; |
dd67de8c | 93 | struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; |
b36ece83 | 94 | __be32 __iomem *mode = ®_base->mode; |
a35c1710 AV |
95 | unsigned long flags; |
96 | ||
97 | if (cs->hw_mode == mpc8xxx_spi_read_reg(mode)) | |
98 | return; | |
99 | ||
100 | /* Turn off IRQs locally to minimize time that SPI is disabled. */ | |
101 | local_irq_save(flags); | |
102 | ||
103 | /* Turn off SPI unit prior changing mode */ | |
104 | mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE); | |
a35c1710 | 105 | |
4c1fba44 AV |
106 | /* When in CPM mode, we need to reinit tx and rx. */ |
107 | if (mspi->flags & SPI_CPM_MODE) { | |
e8beacbb | 108 | fsl_spi_cpm_reinit_txrx(mspi); |
4c1fba44 | 109 | } |
f9218c2a | 110 | mpc8xxx_spi_write_reg(mode, cs->hw_mode); |
a35c1710 AV |
111 | local_irq_restore(flags); |
112 | } | |
113 | ||
b48c4e3c AL |
114 | static void fsl_spi_qe_cpu_set_shifts(u32 *rx_shift, u32 *tx_shift, |
115 | int bits_per_word, int msb_first) | |
116 | { | |
117 | *rx_shift = 0; | |
118 | *tx_shift = 0; | |
119 | if (msb_first) { | |
120 | if (bits_per_word <= 8) { | |
121 | *rx_shift = 16; | |
122 | *tx_shift = 24; | |
123 | } else if (bits_per_word <= 16) { | |
124 | *rx_shift = 16; | |
125 | *tx_shift = 16; | |
126 | } | |
127 | } else { | |
128 | if (bits_per_word <= 8) | |
129 | *rx_shift = 8; | |
130 | } | |
131 | } | |
132 | ||
447b0c7b AL |
133 | static void fsl_spi_grlib_set_shifts(u32 *rx_shift, u32 *tx_shift, |
134 | int bits_per_word, int msb_first) | |
135 | { | |
136 | *rx_shift = 0; | |
137 | *tx_shift = 0; | |
138 | if (bits_per_word <= 16) { | |
139 | if (msb_first) { | |
140 | *rx_shift = 16; /* LSB in bit 16 */ | |
141 | *tx_shift = 32 - bits_per_word; /* MSB in bit 31 */ | |
142 | } else { | |
143 | *rx_shift = 16 - bits_per_word; /* MSB in bit 15 */ | |
144 | } | |
145 | } | |
146 | } | |
147 | ||
99aebb3c CL |
148 | static void mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs, |
149 | struct spi_device *spi, | |
150 | struct mpc8xxx_spi *mpc8xxx_spi, | |
151 | int bits_per_word) | |
ccf06998 | 152 | { |
c9bfcb31 JT |
153 | cs->rx_shift = 0; |
154 | cs->tx_shift = 0; | |
ccf06998 | 155 | if (bits_per_word <= 8) { |
575c5807 AV |
156 | cs->get_rx = mpc8xxx_spi_rx_buf_u8; |
157 | cs->get_tx = mpc8xxx_spi_tx_buf_u8; | |
ccf06998 | 158 | } else if (bits_per_word <= 16) { |
575c5807 AV |
159 | cs->get_rx = mpc8xxx_spi_rx_buf_u16; |
160 | cs->get_tx = mpc8xxx_spi_tx_buf_u16; | |
ccf06998 | 161 | } else if (bits_per_word <= 32) { |
575c5807 AV |
162 | cs->get_rx = mpc8xxx_spi_rx_buf_u32; |
163 | cs->get_tx = mpc8xxx_spi_tx_buf_u32; | |
99aebb3c | 164 | } |
ccf06998 | 165 | |
b48c4e3c AL |
166 | if (mpc8xxx_spi->set_shifts) |
167 | mpc8xxx_spi->set_shifts(&cs->rx_shift, &cs->tx_shift, | |
168 | bits_per_word, | |
169 | !(spi->mode & SPI_LSB_FIRST)); | |
170 | ||
575c5807 AV |
171 | mpc8xxx_spi->rx_shift = cs->rx_shift; |
172 | mpc8xxx_spi->tx_shift = cs->tx_shift; | |
173 | mpc8xxx_spi->get_rx = cs->get_rx; | |
174 | mpc8xxx_spi->get_tx = cs->get_tx; | |
0398fb70 JT |
175 | } |
176 | ||
b36ece83 MH |
177 | static int fsl_spi_setup_transfer(struct spi_device *spi, |
178 | struct spi_transfer *t) | |
0398fb70 JT |
179 | { |
180 | struct mpc8xxx_spi *mpc8xxx_spi; | |
b36ece83 | 181 | int bits_per_word = 0; |
0398fb70 | 182 | u8 pm; |
b36ece83 | 183 | u32 hz = 0; |
0398fb70 JT |
184 | struct spi_mpc8xxx_cs *cs = spi->controller_state; |
185 | ||
d32382ca | 186 | mpc8xxx_spi = spi_controller_get_devdata(spi->controller); |
0398fb70 JT |
187 | |
188 | if (t) { | |
189 | bits_per_word = t->bits_per_word; | |
190 | hz = t->speed_hz; | |
0398fb70 JT |
191 | } |
192 | ||
193 | /* spi_transfer level calls that work per-word */ | |
194 | if (!bits_per_word) | |
195 | bits_per_word = spi->bits_per_word; | |
196 | ||
0398fb70 JT |
197 | if (!hz) |
198 | hz = spi->max_speed_hz; | |
199 | ||
200 | if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) | |
99aebb3c | 201 | mspi_apply_cpu_mode_quirks(cs, spi, mpc8xxx_spi, bits_per_word); |
0398fb70 | 202 | |
ccf06998 KG |
203 | if (bits_per_word == 32) |
204 | bits_per_word = 0; | |
205 | else | |
206 | bits_per_word = bits_per_word - 1; | |
207 | ||
32421daa | 208 | /* mask out bits we are going to set */ |
c9bfcb31 JT |
209 | cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16 |
210 | | SPMODE_PM(0xF)); | |
211 | ||
212 | cs->hw_mode |= SPMODE_LEN(bits_per_word); | |
213 | ||
575c5807 | 214 | if ((mpc8xxx_spi->spibrg / hz) > 64) { |
53604dbe | 215 | cs->hw_mode |= SPMODE_DIV16; |
4f4517c4 | 216 | pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1; |
31ae7794 ME |
217 | WARN_ONCE(pm > 16, |
218 | "%s: Requested speed is too low: %d Hz. Will use %d Hz instead.\n", | |
219 | dev_name(&spi->dev), hz, mpc8xxx_spi->spibrg / 1024); | |
fd8a11e1 | 220 | if (pm > 16) |
53604dbe | 221 | pm = 16; |
b36ece83 | 222 | } else { |
4f4517c4 | 223 | pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1; |
b36ece83 | 224 | } |
a61f5345 CG |
225 | if (pm) |
226 | pm--; | |
227 | ||
228 | cs->hw_mode |= SPMODE_PM(pm); | |
a35c1710 | 229 | |
b36ece83 | 230 | fsl_spi_change_mode(spi); |
c9bfcb31 JT |
231 | return 0; |
232 | } | |
ccf06998 | 233 | |
b36ece83 | 234 | static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi, |
4c1fba44 AV |
235 | struct spi_transfer *t, unsigned int len) |
236 | { | |
237 | u32 word; | |
dd67de8c | 238 | struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; |
4c1fba44 AV |
239 | |
240 | mspi->count = len; | |
241 | ||
242 | /* enable rx ints */ | |
b36ece83 | 243 | mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE); |
4c1fba44 AV |
244 | |
245 | /* transmit word */ | |
246 | word = mspi->get_tx(mspi); | |
b36ece83 | 247 | mpc8xxx_spi_write_reg(®_base->transmit, word); |
4c1fba44 AV |
248 | |
249 | return 0; | |
250 | } | |
251 | ||
64fe73d1 | 252 | static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t) |
4c1fba44 | 253 | { |
d32382ca | 254 | struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(spi->controller); |
dd67de8c | 255 | struct fsl_spi_reg __iomem *reg_base; |
4c1fba44 AV |
256 | unsigned int len = t->len; |
257 | u8 bits_per_word; | |
258 | int ret; | |
c9bfcb31 | 259 | |
b36ece83 | 260 | reg_base = mpc8xxx_spi->reg_base; |
c9bfcb31 JT |
261 | bits_per_word = spi->bits_per_word; |
262 | if (t->bits_per_word) | |
263 | bits_per_word = t->bits_per_word; | |
4c1fba44 | 264 | |
4084c8ca | 265 | if (bits_per_word > 8) |
c9bfcb31 | 266 | len /= 2; |
4084c8ca | 267 | if (bits_per_word > 16) |
c9bfcb31 | 268 | len /= 2; |
aa77d96b | 269 | |
4c1fba44 AV |
270 | mpc8xxx_spi->tx = t->tx_buf; |
271 | mpc8xxx_spi->rx = t->rx_buf; | |
c9bfcb31 | 272 | |
16735d02 | 273 | reinit_completion(&mpc8xxx_spi->done); |
c9bfcb31 | 274 | |
4c1fba44 | 275 | if (mpc8xxx_spi->flags & SPI_CPM_MODE) |
64fe73d1 | 276 | ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t); |
4c1fba44 | 277 | else |
b36ece83 | 278 | ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len); |
4c1fba44 AV |
279 | if (ret) |
280 | return ret; | |
c9bfcb31 | 281 | |
575c5807 | 282 | wait_for_completion(&mpc8xxx_spi->done); |
c9bfcb31 JT |
283 | |
284 | /* disable rx ints */ | |
b36ece83 | 285 | mpc8xxx_spi_write_reg(®_base->mask, 0); |
c9bfcb31 | 286 | |
4c1fba44 | 287 | if (mpc8xxx_spi->flags & SPI_CPM_MODE) |
b36ece83 | 288 | fsl_spi_cpm_bufs_complete(mpc8xxx_spi); |
4c1fba44 | 289 | |
575c5807 | 290 | return mpc8xxx_spi->count; |
c9bfcb31 JT |
291 | } |
292 | ||
64ca1a03 CL |
293 | static int fsl_spi_prepare_message(struct spi_controller *ctlr, |
294 | struct spi_message *m) | |
c9bfcb31 | 295 | { |
64ca1a03 CL |
296 | struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(ctlr); |
297 | struct spi_transfer *t; | |
3b553e00 CL |
298 | struct spi_transfer *first; |
299 | ||
300 | first = list_first_entry(&m->transfers, struct spi_transfer, | |
301 | transfer_list); | |
b9b9af11 | 302 | |
af0e6242 RV |
303 | /* |
304 | * In CPU mode, optimize large byte transfers to use larger | |
305 | * bits_per_word values to reduce number of interrupts taken. | |
3b553e00 CL |
306 | * |
307 | * Some glitches can appear on the SPI clock when the mode changes. | |
308 | * Check that there is no speed change during the transfer and set it up | |
309 | * now to change the mode without having a chip-select asserted. | |
af0e6242 | 310 | */ |
3b553e00 CL |
311 | list_for_each_entry(t, &m->transfers, transfer_list) { |
312 | if (t->speed_hz != first->speed_hz) { | |
313 | dev_err(&m->spi->dev, | |
314 | "speed_hz cannot change during message.\n"); | |
315 | return -EINVAL; | |
316 | } | |
317 | if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) { | |
af0e6242 RV |
318 | if (t->len < 256 || t->bits_per_word != 8) |
319 | continue; | |
320 | if ((t->len & 3) == 0) | |
321 | t->bits_per_word = 32; | |
322 | else if ((t->len & 1) == 0) | |
323 | t->bits_per_word = 16; | |
8a5299a1 CL |
324 | } else { |
325 | /* | |
326 | * CPM/QE uses Little Endian for words > 8 | |
327 | * so transform 16 and 32 bits words into 8 bits | |
328 | * Unfortnatly that doesn't work for LSB so | |
329 | * reject these for now | |
330 | * Note: 32 bits word, LSB works iff | |
331 | * tfcr/rfcr is set to CPMFCR_GBL | |
332 | */ | |
333 | if (m->spi->mode & SPI_LSB_FIRST && t->bits_per_word > 8) | |
334 | return -EINVAL; | |
335 | if (t->bits_per_word == 16 || t->bits_per_word == 32) | |
336 | t->bits_per_word = 8; /* pretend its 8 bits */ | |
fc96ec82 CL |
337 | if (t->bits_per_word == 8 && t->len >= 256 && |
338 | (mpc8xxx_spi->flags & SPI_CPM1)) | |
339 | t->bits_per_word = 16; | |
af0e6242 RV |
340 | } |
341 | } | |
3b553e00 | 342 | return fsl_spi_setup_transfer(m->spi, first); |
64ca1a03 | 343 | } |
af0e6242 | 344 | |
64ca1a03 CL |
345 | static int fsl_spi_transfer_one(struct spi_controller *controller, |
346 | struct spi_device *spi, | |
347 | struct spi_transfer *t) | |
348 | { | |
349 | int status; | |
b9b9af11 | 350 | |
64ca1a03 CL |
351 | status = fsl_spi_setup_transfer(spi, t); |
352 | if (status < 0) | |
353 | return status; | |
354 | if (t->len) | |
64fe73d1 | 355 | status = fsl_spi_bufs(spi, t); |
64ca1a03 CL |
356 | if (status > 0) |
357 | return -EMSGSIZE; | |
b9b9af11 | 358 | |
64ca1a03 CL |
359 | return status; |
360 | } | |
b9b9af11 | 361 | |
64ca1a03 CL |
362 | static int fsl_spi_unprepare_message(struct spi_controller *controller, |
363 | struct spi_message *msg) | |
364 | { | |
365 | return fsl_spi_setup_transfer(msg->spi, NULL); | |
ccf06998 KG |
366 | } |
367 | ||
b36ece83 | 368 | static int fsl_spi_setup(struct spi_device *spi) |
ccf06998 | 369 | { |
575c5807 | 370 | struct mpc8xxx_spi *mpc8xxx_spi; |
dd67de8c | 371 | struct fsl_spi_reg __iomem *reg_base; |
2ec6f20b | 372 | bool initial_setup = false; |
ccf06998 | 373 | int retval; |
c9bfcb31 | 374 | u32 hw_mode; |
d9f26748 | 375 | struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi); |
ccf06998 KG |
376 | |
377 | if (!spi->max_speed_hz) | |
378 | return -EINVAL; | |
379 | ||
c9bfcb31 | 380 | if (!cs) { |
d9f26748 | 381 | cs = kzalloc(sizeof(*cs), GFP_KERNEL); |
c9bfcb31 JT |
382 | if (!cs) |
383 | return -ENOMEM; | |
d9f26748 | 384 | spi_set_ctldata(spi, cs); |
2ec6f20b | 385 | initial_setup = true; |
c9bfcb31 | 386 | } |
d32382ca | 387 | mpc8xxx_spi = spi_controller_get_devdata(spi->controller); |
ccf06998 | 388 | |
b36ece83 MH |
389 | reg_base = mpc8xxx_spi->reg_base; |
390 | ||
88393161 | 391 | hw_mode = cs->hw_mode; /* Save original settings */ |
b36ece83 | 392 | cs->hw_mode = mpc8xxx_spi_read_reg(®_base->mode); |
c9bfcb31 JT |
393 | /* mask out bits we are going to set */ |
394 | cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH | |
395 | | SPMODE_REV | SPMODE_LOOP); | |
396 | ||
397 | if (spi->mode & SPI_CPHA) | |
398 | cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK; | |
399 | if (spi->mode & SPI_CPOL) | |
400 | cs->hw_mode |= SPMODE_CI_INACTIVEHIGH; | |
401 | if (!(spi->mode & SPI_LSB_FIRST)) | |
402 | cs->hw_mode |= SPMODE_REV; | |
403 | if (spi->mode & SPI_LOOP) | |
404 | cs->hw_mode |= SPMODE_LOOP; | |
405 | ||
b36ece83 | 406 | retval = fsl_spi_setup_transfer(spi, NULL); |
c9bfcb31 JT |
407 | if (retval < 0) { |
408 | cs->hw_mode = hw_mode; /* Restore settings */ | |
2ec6f20b LW |
409 | if (initial_setup) |
410 | kfree(cs); | |
ccf06998 | 411 | return retval; |
c9bfcb31 | 412 | } |
f482cd0f | 413 | |
ccf06998 KG |
414 | return 0; |
415 | } | |
416 | ||
76a7498f AL |
417 | static void fsl_spi_cleanup(struct spi_device *spi) |
418 | { | |
d9f26748 | 419 | struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi); |
76a7498f | 420 | |
d9f26748 AL |
421 | kfree(cs); |
422 | spi_set_ctldata(spi, NULL); | |
76a7498f AL |
423 | } |
424 | ||
b36ece83 | 425 | static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events) |
4c1fba44 | 426 | { |
dd67de8c | 427 | struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; |
b36ece83 | 428 | |
4c1fba44 AV |
429 | /* We need handle RX first */ |
430 | if (events & SPIE_NE) { | |
b36ece83 | 431 | u32 rx_data = mpc8xxx_spi_read_reg(®_base->receive); |
4c1fba44 AV |
432 | |
433 | if (mspi->rx) | |
434 | mspi->get_rx(rx_data, mspi); | |
ccf06998 KG |
435 | } |
436 | ||
4c1fba44 | 437 | if ((events & SPIE_NF) == 0) |
ccf06998 | 438 | /* spin until TX is done */ |
4c1fba44 | 439 | while (((events = |
b36ece83 | 440 | mpc8xxx_spi_read_reg(®_base->event)) & |
ccf06998 | 441 | SPIE_NF) == 0) |
9effb959 | 442 | cpu_relax(); |
ccf06998 | 443 | |
4c1fba44 | 444 | /* Clear the events */ |
b36ece83 | 445 | mpc8xxx_spi_write_reg(®_base->event, events); |
4c1fba44 AV |
446 | |
447 | mspi->count -= 1; | |
448 | if (mspi->count) { | |
449 | u32 word = mspi->get_tx(mspi); | |
450 | ||
b36ece83 | 451 | mpc8xxx_spi_write_reg(®_base->transmit, word); |
ccf06998 | 452 | } else { |
4c1fba44 | 453 | complete(&mspi->done); |
ccf06998 | 454 | } |
4c1fba44 | 455 | } |
ccf06998 | 456 | |
b36ece83 | 457 | static irqreturn_t fsl_spi_irq(s32 irq, void *context_data) |
4c1fba44 AV |
458 | { |
459 | struct mpc8xxx_spi *mspi = context_data; | |
460 | irqreturn_t ret = IRQ_NONE; | |
461 | u32 events; | |
dd67de8c | 462 | struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; |
4c1fba44 AV |
463 | |
464 | /* Get interrupt events(tx/rx) */ | |
b36ece83 | 465 | events = mpc8xxx_spi_read_reg(®_base->event); |
4c1fba44 AV |
466 | if (events) |
467 | ret = IRQ_HANDLED; | |
468 | ||
469 | dev_dbg(mspi->dev, "%s: events %x\n", __func__, events); | |
470 | ||
471 | if (mspi->flags & SPI_CPM_MODE) | |
b36ece83 | 472 | fsl_spi_cpm_irq(mspi, events); |
4c1fba44 | 473 | else |
b36ece83 | 474 | fsl_spi_cpu_irq(mspi, events); |
ccf06998 KG |
475 | |
476 | return ret; | |
477 | } | |
4c1fba44 | 478 | |
447b0c7b AL |
479 | static void fsl_spi_grlib_cs_control(struct spi_device *spi, bool on) |
480 | { | |
d32382ca | 481 | struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(spi->controller); |
dd67de8c | 482 | struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base; |
447b0c7b | 483 | u32 slvsel; |
9e264f3f | 484 | u16 cs = spi_get_chipselect(spi, 0); |
447b0c7b | 485 | |
64ca1a03 | 486 | if (cs < mpc8xxx_spi->native_chipselects) { |
76a7498f AL |
487 | slvsel = mpc8xxx_spi_read_reg(®_base->slvsel); |
488 | slvsel = on ? (slvsel | (1 << cs)) : (slvsel & ~(1 << cs)); | |
489 | mpc8xxx_spi_write_reg(®_base->slvsel, slvsel); | |
490 | } | |
447b0c7b AL |
491 | } |
492 | ||
493 | static void fsl_spi_grlib_probe(struct device *dev) | |
494 | { | |
d32382ca YY |
495 | struct spi_controller *host = dev_get_drvdata(dev); |
496 | struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(host); | |
dd67de8c | 497 | struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base; |
447b0c7b AL |
498 | int mbits; |
499 | u32 capabilities; | |
500 | ||
501 | capabilities = mpc8xxx_spi_read_reg(®_base->cap); | |
502 | ||
503 | mpc8xxx_spi->set_shifts = fsl_spi_grlib_set_shifts; | |
504 | mbits = SPCAP_MAXWLEN(capabilities); | |
505 | if (mbits) | |
506 | mpc8xxx_spi->max_bits_per_word = mbits + 1; | |
507 | ||
76a7498f | 508 | mpc8xxx_spi->native_chipselects = 0; |
447b0c7b | 509 | if (SPCAP_SSEN(capabilities)) { |
76a7498f | 510 | mpc8xxx_spi->native_chipselects = SPCAP_SSSZ(capabilities); |
447b0c7b AL |
511 | mpc8xxx_spi_write_reg(®_base->slvsel, 0xffffffff); |
512 | } | |
d32382ca YY |
513 | host->num_chipselect = mpc8xxx_spi->native_chipselects; |
514 | host->set_cs = fsl_spi_grlib_cs_control; | |
64ca1a03 CL |
515 | } |
516 | ||
517 | static void fsl_spi_cs_control(struct spi_device *spi, bool on) | |
518 | { | |
519 | struct device *dev = spi->dev.parent->parent; | |
520 | struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); | |
521 | struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata); | |
522 | ||
523 | if (WARN_ON_ONCE(!pinfo->immr_spi_cs)) | |
524 | return; | |
525 | iowrite32be(on ? 0 : SPI_BOOT_SEL_BIT, pinfo->immr_spi_cs); | |
447b0c7b AL |
526 | } |
527 | ||
d32382ca | 528 | static struct spi_controller *fsl_spi_probe(struct device *dev, |
b36ece83 | 529 | struct resource *mem, unsigned int irq) |
ccf06998 | 530 | { |
8074cf06 | 531 | struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); |
d32382ca | 532 | struct spi_controller *host; |
575c5807 | 533 | struct mpc8xxx_spi *mpc8xxx_spi; |
dd67de8c | 534 | struct fsl_spi_reg __iomem *reg_base; |
ccf06998 KG |
535 | u32 regval; |
536 | int ret = 0; | |
537 | ||
d32382ca YY |
538 | host = spi_alloc_host(dev, sizeof(struct mpc8xxx_spi)); |
539 | if (host == NULL) { | |
ccf06998 KG |
540 | ret = -ENOMEM; |
541 | goto err; | |
542 | } | |
543 | ||
d32382ca | 544 | dev_set_drvdata(dev, host); |
ccf06998 | 545 | |
c592becb | 546 | mpc8xxx_spi_probe(dev, mem, irq); |
e7db06b5 | 547 | |
d32382ca YY |
548 | host->setup = fsl_spi_setup; |
549 | host->cleanup = fsl_spi_cleanup; | |
550 | host->prepare_message = fsl_spi_prepare_message; | |
551 | host->transfer_one = fsl_spi_transfer_one; | |
552 | host->unprepare_message = fsl_spi_unprepare_message; | |
553 | host->use_gpio_descriptors = true; | |
554 | host->set_cs = fsl_spi_cs_control; | |
575c5807 | 555 | |
d32382ca | 556 | mpc8xxx_spi = spi_controller_get_devdata(host); |
8922a366 | 557 | mpc8xxx_spi->max_bits_per_word = 32; |
c3f3e771 | 558 | mpc8xxx_spi->type = fsl_spi_get_type(dev); |
575c5807 | 559 | |
b36ece83 | 560 | ret = fsl_spi_cpm_init(mpc8xxx_spi); |
4c1fba44 AV |
561 | if (ret) |
562 | goto err_cpm_init; | |
563 | ||
4178b6b1 | 564 | mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem); |
37c5db79 AL |
565 | if (IS_ERR(mpc8xxx_spi->reg_base)) { |
566 | ret = PTR_ERR(mpc8xxx_spi->reg_base); | |
4178b6b1 | 567 | goto err_probe; |
447b0c7b AL |
568 | } |
569 | ||
570 | if (mpc8xxx_spi->type == TYPE_GRLIB) | |
571 | fsl_spi_grlib_probe(dev); | |
572 | ||
8a5299a1 | 573 | if (mpc8xxx_spi->flags & SPI_CPM_MODE) |
d32382ca | 574 | host->bits_per_word_mask = |
8a5299a1 CL |
575 | (SPI_BPW_RANGE_MASK(4, 8) | SPI_BPW_MASK(16) | SPI_BPW_MASK(32)); |
576 | else | |
d32382ca | 577 | host->bits_per_word_mask = |
8a5299a1 CL |
578 | (SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32)); |
579 | ||
d32382ca | 580 | host->bits_per_word_mask &= |
f734394d AL |
581 | SPI_BPW_RANGE_MASK(1, mpc8xxx_spi->max_bits_per_word); |
582 | ||
b48c4e3c AL |
583 | if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) |
584 | mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts; | |
585 | ||
586 | if (mpc8xxx_spi->set_shifts) | |
587 | /* 8 bits per word and MSB first */ | |
588 | mpc8xxx_spi->set_shifts(&mpc8xxx_spi->rx_shift, | |
589 | &mpc8xxx_spi->tx_shift, 8, 1); | |
f29ba280 | 590 | |
ccf06998 | 591 | /* Register for SPI Interrupt */ |
4178b6b1 HK |
592 | ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_spi_irq, |
593 | 0, "fsl_spi", mpc8xxx_spi); | |
ccf06998 KG |
594 | |
595 | if (ret != 0) | |
4178b6b1 | 596 | goto err_probe; |
ccf06998 | 597 | |
b36ece83 | 598 | reg_base = mpc8xxx_spi->reg_base; |
ccf06998 KG |
599 | |
600 | /* SPI controller initializations */ | |
b36ece83 MH |
601 | mpc8xxx_spi_write_reg(®_base->mode, 0); |
602 | mpc8xxx_spi_write_reg(®_base->mask, 0); | |
603 | mpc8xxx_spi_write_reg(®_base->command, 0); | |
604 | mpc8xxx_spi_write_reg(®_base->event, 0xffffffff); | |
ccf06998 KG |
605 | |
606 | /* Enable SPI interface */ | |
607 | regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE; | |
8922a366 AL |
608 | if (mpc8xxx_spi->max_bits_per_word < 8) { |
609 | regval &= ~SPMODE_LEN(0xF); | |
610 | regval |= SPMODE_LEN(mpc8xxx_spi->max_bits_per_word - 1); | |
611 | } | |
87ec0e98 | 612 | if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) |
f29ba280 JT |
613 | regval |= SPMODE_OP; |
614 | ||
b36ece83 | 615 | mpc8xxx_spi_write_reg(®_base->mode, regval); |
c9bfcb31 | 616 | |
d32382ca | 617 | ret = devm_spi_register_controller(dev, host); |
c9bfcb31 | 618 | if (ret < 0) |
4178b6b1 | 619 | goto err_probe; |
ccf06998 | 620 | |
b36ece83 | 621 | dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base, |
87ec0e98 | 622 | mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags)); |
ccf06998 | 623 | |
d32382ca | 624 | return host; |
ccf06998 | 625 | |
4178b6b1 | 626 | err_probe: |
b36ece83 | 627 | fsl_spi_cpm_free(mpc8xxx_spi); |
4c1fba44 | 628 | err_cpm_init: |
d32382ca | 629 | spi_controller_put(host); |
ccf06998 | 630 | err: |
35b4b3c0 | 631 | return ERR_PTR(ret); |
ccf06998 KG |
632 | } |
633 | ||
fd4a319b | 634 | static int of_fsl_spi_probe(struct platform_device *ofdev) |
35b4b3c0 AV |
635 | { |
636 | struct device *dev = &ofdev->dev; | |
61c7a080 | 637 | struct device_node *np = ofdev->dev.of_node; |
d32382ca | 638 | struct spi_controller *host; |
35b4b3c0 | 639 | struct resource mem; |
2f3d8035 CL |
640 | int irq, type; |
641 | int ret; | |
5fed9fe5 YY |
642 | bool spisel_boot = false; |
643 | #if IS_ENABLED(CONFIG_FSL_SOC) | |
644 | struct mpc8xxx_spi_probe_info *pinfo = NULL; | |
645 | #endif | |
646 | ||
35b4b3c0 | 647 | |
18d306d1 | 648 | ret = of_mpc8xxx_spi_probe(ofdev); |
b36ece83 MH |
649 | if (ret) |
650 | return ret; | |
35b4b3c0 | 651 | |
447b0c7b AL |
652 | type = fsl_spi_get_type(&ofdev->dev); |
653 | if (type == TYPE_FSL) { | |
0f0581b2 LW |
654 | struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); |
655 | #if IS_ENABLED(CONFIG_FSL_SOC) | |
5fed9fe5 | 656 | pinfo = to_of_pinfo(pdata); |
0f0581b2 | 657 | |
122541f2 | 658 | spisel_boot = of_property_read_bool(np, "fsl,spisel_boot"); |
0f0581b2 LW |
659 | if (spisel_boot) { |
660 | pinfo->immr_spi_cs = ioremap(get_immrbase() + IMMR_SPI_CS_OFFSET, 4); | |
2f3d8035 CL |
661 | if (!pinfo->immr_spi_cs) |
662 | return -ENOMEM; | |
0f0581b2 LW |
663 | } |
664 | #endif | |
7251953d LW |
665 | /* |
666 | * Handle the case where we have one hardwired (always selected) | |
667 | * device on the first "chipselect". Else we let the core code | |
668 | * handle any GPIOs or native chip selects and assign the | |
669 | * appropriate callback for dealing with the CS lines. This isn't | |
670 | * supported on the GRLIB variant. | |
671 | */ | |
672 | ret = gpiod_count(dev, "cs"); | |
122541f2 RV |
673 | if (ret < 0) |
674 | ret = 0; | |
64ca1a03 | 675 | if (ret == 0 && !spisel_boot) |
7251953d | 676 | pdata->max_chipselect = 1; |
64ca1a03 | 677 | else |
122541f2 | 678 | pdata->max_chipselect = ret + spisel_boot; |
447b0c7b | 679 | } |
35b4b3c0 AV |
680 | |
681 | ret = of_address_to_resource(np, 0, &mem); | |
682 | if (ret) | |
5fed9fe5 | 683 | goto unmap_out; |
35b4b3c0 | 684 | |
63aa6a69 | 685 | irq = platform_get_irq(ofdev, 0); |
5fed9fe5 YY |
686 | if (irq < 0) { |
687 | ret = irq; | |
688 | goto unmap_out; | |
689 | } | |
35b4b3c0 | 690 | |
d32382ca | 691 | host = fsl_spi_probe(dev, &mem, irq); |
35b4b3c0 | 692 | |
d32382ca | 693 | return PTR_ERR_OR_ZERO(host); |
5fed9fe5 YY |
694 | |
695 | unmap_out: | |
696 | #if IS_ENABLED(CONFIG_FSL_SOC) | |
697 | if (spisel_boot) | |
698 | iounmap(pinfo->immr_spi_cs); | |
699 | #endif | |
700 | return ret; | |
35b4b3c0 AV |
701 | } |
702 | ||
fc4935a0 | 703 | static void of_fsl_spi_remove(struct platform_device *ofdev) |
35b4b3c0 | 704 | { |
d32382ca YY |
705 | struct spi_controller *host = platform_get_drvdata(ofdev); |
706 | struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(host); | |
35b4b3c0 | 707 | |
3c5395b6 | 708 | fsl_spi_cpm_free(mpc8xxx_spi); |
35b4b3c0 AV |
709 | } |
710 | ||
18d306d1 | 711 | static struct platform_driver of_fsl_spi_driver = { |
4018294b | 712 | .driver = { |
b36ece83 | 713 | .name = "fsl_spi", |
b36ece83 | 714 | .of_match_table = of_fsl_spi_match, |
4018294b | 715 | }, |
b36ece83 | 716 | .probe = of_fsl_spi_probe, |
fc4935a0 | 717 | .remove_new = of_fsl_spi_remove, |
35b4b3c0 AV |
718 | }; |
719 | ||
720 | #ifdef CONFIG_MPC832x_RDB | |
721 | /* | |
b36ece83 | 722 | * XXX XXX XXX |
35b4b3c0 AV |
723 | * This is "legacy" platform driver, was used by the MPC8323E-RDB boards |
724 | * only. The driver should go away soon, since newer MPC8323E-RDB's device | |
725 | * tree can work with OpenFirmware driver. But for now we support old trees | |
726 | * as well. | |
727 | */ | |
fd4a319b | 728 | static int plat_mpc8xxx_spi_probe(struct platform_device *pdev) |
35b4b3c0 AV |
729 | { |
730 | struct resource *mem; | |
e9a172f0 | 731 | int irq; |
d32382ca | 732 | struct spi_controller *host; |
35b4b3c0 | 733 | |
8074cf06 | 734 | if (!dev_get_platdata(&pdev->dev)) |
35b4b3c0 AV |
735 | return -EINVAL; |
736 | ||
737 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
738 | if (!mem) | |
739 | return -EINVAL; | |
740 | ||
741 | irq = platform_get_irq(pdev, 0); | |
d8736266 ZW |
742 | if (irq < 0) |
743 | return irq; | |
35b4b3c0 | 744 | |
d32382ca YY |
745 | host = fsl_spi_probe(&pdev->dev, mem, irq); |
746 | return PTR_ERR_OR_ZERO(host); | |
35b4b3c0 AV |
747 | } |
748 | ||
fc4935a0 | 749 | static void plat_mpc8xxx_spi_remove(struct platform_device *pdev) |
35b4b3c0 | 750 | { |
d32382ca YY |
751 | struct spi_controller *host = platform_get_drvdata(pdev); |
752 | struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(host); | |
3c5395b6 HK |
753 | |
754 | fsl_spi_cpm_free(mpc8xxx_spi); | |
35b4b3c0 AV |
755 | } |
756 | ||
575c5807 AV |
757 | MODULE_ALIAS("platform:mpc8xxx_spi"); |
758 | static struct platform_driver mpc8xxx_spi_driver = { | |
759 | .probe = plat_mpc8xxx_spi_probe, | |
fc4935a0 | 760 | .remove_new = plat_mpc8xxx_spi_remove, |
ccf06998 | 761 | .driver = { |
575c5807 | 762 | .name = "mpc8xxx_spi", |
ccf06998 KG |
763 | }, |
764 | }; | |
765 | ||
35b4b3c0 AV |
766 | static bool legacy_driver_failed; |
767 | ||
768 | static void __init legacy_driver_register(void) | |
769 | { | |
575c5807 | 770 | legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver); |
35b4b3c0 AV |
771 | } |
772 | ||
773 | static void __exit legacy_driver_unregister(void) | |
774 | { | |
775 | if (legacy_driver_failed) | |
776 | return; | |
575c5807 | 777 | platform_driver_unregister(&mpc8xxx_spi_driver); |
35b4b3c0 AV |
778 | } |
779 | #else | |
780 | static void __init legacy_driver_register(void) {} | |
781 | static void __exit legacy_driver_unregister(void) {} | |
782 | #endif /* CONFIG_MPC832x_RDB */ | |
783 | ||
b36ece83 | 784 | static int __init fsl_spi_init(void) |
ccf06998 | 785 | { |
35b4b3c0 | 786 | legacy_driver_register(); |
18d306d1 | 787 | return platform_driver_register(&of_fsl_spi_driver); |
ccf06998 | 788 | } |
b36ece83 | 789 | module_init(fsl_spi_init); |
ccf06998 | 790 | |
b36ece83 | 791 | static void __exit fsl_spi_exit(void) |
ccf06998 | 792 | { |
18d306d1 | 793 | platform_driver_unregister(&of_fsl_spi_driver); |
35b4b3c0 | 794 | legacy_driver_unregister(); |
ccf06998 | 795 | } |
b36ece83 | 796 | module_exit(fsl_spi_exit); |
ccf06998 KG |
797 | |
798 | MODULE_AUTHOR("Kumar Gala"); | |
b36ece83 | 799 | MODULE_DESCRIPTION("Simple Freescale SPI Driver"); |
ccf06998 | 800 | MODULE_LICENSE("GPL"); |