]>
Commit | Line | Data |
---|---|---|
79650597 FE |
1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
3 | // Copyright (C) 2008 Juergen Beisert | |
b5f3294f SH |
4 | |
5 | #include <linux/clk.h> | |
6 | #include <linux/completion.h> | |
7 | #include <linux/delay.h> | |
f62caccd RG |
8 | #include <linux/dmaengine.h> |
9 | #include <linux/dma-mapping.h> | |
b5f3294f SH |
10 | #include <linux/err.h> |
11 | #include <linux/gpio.h> | |
b5f3294f SH |
12 | #include <linux/interrupt.h> |
13 | #include <linux/io.h> | |
14 | #include <linux/irq.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/platform_device.h> | |
5a0e3ad6 | 18 | #include <linux/slab.h> |
b5f3294f SH |
19 | #include <linux/spi/spi.h> |
20 | #include <linux/spi/spi_bitbang.h> | |
21 | #include <linux/types.h> | |
22a85e4c SG |
22 | #include <linux/of.h> |
23 | #include <linux/of_device.h> | |
24 | #include <linux/of_gpio.h> | |
b5f3294f | 25 | |
f62caccd | 26 | #include <linux/platform_data/dma-imx.h> |
82906b13 | 27 | #include <linux/platform_data/spi-imx.h> |
b5f3294f SH |
28 | |
29 | #define DRIVER_NAME "spi_imx" | |
30 | ||
0a9c8998 TP |
31 | static bool use_dma = true; |
32 | module_param(use_dma, bool, 0644); | |
33 | MODULE_PARM_DESC(use_dma, "Enable usage of DMA when available (default)"); | |
34 | ||
b5f3294f SH |
35 | #define MXC_CSPIRXDATA 0x00 |
36 | #define MXC_CSPITXDATA 0x04 | |
37 | #define MXC_CSPICTRL 0x08 | |
38 | #define MXC_CSPIINT 0x0c | |
39 | #define MXC_RESET 0x1c | |
40 | ||
41 | /* generic defines to abstract from the different register layouts */ | |
42 | #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */ | |
43 | #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */ | |
71abd290 | 44 | #define MXC_INT_RDR BIT(4) /* Receive date threshold interrupt */ |
b5f3294f | 45 | |
30d67142 UKK |
46 | /* The maximum bytes that a sdma BD can transfer. */ |
47 | #define MAX_SDMA_BD_BYTES (1 << 15) | |
1673c81d | 48 | #define MX51_ECSPI_CTRL_MAX_BURST 512 |
71abd290 | 49 | /* The maximum bytes that IMX53_ECSPI can transfer in slave mode.*/ |
50 | #define MX53_MAX_TRANSFER_BYTES 512 | |
b5f3294f | 51 | |
f4ba6315 | 52 | enum spi_imx_devtype { |
04ee5854 SG |
53 | IMX1_CSPI, |
54 | IMX21_CSPI, | |
55 | IMX27_CSPI, | |
56 | IMX31_CSPI, | |
57 | IMX35_CSPI, /* CSPI on all i.mx except above */ | |
26e4bb86 | 58 | IMX51_ECSPI, /* ECSPI on i.mx51 */ |
59 | IMX53_ECSPI, /* ECSPI on i.mx53 and later */ | |
f4ba6315 UKK |
60 | }; |
61 | ||
62 | struct spi_imx_data; | |
63 | ||
64 | struct spi_imx_devtype_data { | |
65 | void (*intctrl)(struct spi_imx_data *, int); | |
e697271c | 66 | int (*prepare_message)(struct spi_imx_data *, struct spi_message *); |
1d374703 UKK |
67 | int (*prepare_transfer)(struct spi_imx_data *, struct spi_device *, |
68 | struct spi_transfer *); | |
f4ba6315 UKK |
69 | void (*trigger)(struct spi_imx_data *); |
70 | int (*rx_available)(struct spi_imx_data *); | |
1723e66b | 71 | void (*reset)(struct spi_imx_data *); |
987a2dfe | 72 | void (*setup_wml)(struct spi_imx_data *); |
71abd290 | 73 | void (*disable)(struct spi_imx_data *); |
bcd8e776 | 74 | void (*disable_dma)(struct spi_imx_data *); |
fd8d4e2d | 75 | bool has_dmamode; |
71abd290 | 76 | bool has_slavemode; |
fd8d4e2d | 77 | unsigned int fifo_size; |
1673c81d | 78 | bool dynamic_burst; |
04ee5854 | 79 | enum spi_imx_devtype devtype; |
f4ba6315 UKK |
80 | }; |
81 | ||
6cdeb002 | 82 | struct spi_imx_data { |
b5f3294f | 83 | struct spi_bitbang bitbang; |
6aa800ca | 84 | struct device *dev; |
b5f3294f SH |
85 | |
86 | struct completion xfer_done; | |
cc4d22ae | 87 | void __iomem *base; |
f12ae171 AB |
88 | unsigned long base_phys; |
89 | ||
aa29d840 SH |
90 | struct clk *clk_per; |
91 | struct clk *clk_ipg; | |
b5f3294f | 92 | unsigned long spi_clk; |
4bfe927a | 93 | unsigned int spi_bus_clk; |
b5f3294f | 94 | |
d52345b6 | 95 | unsigned int bits_per_word; |
f72efa7e | 96 | unsigned int spi_drctl; |
f12ae171 | 97 | |
1673c81d | 98 | unsigned int count, remainder; |
6cdeb002 UKK |
99 | void (*tx)(struct spi_imx_data *); |
100 | void (*rx)(struct spi_imx_data *); | |
b5f3294f SH |
101 | void *rx_buf; |
102 | const void *tx_buf; | |
103 | unsigned int txfifo; /* number of words pushed in tx FIFO */ | |
2ca300ac | 104 | unsigned int dynamic_burst; |
b5f3294f | 105 | |
71abd290 | 106 | /* Slave mode */ |
107 | bool slave_mode; | |
108 | bool slave_aborted; | |
109 | unsigned int slave_burst; | |
110 | ||
f62caccd | 111 | /* DMA */ |
f62caccd | 112 | bool usedma; |
0dfbaa89 | 113 | u32 wml; |
f62caccd RG |
114 | struct completion dma_rx_completion; |
115 | struct completion dma_tx_completion; | |
116 | ||
80023cb3 | 117 | const struct spi_imx_devtype_data *devtype_data; |
b5f3294f SH |
118 | }; |
119 | ||
04ee5854 SG |
120 | static inline int is_imx27_cspi(struct spi_imx_data *d) |
121 | { | |
122 | return d->devtype_data->devtype == IMX27_CSPI; | |
123 | } | |
124 | ||
125 | static inline int is_imx35_cspi(struct spi_imx_data *d) | |
126 | { | |
127 | return d->devtype_data->devtype == IMX35_CSPI; | |
128 | } | |
129 | ||
f8a87617 AB |
130 | static inline int is_imx51_ecspi(struct spi_imx_data *d) |
131 | { | |
132 | return d->devtype_data->devtype == IMX51_ECSPI; | |
133 | } | |
134 | ||
26e4bb86 | 135 | static inline int is_imx53_ecspi(struct spi_imx_data *d) |
136 | { | |
137 | return d->devtype_data->devtype == IMX53_ECSPI; | |
138 | } | |
139 | ||
b5f3294f | 140 | #define MXC_SPI_BUF_RX(type) \ |
6cdeb002 | 141 | static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \ |
b5f3294f | 142 | { \ |
6cdeb002 | 143 | unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \ |
b5f3294f | 144 | \ |
6cdeb002 UKK |
145 | if (spi_imx->rx_buf) { \ |
146 | *(type *)spi_imx->rx_buf = val; \ | |
147 | spi_imx->rx_buf += sizeof(type); \ | |
b5f3294f | 148 | } \ |
2ca300ac MC |
149 | \ |
150 | spi_imx->remainder -= sizeof(type); \ | |
b5f3294f SH |
151 | } |
152 | ||
153 | #define MXC_SPI_BUF_TX(type) \ | |
6cdeb002 | 154 | static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \ |
b5f3294f SH |
155 | { \ |
156 | type val = 0; \ | |
157 | \ | |
6cdeb002 UKK |
158 | if (spi_imx->tx_buf) { \ |
159 | val = *(type *)spi_imx->tx_buf; \ | |
160 | spi_imx->tx_buf += sizeof(type); \ | |
b5f3294f SH |
161 | } \ |
162 | \ | |
6cdeb002 | 163 | spi_imx->count -= sizeof(type); \ |
b5f3294f | 164 | \ |
6cdeb002 | 165 | writel(val, spi_imx->base + MXC_CSPITXDATA); \ |
b5f3294f SH |
166 | } |
167 | ||
168 | MXC_SPI_BUF_RX(u8) | |
169 | MXC_SPI_BUF_TX(u8) | |
170 | MXC_SPI_BUF_RX(u16) | |
171 | MXC_SPI_BUF_TX(u16) | |
172 | MXC_SPI_BUF_RX(u32) | |
173 | MXC_SPI_BUF_TX(u32) | |
174 | ||
175 | /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set | |
176 | * (which is currently not the case in this driver) | |
177 | */ | |
178 | static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192, | |
179 | 256, 384, 512, 768, 1024}; | |
180 | ||
181 | /* MX21, MX27 */ | |
6cdeb002 | 182 | static unsigned int spi_imx_clkdiv_1(unsigned int fin, |
32df9ff2 | 183 | unsigned int fspi, unsigned int max, unsigned int *fres) |
b5f3294f | 184 | { |
04ee5854 | 185 | int i; |
b5f3294f SH |
186 | |
187 | for (i = 2; i < max; i++) | |
188 | if (fspi * mxc_clkdivs[i] >= fin) | |
32df9ff2 | 189 | break; |
b5f3294f | 190 | |
32df9ff2 RB |
191 | *fres = fin / mxc_clkdivs[i]; |
192 | return i; | |
b5f3294f SH |
193 | } |
194 | ||
0b599603 | 195 | /* MX1, MX31, MX35, MX51 CSPI */ |
6cdeb002 | 196 | static unsigned int spi_imx_clkdiv_2(unsigned int fin, |
2636ba8f | 197 | unsigned int fspi, unsigned int *fres) |
b5f3294f SH |
198 | { |
199 | int i, div = 4; | |
200 | ||
201 | for (i = 0; i < 7; i++) { | |
202 | if (fspi * div >= fin) | |
2636ba8f | 203 | goto out; |
b5f3294f SH |
204 | div <<= 1; |
205 | } | |
206 | ||
2636ba8f MK |
207 | out: |
208 | *fres = fin / div; | |
209 | return i; | |
b5f3294f SH |
210 | } |
211 | ||
2e312f6c | 212 | static int spi_imx_bytes_per_word(const int bits_per_word) |
f12ae171 | 213 | { |
afb27208 MC |
214 | if (bits_per_word <= 8) |
215 | return 1; | |
216 | else if (bits_per_word <= 16) | |
217 | return 2; | |
218 | else | |
219 | return 4; | |
f12ae171 AB |
220 | } |
221 | ||
f62caccd RG |
222 | static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi, |
223 | struct spi_transfer *transfer) | |
224 | { | |
225 | struct spi_imx_data *spi_imx = spi_master_get_devdata(master); | |
f12ae171 | 226 | |
0a9c8998 TP |
227 | if (!use_dma) |
228 | return false; | |
229 | ||
f12ae171 AB |
230 | if (!master->dma_rx) |
231 | return false; | |
232 | ||
71abd290 | 233 | if (spi_imx->slave_mode) |
234 | return false; | |
235 | ||
133eb8e3 RG |
236 | if (transfer->len < spi_imx->devtype_data->fifo_size) |
237 | return false; | |
238 | ||
1673c81d | 239 | spi_imx->dynamic_burst = 0; |
66459c5a | 240 | |
f12ae171 | 241 | return true; |
f62caccd RG |
242 | } |
243 | ||
66de757c SG |
244 | #define MX51_ECSPI_CTRL 0x08 |
245 | #define MX51_ECSPI_CTRL_ENABLE (1 << 0) | |
246 | #define MX51_ECSPI_CTRL_XCH (1 << 2) | |
f62caccd | 247 | #define MX51_ECSPI_CTRL_SMC (1 << 3) |
66de757c | 248 | #define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4) |
f72efa7e | 249 | #define MX51_ECSPI_CTRL_DRCTL(drctl) ((drctl) << 16) |
66de757c SG |
250 | #define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8 |
251 | #define MX51_ECSPI_CTRL_PREDIV_OFFSET 12 | |
252 | #define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18) | |
253 | #define MX51_ECSPI_CTRL_BL_OFFSET 20 | |
1673c81d | 254 | #define MX51_ECSPI_CTRL_BL_MASK (0xfff << 20) |
66de757c SG |
255 | |
256 | #define MX51_ECSPI_CONFIG 0x0c | |
257 | #define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0)) | |
258 | #define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4)) | |
259 | #define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8)) | |
260 | #define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12)) | |
c09b890b | 261 | #define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20)) |
66de757c SG |
262 | |
263 | #define MX51_ECSPI_INT 0x10 | |
264 | #define MX51_ECSPI_INT_TEEN (1 << 0) | |
265 | #define MX51_ECSPI_INT_RREN (1 << 3) | |
71abd290 | 266 | #define MX51_ECSPI_INT_RDREN (1 << 4) |
66de757c | 267 | |
30d67142 | 268 | #define MX51_ECSPI_DMA 0x14 |
d629c2a0 SH |
269 | #define MX51_ECSPI_DMA_TX_WML(wml) ((wml) & 0x3f) |
270 | #define MX51_ECSPI_DMA_RX_WML(wml) (((wml) & 0x3f) << 16) | |
271 | #define MX51_ECSPI_DMA_RXT_WML(wml) (((wml) & 0x3f) << 24) | |
f62caccd | 272 | |
2b0fd069 SH |
273 | #define MX51_ECSPI_DMA_TEDEN (1 << 7) |
274 | #define MX51_ECSPI_DMA_RXDEN (1 << 23) | |
275 | #define MX51_ECSPI_DMA_RXTDEN (1 << 31) | |
f62caccd | 276 | |
66de757c SG |
277 | #define MX51_ECSPI_STAT 0x18 |
278 | #define MX51_ECSPI_STAT_RR (1 << 3) | |
0b599603 | 279 | |
9f6aa42b FE |
280 | #define MX51_ECSPI_TESTREG 0x20 |
281 | #define MX51_ECSPI_TESTREG_LBC BIT(31) | |
282 | ||
1673c81d | 283 | static void spi_imx_buf_rx_swap_u32(struct spi_imx_data *spi_imx) |
284 | { | |
285 | unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); | |
5904c9d3 | 286 | #ifdef __LITTLE_ENDIAN |
1673c81d | 287 | unsigned int bytes_per_word; |
5904c9d3 | 288 | #endif |
1673c81d | 289 | |
290 | if (spi_imx->rx_buf) { | |
291 | #ifdef __LITTLE_ENDIAN | |
292 | bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word); | |
293 | if (bytes_per_word == 1) | |
294 | val = cpu_to_be32(val); | |
295 | else if (bytes_per_word == 2) | |
296 | val = (val << 16) | (val >> 16); | |
297 | #endif | |
1673c81d | 298 | *(u32 *)spi_imx->rx_buf = val; |
299 | spi_imx->rx_buf += sizeof(u32); | |
300 | } | |
2ca300ac MC |
301 | |
302 | spi_imx->remainder -= sizeof(u32); | |
1673c81d | 303 | } |
304 | ||
305 | static void spi_imx_buf_rx_swap(struct spi_imx_data *spi_imx) | |
306 | { | |
2ca300ac MC |
307 | int unaligned; |
308 | u32 val; | |
1673c81d | 309 | |
2ca300ac MC |
310 | unaligned = spi_imx->remainder % 4; |
311 | ||
312 | if (!unaligned) { | |
1673c81d | 313 | spi_imx_buf_rx_swap_u32(spi_imx); |
314 | return; | |
315 | } | |
316 | ||
2ca300ac | 317 | if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) { |
1673c81d | 318 | spi_imx_buf_rx_u16(spi_imx); |
2ca300ac MC |
319 | return; |
320 | } | |
321 | ||
322 | val = readl(spi_imx->base + MXC_CSPIRXDATA); | |
323 | ||
324 | while (unaligned--) { | |
325 | if (spi_imx->rx_buf) { | |
326 | *(u8 *)spi_imx->rx_buf = (val >> (8 * unaligned)) & 0xff; | |
327 | spi_imx->rx_buf++; | |
328 | } | |
329 | spi_imx->remainder--; | |
330 | } | |
1673c81d | 331 | } |
332 | ||
333 | static void spi_imx_buf_tx_swap_u32(struct spi_imx_data *spi_imx) | |
334 | { | |
335 | u32 val = 0; | |
5904c9d3 | 336 | #ifdef __LITTLE_ENDIAN |
1673c81d | 337 | unsigned int bytes_per_word; |
5904c9d3 | 338 | #endif |
1673c81d | 339 | |
340 | if (spi_imx->tx_buf) { | |
341 | val = *(u32 *)spi_imx->tx_buf; | |
1673c81d | 342 | spi_imx->tx_buf += sizeof(u32); |
343 | } | |
344 | ||
345 | spi_imx->count -= sizeof(u32); | |
346 | #ifdef __LITTLE_ENDIAN | |
347 | bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word); | |
348 | ||
349 | if (bytes_per_word == 1) | |
350 | val = cpu_to_be32(val); | |
351 | else if (bytes_per_word == 2) | |
352 | val = (val << 16) | (val >> 16); | |
353 | #endif | |
354 | writel(val, spi_imx->base + MXC_CSPITXDATA); | |
355 | } | |
356 | ||
357 | static void spi_imx_buf_tx_swap(struct spi_imx_data *spi_imx) | |
358 | { | |
2ca300ac MC |
359 | int unaligned; |
360 | u32 val = 0; | |
1673c81d | 361 | |
2ca300ac | 362 | unaligned = spi_imx->count % 4; |
1673c81d | 363 | |
2ca300ac MC |
364 | if (!unaligned) { |
365 | spi_imx_buf_tx_swap_u32(spi_imx); | |
366 | return; | |
1673c81d | 367 | } |
368 | ||
2ca300ac MC |
369 | if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) { |
370 | spi_imx_buf_tx_u16(spi_imx); | |
1673c81d | 371 | return; |
372 | } | |
373 | ||
2ca300ac MC |
374 | while (unaligned--) { |
375 | if (spi_imx->tx_buf) { | |
376 | val |= *(u8 *)spi_imx->tx_buf << (8 * unaligned); | |
377 | spi_imx->tx_buf++; | |
378 | } | |
379 | spi_imx->count--; | |
380 | } | |
1673c81d | 381 | |
2ca300ac | 382 | writel(val, spi_imx->base + MXC_CSPITXDATA); |
1673c81d | 383 | } |
384 | ||
71abd290 | 385 | static void mx53_ecspi_rx_slave(struct spi_imx_data *spi_imx) |
386 | { | |
387 | u32 val = be32_to_cpu(readl(spi_imx->base + MXC_CSPIRXDATA)); | |
388 | ||
389 | if (spi_imx->rx_buf) { | |
390 | int n_bytes = spi_imx->slave_burst % sizeof(val); | |
391 | ||
392 | if (!n_bytes) | |
393 | n_bytes = sizeof(val); | |
394 | ||
395 | memcpy(spi_imx->rx_buf, | |
396 | ((u8 *)&val) + sizeof(val) - n_bytes, n_bytes); | |
397 | ||
398 | spi_imx->rx_buf += n_bytes; | |
399 | spi_imx->slave_burst -= n_bytes; | |
400 | } | |
2ca300ac MC |
401 | |
402 | spi_imx->remainder -= sizeof(u32); | |
71abd290 | 403 | } |
404 | ||
405 | static void mx53_ecspi_tx_slave(struct spi_imx_data *spi_imx) | |
406 | { | |
407 | u32 val = 0; | |
408 | int n_bytes = spi_imx->count % sizeof(val); | |
409 | ||
410 | if (!n_bytes) | |
411 | n_bytes = sizeof(val); | |
412 | ||
413 | if (spi_imx->tx_buf) { | |
414 | memcpy(((u8 *)&val) + sizeof(val) - n_bytes, | |
415 | spi_imx->tx_buf, n_bytes); | |
416 | val = cpu_to_be32(val); | |
417 | spi_imx->tx_buf += n_bytes; | |
418 | } | |
419 | ||
420 | spi_imx->count -= n_bytes; | |
421 | ||
422 | writel(val, spi_imx->base + MXC_CSPITXDATA); | |
423 | } | |
424 | ||
0b599603 | 425 | /* MX51 eCSPI */ |
6aa800ca SH |
426 | static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx, |
427 | unsigned int fspi, unsigned int *fres) | |
0b599603 UKK |
428 | { |
429 | /* | |
430 | * there are two 4-bit dividers, the pre-divider divides by | |
431 | * $pre, the post-divider by 2^$post | |
432 | */ | |
433 | unsigned int pre, post; | |
6aa800ca | 434 | unsigned int fin = spi_imx->spi_clk; |
0b599603 UKK |
435 | |
436 | if (unlikely(fspi > fin)) | |
437 | return 0; | |
438 | ||
439 | post = fls(fin) - fls(fspi); | |
440 | if (fin > fspi << post) | |
441 | post++; | |
442 | ||
443 | /* now we have: (fin <= fspi << post) with post being minimal */ | |
444 | ||
445 | post = max(4U, post) - 4; | |
446 | if (unlikely(post > 0xf)) { | |
6aa800ca SH |
447 | dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n", |
448 | fspi, fin); | |
0b599603 UKK |
449 | return 0xff; |
450 | } | |
451 | ||
452 | pre = DIV_ROUND_UP(fin, fspi << post) - 1; | |
453 | ||
6aa800ca | 454 | dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n", |
0b599603 | 455 | __func__, fin, fspi, post, pre); |
6fd8b850 MV |
456 | |
457 | /* Resulting frequency for the SCLK line. */ | |
458 | *fres = (fin / (pre + 1)) >> post; | |
459 | ||
66de757c SG |
460 | return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) | |
461 | (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET); | |
0b599603 UKK |
462 | } |
463 | ||
f989bc69 | 464 | static void mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable) |
0b599603 UKK |
465 | { |
466 | unsigned val = 0; | |
467 | ||
468 | if (enable & MXC_INT_TE) | |
66de757c | 469 | val |= MX51_ECSPI_INT_TEEN; |
0b599603 UKK |
470 | |
471 | if (enable & MXC_INT_RR) | |
66de757c | 472 | val |= MX51_ECSPI_INT_RREN; |
0b599603 | 473 | |
71abd290 | 474 | if (enable & MXC_INT_RDR) |
475 | val |= MX51_ECSPI_INT_RDREN; | |
476 | ||
66de757c | 477 | writel(val, spi_imx->base + MX51_ECSPI_INT); |
0b599603 UKK |
478 | } |
479 | ||
f989bc69 | 480 | static void mx51_ecspi_trigger(struct spi_imx_data *spi_imx) |
0b599603 | 481 | { |
b03c3884 | 482 | u32 reg; |
f62caccd | 483 | |
b03c3884 SH |
484 | reg = readl(spi_imx->base + MX51_ECSPI_CTRL); |
485 | reg |= MX51_ECSPI_CTRL_XCH; | |
66de757c | 486 | writel(reg, spi_imx->base + MX51_ECSPI_CTRL); |
0b599603 UKK |
487 | } |
488 | ||
bcd8e776 RG |
489 | static void mx51_disable_dma(struct spi_imx_data *spi_imx) |
490 | { | |
491 | writel(0, spi_imx->base + MX51_ECSPI_DMA); | |
492 | } | |
493 | ||
71abd290 | 494 | static void mx51_ecspi_disable(struct spi_imx_data *spi_imx) |
495 | { | |
496 | u32 ctrl; | |
497 | ||
498 | ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); | |
499 | ctrl &= ~MX51_ECSPI_CTRL_ENABLE; | |
500 | writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); | |
501 | } | |
502 | ||
e697271c UKK |
503 | static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx, |
504 | struct spi_message *msg) | |
505 | { | |
00b80ac9 | 506 | struct spi_device *spi = msg->spi; |
793c7f92 | 507 | u32 ctrl = MX51_ECSPI_CTRL_ENABLE; |
00b80ac9 | 508 | u32 testreg; |
793c7f92 | 509 | u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG); |
0b599603 | 510 | |
71abd290 | 511 | /* set Master or Slave mode */ |
512 | if (spi_imx->slave_mode) | |
513 | ctrl &= ~MX51_ECSPI_CTRL_MODE_MASK; | |
514 | else | |
515 | ctrl |= MX51_ECSPI_CTRL_MODE_MASK; | |
0b599603 | 516 | |
f72efa7e LM |
517 | /* |
518 | * Enable SPI_RDY handling (falling edge/level triggered). | |
519 | */ | |
520 | if (spi->mode & SPI_READY) | |
521 | ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl); | |
522 | ||
0b599603 | 523 | /* set chip select to use */ |
b36581df | 524 | ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select); |
0b599603 | 525 | |
00b80ac9 UKK |
526 | /* |
527 | * The ctrl register must be written first, with the EN bit set other | |
528 | * registers must not be written to. | |
529 | */ | |
530 | writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); | |
531 | ||
532 | testreg = readl(spi_imx->base + MX51_ECSPI_TESTREG); | |
533 | if (spi->mode & SPI_LOOP) | |
534 | testreg |= MX51_ECSPI_TESTREG_LBC; | |
71abd290 | 535 | else |
00b80ac9 UKK |
536 | testreg &= ~MX51_ECSPI_TESTREG_LBC; |
537 | writel(testreg, spi_imx->base + MX51_ECSPI_TESTREG); | |
0b599603 | 538 | |
71abd290 | 539 | /* |
540 | * eCSPI burst completion by Chip Select signal in Slave mode | |
541 | * is not functional for imx53 Soc, config SPI burst completed when | |
542 | * BURST_LENGTH + 1 bits are received | |
543 | */ | |
544 | if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx)) | |
545 | cfg &= ~MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select); | |
546 | else | |
547 | cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select); | |
0b599603 | 548 | |
c0c7a5d7 | 549 | if (spi->mode & SPI_CPHA) |
b36581df | 550 | cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); |
793c7f92 | 551 | else |
b36581df | 552 | cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); |
0b599603 | 553 | |
c0c7a5d7 | 554 | if (spi->mode & SPI_CPOL) { |
b36581df AS |
555 | cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select); |
556 | cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select); | |
793c7f92 | 557 | } else { |
b36581df AS |
558 | cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select); |
559 | cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select); | |
c09b890b | 560 | } |
00b80ac9 | 561 | |
c0c7a5d7 | 562 | if (spi->mode & SPI_CS_HIGH) |
b36581df | 563 | cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select); |
793c7f92 | 564 | else |
b36581df | 565 | cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select); |
0b599603 | 566 | |
00b80ac9 | 567 | writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG); |
b03c3884 | 568 | |
00b80ac9 UKK |
569 | return 0; |
570 | } | |
f677f17c | 571 | |
1d374703 UKK |
572 | static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx, |
573 | struct spi_device *spi, | |
574 | struct spi_transfer *t) | |
00b80ac9 | 575 | { |
00b80ac9 | 576 | u32 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); |
3f75720d | 577 | u32 clk = t->speed_hz, delay; |
00b80ac9 UKK |
578 | |
579 | /* Clear BL field and set the right value */ | |
580 | ctrl &= ~MX51_ECSPI_CTRL_BL_MASK; | |
581 | if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx)) | |
582 | ctrl |= (spi_imx->slave_burst * 8 - 1) | |
583 | << MX51_ECSPI_CTRL_BL_OFFSET; | |
9f6aa42b | 584 | else |
00b80ac9 UKK |
585 | ctrl |= (spi_imx->bits_per_word - 1) |
586 | << MX51_ECSPI_CTRL_BL_OFFSET; | |
9f6aa42b | 587 | |
00b80ac9 UKK |
588 | /* set clock speed */ |
589 | ctrl &= ~(0xf << MX51_ECSPI_CTRL_POSTDIV_OFFSET | | |
590 | 0xf << MX51_ECSPI_CTRL_PREDIV_OFFSET); | |
3f75720d | 591 | ctrl |= mx51_ecspi_clkdiv(spi_imx, t->speed_hz, &clk); |
00b80ac9 UKK |
592 | spi_imx->spi_bus_clk = clk; |
593 | ||
594 | if (spi_imx->usedma) | |
595 | ctrl |= MX51_ECSPI_CTRL_SMC; | |
596 | ||
597 | writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); | |
0b599603 | 598 | |
6fd8b850 MV |
599 | /* |
600 | * Wait until the changes in the configuration register CONFIGREG | |
601 | * propagate into the hardware. It takes exactly one tick of the | |
602 | * SCLK clock, but we will wait two SCLK clock just to be sure. The | |
603 | * effect of the delay it takes for the hardware to apply changes | |
604 | * is noticable if the SCLK clock run very slow. In such a case, if | |
605 | * the polarity of SCLK should be inverted, the GPIO ChipSelect might | |
606 | * be asserted before the SCLK polarity changes, which would disrupt | |
607 | * the SPI communication as the device on the other end would consider | |
608 | * the change of SCLK polarity as a clock tick already. | |
609 | */ | |
610 | delay = (2 * 1000000) / clk; | |
611 | if (likely(delay < 10)) /* SCLK is faster than 100 kHz */ | |
612 | udelay(delay); | |
613 | else /* SCLK is _very_ slow */ | |
614 | usleep_range(delay, delay + 10); | |
615 | ||
987a2dfe RG |
616 | return 0; |
617 | } | |
618 | ||
619 | static void mx51_setup_wml(struct spi_imx_data *spi_imx) | |
620 | { | |
f62caccd RG |
621 | /* |
622 | * Configure the DMA register: setup the watermark | |
623 | * and enable DMA request. | |
624 | */ | |
5ba5a373 | 625 | writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) | |
d629c2a0 SH |
626 | MX51_ECSPI_DMA_TX_WML(spi_imx->wml) | |
627 | MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) | | |
2b0fd069 SH |
628 | MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN | |
629 | MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA); | |
0b599603 UKK |
630 | } |
631 | ||
f989bc69 | 632 | static int mx51_ecspi_rx_available(struct spi_imx_data *spi_imx) |
0b599603 | 633 | { |
66de757c | 634 | return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR; |
0b599603 UKK |
635 | } |
636 | ||
f989bc69 | 637 | static void mx51_ecspi_reset(struct spi_imx_data *spi_imx) |
0b599603 UKK |
638 | { |
639 | /* drain receive buffer */ | |
66de757c | 640 | while (mx51_ecspi_rx_available(spi_imx)) |
0b599603 UKK |
641 | readl(spi_imx->base + MXC_CSPIRXDATA); |
642 | } | |
643 | ||
b5f3294f SH |
644 | #define MX31_INTREG_TEEN (1 << 0) |
645 | #define MX31_INTREG_RREN (1 << 3) | |
646 | ||
647 | #define MX31_CSPICTRL_ENABLE (1 << 0) | |
648 | #define MX31_CSPICTRL_MASTER (1 << 1) | |
649 | #define MX31_CSPICTRL_XCH (1 << 2) | |
2dd33f9c | 650 | #define MX31_CSPICTRL_SMC (1 << 3) |
b5f3294f SH |
651 | #define MX31_CSPICTRL_POL (1 << 4) |
652 | #define MX31_CSPICTRL_PHA (1 << 5) | |
653 | #define MX31_CSPICTRL_SSCTL (1 << 6) | |
654 | #define MX31_CSPICTRL_SSPOL (1 << 7) | |
655 | #define MX31_CSPICTRL_BC_SHIFT 8 | |
656 | #define MX35_CSPICTRL_BL_SHIFT 20 | |
657 | #define MX31_CSPICTRL_CS_SHIFT 24 | |
658 | #define MX35_CSPICTRL_CS_SHIFT 12 | |
659 | #define MX31_CSPICTRL_DR_SHIFT 16 | |
660 | ||
2dd33f9c MK |
661 | #define MX31_CSPI_DMAREG 0x10 |
662 | #define MX31_DMAREG_RH_DEN (1<<4) | |
663 | #define MX31_DMAREG_TH_DEN (1<<1) | |
664 | ||
b5f3294f SH |
665 | #define MX31_CSPISTATUS 0x14 |
666 | #define MX31_STATUS_RR (1 << 3) | |
667 | ||
15ca9215 MK |
668 | #define MX31_CSPI_TESTREG 0x1C |
669 | #define MX31_TEST_LBC (1 << 14) | |
670 | ||
b5f3294f SH |
671 | /* These functions also work for the i.MX35, but be aware that |
672 | * the i.MX35 has a slightly different register layout for bits | |
673 | * we do not use here. | |
674 | */ | |
f989bc69 | 675 | static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable) |
b5f3294f SH |
676 | { |
677 | unsigned int val = 0; | |
678 | ||
679 | if (enable & MXC_INT_TE) | |
680 | val |= MX31_INTREG_TEEN; | |
681 | if (enable & MXC_INT_RR) | |
682 | val |= MX31_INTREG_RREN; | |
683 | ||
6cdeb002 | 684 | writel(val, spi_imx->base + MXC_CSPIINT); |
b5f3294f SH |
685 | } |
686 | ||
f989bc69 | 687 | static void mx31_trigger(struct spi_imx_data *spi_imx) |
b5f3294f SH |
688 | { |
689 | unsigned int reg; | |
690 | ||
6cdeb002 | 691 | reg = readl(spi_imx->base + MXC_CSPICTRL); |
b5f3294f | 692 | reg |= MX31_CSPICTRL_XCH; |
6cdeb002 | 693 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
694 | } |
695 | ||
e697271c UKK |
696 | static int mx31_prepare_message(struct spi_imx_data *spi_imx, |
697 | struct spi_message *msg) | |
698 | { | |
699 | return 0; | |
700 | } | |
701 | ||
1d374703 UKK |
702 | static int mx31_prepare_transfer(struct spi_imx_data *spi_imx, |
703 | struct spi_device *spi, | |
704 | struct spi_transfer *t) | |
1723e66b UKK |
705 | { |
706 | unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER; | |
2636ba8f | 707 | unsigned int clk; |
1723e66b | 708 | |
3f75720d | 709 | reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, t->speed_hz, &clk) << |
1723e66b | 710 | MX31_CSPICTRL_DR_SHIFT; |
2636ba8f | 711 | spi_imx->spi_bus_clk = clk; |
1723e66b | 712 | |
04ee5854 | 713 | if (is_imx35_cspi(spi_imx)) { |
d52345b6 | 714 | reg |= (spi_imx->bits_per_word - 1) << MX35_CSPICTRL_BL_SHIFT; |
2a64a90a SG |
715 | reg |= MX31_CSPICTRL_SSCTL; |
716 | } else { | |
d52345b6 | 717 | reg |= (spi_imx->bits_per_word - 1) << MX31_CSPICTRL_BC_SHIFT; |
2a64a90a | 718 | } |
1723e66b | 719 | |
c0c7a5d7 | 720 | if (spi->mode & SPI_CPHA) |
1723e66b | 721 | reg |= MX31_CSPICTRL_PHA; |
c0c7a5d7 | 722 | if (spi->mode & SPI_CPOL) |
1723e66b | 723 | reg |= MX31_CSPICTRL_POL; |
c0c7a5d7 | 724 | if (spi->mode & SPI_CS_HIGH) |
1723e66b | 725 | reg |= MX31_CSPICTRL_SSPOL; |
602c8f44 GU |
726 | if (!gpio_is_valid(spi->cs_gpio)) |
727 | reg |= (spi->chip_select) << | |
04ee5854 SG |
728 | (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT : |
729 | MX31_CSPICTRL_CS_SHIFT); | |
1723e66b | 730 | |
2dd33f9c MK |
731 | if (spi_imx->usedma) |
732 | reg |= MX31_CSPICTRL_SMC; | |
733 | ||
1723e66b UKK |
734 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
735 | ||
15ca9215 MK |
736 | reg = readl(spi_imx->base + MX31_CSPI_TESTREG); |
737 | if (spi->mode & SPI_LOOP) | |
738 | reg |= MX31_TEST_LBC; | |
739 | else | |
740 | reg &= ~MX31_TEST_LBC; | |
741 | writel(reg, spi_imx->base + MX31_CSPI_TESTREG); | |
742 | ||
2dd33f9c | 743 | if (spi_imx->usedma) { |
30d67142 UKK |
744 | /* |
745 | * configure DMA requests when RXFIFO is half full and | |
746 | * when TXFIFO is half empty | |
747 | */ | |
2dd33f9c MK |
748 | writel(MX31_DMAREG_RH_DEN | MX31_DMAREG_TH_DEN, |
749 | spi_imx->base + MX31_CSPI_DMAREG); | |
750 | } | |
751 | ||
1723e66b UKK |
752 | return 0; |
753 | } | |
754 | ||
f989bc69 | 755 | static int mx31_rx_available(struct spi_imx_data *spi_imx) |
b5f3294f | 756 | { |
6cdeb002 | 757 | return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR; |
b5f3294f SH |
758 | } |
759 | ||
f989bc69 | 760 | static void mx31_reset(struct spi_imx_data *spi_imx) |
1723e66b UKK |
761 | { |
762 | /* drain receive buffer */ | |
2a64a90a | 763 | while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR) |
1723e66b UKK |
764 | readl(spi_imx->base + MXC_CSPIRXDATA); |
765 | } | |
766 | ||
3451fb15 SG |
767 | #define MX21_INTREG_RR (1 << 4) |
768 | #define MX21_INTREG_TEEN (1 << 9) | |
769 | #define MX21_INTREG_RREN (1 << 13) | |
770 | ||
771 | #define MX21_CSPICTRL_POL (1 << 5) | |
772 | #define MX21_CSPICTRL_PHA (1 << 6) | |
773 | #define MX21_CSPICTRL_SSPOL (1 << 8) | |
774 | #define MX21_CSPICTRL_XCH (1 << 9) | |
775 | #define MX21_CSPICTRL_ENABLE (1 << 10) | |
776 | #define MX21_CSPICTRL_MASTER (1 << 11) | |
777 | #define MX21_CSPICTRL_DR_SHIFT 14 | |
778 | #define MX21_CSPICTRL_CS_SHIFT 19 | |
779 | ||
f989bc69 | 780 | static void mx21_intctrl(struct spi_imx_data *spi_imx, int enable) |
b5f3294f SH |
781 | { |
782 | unsigned int val = 0; | |
783 | ||
784 | if (enable & MXC_INT_TE) | |
3451fb15 | 785 | val |= MX21_INTREG_TEEN; |
b5f3294f | 786 | if (enable & MXC_INT_RR) |
3451fb15 | 787 | val |= MX21_INTREG_RREN; |
b5f3294f | 788 | |
6cdeb002 | 789 | writel(val, spi_imx->base + MXC_CSPIINT); |
b5f3294f SH |
790 | } |
791 | ||
f989bc69 | 792 | static void mx21_trigger(struct spi_imx_data *spi_imx) |
b5f3294f SH |
793 | { |
794 | unsigned int reg; | |
795 | ||
6cdeb002 | 796 | reg = readl(spi_imx->base + MXC_CSPICTRL); |
3451fb15 | 797 | reg |= MX21_CSPICTRL_XCH; |
6cdeb002 | 798 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
799 | } |
800 | ||
e697271c UKK |
801 | static int mx21_prepare_message(struct spi_imx_data *spi_imx, |
802 | struct spi_message *msg) | |
803 | { | |
804 | return 0; | |
805 | } | |
806 | ||
1d374703 UKK |
807 | static int mx21_prepare_transfer(struct spi_imx_data *spi_imx, |
808 | struct spi_device *spi, | |
809 | struct spi_transfer *t) | |
b5f3294f | 810 | { |
3451fb15 | 811 | unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER; |
04ee5854 | 812 | unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18; |
32df9ff2 RB |
813 | unsigned int clk; |
814 | ||
3f75720d | 815 | reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, t->speed_hz, max, &clk) |
32df9ff2 RB |
816 | << MX21_CSPICTRL_DR_SHIFT; |
817 | spi_imx->spi_bus_clk = clk; | |
b5f3294f | 818 | |
d52345b6 | 819 | reg |= spi_imx->bits_per_word - 1; |
b5f3294f | 820 | |
c0c7a5d7 | 821 | if (spi->mode & SPI_CPHA) |
3451fb15 | 822 | reg |= MX21_CSPICTRL_PHA; |
c0c7a5d7 | 823 | if (spi->mode & SPI_CPOL) |
3451fb15 | 824 | reg |= MX21_CSPICTRL_POL; |
c0c7a5d7 | 825 | if (spi->mode & SPI_CS_HIGH) |
3451fb15 | 826 | reg |= MX21_CSPICTRL_SSPOL; |
602c8f44 GU |
827 | if (!gpio_is_valid(spi->cs_gpio)) |
828 | reg |= spi->chip_select << MX21_CSPICTRL_CS_SHIFT; | |
b5f3294f | 829 | |
6cdeb002 | 830 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
831 | |
832 | return 0; | |
833 | } | |
834 | ||
f989bc69 | 835 | static int mx21_rx_available(struct spi_imx_data *spi_imx) |
b5f3294f | 836 | { |
3451fb15 | 837 | return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR; |
b5f3294f SH |
838 | } |
839 | ||
f989bc69 | 840 | static void mx21_reset(struct spi_imx_data *spi_imx) |
1723e66b UKK |
841 | { |
842 | writel(1, spi_imx->base + MXC_RESET); | |
843 | } | |
844 | ||
b5f3294f SH |
845 | #define MX1_INTREG_RR (1 << 3) |
846 | #define MX1_INTREG_TEEN (1 << 8) | |
847 | #define MX1_INTREG_RREN (1 << 11) | |
848 | ||
849 | #define MX1_CSPICTRL_POL (1 << 4) | |
850 | #define MX1_CSPICTRL_PHA (1 << 5) | |
851 | #define MX1_CSPICTRL_XCH (1 << 8) | |
852 | #define MX1_CSPICTRL_ENABLE (1 << 9) | |
853 | #define MX1_CSPICTRL_MASTER (1 << 10) | |
854 | #define MX1_CSPICTRL_DR_SHIFT 13 | |
855 | ||
f989bc69 | 856 | static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable) |
b5f3294f SH |
857 | { |
858 | unsigned int val = 0; | |
859 | ||
860 | if (enable & MXC_INT_TE) | |
861 | val |= MX1_INTREG_TEEN; | |
862 | if (enable & MXC_INT_RR) | |
863 | val |= MX1_INTREG_RREN; | |
864 | ||
6cdeb002 | 865 | writel(val, spi_imx->base + MXC_CSPIINT); |
b5f3294f SH |
866 | } |
867 | ||
f989bc69 | 868 | static void mx1_trigger(struct spi_imx_data *spi_imx) |
b5f3294f SH |
869 | { |
870 | unsigned int reg; | |
871 | ||
6cdeb002 | 872 | reg = readl(spi_imx->base + MXC_CSPICTRL); |
b5f3294f | 873 | reg |= MX1_CSPICTRL_XCH; |
6cdeb002 | 874 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
875 | } |
876 | ||
e697271c UKK |
877 | static int mx1_prepare_message(struct spi_imx_data *spi_imx, |
878 | struct spi_message *msg) | |
879 | { | |
880 | return 0; | |
881 | } | |
882 | ||
1d374703 UKK |
883 | static int mx1_prepare_transfer(struct spi_imx_data *spi_imx, |
884 | struct spi_device *spi, | |
885 | struct spi_transfer *t) | |
b5f3294f SH |
886 | { |
887 | unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER; | |
2636ba8f | 888 | unsigned int clk; |
b5f3294f | 889 | |
3f75720d | 890 | reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, t->speed_hz, &clk) << |
b5f3294f | 891 | MX1_CSPICTRL_DR_SHIFT; |
2636ba8f MK |
892 | spi_imx->spi_bus_clk = clk; |
893 | ||
d52345b6 | 894 | reg |= spi_imx->bits_per_word - 1; |
b5f3294f | 895 | |
c0c7a5d7 | 896 | if (spi->mode & SPI_CPHA) |
b5f3294f | 897 | reg |= MX1_CSPICTRL_PHA; |
c0c7a5d7 | 898 | if (spi->mode & SPI_CPOL) |
b5f3294f SH |
899 | reg |= MX1_CSPICTRL_POL; |
900 | ||
6cdeb002 | 901 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
902 | |
903 | return 0; | |
904 | } | |
905 | ||
f989bc69 | 906 | static int mx1_rx_available(struct spi_imx_data *spi_imx) |
b5f3294f | 907 | { |
6cdeb002 | 908 | return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR; |
b5f3294f SH |
909 | } |
910 | ||
f989bc69 | 911 | static void mx1_reset(struct spi_imx_data *spi_imx) |
1723e66b UKK |
912 | { |
913 | writel(1, spi_imx->base + MXC_RESET); | |
914 | } | |
915 | ||
04ee5854 SG |
916 | static struct spi_imx_devtype_data imx1_cspi_devtype_data = { |
917 | .intctrl = mx1_intctrl, | |
e697271c | 918 | .prepare_message = mx1_prepare_message, |
1d374703 | 919 | .prepare_transfer = mx1_prepare_transfer, |
04ee5854 SG |
920 | .trigger = mx1_trigger, |
921 | .rx_available = mx1_rx_available, | |
922 | .reset = mx1_reset, | |
fd8d4e2d | 923 | .fifo_size = 8, |
924 | .has_dmamode = false, | |
1673c81d | 925 | .dynamic_burst = false, |
71abd290 | 926 | .has_slavemode = false, |
04ee5854 SG |
927 | .devtype = IMX1_CSPI, |
928 | }; | |
929 | ||
930 | static struct spi_imx_devtype_data imx21_cspi_devtype_data = { | |
931 | .intctrl = mx21_intctrl, | |
e697271c | 932 | .prepare_message = mx21_prepare_message, |
1d374703 | 933 | .prepare_transfer = mx21_prepare_transfer, |
04ee5854 SG |
934 | .trigger = mx21_trigger, |
935 | .rx_available = mx21_rx_available, | |
936 | .reset = mx21_reset, | |
fd8d4e2d | 937 | .fifo_size = 8, |
938 | .has_dmamode = false, | |
1673c81d | 939 | .dynamic_burst = false, |
71abd290 | 940 | .has_slavemode = false, |
04ee5854 SG |
941 | .devtype = IMX21_CSPI, |
942 | }; | |
943 | ||
944 | static struct spi_imx_devtype_data imx27_cspi_devtype_data = { | |
945 | /* i.mx27 cspi shares the functions with i.mx21 one */ | |
946 | .intctrl = mx21_intctrl, | |
e697271c | 947 | .prepare_message = mx21_prepare_message, |
1d374703 | 948 | .prepare_transfer = mx21_prepare_transfer, |
04ee5854 SG |
949 | .trigger = mx21_trigger, |
950 | .rx_available = mx21_rx_available, | |
951 | .reset = mx21_reset, | |
fd8d4e2d | 952 | .fifo_size = 8, |
953 | .has_dmamode = false, | |
1673c81d | 954 | .dynamic_burst = false, |
71abd290 | 955 | .has_slavemode = false, |
04ee5854 SG |
956 | .devtype = IMX27_CSPI, |
957 | }; | |
958 | ||
959 | static struct spi_imx_devtype_data imx31_cspi_devtype_data = { | |
960 | .intctrl = mx31_intctrl, | |
e697271c | 961 | .prepare_message = mx31_prepare_message, |
1d374703 | 962 | .prepare_transfer = mx31_prepare_transfer, |
04ee5854 SG |
963 | .trigger = mx31_trigger, |
964 | .rx_available = mx31_rx_available, | |
965 | .reset = mx31_reset, | |
fd8d4e2d | 966 | .fifo_size = 8, |
967 | .has_dmamode = false, | |
1673c81d | 968 | .dynamic_burst = false, |
71abd290 | 969 | .has_slavemode = false, |
04ee5854 SG |
970 | .devtype = IMX31_CSPI, |
971 | }; | |
972 | ||
973 | static struct spi_imx_devtype_data imx35_cspi_devtype_data = { | |
974 | /* i.mx35 and later cspi shares the functions with i.mx31 one */ | |
975 | .intctrl = mx31_intctrl, | |
e697271c | 976 | .prepare_message = mx31_prepare_message, |
1d374703 | 977 | .prepare_transfer = mx31_prepare_transfer, |
04ee5854 SG |
978 | .trigger = mx31_trigger, |
979 | .rx_available = mx31_rx_available, | |
980 | .reset = mx31_reset, | |
fd8d4e2d | 981 | .fifo_size = 8, |
982 | .has_dmamode = true, | |
1673c81d | 983 | .dynamic_burst = false, |
71abd290 | 984 | .has_slavemode = false, |
04ee5854 SG |
985 | .devtype = IMX35_CSPI, |
986 | }; | |
987 | ||
988 | static struct spi_imx_devtype_data imx51_ecspi_devtype_data = { | |
989 | .intctrl = mx51_ecspi_intctrl, | |
e697271c | 990 | .prepare_message = mx51_ecspi_prepare_message, |
1d374703 | 991 | .prepare_transfer = mx51_ecspi_prepare_transfer, |
04ee5854 SG |
992 | .trigger = mx51_ecspi_trigger, |
993 | .rx_available = mx51_ecspi_rx_available, | |
994 | .reset = mx51_ecspi_reset, | |
987a2dfe | 995 | .setup_wml = mx51_setup_wml, |
bcd8e776 | 996 | .disable_dma = mx51_disable_dma, |
fd8d4e2d | 997 | .fifo_size = 64, |
998 | .has_dmamode = true, | |
1673c81d | 999 | .dynamic_burst = true, |
71abd290 | 1000 | .has_slavemode = true, |
1001 | .disable = mx51_ecspi_disable, | |
04ee5854 SG |
1002 | .devtype = IMX51_ECSPI, |
1003 | }; | |
1004 | ||
26e4bb86 | 1005 | static struct spi_imx_devtype_data imx53_ecspi_devtype_data = { |
1006 | .intctrl = mx51_ecspi_intctrl, | |
e697271c | 1007 | .prepare_message = mx51_ecspi_prepare_message, |
1d374703 | 1008 | .prepare_transfer = mx51_ecspi_prepare_transfer, |
26e4bb86 | 1009 | .trigger = mx51_ecspi_trigger, |
1010 | .rx_available = mx51_ecspi_rx_available, | |
bcd8e776 | 1011 | .disable_dma = mx51_disable_dma, |
26e4bb86 | 1012 | .reset = mx51_ecspi_reset, |
1013 | .fifo_size = 64, | |
1014 | .has_dmamode = true, | |
71abd290 | 1015 | .has_slavemode = true, |
1016 | .disable = mx51_ecspi_disable, | |
26e4bb86 | 1017 | .devtype = IMX53_ECSPI, |
1018 | }; | |
1019 | ||
db1b8200 | 1020 | static const struct platform_device_id spi_imx_devtype[] = { |
04ee5854 SG |
1021 | { |
1022 | .name = "imx1-cspi", | |
1023 | .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data, | |
1024 | }, { | |
1025 | .name = "imx21-cspi", | |
1026 | .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data, | |
1027 | }, { | |
1028 | .name = "imx27-cspi", | |
1029 | .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data, | |
1030 | }, { | |
1031 | .name = "imx31-cspi", | |
1032 | .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data, | |
1033 | }, { | |
1034 | .name = "imx35-cspi", | |
1035 | .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data, | |
1036 | }, { | |
1037 | .name = "imx51-ecspi", | |
1038 | .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data, | |
26e4bb86 | 1039 | }, { |
1040 | .name = "imx53-ecspi", | |
1041 | .driver_data = (kernel_ulong_t) &imx53_ecspi_devtype_data, | |
04ee5854 SG |
1042 | }, { |
1043 | /* sentinel */ | |
1044 | } | |
f4ba6315 UKK |
1045 | }; |
1046 | ||
22a85e4c SG |
1047 | static const struct of_device_id spi_imx_dt_ids[] = { |
1048 | { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, }, | |
1049 | { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, }, | |
1050 | { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, }, | |
1051 | { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, }, | |
1052 | { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, }, | |
1053 | { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, }, | |
26e4bb86 | 1054 | { .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, }, |
22a85e4c SG |
1055 | { /* sentinel */ } |
1056 | }; | |
27743e0b | 1057 | MODULE_DEVICE_TABLE(of, spi_imx_dt_ids); |
22a85e4c | 1058 | |
6cdeb002 | 1059 | static void spi_imx_chipselect(struct spi_device *spi, int is_active) |
b5f3294f | 1060 | { |
e6a0a8bf UKK |
1061 | int active = is_active != BITBANG_CS_INACTIVE; |
1062 | int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH); | |
b5f3294f | 1063 | |
ab2f3572 OR |
1064 | if (spi->mode & SPI_NO_CS) |
1065 | return; | |
1066 | ||
b36581df | 1067 | if (!gpio_is_valid(spi->cs_gpio)) |
b5f3294f | 1068 | return; |
b5f3294f | 1069 | |
b36581df | 1070 | gpio_set_value(spi->cs_gpio, dev_is_lowactive ^ active); |
b5f3294f SH |
1071 | } |
1072 | ||
2ca300ac MC |
1073 | static void spi_imx_set_burst_len(struct spi_imx_data *spi_imx, int n_bits) |
1074 | { | |
1075 | u32 ctrl; | |
1076 | ||
1077 | ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); | |
1078 | ctrl &= ~MX51_ECSPI_CTRL_BL_MASK; | |
1079 | ctrl |= ((n_bits - 1) << MX51_ECSPI_CTRL_BL_OFFSET); | |
1080 | writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); | |
1081 | } | |
1082 | ||
6cdeb002 | 1083 | static void spi_imx_push(struct spi_imx_data *spi_imx) |
b5f3294f | 1084 | { |
2ca300ac MC |
1085 | unsigned int burst_len, fifo_words; |
1086 | ||
1087 | if (spi_imx->dynamic_burst) | |
1088 | fifo_words = 4; | |
1089 | else | |
1090 | fifo_words = spi_imx_bytes_per_word(spi_imx->bits_per_word); | |
1091 | /* | |
1092 | * Reload the FIFO when the remaining bytes to be transferred in the | |
1093 | * current burst is 0. This only applies when bits_per_word is a | |
1094 | * multiple of 8. | |
1095 | */ | |
1096 | if (!spi_imx->remainder) { | |
1097 | if (spi_imx->dynamic_burst) { | |
1098 | ||
1099 | /* We need to deal unaligned data first */ | |
1100 | burst_len = spi_imx->count % MX51_ECSPI_CTRL_MAX_BURST; | |
1101 | ||
1102 | if (!burst_len) | |
1103 | burst_len = MX51_ECSPI_CTRL_MAX_BURST; | |
1104 | ||
1105 | spi_imx_set_burst_len(spi_imx, burst_len * 8); | |
1106 | ||
1107 | spi_imx->remainder = burst_len; | |
1108 | } else { | |
1109 | spi_imx->remainder = fifo_words; | |
1110 | } | |
1111 | } | |
1112 | ||
fd8d4e2d | 1113 | while (spi_imx->txfifo < spi_imx->devtype_data->fifo_size) { |
6cdeb002 | 1114 | if (!spi_imx->count) |
b5f3294f | 1115 | break; |
2ca300ac | 1116 | if (spi_imx->dynamic_burst && |
30d67142 | 1117 | spi_imx->txfifo >= DIV_ROUND_UP(spi_imx->remainder, |
2ca300ac | 1118 | fifo_words)) |
1673c81d | 1119 | break; |
6cdeb002 UKK |
1120 | spi_imx->tx(spi_imx); |
1121 | spi_imx->txfifo++; | |
b5f3294f SH |
1122 | } |
1123 | ||
71abd290 | 1124 | if (!spi_imx->slave_mode) |
1125 | spi_imx->devtype_data->trigger(spi_imx); | |
b5f3294f SH |
1126 | } |
1127 | ||
6cdeb002 | 1128 | static irqreturn_t spi_imx_isr(int irq, void *dev_id) |
b5f3294f | 1129 | { |
6cdeb002 | 1130 | struct spi_imx_data *spi_imx = dev_id; |
b5f3294f | 1131 | |
71abd290 | 1132 | while (spi_imx->txfifo && |
1133 | spi_imx->devtype_data->rx_available(spi_imx)) { | |
6cdeb002 UKK |
1134 | spi_imx->rx(spi_imx); |
1135 | spi_imx->txfifo--; | |
b5f3294f SH |
1136 | } |
1137 | ||
6cdeb002 UKK |
1138 | if (spi_imx->count) { |
1139 | spi_imx_push(spi_imx); | |
b5f3294f SH |
1140 | return IRQ_HANDLED; |
1141 | } | |
1142 | ||
6cdeb002 | 1143 | if (spi_imx->txfifo) { |
b5f3294f SH |
1144 | /* No data left to push, but still waiting for rx data, |
1145 | * enable receive data available interrupt. | |
1146 | */ | |
edd501bb | 1147 | spi_imx->devtype_data->intctrl( |
f4ba6315 | 1148 | spi_imx, MXC_INT_RR); |
b5f3294f SH |
1149 | return IRQ_HANDLED; |
1150 | } | |
1151 | ||
edd501bb | 1152 | spi_imx->devtype_data->intctrl(spi_imx, 0); |
6cdeb002 | 1153 | complete(&spi_imx->xfer_done); |
b5f3294f SH |
1154 | |
1155 | return IRQ_HANDLED; | |
1156 | } | |
1157 | ||
65017ee2 | 1158 | static int spi_imx_dma_configure(struct spi_master *master) |
f12ae171 AB |
1159 | { |
1160 | int ret; | |
1161 | enum dma_slave_buswidth buswidth; | |
1162 | struct dma_slave_config rx = {}, tx = {}; | |
1163 | struct spi_imx_data *spi_imx = spi_master_get_devdata(master); | |
1164 | ||
65017ee2 | 1165 | switch (spi_imx_bytes_per_word(spi_imx->bits_per_word)) { |
f12ae171 AB |
1166 | case 4: |
1167 | buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
1168 | break; | |
1169 | case 2: | |
1170 | buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
1171 | break; | |
1172 | case 1: | |
1173 | buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
1174 | break; | |
1175 | default: | |
1176 | return -EINVAL; | |
1177 | } | |
1178 | ||
1179 | tx.direction = DMA_MEM_TO_DEV; | |
1180 | tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA; | |
1181 | tx.dst_addr_width = buswidth; | |
1182 | tx.dst_maxburst = spi_imx->wml; | |
1183 | ret = dmaengine_slave_config(master->dma_tx, &tx); | |
1184 | if (ret) { | |
1185 | dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret); | |
1186 | return ret; | |
1187 | } | |
1188 | ||
1189 | rx.direction = DMA_DEV_TO_MEM; | |
1190 | rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA; | |
1191 | rx.src_addr_width = buswidth; | |
1192 | rx.src_maxburst = spi_imx->wml; | |
1193 | ret = dmaengine_slave_config(master->dma_rx, &rx); | |
1194 | if (ret) { | |
1195 | dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret); | |
1196 | return ret; | |
1197 | } | |
1198 | ||
f12ae171 AB |
1199 | return 0; |
1200 | } | |
1201 | ||
6cdeb002 | 1202 | static int spi_imx_setupxfer(struct spi_device *spi, |
b5f3294f SH |
1203 | struct spi_transfer *t) |
1204 | { | |
6cdeb002 | 1205 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
b5f3294f | 1206 | |
abb1ff19 SH |
1207 | if (!t) |
1208 | return 0; | |
1209 | ||
d52345b6 | 1210 | spi_imx->bits_per_word = t->bits_per_word; |
b5f3294f | 1211 | |
2801b2f5 MC |
1212 | /* |
1213 | * Initialize the functions for transfer. To transfer non byte-aligned | |
1214 | * words, we have to use multiple word-size bursts, we can't use | |
1215 | * dynamic_burst in that case. | |
1216 | */ | |
1217 | if (spi_imx->devtype_data->dynamic_burst && !spi_imx->slave_mode && | |
1218 | (spi_imx->bits_per_word == 8 || | |
1219 | spi_imx->bits_per_word == 16 || | |
1220 | spi_imx->bits_per_word == 32)) { | |
1673c81d | 1221 | |
1673c81d | 1222 | spi_imx->rx = spi_imx_buf_rx_swap; |
1223 | spi_imx->tx = spi_imx_buf_tx_swap; | |
1224 | spi_imx->dynamic_burst = 1; | |
1673c81d | 1225 | |
6051426f | 1226 | } else { |
1673c81d | 1227 | if (spi_imx->bits_per_word <= 8) { |
1228 | spi_imx->rx = spi_imx_buf_rx_u8; | |
1229 | spi_imx->tx = spi_imx_buf_tx_u8; | |
1230 | } else if (spi_imx->bits_per_word <= 16) { | |
1231 | spi_imx->rx = spi_imx_buf_rx_u16; | |
1232 | spi_imx->tx = spi_imx_buf_tx_u16; | |
1233 | } else { | |
1234 | spi_imx->rx = spi_imx_buf_rx_u32; | |
1235 | spi_imx->tx = spi_imx_buf_tx_u32; | |
1236 | } | |
2ca300ac | 1237 | spi_imx->dynamic_burst = 0; |
24778be2 | 1238 | } |
e6a0a8bf | 1239 | |
c008a800 | 1240 | if (spi_imx_can_dma(spi_imx->bitbang.master, spi, t)) |
e6a8b2cc | 1241 | spi_imx->usedma = true; |
c008a800 | 1242 | else |
e6a8b2cc | 1243 | spi_imx->usedma = false; |
c008a800 | 1244 | |
71abd290 | 1245 | if (is_imx53_ecspi(spi_imx) && spi_imx->slave_mode) { |
1246 | spi_imx->rx = mx53_ecspi_rx_slave; | |
1247 | spi_imx->tx = mx53_ecspi_tx_slave; | |
1248 | spi_imx->slave_burst = t->len; | |
1249 | } | |
1250 | ||
1d374703 | 1251 | spi_imx->devtype_data->prepare_transfer(spi_imx, spi, t); |
b5f3294f SH |
1252 | |
1253 | return 0; | |
1254 | } | |
1255 | ||
f62caccd RG |
1256 | static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx) |
1257 | { | |
1258 | struct spi_master *master = spi_imx->bitbang.master; | |
1259 | ||
1260 | if (master->dma_rx) { | |
1261 | dma_release_channel(master->dma_rx); | |
1262 | master->dma_rx = NULL; | |
1263 | } | |
1264 | ||
1265 | if (master->dma_tx) { | |
1266 | dma_release_channel(master->dma_tx); | |
1267 | master->dma_tx = NULL; | |
1268 | } | |
f62caccd RG |
1269 | } |
1270 | ||
1271 | static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx, | |
f12ae171 | 1272 | struct spi_master *master) |
f62caccd | 1273 | { |
f62caccd RG |
1274 | int ret; |
1275 | ||
a02bb401 RG |
1276 | /* use pio mode for i.mx6dl chip TKT238285 */ |
1277 | if (of_machine_is_compatible("fsl,imx6dl")) | |
1278 | return 0; | |
1279 | ||
fd8d4e2d | 1280 | spi_imx->wml = spi_imx->devtype_data->fifo_size / 2; |
0dfbaa89 | 1281 | |
f62caccd | 1282 | /* Prepare for TX DMA: */ |
5d3aa9cc | 1283 | master->dma_tx = dma_request_chan(dev, "tx"); |
3760047a AB |
1284 | if (IS_ERR(master->dma_tx)) { |
1285 | ret = PTR_ERR(master->dma_tx); | |
1286 | dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret); | |
1287 | master->dma_tx = NULL; | |
f62caccd RG |
1288 | goto err; |
1289 | } | |
1290 | ||
f62caccd | 1291 | /* Prepare for RX : */ |
5d3aa9cc | 1292 | master->dma_rx = dma_request_chan(dev, "rx"); |
3760047a AB |
1293 | if (IS_ERR(master->dma_rx)) { |
1294 | ret = PTR_ERR(master->dma_rx); | |
1295 | dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret); | |
1296 | master->dma_rx = NULL; | |
f62caccd RG |
1297 | goto err; |
1298 | } | |
1299 | ||
f62caccd RG |
1300 | init_completion(&spi_imx->dma_rx_completion); |
1301 | init_completion(&spi_imx->dma_tx_completion); | |
1302 | master->can_dma = spi_imx_can_dma; | |
1303 | master->max_dma_len = MAX_SDMA_BD_BYTES; | |
1304 | spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX | | |
1305 | SPI_MASTER_MUST_TX; | |
f62caccd RG |
1306 | |
1307 | return 0; | |
1308 | err: | |
1309 | spi_imx_sdma_exit(spi_imx); | |
1310 | return ret; | |
1311 | } | |
1312 | ||
1313 | static void spi_imx_dma_rx_callback(void *cookie) | |
1314 | { | |
1315 | struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie; | |
1316 | ||
1317 | complete(&spi_imx->dma_rx_completion); | |
1318 | } | |
1319 | ||
1320 | static void spi_imx_dma_tx_callback(void *cookie) | |
1321 | { | |
1322 | struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie; | |
1323 | ||
1324 | complete(&spi_imx->dma_tx_completion); | |
1325 | } | |
1326 | ||
4bfe927a AB |
1327 | static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size) |
1328 | { | |
1329 | unsigned long timeout = 0; | |
1330 | ||
1331 | /* Time with actual data transfer and CS change delay related to HW */ | |
1332 | timeout = (8 + 4) * size / spi_imx->spi_bus_clk; | |
1333 | ||
1334 | /* Add extra second for scheduler related activities */ | |
1335 | timeout += 1; | |
1336 | ||
1337 | /* Double calculated timeout */ | |
1338 | return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC); | |
1339 | } | |
1340 | ||
f62caccd RG |
1341 | static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx, |
1342 | struct spi_transfer *transfer) | |
1343 | { | |
6b6192c0 | 1344 | struct dma_async_tx_descriptor *desc_tx, *desc_rx; |
4bfe927a | 1345 | unsigned long transfer_timeout; |
56536a7f | 1346 | unsigned long timeout; |
f62caccd RG |
1347 | struct spi_master *master = spi_imx->bitbang.master; |
1348 | struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg; | |
5ba5a373 RG |
1349 | struct scatterlist *last_sg = sg_last(rx->sgl, rx->nents); |
1350 | unsigned int bytes_per_word, i; | |
987a2dfe RG |
1351 | int ret; |
1352 | ||
5ba5a373 RG |
1353 | /* Get the right burst length from the last sg to ensure no tail data */ |
1354 | bytes_per_word = spi_imx_bytes_per_word(transfer->bits_per_word); | |
1355 | for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) { | |
1356 | if (!(sg_dma_len(last_sg) % (i * bytes_per_word))) | |
1357 | break; | |
1358 | } | |
1359 | /* Use 1 as wml in case no available burst length got */ | |
1360 | if (i == 0) | |
1361 | i = 1; | |
1362 | ||
1363 | spi_imx->wml = i; | |
1364 | ||
987a2dfe RG |
1365 | ret = spi_imx_dma_configure(master); |
1366 | if (ret) | |
1367 | return ret; | |
1368 | ||
5ba5a373 RG |
1369 | if (!spi_imx->devtype_data->setup_wml) { |
1370 | dev_err(spi_imx->dev, "No setup_wml()?\n"); | |
1371 | return -EINVAL; | |
1372 | } | |
987a2dfe | 1373 | spi_imx->devtype_data->setup_wml(spi_imx); |
f62caccd | 1374 | |
6b6192c0 SH |
1375 | /* |
1376 | * The TX DMA setup starts the transfer, so make sure RX is configured | |
1377 | * before TX. | |
1378 | */ | |
1379 | desc_rx = dmaengine_prep_slave_sg(master->dma_rx, | |
1380 | rx->sgl, rx->nents, DMA_DEV_TO_MEM, | |
1381 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
1382 | if (!desc_rx) | |
1383 | return -EINVAL; | |
f62caccd | 1384 | |
6b6192c0 SH |
1385 | desc_rx->callback = spi_imx_dma_rx_callback; |
1386 | desc_rx->callback_param = (void *)spi_imx; | |
1387 | dmaengine_submit(desc_rx); | |
1388 | reinit_completion(&spi_imx->dma_rx_completion); | |
1389 | dma_async_issue_pending(master->dma_rx); | |
f62caccd | 1390 | |
6b6192c0 SH |
1391 | desc_tx = dmaengine_prep_slave_sg(master->dma_tx, |
1392 | tx->sgl, tx->nents, DMA_MEM_TO_DEV, | |
1393 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
1394 | if (!desc_tx) { | |
1395 | dmaengine_terminate_all(master->dma_tx); | |
bcd8e776 | 1396 | dmaengine_terminate_all(master->dma_rx); |
6b6192c0 | 1397 | return -EINVAL; |
f62caccd RG |
1398 | } |
1399 | ||
6b6192c0 SH |
1400 | desc_tx->callback = spi_imx_dma_tx_callback; |
1401 | desc_tx->callback_param = (void *)spi_imx; | |
1402 | dmaengine_submit(desc_tx); | |
f62caccd | 1403 | reinit_completion(&spi_imx->dma_tx_completion); |
fab44ef1 | 1404 | dma_async_issue_pending(master->dma_tx); |
f62caccd | 1405 | |
4bfe927a AB |
1406 | transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len); |
1407 | ||
f62caccd | 1408 | /* Wait SDMA to finish the data transfer.*/ |
56536a7f | 1409 | timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion, |
4bfe927a | 1410 | transfer_timeout); |
56536a7f | 1411 | if (!timeout) { |
6aa800ca | 1412 | dev_err(spi_imx->dev, "I/O Error in DMA TX\n"); |
f62caccd | 1413 | dmaengine_terminate_all(master->dma_tx); |
e47b33c0 | 1414 | dmaengine_terminate_all(master->dma_rx); |
6b6192c0 | 1415 | return -ETIMEDOUT; |
f62caccd RG |
1416 | } |
1417 | ||
6b6192c0 SH |
1418 | timeout = wait_for_completion_timeout(&spi_imx->dma_rx_completion, |
1419 | transfer_timeout); | |
1420 | if (!timeout) { | |
1421 | dev_err(&master->dev, "I/O Error in DMA RX\n"); | |
1422 | spi_imx->devtype_data->reset(spi_imx); | |
1423 | dmaengine_terminate_all(master->dma_rx); | |
1424 | return -ETIMEDOUT; | |
1425 | } | |
f62caccd | 1426 | |
6b6192c0 | 1427 | return transfer->len; |
f62caccd RG |
1428 | } |
1429 | ||
1430 | static int spi_imx_pio_transfer(struct spi_device *spi, | |
b5f3294f SH |
1431 | struct spi_transfer *transfer) |
1432 | { | |
6cdeb002 | 1433 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
ff1ba3da CG |
1434 | unsigned long transfer_timeout; |
1435 | unsigned long timeout; | |
b5f3294f | 1436 | |
6cdeb002 UKK |
1437 | spi_imx->tx_buf = transfer->tx_buf; |
1438 | spi_imx->rx_buf = transfer->rx_buf; | |
1439 | spi_imx->count = transfer->len; | |
1440 | spi_imx->txfifo = 0; | |
2ca300ac | 1441 | spi_imx->remainder = 0; |
b5f3294f | 1442 | |
aa0fe826 | 1443 | reinit_completion(&spi_imx->xfer_done); |
b5f3294f | 1444 | |
6cdeb002 | 1445 | spi_imx_push(spi_imx); |
b5f3294f | 1446 | |
edd501bb | 1447 | spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE); |
b5f3294f | 1448 | |
ff1ba3da CG |
1449 | transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len); |
1450 | ||
1451 | timeout = wait_for_completion_timeout(&spi_imx->xfer_done, | |
1452 | transfer_timeout); | |
1453 | if (!timeout) { | |
1454 | dev_err(&spi->dev, "I/O Error in PIO\n"); | |
1455 | spi_imx->devtype_data->reset(spi_imx); | |
1456 | return -ETIMEDOUT; | |
1457 | } | |
b5f3294f SH |
1458 | |
1459 | return transfer->len; | |
1460 | } | |
1461 | ||
71abd290 | 1462 | static int spi_imx_pio_transfer_slave(struct spi_device *spi, |
1463 | struct spi_transfer *transfer) | |
1464 | { | |
1465 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); | |
1466 | int ret = transfer->len; | |
1467 | ||
1468 | if (is_imx53_ecspi(spi_imx) && | |
1469 | transfer->len > MX53_MAX_TRANSFER_BYTES) { | |
1470 | dev_err(&spi->dev, "Transaction too big, max size is %d bytes\n", | |
1471 | MX53_MAX_TRANSFER_BYTES); | |
1472 | return -EMSGSIZE; | |
1473 | } | |
1474 | ||
1475 | spi_imx->tx_buf = transfer->tx_buf; | |
1476 | spi_imx->rx_buf = transfer->rx_buf; | |
1477 | spi_imx->count = transfer->len; | |
1478 | spi_imx->txfifo = 0; | |
2ca300ac | 1479 | spi_imx->remainder = 0; |
71abd290 | 1480 | |
1481 | reinit_completion(&spi_imx->xfer_done); | |
1482 | spi_imx->slave_aborted = false; | |
1483 | ||
1484 | spi_imx_push(spi_imx); | |
1485 | ||
1486 | spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE | MXC_INT_RDR); | |
1487 | ||
1488 | if (wait_for_completion_interruptible(&spi_imx->xfer_done) || | |
1489 | spi_imx->slave_aborted) { | |
1490 | dev_dbg(&spi->dev, "interrupted\n"); | |
1491 | ret = -EINTR; | |
1492 | } | |
1493 | ||
1494 | /* ecspi has a HW issue when works in Slave mode, | |
1495 | * after 64 words writtern to TXFIFO, even TXFIFO becomes empty, | |
1496 | * ECSPI_TXDATA keeps shift out the last word data, | |
1497 | * so we have to disable ECSPI when in slave mode after the | |
1498 | * transfer completes | |
1499 | */ | |
1500 | if (spi_imx->devtype_data->disable) | |
1501 | spi_imx->devtype_data->disable(spi_imx); | |
1502 | ||
1503 | return ret; | |
1504 | } | |
1505 | ||
f62caccd RG |
1506 | static int spi_imx_transfer(struct spi_device *spi, |
1507 | struct spi_transfer *transfer) | |
1508 | { | |
f62caccd | 1509 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
bcd8e776 | 1510 | int ret; |
f62caccd | 1511 | |
71abd290 | 1512 | /* flush rxfifo before transfer */ |
1513 | while (spi_imx->devtype_data->rx_available(spi_imx)) | |
c842749e | 1514 | readl(spi_imx->base + MXC_CSPIRXDATA); |
71abd290 | 1515 | |
1516 | if (spi_imx->slave_mode) | |
1517 | return spi_imx_pio_transfer_slave(spi, transfer); | |
1518 | ||
bcd8e776 RG |
1519 | /* |
1520 | * fallback PIO mode if dma setup error happen, for example sdma | |
1521 | * firmware may not be updated as ERR009165 required. | |
1522 | */ | |
1523 | if (spi_imx->usedma) { | |
1524 | ret = spi_imx_dma_transfer(spi_imx, transfer); | |
1525 | if (ret != -EINVAL) | |
1526 | return ret; | |
1527 | ||
1528 | spi_imx->devtype_data->disable_dma(spi_imx); | |
1529 | ||
1530 | spi_imx->usedma = false; | |
1531 | spi_imx->dynamic_burst = spi_imx->devtype_data->dynamic_burst; | |
1532 | dev_dbg(&spi->dev, "Fallback to PIO mode\n"); | |
1533 | } | |
1534 | ||
1535 | return spi_imx_pio_transfer(spi, transfer); | |
f62caccd RG |
1536 | } |
1537 | ||
6cdeb002 | 1538 | static int spi_imx_setup(struct spi_device *spi) |
b5f3294f | 1539 | { |
f4d4ecfe | 1540 | dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__, |
b5f3294f SH |
1541 | spi->mode, spi->bits_per_word, spi->max_speed_hz); |
1542 | ||
ab2f3572 OR |
1543 | if (spi->mode & SPI_NO_CS) |
1544 | return 0; | |
1545 | ||
b36581df AS |
1546 | if (gpio_is_valid(spi->cs_gpio)) |
1547 | gpio_direction_output(spi->cs_gpio, | |
1548 | spi->mode & SPI_CS_HIGH ? 0 : 1); | |
6c23e5d4 | 1549 | |
6cdeb002 | 1550 | spi_imx_chipselect(spi, BITBANG_CS_INACTIVE); |
b5f3294f SH |
1551 | |
1552 | return 0; | |
1553 | } | |
1554 | ||
6cdeb002 | 1555 | static void spi_imx_cleanup(struct spi_device *spi) |
b5f3294f SH |
1556 | { |
1557 | } | |
1558 | ||
9e556dcc HS |
1559 | static int |
1560 | spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg) | |
1561 | { | |
1562 | struct spi_imx_data *spi_imx = spi_master_get_devdata(master); | |
1563 | int ret; | |
1564 | ||
1565 | ret = clk_enable(spi_imx->clk_per); | |
1566 | if (ret) | |
1567 | return ret; | |
1568 | ||
1569 | ret = clk_enable(spi_imx->clk_ipg); | |
1570 | if (ret) { | |
1571 | clk_disable(spi_imx->clk_per); | |
1572 | return ret; | |
1573 | } | |
1574 | ||
e697271c UKK |
1575 | ret = spi_imx->devtype_data->prepare_message(spi_imx, msg); |
1576 | if (ret) { | |
1577 | clk_disable(spi_imx->clk_ipg); | |
1578 | clk_disable(spi_imx->clk_per); | |
1579 | } | |
1580 | ||
1581 | return ret; | |
9e556dcc HS |
1582 | } |
1583 | ||
1584 | static int | |
1585 | spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg) | |
1586 | { | |
1587 | struct spi_imx_data *spi_imx = spi_master_get_devdata(master); | |
1588 | ||
1589 | clk_disable(spi_imx->clk_ipg); | |
1590 | clk_disable(spi_imx->clk_per); | |
1591 | return 0; | |
1592 | } | |
1593 | ||
71abd290 | 1594 | static int spi_imx_slave_abort(struct spi_master *master) |
1595 | { | |
1596 | struct spi_imx_data *spi_imx = spi_master_get_devdata(master); | |
1597 | ||
1598 | spi_imx->slave_aborted = true; | |
1599 | complete(&spi_imx->xfer_done); | |
1600 | ||
1601 | return 0; | |
1602 | } | |
1603 | ||
fd4a319b | 1604 | static int spi_imx_probe(struct platform_device *pdev) |
b5f3294f | 1605 | { |
22a85e4c SG |
1606 | struct device_node *np = pdev->dev.of_node; |
1607 | const struct of_device_id *of_id = | |
1608 | of_match_device(spi_imx_dt_ids, &pdev->dev); | |
1609 | struct spi_imx_master *mxc_platform_info = | |
1610 | dev_get_platdata(&pdev->dev); | |
b5f3294f | 1611 | struct spi_master *master; |
6cdeb002 | 1612 | struct spi_imx_data *spi_imx; |
b5f3294f | 1613 | struct resource *res; |
f72efa7e | 1614 | int i, ret, irq, spi_drctl; |
71abd290 | 1615 | const struct spi_imx_devtype_data *devtype_data = of_id ? of_id->data : |
1616 | (struct spi_imx_devtype_data *)pdev->id_entry->driver_data; | |
1617 | bool slave_mode; | |
b5f3294f | 1618 | |
22a85e4c | 1619 | if (!np && !mxc_platform_info) { |
b5f3294f SH |
1620 | dev_err(&pdev->dev, "can't get the platform data\n"); |
1621 | return -EINVAL; | |
1622 | } | |
1623 | ||
71abd290 | 1624 | slave_mode = devtype_data->has_slavemode && |
1625 | of_property_read_bool(np, "spi-slave"); | |
1626 | if (slave_mode) | |
1627 | master = spi_alloc_slave(&pdev->dev, | |
1628 | sizeof(struct spi_imx_data)); | |
1629 | else | |
1630 | master = spi_alloc_master(&pdev->dev, | |
1631 | sizeof(struct spi_imx_data)); | |
2c147776 FE |
1632 | if (!master) |
1633 | return -ENOMEM; | |
1634 | ||
f72efa7e LM |
1635 | ret = of_property_read_u32(np, "fsl,spi-rdy-drctl", &spi_drctl); |
1636 | if ((ret < 0) || (spi_drctl >= 0x3)) { | |
1637 | /* '11' is reserved */ | |
1638 | spi_drctl = 0; | |
1639 | } | |
1640 | ||
b5f3294f SH |
1641 | platform_set_drvdata(pdev, master); |
1642 | ||
24778be2 | 1643 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); |
b36581df | 1644 | master->bus_num = np ? -1 : pdev->id; |
b5f3294f | 1645 | |
6cdeb002 | 1646 | spi_imx = spi_master_get_devdata(master); |
94c69f76 | 1647 | spi_imx->bitbang.master = master; |
6aa800ca | 1648 | spi_imx->dev = &pdev->dev; |
71abd290 | 1649 | spi_imx->slave_mode = slave_mode; |
b5f3294f | 1650 | |
71abd290 | 1651 | spi_imx->devtype_data = devtype_data; |
4686d1c3 | 1652 | |
881a0b99 | 1653 | /* Get number of chip selects, either platform data or OF */ |
b36581df AS |
1654 | if (mxc_platform_info) { |
1655 | master->num_chipselect = mxc_platform_info->num_chipselect; | |
ffd4db9e | 1656 | if (mxc_platform_info->chipselect) { |
a86854d0 KC |
1657 | master->cs_gpios = devm_kcalloc(&master->dev, |
1658 | master->num_chipselect, sizeof(int), | |
1659 | GFP_KERNEL); | |
ffd4db9e TP |
1660 | if (!master->cs_gpios) |
1661 | return -ENOMEM; | |
1662 | ||
1663 | for (i = 0; i < master->num_chipselect; i++) | |
1664 | master->cs_gpios[i] = mxc_platform_info->chipselect[i]; | |
1665 | } | |
881a0b99 TP |
1666 | } else { |
1667 | u32 num_cs; | |
1668 | ||
1669 | if (!of_property_read_u32(np, "num-cs", &num_cs)) | |
1670 | master->num_chipselect = num_cs; | |
1671 | /* If not preset, default value of 1 is used */ | |
1672 | } | |
b5f3294f | 1673 | |
6cdeb002 UKK |
1674 | spi_imx->bitbang.chipselect = spi_imx_chipselect; |
1675 | spi_imx->bitbang.setup_transfer = spi_imx_setupxfer; | |
1676 | spi_imx->bitbang.txrx_bufs = spi_imx_transfer; | |
1677 | spi_imx->bitbang.master->setup = spi_imx_setup; | |
1678 | spi_imx->bitbang.master->cleanup = spi_imx_cleanup; | |
9e556dcc HS |
1679 | spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message; |
1680 | spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message; | |
71abd290 | 1681 | spi_imx->bitbang.master->slave_abort = spi_imx_slave_abort; |
ab2f3572 OR |
1682 | spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \ |
1683 | | SPI_NO_CS; | |
26e4bb86 | 1684 | if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) || |
1685 | is_imx53_ecspi(spi_imx)) | |
f72efa7e LM |
1686 | spi_imx->bitbang.master->mode_bits |= SPI_LOOP | SPI_READY; |
1687 | ||
1688 | spi_imx->spi_drctl = spi_drctl; | |
b5f3294f | 1689 | |
6cdeb002 | 1690 | init_completion(&spi_imx->xfer_done); |
b5f3294f SH |
1691 | |
1692 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
130b82c0 FE |
1693 | spi_imx->base = devm_ioremap_resource(&pdev->dev, res); |
1694 | if (IS_ERR(spi_imx->base)) { | |
1695 | ret = PTR_ERR(spi_imx->base); | |
1696 | goto out_master_put; | |
b5f3294f | 1697 | } |
f12ae171 | 1698 | spi_imx->base_phys = res->start; |
b5f3294f | 1699 | |
4b5d6aad FE |
1700 | irq = platform_get_irq(pdev, 0); |
1701 | if (irq < 0) { | |
1702 | ret = irq; | |
130b82c0 | 1703 | goto out_master_put; |
b5f3294f SH |
1704 | } |
1705 | ||
4b5d6aad | 1706 | ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0, |
8fc39b51 | 1707 | dev_name(&pdev->dev), spi_imx); |
b5f3294f | 1708 | if (ret) { |
4b5d6aad | 1709 | dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret); |
130b82c0 | 1710 | goto out_master_put; |
b5f3294f SH |
1711 | } |
1712 | ||
aa29d840 SH |
1713 | spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
1714 | if (IS_ERR(spi_imx->clk_ipg)) { | |
1715 | ret = PTR_ERR(spi_imx->clk_ipg); | |
130b82c0 | 1716 | goto out_master_put; |
b5f3294f SH |
1717 | } |
1718 | ||
aa29d840 SH |
1719 | spi_imx->clk_per = devm_clk_get(&pdev->dev, "per"); |
1720 | if (IS_ERR(spi_imx->clk_per)) { | |
1721 | ret = PTR_ERR(spi_imx->clk_per); | |
130b82c0 | 1722 | goto out_master_put; |
aa29d840 SH |
1723 | } |
1724 | ||
83174626 FE |
1725 | ret = clk_prepare_enable(spi_imx->clk_per); |
1726 | if (ret) | |
1727 | goto out_master_put; | |
1728 | ||
1729 | ret = clk_prepare_enable(spi_imx->clk_ipg); | |
1730 | if (ret) | |
1731 | goto out_put_per; | |
aa29d840 SH |
1732 | |
1733 | spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per); | |
f62caccd | 1734 | /* |
2dd33f9c MK |
1735 | * Only validated on i.mx35 and i.mx6 now, can remove the constraint |
1736 | * if validated on other chips. | |
f62caccd | 1737 | */ |
fd8d4e2d | 1738 | if (spi_imx->devtype_data->has_dmamode) { |
f12ae171 | 1739 | ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master); |
bf9af08c AB |
1740 | if (ret == -EPROBE_DEFER) |
1741 | goto out_clk_put; | |
1742 | ||
3760047a AB |
1743 | if (ret < 0) |
1744 | dev_err(&pdev->dev, "dma setup error %d, use pio\n", | |
1745 | ret); | |
1746 | } | |
b5f3294f | 1747 | |
edd501bb | 1748 | spi_imx->devtype_data->reset(spi_imx); |
ce1807b2 | 1749 | |
edd501bb | 1750 | spi_imx->devtype_data->intctrl(spi_imx, 0); |
b5f3294f | 1751 | |
22a85e4c | 1752 | master->dev.of_node = pdev->dev.of_node; |
8197f489 TP |
1753 | ret = spi_bitbang_start(&spi_imx->bitbang); |
1754 | if (ret) { | |
1755 | dev_err(&pdev->dev, "bitbang start failed with %d\n", ret); | |
1756 | goto out_clk_put; | |
1757 | } | |
b5f3294f | 1758 | |
881a0b99 TP |
1759 | /* Request GPIO CS lines, if any */ |
1760 | if (!spi_imx->slave_mode && master->cs_gpios) { | |
71abd290 | 1761 | for (i = 0; i < master->num_chipselect; i++) { |
1762 | if (!gpio_is_valid(master->cs_gpios[i])) | |
1763 | continue; | |
1764 | ||
1765 | ret = devm_gpio_request(&pdev->dev, | |
1766 | master->cs_gpios[i], | |
1767 | DRIVER_NAME); | |
1768 | if (ret) { | |
1769 | dev_err(&pdev->dev, "Can't get CS GPIO %i\n", | |
1770 | master->cs_gpios[i]); | |
4e21791e | 1771 | goto out_spi_bitbang; |
71abd290 | 1772 | } |
1773 | } | |
b36581df AS |
1774 | } |
1775 | ||
b5f3294f SH |
1776 | dev_info(&pdev->dev, "probed\n"); |
1777 | ||
9e556dcc HS |
1778 | clk_disable(spi_imx->clk_ipg); |
1779 | clk_disable(spi_imx->clk_per); | |
b5f3294f SH |
1780 | return ret; |
1781 | ||
4e21791e TP |
1782 | out_spi_bitbang: |
1783 | spi_bitbang_stop(&spi_imx->bitbang); | |
b5f3294f | 1784 | out_clk_put: |
aa29d840 | 1785 | clk_disable_unprepare(spi_imx->clk_ipg); |
83174626 FE |
1786 | out_put_per: |
1787 | clk_disable_unprepare(spi_imx->clk_per); | |
130b82c0 | 1788 | out_master_put: |
b5f3294f | 1789 | spi_master_put(master); |
130b82c0 | 1790 | |
b5f3294f SH |
1791 | return ret; |
1792 | } | |
1793 | ||
fd4a319b | 1794 | static int spi_imx_remove(struct platform_device *pdev) |
b5f3294f SH |
1795 | { |
1796 | struct spi_master *master = platform_get_drvdata(pdev); | |
6cdeb002 | 1797 | struct spi_imx_data *spi_imx = spi_master_get_devdata(master); |
d593574a | 1798 | int ret; |
b5f3294f | 1799 | |
6cdeb002 | 1800 | spi_bitbang_stop(&spi_imx->bitbang); |
b5f3294f | 1801 | |
d593574a SA |
1802 | ret = clk_enable(spi_imx->clk_per); |
1803 | if (ret) | |
1804 | return ret; | |
1805 | ||
1806 | ret = clk_enable(spi_imx->clk_ipg); | |
1807 | if (ret) { | |
1808 | clk_disable(spi_imx->clk_per); | |
1809 | return ret; | |
1810 | } | |
1811 | ||
6cdeb002 | 1812 | writel(0, spi_imx->base + MXC_CSPICTRL); |
d593574a SA |
1813 | clk_disable_unprepare(spi_imx->clk_ipg); |
1814 | clk_disable_unprepare(spi_imx->clk_per); | |
f62caccd | 1815 | spi_imx_sdma_exit(spi_imx); |
b5f3294f SH |
1816 | spi_master_put(master); |
1817 | ||
b5f3294f SH |
1818 | return 0; |
1819 | } | |
1820 | ||
6cdeb002 | 1821 | static struct platform_driver spi_imx_driver = { |
b5f3294f SH |
1822 | .driver = { |
1823 | .name = DRIVER_NAME, | |
22a85e4c | 1824 | .of_match_table = spi_imx_dt_ids, |
b5f3294f | 1825 | }, |
f4ba6315 | 1826 | .id_table = spi_imx_devtype, |
6cdeb002 | 1827 | .probe = spi_imx_probe, |
fd4a319b | 1828 | .remove = spi_imx_remove, |
b5f3294f | 1829 | }; |
940ab889 | 1830 | module_platform_driver(spi_imx_driver); |
b5f3294f | 1831 | |
af82800c | 1832 | MODULE_DESCRIPTION("SPI Controller driver"); |
b5f3294f SH |
1833 | MODULE_AUTHOR("Sascha Hauer, Pengutronix"); |
1834 | MODULE_LICENSE("GPL"); | |
3133fba3 | 1835 | MODULE_ALIAS("platform:" DRIVER_NAME); |