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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
5928808e MW |
2 | /* |
3 | * PXA2xx SPI DMA engine support. | |
4 | * | |
8083d6b8 | 5 | * Copyright (C) 2013, 2021 Intel Corporation |
5928808e | 6 | * Author: Mika Westerberg <mika.westerberg@linux.intel.com> |
5928808e MW |
7 | */ |
8 | ||
40917709 AS |
9 | #include <linux/atomic.h> |
10 | #include <linux/dev_printk.h> | |
5928808e MW |
11 | #include <linux/dma-mapping.h> |
12 | #include <linux/dmaengine.h> | |
40917709 AS |
13 | #include <linux/errno.h> |
14 | #include <linux/irqreturn.h> | |
5928808e | 15 | #include <linux/scatterlist.h> |
40917709 AS |
16 | #include <linux/string.h> |
17 | #include <linux/types.h> | |
0e476871 | 18 | |
0e476871 | 19 | #include <linux/spi/spi.h> |
5928808e MW |
20 | |
21 | #include "spi-pxa2xx.h" | |
22 | ||
40917709 AS |
23 | struct device; |
24 | ||
5928808e MW |
25 | static void pxa2xx_spi_dma_transfer_complete(struct driver_data *drv_data, |
26 | bool error) | |
27 | { | |
51eea52d | 28 | struct spi_message *msg = drv_data->controller->cur_msg; |
5928808e MW |
29 | |
30 | /* | |
31 | * It is possible that one CPU is handling ROR interrupt and other | |
32 | * just gets DMA completion. Calling pump_transfers() twice for the | |
33 | * same transfer leads to problems thus we prevent concurrent calls | |
8083d6b8 | 34 | * by using dma_running. |
5928808e MW |
35 | */ |
36 | if (atomic_dec_and_test(&drv_data->dma_running)) { | |
5928808e MW |
37 | /* |
38 | * If the other CPU is still handling the ROR interrupt we | |
39 | * might not know about the error yet. So we re-check the | |
40 | * ROR bit here before we clear the status register. | |
41 | */ | |
6d380132 AS |
42 | if (!error) |
43 | error = read_SSSR_bits(drv_data, drv_data->mask_sr) & SSSR_ROR; | |
5928808e MW |
44 | |
45 | /* Clear status & disable interrupts */ | |
42c80cd4 | 46 | clear_SSCR1_bits(drv_data, drv_data->dma_cr1); |
5928808e MW |
47 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
48 | if (!pxa25x_ssp_comp(drv_data)) | |
c039dd27 | 49 | pxa2xx_spi_write(drv_data, SSTO, 0); |
5928808e | 50 | |
d5898e19 | 51 | if (error) { |
5928808e | 52 | /* In case we got an error we disable the SSP now */ |
0c8ccd8b | 53 | pxa_ssp_disable(drv_data->ssp); |
d5898e19 | 54 | msg->status = -EIO; |
5928808e MW |
55 | } |
56 | ||
51eea52d | 57 | spi_finalize_current_transfer(drv_data->controller); |
5928808e MW |
58 | } |
59 | } | |
60 | ||
61 | static void pxa2xx_spi_dma_callback(void *data) | |
62 | { | |
63 | pxa2xx_spi_dma_transfer_complete(data, false); | |
64 | } | |
65 | ||
66 | static struct dma_async_tx_descriptor * | |
67 | pxa2xx_spi_dma_prepare_one(struct driver_data *drv_data, | |
d5898e19 JN |
68 | enum dma_transfer_direction dir, |
69 | struct spi_transfer *xfer) | |
5928808e | 70 | { |
5928808e MW |
71 | enum dma_slave_buswidth width; |
72 | struct dma_slave_config cfg; | |
73 | struct dma_chan *chan; | |
74 | struct sg_table *sgt; | |
b6ced294 | 75 | int ret; |
5928808e MW |
76 | |
77 | switch (drv_data->n_bytes) { | |
78 | case 1: | |
79 | width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
80 | break; | |
81 | case 2: | |
82 | width = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
83 | break; | |
84 | default: | |
85 | width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
86 | break; | |
87 | } | |
88 | ||
89 | memset(&cfg, 0, sizeof(cfg)); | |
90 | cfg.direction = dir; | |
91 | ||
92 | if (dir == DMA_MEM_TO_DEV) { | |
9e43c9a8 | 93 | cfg.dst_addr = drv_data->ssp->phys_base + SSDR; |
5928808e | 94 | cfg.dst_addr_width = width; |
5c5de36d | 95 | cfg.dst_maxburst = drv_data->controller_info->dma_burst_size; |
5928808e | 96 | |
b6ced294 | 97 | sgt = &xfer->tx_sg; |
51eea52d | 98 | chan = drv_data->controller->dma_tx; |
5928808e | 99 | } else { |
9e43c9a8 | 100 | cfg.src_addr = drv_data->ssp->phys_base + SSDR; |
5928808e | 101 | cfg.src_addr_width = width; |
5c5de36d | 102 | cfg.src_maxburst = drv_data->controller_info->dma_burst_size; |
5928808e | 103 | |
b6ced294 | 104 | sgt = &xfer->rx_sg; |
51eea52d | 105 | chan = drv_data->controller->dma_rx; |
5928808e MW |
106 | } |
107 | ||
108 | ret = dmaengine_slave_config(chan, &cfg); | |
109 | if (ret) { | |
c3dce24c | 110 | dev_warn(drv_data->ssp->dev, "DMA slave config failed\n"); |
5928808e MW |
111 | return NULL; |
112 | } | |
113 | ||
b6ced294 | 114 | return dmaengine_prep_slave_sg(chan, sgt->sgl, sgt->nents, dir, |
5928808e MW |
115 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
116 | } | |
117 | ||
5928808e MW |
118 | irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data) |
119 | { | |
120 | u32 status; | |
121 | ||
6d380132 | 122 | status = read_SSSR_bits(drv_data, drv_data->mask_sr); |
5928808e | 123 | if (status & SSSR_ROR) { |
c3dce24c | 124 | dev_err(drv_data->ssp->dev, "FIFO overrun\n"); |
5928808e | 125 | |
51eea52d LR |
126 | dmaengine_terminate_async(drv_data->controller->dma_rx); |
127 | dmaengine_terminate_async(drv_data->controller->dma_tx); | |
5928808e MW |
128 | |
129 | pxa2xx_spi_dma_transfer_complete(drv_data, true); | |
130 | return IRQ_HANDLED; | |
131 | } | |
132 | ||
133 | return IRQ_NONE; | |
134 | } | |
135 | ||
d5898e19 JN |
136 | int pxa2xx_spi_dma_prepare(struct driver_data *drv_data, |
137 | struct spi_transfer *xfer) | |
5928808e MW |
138 | { |
139 | struct dma_async_tx_descriptor *tx_desc, *rx_desc; | |
bffc967e | 140 | int err; |
5928808e | 141 | |
d5898e19 | 142 | tx_desc = pxa2xx_spi_dma_prepare_one(drv_data, DMA_MEM_TO_DEV, xfer); |
5928808e | 143 | if (!tx_desc) { |
c3dce24c | 144 | dev_err(drv_data->ssp->dev, "failed to get DMA TX descriptor\n"); |
7d1f1bf6 AS |
145 | err = -EBUSY; |
146 | goto err_tx; | |
5928808e MW |
147 | } |
148 | ||
d5898e19 | 149 | rx_desc = pxa2xx_spi_dma_prepare_one(drv_data, DMA_DEV_TO_MEM, xfer); |
5928808e | 150 | if (!rx_desc) { |
c3dce24c | 151 | dev_err(drv_data->ssp->dev, "failed to get DMA RX descriptor\n"); |
7d1f1bf6 AS |
152 | err = -EBUSY; |
153 | goto err_rx; | |
5928808e MW |
154 | } |
155 | ||
156 | /* We are ready when RX completes */ | |
157 | rx_desc->callback = pxa2xx_spi_dma_callback; | |
158 | rx_desc->callback_param = drv_data; | |
159 | ||
160 | dmaengine_submit(rx_desc); | |
161 | dmaengine_submit(tx_desc); | |
162 | return 0; | |
7d1f1bf6 AS |
163 | |
164 | err_rx: | |
51eea52d | 165 | dmaengine_terminate_async(drv_data->controller->dma_tx); |
7d1f1bf6 | 166 | err_tx: |
7d1f1bf6 | 167 | return err; |
5928808e MW |
168 | } |
169 | ||
170 | void pxa2xx_spi_dma_start(struct driver_data *drv_data) | |
171 | { | |
51eea52d LR |
172 | dma_async_issue_pending(drv_data->controller->dma_rx); |
173 | dma_async_issue_pending(drv_data->controller->dma_tx); | |
5928808e MW |
174 | |
175 | atomic_set(&drv_data->dma_running, 1); | |
176 | } | |
177 | ||
d5898e19 JN |
178 | void pxa2xx_spi_dma_stop(struct driver_data *drv_data) |
179 | { | |
180 | atomic_set(&drv_data->dma_running, 0); | |
51eea52d LR |
181 | dmaengine_terminate_sync(drv_data->controller->dma_rx); |
182 | dmaengine_terminate_sync(drv_data->controller->dma_tx); | |
d5898e19 JN |
183 | } |
184 | ||
5928808e MW |
185 | int pxa2xx_spi_dma_setup(struct driver_data *drv_data) |
186 | { | |
51eea52d | 187 | struct pxa2xx_spi_controller *pdata = drv_data->controller_info; |
51eea52d | 188 | struct spi_controller *controller = drv_data->controller; |
c3dce24c | 189 | struct device *dev = drv_data->ssp->dev; |
5928808e MW |
190 | dma_cap_mask_t mask; |
191 | ||
192 | dma_cap_zero(mask); | |
193 | dma_cap_set(DMA_SLAVE, mask); | |
194 | ||
51eea52d | 195 | controller->dma_tx = dma_request_slave_channel_compat(mask, |
b729bf34 | 196 | pdata->dma_filter, pdata->tx_param, dev, "tx"); |
51eea52d | 197 | if (!controller->dma_tx) |
5928808e MW |
198 | return -ENODEV; |
199 | ||
51eea52d | 200 | controller->dma_rx = dma_request_slave_channel_compat(mask, |
b729bf34 | 201 | pdata->dma_filter, pdata->rx_param, dev, "rx"); |
51eea52d LR |
202 | if (!controller->dma_rx) { |
203 | dma_release_channel(controller->dma_tx); | |
204 | controller->dma_tx = NULL; | |
5928808e MW |
205 | return -ENODEV; |
206 | } | |
207 | ||
208 | return 0; | |
209 | } | |
210 | ||
211 | void pxa2xx_spi_dma_release(struct driver_data *drv_data) | |
212 | { | |
51eea52d | 213 | struct spi_controller *controller = drv_data->controller; |
b6ced294 | 214 | |
51eea52d LR |
215 | if (controller->dma_rx) { |
216 | dmaengine_terminate_sync(controller->dma_rx); | |
217 | dma_release_channel(controller->dma_rx); | |
218 | controller->dma_rx = NULL; | |
5928808e | 219 | } |
51eea52d LR |
220 | if (controller->dma_tx) { |
221 | dmaengine_terminate_sync(controller->dma_tx); | |
222 | dma_release_channel(controller->dma_tx); | |
223 | controller->dma_tx = NULL; | |
5928808e MW |
224 | } |
225 | } |