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77c42e80 AM |
1 | /* |
2 | * NVIDIA Tegra SPI controller (T114 and later) | |
3 | * | |
4 | * Copyright (c) 2010-2013 NVIDIA Corporation | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This software is licensed under the terms of the GNU General Public | |
10 | * License version 2, as published by the Free Software Foundation, and | |
11 | * may be copied, distributed, and modified under those terms. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
fda6fac3 | 25 | #include <dm.h> |
77c42e80 | 26 | #include <asm/io.h> |
77c42e80 AM |
27 | #include <asm/arch/clock.h> |
28 | #include <asm/arch-tegra/clk_rst.h> | |
77c42e80 AM |
29 | #include <spi.h> |
30 | #include <fdtdec.h> | |
fda6fac3 | 31 | #include "tegra_spi.h" |
77c42e80 AM |
32 | |
33 | DECLARE_GLOBAL_DATA_PTR; | |
34 | ||
35 | /* COMMAND1 */ | |
36 | #define SPI_CMD1_GO (1 << 31) | |
37 | #define SPI_CMD1_M_S (1 << 30) | |
38 | #define SPI_CMD1_MODE_MASK 0x3 | |
39 | #define SPI_CMD1_MODE_SHIFT 28 | |
40 | #define SPI_CMD1_CS_SEL_MASK 0x3 | |
41 | #define SPI_CMD1_CS_SEL_SHIFT 26 | |
42 | #define SPI_CMD1_CS_POL_INACTIVE3 (1 << 25) | |
43 | #define SPI_CMD1_CS_POL_INACTIVE2 (1 << 24) | |
44 | #define SPI_CMD1_CS_POL_INACTIVE1 (1 << 23) | |
45 | #define SPI_CMD1_CS_POL_INACTIVE0 (1 << 22) | |
46 | #define SPI_CMD1_CS_SW_HW (1 << 21) | |
47 | #define SPI_CMD1_CS_SW_VAL (1 << 20) | |
48 | #define SPI_CMD1_IDLE_SDA_MASK 0x3 | |
49 | #define SPI_CMD1_IDLE_SDA_SHIFT 18 | |
50 | #define SPI_CMD1_BIDIR (1 << 17) | |
51 | #define SPI_CMD1_LSBI_FE (1 << 16) | |
52 | #define SPI_CMD1_LSBY_FE (1 << 15) | |
53 | #define SPI_CMD1_BOTH_EN_BIT (1 << 14) | |
54 | #define SPI_CMD1_BOTH_EN_BYTE (1 << 13) | |
55 | #define SPI_CMD1_RX_EN (1 << 12) | |
56 | #define SPI_CMD1_TX_EN (1 << 11) | |
57 | #define SPI_CMD1_PACKED (1 << 5) | |
58 | #define SPI_CMD1_BIT_LEN_MASK 0x1F | |
59 | #define SPI_CMD1_BIT_LEN_SHIFT 0 | |
60 | ||
61 | /* COMMAND2 */ | |
62 | #define SPI_CMD2_TX_CLK_TAP_DELAY (1 << 6) | |
63 | #define SPI_CMD2_TX_CLK_TAP_DELAY_MASK (0x3F << 6) | |
64 | #define SPI_CMD2_RX_CLK_TAP_DELAY (1 << 0) | |
65 | #define SPI_CMD2_RX_CLK_TAP_DELAY_MASK (0x3F << 0) | |
66 | ||
67 | /* TRANSFER STATUS */ | |
68 | #define SPI_XFER_STS_RDY (1 << 30) | |
69 | ||
70 | /* FIFO STATUS */ | |
71 | #define SPI_FIFO_STS_CS_INACTIVE (1 << 31) | |
72 | #define SPI_FIFO_STS_FRAME_END (1 << 30) | |
73 | #define SPI_FIFO_STS_RX_FIFO_FLUSH (1 << 15) | |
74 | #define SPI_FIFO_STS_TX_FIFO_FLUSH (1 << 14) | |
75 | #define SPI_FIFO_STS_ERR (1 << 8) | |
76 | #define SPI_FIFO_STS_TX_FIFO_OVF (1 << 7) | |
77 | #define SPI_FIFO_STS_TX_FIFO_UNR (1 << 6) | |
78 | #define SPI_FIFO_STS_RX_FIFO_OVF (1 << 5) | |
79 | #define SPI_FIFO_STS_RX_FIFO_UNR (1 << 4) | |
80 | #define SPI_FIFO_STS_TX_FIFO_FULL (1 << 3) | |
81 | #define SPI_FIFO_STS_TX_FIFO_EMPTY (1 << 2) | |
82 | #define SPI_FIFO_STS_RX_FIFO_FULL (1 << 1) | |
83 | #define SPI_FIFO_STS_RX_FIFO_EMPTY (1 << 0) | |
84 | ||
85 | #define SPI_TIMEOUT 1000 | |
86 | #define TEGRA_SPI_MAX_FREQ 52000000 | |
87 | ||
88 | struct spi_regs { | |
89 | u32 command1; /* 000:SPI_COMMAND1 register */ | |
90 | u32 command2; /* 004:SPI_COMMAND2 register */ | |
91 | u32 timing1; /* 008:SPI_CS_TIM1 register */ | |
92 | u32 timing2; /* 00c:SPI_CS_TIM2 register */ | |
93 | u32 xfer_status;/* 010:SPI_TRANS_STATUS register */ | |
94 | u32 fifo_status;/* 014:SPI_FIFO_STATUS register */ | |
95 | u32 tx_data; /* 018:SPI_TX_DATA register */ | |
96 | u32 rx_data; /* 01c:SPI_RX_DATA register */ | |
97 | u32 dma_ctl; /* 020:SPI_DMA_CTL register */ | |
98 | u32 dma_blk; /* 024:SPI_DMA_BLK register */ | |
99 | u32 rsvd[56]; /* 028-107 reserved */ | |
100 | u32 tx_fifo; /* 108:SPI_FIFO1 register */ | |
101 | u32 rsvd2[31]; /* 10c-187 reserved */ | |
102 | u32 rx_fifo; /* 188:SPI_FIFO2 register */ | |
103 | u32 spare_ctl; /* 18c:SPI_SPARE_CTRL register */ | |
104 | }; | |
105 | ||
fda6fac3 | 106 | struct tegra114_spi_priv { |
77c42e80 AM |
107 | struct spi_regs *regs; |
108 | unsigned int freq; | |
109 | unsigned int mode; | |
110 | int periph_id; | |
111 | int valid; | |
fda6fac3 | 112 | int last_transaction_us; |
77c42e80 AM |
113 | }; |
114 | ||
fda6fac3 | 115 | static int tegra114_spi_ofdata_to_platdata(struct udevice *bus) |
77c42e80 | 116 | { |
fda6fac3 SG |
117 | struct tegra_spi_platdata *plat = bus->platdata; |
118 | const void *blob = gd->fdt_blob; | |
119 | int node = bus->of_offset; | |
77c42e80 | 120 | |
fda6fac3 SG |
121 | plat->base = fdtdec_get_addr(blob, node, "reg"); |
122 | plat->periph_id = clock_decode_periph_id(blob, node); | |
77c42e80 | 123 | |
fda6fac3 SG |
124 | if (plat->periph_id == PERIPH_ID_NONE) { |
125 | debug("%s: could not decode periph id %d\n", __func__, | |
126 | plat->periph_id); | |
127 | return -FDT_ERR_NOTFOUND; | |
77c42e80 AM |
128 | } |
129 | ||
fda6fac3 SG |
130 | /* Use 500KHz as a suitable default */ |
131 | plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", | |
132 | 500000); | |
133 | plat->deactivate_delay_us = fdtdec_get_int(blob, node, | |
134 | "spi-deactivate-delay", 0); | |
135 | debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n", | |
136 | __func__, plat->base, plat->periph_id, plat->frequency, | |
137 | plat->deactivate_delay_us); | |
77c42e80 | 138 | |
fda6fac3 | 139 | return 0; |
77c42e80 AM |
140 | } |
141 | ||
fda6fac3 | 142 | static int tegra114_spi_probe(struct udevice *bus) |
77c42e80 | 143 | { |
fda6fac3 SG |
144 | struct tegra_spi_platdata *plat = dev_get_platdata(bus); |
145 | struct tegra114_spi_priv *priv = dev_get_priv(bus); | |
77c42e80 | 146 | |
fda6fac3 | 147 | priv->regs = (struct spi_regs *)plat->base; |
77c42e80 | 148 | |
fda6fac3 SG |
149 | priv->last_transaction_us = timer_get_us(); |
150 | priv->freq = plat->frequency; | |
151 | priv->periph_id = plat->periph_id; | |
77c42e80 | 152 | |
fda6fac3 | 153 | return 0; |
77c42e80 AM |
154 | } |
155 | ||
fda6fac3 | 156 | static int tegra114_spi_claim_bus(struct udevice *bus) |
77c42e80 | 157 | { |
fda6fac3 SG |
158 | struct tegra114_spi_priv *priv = dev_get_priv(bus); |
159 | struct spi_regs *regs = priv->regs; | |
77c42e80 AM |
160 | |
161 | /* Change SPI clock to correct frequency, PLLP_OUT0 source */ | |
fda6fac3 | 162 | clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq); |
77c42e80 AM |
163 | |
164 | /* Clear stale status here */ | |
165 | setbits_le32(®s->fifo_status, | |
166 | SPI_FIFO_STS_ERR | | |
167 | SPI_FIFO_STS_TX_FIFO_OVF | | |
168 | SPI_FIFO_STS_TX_FIFO_UNR | | |
169 | SPI_FIFO_STS_RX_FIFO_OVF | | |
170 | SPI_FIFO_STS_RX_FIFO_UNR | | |
171 | SPI_FIFO_STS_TX_FIFO_FULL | | |
172 | SPI_FIFO_STS_TX_FIFO_EMPTY | | |
173 | SPI_FIFO_STS_RX_FIFO_FULL | | |
174 | SPI_FIFO_STS_RX_FIFO_EMPTY); | |
175 | debug("%s: FIFO STATUS = %08x\n", __func__, readl(®s->fifo_status)); | |
176 | ||
177 | /* Set master mode and sw controlled CS */ | |
178 | setbits_le32(®s->command1, SPI_CMD1_M_S | SPI_CMD1_CS_SW_HW | | |
fda6fac3 | 179 | (priv->mode << SPI_CMD1_MODE_SHIFT)); |
77c42e80 AM |
180 | debug("%s: COMMAND1 = %08x\n", __func__, readl(®s->command1)); |
181 | ||
182 | return 0; | |
183 | } | |
184 | ||
fda6fac3 SG |
185 | /** |
186 | * Activate the CS by driving it LOW | |
187 | * | |
188 | * @param slave Pointer to spi_slave to which controller has to | |
189 | * communicate with | |
190 | */ | |
191 | static void spi_cs_activate(struct udevice *dev) | |
77c42e80 | 192 | { |
fda6fac3 SG |
193 | struct udevice *bus = dev->parent; |
194 | struct tegra_spi_platdata *pdata = dev_get_platdata(bus); | |
195 | struct tegra114_spi_priv *priv = dev_get_priv(bus); | |
196 | ||
197 | /* If it's too soon to do another transaction, wait */ | |
198 | if (pdata->deactivate_delay_us && | |
199 | priv->last_transaction_us) { | |
200 | ulong delay_us; /* The delay completed so far */ | |
201 | delay_us = timer_get_us() - priv->last_transaction_us; | |
202 | if (delay_us < pdata->deactivate_delay_us) | |
203 | udelay(pdata->deactivate_delay_us - delay_us); | |
204 | } | |
77c42e80 | 205 | |
fda6fac3 | 206 | clrbits_le32(&priv->regs->command1, SPI_CMD1_CS_SW_VAL); |
77c42e80 AM |
207 | } |
208 | ||
fda6fac3 SG |
209 | /** |
210 | * Deactivate the CS by driving it HIGH | |
211 | * | |
212 | * @param slave Pointer to spi_slave to which controller has to | |
213 | * communicate with | |
214 | */ | |
215 | static void spi_cs_deactivate(struct udevice *dev) | |
77c42e80 | 216 | { |
fda6fac3 SG |
217 | struct udevice *bus = dev->parent; |
218 | struct tegra_spi_platdata *pdata = dev_get_platdata(bus); | |
219 | struct tegra114_spi_priv *priv = dev_get_priv(bus); | |
220 | ||
221 | setbits_le32(&priv->regs->command1, SPI_CMD1_CS_SW_VAL); | |
77c42e80 | 222 | |
fda6fac3 SG |
223 | /* Remember time of this transaction so we can honour the bus delay */ |
224 | if (pdata->deactivate_delay_us) | |
225 | priv->last_transaction_us = timer_get_us(); | |
226 | ||
227 | debug("Deactivate CS, bus '%s'\n", bus->name); | |
77c42e80 AM |
228 | } |
229 | ||
fda6fac3 SG |
230 | static int tegra114_spi_xfer(struct udevice *dev, unsigned int bitlen, |
231 | const void *data_out, void *data_in, | |
232 | unsigned long flags) | |
77c42e80 | 233 | { |
fda6fac3 SG |
234 | struct udevice *bus = dev->parent; |
235 | struct tegra114_spi_priv *priv = dev_get_priv(bus); | |
236 | struct spi_regs *regs = priv->regs; | |
77c42e80 AM |
237 | u32 reg, tmpdout, tmpdin = 0; |
238 | const u8 *dout = data_out; | |
239 | u8 *din = data_in; | |
240 | int num_bytes; | |
241 | int ret; | |
242 | ||
243 | debug("%s: slave %u:%u dout %p din %p bitlen %u\n", | |
fda6fac3 | 244 | __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen); |
77c42e80 AM |
245 | if (bitlen % 8) |
246 | return -1; | |
247 | num_bytes = bitlen / 8; | |
248 | ||
249 | ret = 0; | |
250 | ||
251 | /* clear all error status bits */ | |
252 | reg = readl(®s->fifo_status); | |
253 | writel(reg, ®s->fifo_status); | |
254 | ||
77c42e80 AM |
255 | clrsetbits_le32(®s->command1, SPI_CMD1_CS_SW_VAL, |
256 | SPI_CMD1_RX_EN | SPI_CMD1_TX_EN | SPI_CMD1_LSBY_FE | | |
fda6fac3 | 257 | (spi_chip_select(dev) << SPI_CMD1_CS_SEL_SHIFT)); |
77c42e80 AM |
258 | |
259 | /* set xfer size to 1 block (32 bits) */ | |
260 | writel(0, ®s->dma_blk); | |
261 | ||
262 | if (flags & SPI_XFER_BEGIN) | |
fda6fac3 | 263 | spi_cs_activate(dev); |
77c42e80 AM |
264 | |
265 | /* handle data in 32-bit chunks */ | |
266 | while (num_bytes > 0) { | |
267 | int bytes; | |
77c42e80 AM |
268 | int tm, i; |
269 | ||
270 | tmpdout = 0; | |
271 | bytes = (num_bytes > 4) ? 4 : num_bytes; | |
272 | ||
273 | if (dout != NULL) { | |
274 | for (i = 0; i < bytes; ++i) | |
275 | tmpdout = (tmpdout << 8) | dout[i]; | |
276 | dout += bytes; | |
277 | } | |
278 | ||
279 | num_bytes -= bytes; | |
280 | ||
60acde43 YL |
281 | /* clear ready bit */ |
282 | setbits_le32(®s->xfer_status, SPI_XFER_STS_RDY); | |
283 | ||
77c42e80 AM |
284 | clrsetbits_le32(®s->command1, |
285 | SPI_CMD1_BIT_LEN_MASK << SPI_CMD1_BIT_LEN_SHIFT, | |
286 | (bytes * 8 - 1) << SPI_CMD1_BIT_LEN_SHIFT); | |
287 | writel(tmpdout, ®s->tx_fifo); | |
288 | setbits_le32(®s->command1, SPI_CMD1_GO); | |
289 | ||
290 | /* | |
291 | * Wait for SPI transmit FIFO to empty, or to time out. | |
292 | * The RX FIFO status will be read and cleared last | |
293 | */ | |
60acde43 | 294 | for (tm = 0; tm < SPI_TIMEOUT; ++tm) { |
77c42e80 AM |
295 | u32 fifo_status, xfer_status; |
296 | ||
77c42e80 AM |
297 | xfer_status = readl(®s->xfer_status); |
298 | if (!(xfer_status & SPI_XFER_STS_RDY)) | |
299 | continue; | |
300 | ||
60acde43 | 301 | fifo_status = readl(®s->fifo_status); |
77c42e80 AM |
302 | if (fifo_status & SPI_FIFO_STS_ERR) { |
303 | debug("%s: got a fifo error: ", __func__); | |
304 | if (fifo_status & SPI_FIFO_STS_TX_FIFO_OVF) | |
305 | debug("tx FIFO overflow "); | |
306 | if (fifo_status & SPI_FIFO_STS_TX_FIFO_UNR) | |
307 | debug("tx FIFO underrun "); | |
308 | if (fifo_status & SPI_FIFO_STS_RX_FIFO_OVF) | |
309 | debug("rx FIFO overflow "); | |
310 | if (fifo_status & SPI_FIFO_STS_RX_FIFO_UNR) | |
311 | debug("rx FIFO underrun "); | |
312 | if (fifo_status & SPI_FIFO_STS_TX_FIFO_FULL) | |
313 | debug("tx FIFO full "); | |
314 | if (fifo_status & SPI_FIFO_STS_TX_FIFO_EMPTY) | |
315 | debug("tx FIFO empty "); | |
316 | if (fifo_status & SPI_FIFO_STS_RX_FIFO_FULL) | |
317 | debug("rx FIFO full "); | |
318 | if (fifo_status & SPI_FIFO_STS_RX_FIFO_EMPTY) | |
319 | debug("rx FIFO empty "); | |
320 | debug("\n"); | |
321 | break; | |
322 | } | |
323 | ||
324 | if (!(fifo_status & SPI_FIFO_STS_RX_FIFO_EMPTY)) { | |
325 | tmpdin = readl(®s->rx_fifo); | |
77c42e80 AM |
326 | |
327 | /* swap bytes read in */ | |
328 | if (din != NULL) { | |
329 | for (i = bytes - 1; i >= 0; --i) { | |
330 | din[i] = tmpdin & 0xff; | |
331 | tmpdin >>= 8; | |
332 | } | |
333 | din += bytes; | |
334 | } | |
60acde43 YL |
335 | |
336 | /* We can exit when we've had both RX and TX */ | |
337 | break; | |
77c42e80 AM |
338 | } |
339 | } | |
340 | ||
341 | if (tm >= SPI_TIMEOUT) | |
342 | ret = tm; | |
343 | ||
344 | /* clear ACK RDY, etc. bits */ | |
345 | writel(readl(®s->fifo_status), ®s->fifo_status); | |
346 | } | |
347 | ||
348 | if (flags & SPI_XFER_END) | |
fda6fac3 | 349 | spi_cs_deactivate(dev); |
77c42e80 AM |
350 | |
351 | debug("%s: transfer ended. Value=%08x, fifo_status = %08x\n", | |
352 | __func__, tmpdin, readl(®s->fifo_status)); | |
353 | ||
354 | if (ret) { | |
355 | printf("%s: timeout during SPI transfer, tm %d\n", | |
356 | __func__, ret); | |
357 | return -1; | |
358 | } | |
359 | ||
fda6fac3 SG |
360 | return ret; |
361 | } | |
362 | ||
363 | static int tegra114_spi_set_speed(struct udevice *bus, uint speed) | |
364 | { | |
365 | struct tegra_spi_platdata *plat = bus->platdata; | |
366 | struct tegra114_spi_priv *priv = dev_get_priv(bus); | |
367 | ||
368 | if (speed > plat->frequency) | |
369 | speed = plat->frequency; | |
370 | priv->freq = speed; | |
371 | debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq); | |
372 | ||
77c42e80 AM |
373 | return 0; |
374 | } | |
fda6fac3 SG |
375 | |
376 | static int tegra114_spi_set_mode(struct udevice *bus, uint mode) | |
377 | { | |
378 | struct tegra114_spi_priv *priv = dev_get_priv(bus); | |
379 | ||
380 | priv->mode = mode; | |
381 | debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode); | |
382 | ||
383 | return 0; | |
384 | } | |
385 | ||
386 | static const struct dm_spi_ops tegra114_spi_ops = { | |
387 | .claim_bus = tegra114_spi_claim_bus, | |
388 | .xfer = tegra114_spi_xfer, | |
389 | .set_speed = tegra114_spi_set_speed, | |
390 | .set_mode = tegra114_spi_set_mode, | |
391 | /* | |
392 | * cs_info is not needed, since we require all chip selects to be | |
393 | * in the device tree explicitly | |
394 | */ | |
395 | }; | |
396 | ||
397 | static const struct udevice_id tegra114_spi_ids[] = { | |
398 | { .compatible = "nvidia,tegra114-spi" }, | |
399 | { } | |
400 | }; | |
401 | ||
402 | U_BOOT_DRIVER(tegra114_spi) = { | |
403 | .name = "tegra114_spi", | |
404 | .id = UCLASS_SPI, | |
405 | .of_match = tegra114_spi_ids, | |
406 | .ops = &tegra114_spi_ops, | |
407 | .ofdata_to_platdata = tegra114_spi_ofdata_to_platdata, | |
408 | .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata), | |
409 | .priv_auto_alloc_size = sizeof(struct tegra114_spi_priv), | |
410 | .per_child_auto_alloc_size = sizeof(struct spi_slave), | |
411 | .probe = tegra114_spi_probe, | |
412 | }; |