[thirdparty/u-boot.git] / drivers / spi / ti_qspi.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * TI QSPI driver
 *
 * Copyright (C) 2013, Texas Instruments, Incorporated
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/omap.h>
#include <malloc.h>
#include <spi.h>
#include <dm.h>
#include <asm/gpio.h>
#include <asm/omap_gpio.h>
#include <asm/omap_common.h>
#include <asm/ti-common/ti-edma3.h>
#include <linux/kernel.h>
#include <regmap.h>
#include <syscon.h>

DECLARE_GLOBAL_DATA_PTR;

/* ti qpsi register bit masks */
#define QSPI_TIMEOUT                    2000000
#define QSPI_FCLK			192000000
#define QSPI_DRA7XX_FCLK                76800000
#define QSPI_WLEN_MAX_BITS		128
#define QSPI_WLEN_MAX_BYTES		(QSPI_WLEN_MAX_BITS >> 3)
#define QSPI_WLEN_MASK			QSPI_WLEN(QSPI_WLEN_MAX_BITS)
/* clock control */
#define QSPI_CLK_EN                     BIT(31)
#define QSPI_CLK_DIV_MAX                0xffff
/* command */
#define QSPI_EN_CS(n)                   (n << 28)
#define QSPI_WLEN(n)                    ((n-1) << 19)
#define QSPI_3_PIN                      BIT(18)
#define QSPI_RD_SNGL                    BIT(16)
#define QSPI_WR_SNGL                    (2 << 16)
#define QSPI_INVAL                      (4 << 16)
#define QSPI_RD_QUAD                    (7 << 16)
/* device control */
#define QSPI_DD(m, n)                   (m << (3 + n*8))
#define QSPI_CKPHA(n)                   (1 << (2 + n*8))
#define QSPI_CSPOL(n)                   (1 << (1 + n*8))
#define QSPI_CKPOL(n)                   (1 << (n*8))
/* status */
#define QSPI_WC                         BIT(1)
#define QSPI_BUSY                       BIT(0)
#define QSPI_WC_BUSY                    (QSPI_WC | QSPI_BUSY)
#define QSPI_XFER_DONE                  QSPI_WC
#define MM_SWITCH                       0x01
#define MEM_CS(cs)                      ((cs + 1) << 8)
#define MEM_CS_UNSELECT                 0xfffff8ff
#define MMAP_START_ADDR_DRA		0x5c000000
#define MMAP_START_ADDR_AM43x		0x30000000
#define CORE_CTRL_IO                    0x4a002558

#define QSPI_CMD_READ                   (0x3 << 0)
#define QSPI_CMD_READ_DUAL		(0x6b << 0)
#define QSPI_CMD_READ_QUAD              (0x6c << 0)
#define QSPI_CMD_READ_FAST              (0x0b << 0)
#define QSPI_SETUP0_NUM_A_BYTES         (0x3 << 8)
#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10)
#define QSPI_SETUP0_NUM_D_BYTES_8_BITS  (0x1 << 10)
#define QSPI_SETUP0_READ_NORMAL         (0x0 << 12)
#define QSPI_SETUP0_READ_DUAL           (0x1 << 12)
#define QSPI_SETUP0_READ_QUAD           (0x3 << 12)
#define QSPI_CMD_WRITE                  (0x12 << 16)
#define QSPI_NUM_DUMMY_BITS             (0x0 << 24)

/* ti qspi register set */
struct ti_qspi_regs {
	u32 pid;
	u32 pad0[3];
	u32 sysconfig;
	u32 pad1[3];
	u32 int_stat_raw;
	u32 int_stat_en;
	u32 int_en_set;
	u32 int_en_ctlr;
	u32 intc_eoi;
	u32 pad2[3];
	u32 clk_ctrl;
	u32 dc;
	u32 cmd;
	u32 status;
	u32 data;
	u32 setup0;
	u32 setup1;
	u32 setup2;
	u32 setup3;
	u32 memswitch;
	u32 data1;
	u32 data2;
	u32 data3;
};

/* ti qspi priv */
struct ti_qspi_priv {
#ifndef CONFIG_DM_SPI
	struct spi_slave slave;
#else
	void *memory_map;
	uint max_hz;
	u32 num_cs;
#endif
	struct ti_qspi_regs *base;
	void *ctrl_mod_mmap;
	ulong fclk;
	unsigned int mode;
	u32 cmd;
	u32 dc;
};

static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
{
	uint clk_div;

	if (!hz)
		clk_div = 0;
	else
		clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1;

	/* truncate clk_div value to QSPI_CLK_DIV_MAX */
	if (clk_div > QSPI_CLK_DIV_MAX)
		clk_div = QSPI_CLK_DIV_MAX;

	debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);

	/* disable SCLK */
	writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
	       &priv->base->clk_ctrl);
	/* enable SCLK and program the clk divider */
	writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
}

static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
{
	writel(priv->cmd | QSPI_INVAL, &priv->base->cmd);
	/* dummy readl to ensure bus sync */
	readl(&priv->base->cmd);
}

static int __ti_qspi_set_mode(struct ti_qspi_priv *priv, unsigned int mode)
{
	priv->dc = 0;
	if (mode & SPI_CPHA)
		priv->dc |= QSPI_CKPHA(0);
	if (mode & SPI_CPOL)
		priv->dc |= QSPI_CKPOL(0);
	if (mode & SPI_CS_HIGH)
		priv->dc |= QSPI_CSPOL(0);

	return 0;
}

static int __ti_qspi_claim_bus(struct ti_qspi_priv *priv, int cs)
{
	writel(priv->dc, &priv->base->dc);
	writel(0, &priv->base->cmd);
	writel(0, &priv->base->data);

	priv->dc <<= cs * 8;
	writel(priv->dc, &priv->base->dc);

	return 0;
}

static void __ti_qspi_release_bus(struct ti_qspi_priv *priv)
{
	writel(0, &priv->base->dc);
	writel(0, &priv->base->cmd);
	writel(0, &priv->base->data);
}

static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
{
	u32 val;

	val = readl(ctrl_mod_mmap);
	if (enable)
		val |= MEM_CS(cs);
	else
		val &= MEM_CS_UNSELECT;
	writel(val, ctrl_mod_mmap);
}

static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen,
			const void *dout, void *din, unsigned long flags,
			u32 cs)
{
	uint words = bitlen >> 3; /* fixed 8-bit word length */
	const uchar *txp = dout;
	uchar *rxp = din;
	uint status;
	int timeout;

	/* Setup mmap flags */
	if (flags & SPI_XFER_MMAP) {
		writel(MM_SWITCH, &priv->base->memswitch);
		if (priv->ctrl_mod_mmap)
			ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, true);
		return 0;
	} else if (flags & SPI_XFER_MMAP_END) {
		writel(~MM_SWITCH, &priv->base->memswitch);
		if (priv->ctrl_mod_mmap)
			ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, false);
		return 0;
	}

	if (bitlen == 0)
		return -1;

	if (bitlen % 8) {
		debug("spi_xfer: Non byte aligned SPI transfer\n");
		return -1;
	}

	/* Setup command reg */
	priv->cmd = 0;
	priv->cmd |= QSPI_WLEN(8);
	priv->cmd |= QSPI_EN_CS(cs);
	if (priv->mode & SPI_3WIRE)
		priv->cmd |= QSPI_3_PIN;
	priv->cmd |= 0xfff;

	while (words) {
		u8 xfer_len = 0;

		if (txp) {
			u32 cmd = priv->cmd;

			if (words >= QSPI_WLEN_MAX_BYTES) {
				u32 *txbuf = (u32 *)txp;
				u32 data;

				data = cpu_to_be32(*txbuf++);
				writel(data, &priv->base->data3);
				data = cpu_to_be32(*txbuf++);
				writel(data, &priv->base->data2);
				data = cpu_to_be32(*txbuf++);
				writel(data, &priv->base->data1);
				data = cpu_to_be32(*txbuf++);
				writel(data, &priv->base->data);
				cmd &= ~QSPI_WLEN_MASK;
				cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
				xfer_len = QSPI_WLEN_MAX_BYTES;
			} else {
				writeb(*txp, &priv->base->data);
				xfer_len = 1;
			}
			debug("tx cmd %08x dc %08x\n",
			      cmd | QSPI_WR_SNGL, priv->dc);
			writel(cmd | QSPI_WR_SNGL, &priv->base->cmd);
			status = readl(&priv->base->status);
			timeout = QSPI_TIMEOUT;
			while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
				if (--timeout < 0) {
					printf("spi_xfer: TX timeout!\n");
					return -1;
				}
				status = readl(&priv->base->status);
			}
			txp += xfer_len;
			debug("tx done, status %08x\n", status);
		}
		if (rxp) {
			debug("rx cmd %08x dc %08x\n",
			      ((u32)(priv->cmd | QSPI_RD_SNGL)), priv->dc);
			writel(priv->cmd | QSPI_RD_SNGL, &priv->base->cmd);
			status = readl(&priv->base->status);
			timeout = QSPI_TIMEOUT;
			while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
				if (--timeout < 0) {
					printf("spi_xfer: RX timeout!\n");
					return -1;
				}
				status = readl(&priv->base->status);
			}
			*rxp++ = readl(&priv->base->data);
			xfer_len = 1;
			debug("rx done, status %08x, read %02x\n",
			      status, *(rxp-1));
		}
		words -= xfer_len;
	}

	/* Terminate frame */
	if (flags & SPI_XFER_END)
		ti_qspi_cs_deactivate(priv);

	return 0;
}

/* TODO: control from sf layer to here through dm-spi */
#if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
void spi_flash_copy_mmap(void *data, void *offset, size_t len)
{
	unsigned int			addr = (unsigned int) (data);
	unsigned int			edma_slot_num = 1;

	/* Invalidate the area, so no writeback into the RAM races with DMA */
	invalidate_dcache_range(addr, addr + roundup(len, ARCH_DMA_MINALIGN));

	/* enable edma3 clocks */
	enable_edma3_clocks();

	/* Call edma3 api to do actual DMA transfer	*/
	edma3_transfer(EDMA3_BASE, edma_slot_num, data, offset, len);

	/* disable edma3 clocks */
	disable_edma3_clocks();

	*((unsigned int *)offset) += len;
}
#endif

#ifndef CONFIG_DM_SPI

static inline struct ti_qspi_priv *to_ti_qspi_priv(struct spi_slave *slave)
{
	return container_of(slave, struct ti_qspi_priv, slave);
}

int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
	return 1;
}

void spi_cs_activate(struct spi_slave *slave)
{
	/* CS handled in xfer */
	return;
}

void spi_cs_deactivate(struct spi_slave *slave)
{
	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
	ti_qspi_cs_deactivate(priv);
}

void spi_init(void)
{
	/* nothing to do */
}

static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv)
{
	u32 memval = 0;

#ifdef CONFIG_QSPI_QUAD_SUPPORT
	struct spi_slave *slave = &priv->slave;
	memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES |
			QSPI_SETUP0_NUM_D_BYTES_8_BITS |
			QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE |
			QSPI_NUM_DUMMY_BITS);
	slave->mode |= SPI_RX_QUAD;
#else
	memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
			QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
			QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE |
			QSPI_NUM_DUMMY_BITS;
#endif

	writel(memval, &priv->base->setup0);
}

struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
				  unsigned int max_hz, unsigned int mode)
{
	struct ti_qspi_priv *priv;

#ifdef CONFIG_AM43XX
	gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio");
	gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
#endif

	priv = spi_alloc_slave(struct ti_qspi_priv, bus, cs);
	if (!priv) {
		printf("SPI_error: Fail to allocate ti_qspi_priv\n");
		return NULL;
	}

	priv->base = (struct ti_qspi_regs *)QSPI_BASE;
	priv->mode = mode;
#if defined(CONFIG_DRA7XX)
	priv->ctrl_mod_mmap = (void *)CORE_CTRL_IO;
	priv->slave.memory_map = (void *)MMAP_START_ADDR_DRA;
	priv->fclk = QSPI_DRA7XX_FCLK;
#else
	priv->slave.memory_map = (void *)MMAP_START_ADDR_AM43x;
	priv->fclk = QSPI_FCLK;
#endif

	ti_spi_set_speed(priv, max_hz);

#ifdef CONFIG_TI_SPI_MMAP
	ti_spi_setup_spi_register(priv);
#endif

	return &priv->slave;
}

void spi_free_slave(struct spi_slave *slave)
{
	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
	free(priv);
}

int spi_claim_bus(struct spi_slave *slave)
{
	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);

	debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
	__ti_qspi_set_mode(priv, priv->mode);
	return __ti_qspi_claim_bus(priv, priv->slave.cs);
}
void spi_release_bus(struct spi_slave *slave)
{
	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);

	debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
	__ti_qspi_release_bus(priv);
}

int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
	     void *din, unsigned long flags)
{
	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);

	debug("spi_xfer: bus:%i cs:%i bitlen:%i flags:%lx\n",
	      priv->slave.bus, priv->slave.cs, bitlen, flags);
	return __ti_qspi_xfer(priv, bitlen, dout, din, flags, priv->slave.cs);
}

#else /* CONFIG_DM_SPI */

static void __ti_qspi_setup_memorymap(struct ti_qspi_priv *priv,
				      struct spi_slave *slave,
				      bool enable)
{
	u32 memval;
	u32 mode = slave->mode & (SPI_RX_QUAD | SPI_RX_DUAL);

	if (!enable) {
		writel(0, &priv->base->setup0);
		return;
	}

	memval = QSPI_SETUP0_NUM_A_BYTES | QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS;

	switch (mode) {
	case SPI_RX_QUAD:
		memval |= QSPI_CMD_READ_QUAD;
		memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
		memval |= QSPI_SETUP0_READ_QUAD;
		slave->mode |= SPI_RX_QUAD;
		break;
	case SPI_RX_DUAL:
		memval |= QSPI_CMD_READ_DUAL;
		memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
		memval |= QSPI_SETUP0_READ_DUAL;
		break;
	default:
		memval |= QSPI_CMD_READ;
		memval |= QSPI_SETUP0_NUM_D_BYTES_NO_BITS;
		memval |= QSPI_SETUP0_READ_NORMAL;
		break;
	}

	writel(memval, &priv->base->setup0);
}


static int ti_qspi_set_speed(struct udevice *bus, uint max_hz)
{
	struct ti_qspi_priv *priv = dev_get_priv(bus);

	ti_spi_set_speed(priv, max_hz);

	return 0;
}

static int ti_qspi_set_mode(struct udevice *bus, uint mode)
{
	struct ti_qspi_priv *priv = dev_get_priv(bus);
	return __ti_qspi_set_mode(priv, mode);
}

static int ti_qspi_claim_bus(struct udevice *dev)
{
	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
	struct spi_slave *slave = dev_get_parent_priv(dev);
	struct ti_qspi_priv *priv;
	struct udevice *bus;

	bus = dev->parent;
	priv = dev_get_priv(bus);

	if (slave_plat->cs > priv->num_cs) {
		debug("invalid qspi chip select\n");
		return -EINVAL;
	}

	__ti_qspi_setup_memorymap(priv, slave, true);

	return __ti_qspi_claim_bus(priv, slave_plat->cs);
}

static int ti_qspi_release_bus(struct udevice *dev)
{
	struct spi_slave *slave = dev_get_parent_priv(dev);
	struct ti_qspi_priv *priv;
	struct udevice *bus;

	bus = dev->parent;
	priv = dev_get_priv(bus);

	__ti_qspi_setup_memorymap(priv, slave, false);
	__ti_qspi_release_bus(priv);

	return 0;
}

static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
			const void *dout, void *din, unsigned long flags)
{
	struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
	struct ti_qspi_priv *priv;
	struct udevice *bus;

	bus = dev->parent;
	priv = dev_get_priv(bus);

	if (slave->cs > priv->num_cs) {
		debug("invalid qspi chip select\n");
		return -EINVAL;
	}

	return __ti_qspi_xfer(priv, bitlen, dout, din, flags, slave->cs);
}

static int ti_qspi_probe(struct udevice *bus)
{
	struct ti_qspi_priv *priv = dev_get_priv(bus);

	priv->fclk = dev_get_driver_data(bus);

	return 0;
}

static void *map_syscon_chipselects(struct udevice *bus)
{
#if CONFIG_IS_ENABLED(SYSCON)
	struct udevice *syscon;
	struct regmap *regmap;
	const fdt32_t *cell;
	int len, err;

	err = uclass_get_device_by_phandle(UCLASS_SYSCON, bus,
					   "syscon-chipselects", &syscon);
	if (err) {
		debug("%s: unable to find syscon device (%d)\n", __func__,
		      err);
		return NULL;
	}

	regmap = syscon_get_regmap(syscon);
	if (IS_ERR(regmap)) {
		debug("%s: unable to find regmap (%ld)\n", __func__,
		      PTR_ERR(regmap));
		return NULL;
	}

	cell = fdt_getprop(gd->fdt_blob, dev_of_offset(bus),
			   "syscon-chipselects", &len);
	if (len < 2*sizeof(fdt32_t)) {
		debug("%s: offset not available\n", __func__);
		return NULL;
	}

	return fdtdec_get_number(cell + 1, 1) + regmap_get_range(regmap, 0);
#else
	fdt_addr_t addr;
	addr = devfdt_get_addr_index(bus, 2);
	return (addr == FDT_ADDR_T_NONE) ? NULL :
		map_physmem(addr, 0, MAP_NOCACHE);
#endif
}

static int ti_qspi_ofdata_to_platdata(struct udevice *bus)
{
	struct ti_qspi_priv *priv = dev_get_priv(bus);
	const void *blob = gd->fdt_blob;
	int node = dev_of_offset(bus);

	priv->ctrl_mod_mmap = map_syscon_chipselects(bus);
	priv->base = map_physmem(devfdt_get_addr(bus),
				 sizeof(struct ti_qspi_regs), MAP_NOCACHE);
	priv->memory_map = map_physmem(devfdt_get_addr_index(bus, 1), 0,
				       MAP_NOCACHE);

	priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
	if (priv->max_hz < 0) {
		debug("Error: Max frequency missing\n");
		return -ENODEV;
	}
	priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);

	debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__,
	      (int)priv->base, priv->max_hz);

	return 0;
}

static int ti_qspi_child_pre_probe(struct udevice *dev)
{
	struct spi_slave *slave = dev_get_parent_priv(dev);
	struct udevice *bus = dev_get_parent(dev);
	struct ti_qspi_priv *priv = dev_get_priv(bus);

	slave->memory_map = priv->memory_map;
	return 0;
}

static const struct dm_spi_ops ti_qspi_ops = {
	.claim_bus	= ti_qspi_claim_bus,
	.release_bus	= ti_qspi_release_bus,
	.xfer		= ti_qspi_xfer,
	.set_speed	= ti_qspi_set_speed,
	.set_mode	= ti_qspi_set_mode,
};

static const struct udevice_id ti_qspi_ids[] = {
	{ .compatible = "ti,dra7xxx-qspi",	.data = QSPI_DRA7XX_FCLK},
	{ .compatible = "ti,am4372-qspi",	.data = QSPI_FCLK},
	{ }
};

U_BOOT_DRIVER(ti_qspi) = {
	.name	= "ti_qspi",
	.id	= UCLASS_SPI,
	.of_match = ti_qspi_ids,
	.ops	= &ti_qspi_ops,
	.ofdata_to_platdata = ti_qspi_ofdata_to_platdata,
	.priv_auto_alloc_size = sizeof(struct ti_qspi_priv),
	.probe	= ti_qspi_probe,
	.child_pre_probe = ti_qspi_child_pre_probe,
};
#endif /* CONFIG_DM_SPI */
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
1d0933ea MP	2	/*
	3	* TI QSPI driver
	4	*
	5	* Copyright (C) 2013, Texas Instruments, Incorporated
1d0933ea MP	6	*/
	7
	8	#include <common.h>
	9	#include <asm/io.h>
	10	#include <asm/arch/omap.h>
	11	#include <malloc.h>
	12	#include <spi.h>
106f8139	13	#include <dm.h>
570533b8 SP	14	#include <asm/gpio.h>
570533b8 SP	15	#include <asm/omap_gpio.h>
8ddd9c48 V	16	#include <asm/omap_common.h>
8ddd9c48 V	17	#include <asm/ti-common/ti-edma3.h>
948b8bbd	18	#include <linux/kernel.h>
b06a381a JJH	19	#include <regmap.h>
b06a381a JJH	20	#include <syscon.h>
1d0933ea	21
106f8139 M	22	DECLARE_GLOBAL_DATA_PTR;
106f8139 M	23
1d0933ea MP	24	/* ti qpsi register bit masks */
1d0933ea MP	25	#define QSPI_TIMEOUT 2000000
a6f56ad1 V	26	#define QSPI_FCLK 192000000
a6f56ad1 V	27	#define QSPI_DRA7XX_FCLK 76800000
26036850 V	28	#define QSPI_WLEN_MAX_BITS 128
	29	#define QSPI_WLEN_MAX_BYTES (QSPI_WLEN_MAX_BITS >> 3)
	30	#define QSPI_WLEN_MASK QSPI_WLEN(QSPI_WLEN_MAX_BITS)
1d0933ea	31	/* clock control */
847720c4	32	#define QSPI_CLK_EN BIT(31)
1d0933ea MP	33	#define QSPI_CLK_DIV_MAX 0xffff
	34	/* command */
	35	#define QSPI_EN_CS(n) (n << 28)
	36	#define QSPI_WLEN(n) ((n-1) << 19)
847720c4 JT	37	#define QSPI_3_PIN BIT(18)
847720c4 JT	38	#define QSPI_RD_SNGL BIT(16)
1d0933ea MP	39	#define QSPI_WR_SNGL (2 << 16)
	40	#define QSPI_INVAL (4 << 16)
	41	#define QSPI_RD_QUAD (7 << 16)
	42	/* device control */
	43	#define QSPI_DD(m, n) (m << (3 + n*8))
	44	#define QSPI_CKPHA(n) (1 << (2 + n*8))
	45	#define QSPI_CSPOL(n) (1 << (1 + n*8))
	46	#define QSPI_CKPOL(n) (1 << (n*8))
	47	/* status */
847720c4 JT	48	#define QSPI_WC BIT(1)
847720c4 JT	49	#define QSPI_BUSY BIT(0)
1d0933ea MP	50	#define QSPI_WC_BUSY (QSPI_WC \| QSPI_BUSY)
	51	#define QSPI_XFER_DONE QSPI_WC
	52	#define MM_SWITCH 0x01
ec712f49	53	#define MEM_CS(cs) ((cs + 1) << 8)
8dfd6e21	54	#define MEM_CS_UNSELECT 0xfffff8ff
570533b8 SP	55	#define MMAP_START_ADDR_DRA 0x5c000000
570533b8 SP	56	#define MMAP_START_ADDR_AM43x 0x30000000
1d0933ea MP	57	#define CORE_CTRL_IO 0x4a002558
	58
	59	#define QSPI_CMD_READ (0x3 << 0)
106f8139	60	#define QSPI_CMD_READ_DUAL (0x6b << 0)
74d49bfd	61	#define QSPI_CMD_READ_QUAD (0x6c << 0)
1d0933ea	62	#define QSPI_CMD_READ_FAST (0x0b << 0)
74d49bfd	63	#define QSPI_SETUP0_NUM_A_BYTES (0x3 << 8)
1d0933ea MP	64	#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10)
	65	#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10)
	66	#define QSPI_SETUP0_READ_NORMAL (0x0 << 12)
106f8139	67	#define QSPI_SETUP0_READ_DUAL (0x1 << 12)
1d0933ea	68	#define QSPI_SETUP0_READ_QUAD (0x3 << 12)
74d49bfd	69	#define QSPI_CMD_WRITE (0x12 << 16)
1d0933ea MP	70	#define QSPI_NUM_DUMMY_BITS (0x0 << 24)
	71
	72	/* ti qspi register set */
	73	struct ti_qspi_regs {
	74	u32 pid;
	75	u32 pad0[3];
	76	u32 sysconfig;
	77	u32 pad1[3];
	78	u32 int_stat_raw;
	79	u32 int_stat_en;
	80	u32 int_en_set;
	81	u32 int_en_ctlr;
	82	u32 intc_eoi;
	83	u32 pad2[3];
	84	u32 clk_ctrl;
	85	u32 dc;
	86	u32 cmd;
	87	u32 status;
	88	u32 data;
	89	u32 setup0;
	90	u32 setup1;
	91	u32 setup2;
	92	u32 setup3;
	93	u32 memswitch;
	94	u32 data1;
	95	u32 data2;
	96	u32 data3;
	97	};
	98
9c42558a M	99	/* ti qspi priv */
9c42558a M	100	struct ti_qspi_priv {
106f8139	101	#ifndef CONFIG_DM_SPI
1d0933ea	102	struct spi_slave slave;
106f8139 M	103	#else
	104	void *memory_map;
	105	uint max_hz;
	106	u32 num_cs;
	107	#endif
1d0933ea	108	struct ti_qspi_regs *base;
22309144	109	void *ctrl_mod_mmap;
a6f56ad1	110	ulong fclk;
1d0933ea MP	111	unsigned int mode;
	112	u32 cmd;
	113	u32 dc;
	114	};
	115
22309144	116	static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
1d0933ea	117	{
1d0933ea MP	118	uint clk_div;
1d0933ea MP	119
1d0933ea MP	120	if (!hz)
	121	clk_div = 0;
	122	else
948b8bbd V	123	clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1;
	124
	125	/* truncate clk_div value to QSPI_CLK_DIV_MAX */
	126	if (clk_div > QSPI_CLK_DIV_MAX)
	127	clk_div = QSPI_CLK_DIV_MAX;
1d0933ea	128
c595a285 V	129	debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
c595a285 V	130
1d0933ea	131	/* disable SCLK */
9c42558a M	132	writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
9c42558a M	133	&priv->base->clk_ctrl);
948b8bbd	134	/* enable SCLK and program the clk divider */
9c42558a	135	writel(QSPI_CLK_EN \| clk_div, &priv->base->clk_ctrl);
1d0933ea MP	136	}
1d0933ea MP	137
22309144	138	static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
1d0933ea	139	{
9c42558a	140	writel(priv->cmd \| QSPI_INVAL, &priv->base->cmd);
857db48e	141	/* dummy readl to ensure bus sync */
22309144	142	readl(&priv->base->cmd);
1d0933ea MP	143	}
1d0933ea MP	144
22309144	145	static int __ti_qspi_set_mode(struct ti_qspi_priv *priv, unsigned int mode)
1d0933ea	146	{
22309144 M	147	priv->dc = 0;
	148	if (mode & SPI_CPHA)
	149	priv->dc \|= QSPI_CKPHA(0);
	150	if (mode & SPI_CPOL)
	151	priv->dc \|= QSPI_CKPOL(0);
	152	if (mode & SPI_CS_HIGH)
	153	priv->dc \|= QSPI_CSPOL(0);
1d0933ea	154
22309144	155	return 0;
1d0933ea MP	156	}
1d0933ea MP	157
22309144	158	static int __ti_qspi_claim_bus(struct ti_qspi_priv *priv, int cs)
1d0933ea	159	{
9c42558a M	160	writel(priv->dc, &priv->base->dc);
	161	writel(0, &priv->base->cmd);
	162	writel(0, &priv->base->data);
1d0933ea	163
22309144 M	164	priv->dc <<= cs * 8;
	165	writel(priv->dc, &priv->base->dc);
	166
1d0933ea MP	167	return 0;
	168	}
	169
22309144	170	static void __ti_qspi_release_bus(struct ti_qspi_priv *priv)
1d0933ea	171	{
9c42558a M	172	writel(0, &priv->base->dc);
	173	writel(0, &priv->base->cmd);
	174	writel(0, &priv->base->data);
1d0933ea MP	175	}
1d0933ea MP	176
22309144 M	177	static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
	178	{
	179	u32 val;
	180
	181	val = readl(ctrl_mod_mmap);
	182	if (enable)
	183	val \|= MEM_CS(cs);
	184	else
	185	val &= MEM_CS_UNSELECT;
	186	writel(val, ctrl_mod_mmap);
	187	}
	188
	189	static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen,
	190	const void dout, void din, unsigned long flags,
	191	u32 cs)
1d0933ea	192	{
1d0933ea MP	193	uint words = bitlen >> 3; /* fixed 8-bit word length */
	194	const uchar *txp = dout;
	195	uchar *rxp = din;
	196	uint status;
570533b8 SP	197	int timeout;
570533b8 SP	198
1d0933ea MP	199	/* Setup mmap flags */
1d0933ea MP	200	if (flags & SPI_XFER_MMAP) {
9c42558a	201	writel(MM_SWITCH, &priv->base->memswitch);
22309144 M	202	if (priv->ctrl_mod_mmap)
22309144 M	203	ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, true);
1d0933ea MP	204	return 0;
1d0933ea MP	205	} else if (flags & SPI_XFER_MMAP_END) {
9c42558a	206	writel(~MM_SWITCH, &priv->base->memswitch);
22309144 M	207	if (priv->ctrl_mod_mmap)
22309144 M	208	ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, false);
1d0933ea MP	209	return 0;
	210	}
	211
	212	if (bitlen == 0)
	213	return -1;
	214
	215	if (bitlen % 8) {
	216	debug("spi_xfer: Non byte aligned SPI transfer\n");
	217	return -1;
	218	}
	219
	220	/* Setup command reg */
9c42558a M	221	priv->cmd = 0;
9c42558a M	222	priv->cmd \|= QSPI_WLEN(8);
22309144	223	priv->cmd \|= QSPI_EN_CS(cs);
9c42558a M	224	if (priv->mode & SPI_3WIRE)
	225	priv->cmd \|= QSPI_3_PIN;
	226	priv->cmd \|= 0xfff;
1d0933ea	227
26036850 V	228	while (words) {
	229	u8 xfer_len = 0;
	230
1d0933ea	231	if (txp) {
26036850 V	232	u32 cmd = priv->cmd;
	233
	234	if (words >= QSPI_WLEN_MAX_BYTES) {
	235	u32 txbuf = (u32 )txp;
	236	u32 data;
	237
	238	data = cpu_to_be32(*txbuf++);
	239	writel(data, &priv->base->data3);
	240	data = cpu_to_be32(*txbuf++);
	241	writel(data, &priv->base->data2);
	242	data = cpu_to_be32(*txbuf++);
	243	writel(data, &priv->base->data1);
	244	data = cpu_to_be32(*txbuf++);
	245	writel(data, &priv->base->data);
	246	cmd &= ~QSPI_WLEN_MASK;
	247	cmd \|= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
	248	xfer_len = QSPI_WLEN_MAX_BYTES;
	249	} else {
	250	writeb(*txp, &priv->base->data);
	251	xfer_len = 1;
	252	}
	253	debug("tx cmd %08x dc %08x\n",
	254	cmd \| QSPI_WR_SNGL, priv->dc);
	255	writel(cmd \| QSPI_WR_SNGL, &priv->base->cmd);
9c42558a	256	status = readl(&priv->base->status);
1d0933ea MP	257	timeout = QSPI_TIMEOUT;
	258	while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
	259	if (--timeout < 0) {
	260	printf("spi_xfer: TX timeout!\n");
	261	return -1;
	262	}
9c42558a	263	status = readl(&priv->base->status);
1d0933ea	264	}
26036850	265	txp += xfer_len;
1d0933ea MP	266	debug("tx done, status %08x\n", status);
	267	}
	268	if (rxp) {
1d0933ea	269	debug("rx cmd %08x dc %08x\n",
69eeefaa	270	((u32)(priv->cmd \| QSPI_RD_SNGL)), priv->dc);
69eeefaa	271	writel(priv->cmd \| QSPI_RD_SNGL, &priv->base->cmd);
9c42558a	272	status = readl(&priv->base->status);
1d0933ea MP	273	timeout = QSPI_TIMEOUT;
	274	while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
	275	if (--timeout < 0) {
	276	printf("spi_xfer: RX timeout!\n");
	277	return -1;
	278	}
9c42558a	279	status = readl(&priv->base->status);
1d0933ea	280	}
9c42558a	281	*rxp++ = readl(&priv->base->data);
26036850	282	xfer_len = 1;
1d0933ea MP	283	debug("rx done, status %08x, read %02x\n",
	284	status, *(rxp-1));
	285	}
26036850	286	words -= xfer_len;
1d0933ea MP	287	}
	288
	289	/* Terminate frame */
	290	if (flags & SPI_XFER_END)
22309144	291	ti_qspi_cs_deactivate(priv);
1d0933ea MP	292
	293	return 0;
	294	}
8ddd9c48 V	295
8ddd9c48 V	296	/* TODO: control from sf layer to here through dm-spi */
518b0afc	297	#if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
8ddd9c48 V	298	void spi_flash_copy_mmap(void data, void offset, size_t len)
	299	{
	300	unsigned int addr = (unsigned int) (data);
	301	unsigned int edma_slot_num = 1;
	302
	303	/* Invalidate the area, so no writeback into the RAM races with DMA */
	304	invalidate_dcache_range(addr, addr + roundup(len, ARCH_DMA_MINALIGN));
	305
	306	/* enable edma3 clocks */
	307	enable_edma3_clocks();
	308
	309	/* Call edma3 api to do actual DMA transfer */
	310	edma3_transfer(EDMA3_BASE, edma_slot_num, data, offset, len);
	311
	312	/* disable edma3 clocks */
	313	disable_edma3_clocks();
	314
	315	((unsigned int )offset) += len;
	316	}
	317	#endif
22309144	318
106f8139 M	319	#ifndef CONFIG_DM_SPI
106f8139 M	320
22309144 M	321	static inline struct ti_qspi_priv to_ti_qspi_priv(struct spi_slave slave)
	322	{
	323	return container_of(slave, struct ti_qspi_priv, slave);
	324	}
	325
	326	int spi_cs_is_valid(unsigned int bus, unsigned int cs)
	327	{
	328	return 1;
	329	}
	330
	331	void spi_cs_activate(struct spi_slave *slave)
	332	{
	333	/* CS handled in xfer */
	334	return;
	335	}
	336
	337	void spi_cs_deactivate(struct spi_slave *slave)
	338	{
	339	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
	340	ti_qspi_cs_deactivate(priv);
	341	}
	342
	343	void spi_init(void)
	344	{
	345	/* nothing to do */
	346	}
	347
	348	static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv)
	349	{
	350	u32 memval = 0;
	351
	352	#ifdef CONFIG_QSPI_QUAD_SUPPORT
	353	struct spi_slave *slave = &priv->slave;
	354	memval \|= (QSPI_CMD_READ_QUAD \| QSPI_SETUP0_NUM_A_BYTES \|
	355	QSPI_SETUP0_NUM_D_BYTES_8_BITS \|
	356	QSPI_SETUP0_READ_QUAD \| QSPI_CMD_WRITE \|
	357	QSPI_NUM_DUMMY_BITS);
08fe9c29	358	slave->mode \|= SPI_RX_QUAD;
22309144 M	359	#else
	360	memval \|= QSPI_CMD_READ \| QSPI_SETUP0_NUM_A_BYTES \|
	361	QSPI_SETUP0_NUM_D_BYTES_NO_BITS \|
	362	QSPI_SETUP0_READ_NORMAL \| QSPI_CMD_WRITE \|
	363	QSPI_NUM_DUMMY_BITS;
	364	#endif
	365
	366	writel(memval, &priv->base->setup0);
	367	}
	368
	369	struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
	370	unsigned int max_hz, unsigned int mode)
	371	{
	372	struct ti_qspi_priv *priv;
	373
	374	#ifdef CONFIG_AM43XX
	375	gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio");
	376	gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
	377	#endif
	378
	379	priv = spi_alloc_slave(struct ti_qspi_priv, bus, cs);
	380	if (!priv) {
	381	printf("SPI_error: Fail to allocate ti_qspi_priv\n");
	382	return NULL;
	383	}
	384
	385	priv->base = (struct ti_qspi_regs *)QSPI_BASE;
	386	priv->mode = mode;
3891a54f	387	#if defined(CONFIG_DRA7XX)
22309144 M	388	priv->ctrl_mod_mmap = (void *)CORE_CTRL_IO;
22309144 M	389	priv->slave.memory_map = (void *)MMAP_START_ADDR_DRA;
a6f56ad1	390	priv->fclk = QSPI_DRA7XX_FCLK;
22309144 M	391	#else
22309144 M	392	priv->slave.memory_map = (void *)MMAP_START_ADDR_AM43x;
a6f56ad1	393	priv->fclk = QSPI_FCLK;
22309144 M	394	#endif
	395
	396	ti_spi_set_speed(priv, max_hz);
	397
	398	#ifdef CONFIG_TI_SPI_MMAP
	399	ti_spi_setup_spi_register(priv);
	400	#endif
	401
	402	return &priv->slave;
	403	}
	404
	405	void spi_free_slave(struct spi_slave *slave)
	406	{
	407	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
	408	free(priv);
	409	}
	410
	411	int spi_claim_bus(struct spi_slave *slave)
	412	{
	413	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
	414
	415	debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
	416	__ti_qspi_set_mode(priv, priv->mode);
	417	return __ti_qspi_claim_bus(priv, priv->slave.cs);
	418	}
	419	void spi_release_bus(struct spi_slave *slave)
	420	{
	421	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
	422
	423	debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
	424	__ti_qspi_release_bus(priv);
	425	}
	426
	427	int spi_xfer(struct spi_slave slave, unsigned int bitlen, const void dout,
	428	void *din, unsigned long flags)
	429	{
	430	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
	431
	432	debug("spi_xfer: bus:%i cs:%i bitlen:%i flags:%lx\n",
	433	priv->slave.bus, priv->slave.cs, bitlen, flags);
	434	return __ti_qspi_xfer(priv, bitlen, dout, din, flags, priv->slave.cs);
	435	}
106f8139 M	436
	437	#else /* CONFIG_DM_SPI */
	438
	439	static void __ti_qspi_setup_memorymap(struct ti_qspi_priv *priv,
	440	struct spi_slave *slave,
	441	bool enable)
	442	{
	443	u32 memval;
08fe9c29	444	u32 mode = slave->mode & (SPI_RX_QUAD \| SPI_RX_DUAL);
106f8139 M	445
	446	if (!enable) {
	447	writel(0, &priv->base->setup0);
	448	return;
	449	}
	450
	451	memval = QSPI_SETUP0_NUM_A_BYTES \| QSPI_CMD_WRITE \| QSPI_NUM_DUMMY_BITS;
	452
	453	switch (mode) {
	454	case SPI_RX_QUAD:
	455	memval \|= QSPI_CMD_READ_QUAD;
	456	memval \|= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
	457	memval \|= QSPI_SETUP0_READ_QUAD;
08fe9c29	458	slave->mode \|= SPI_RX_QUAD;
106f8139 M	459	break;
	460	case SPI_RX_DUAL:
	461	memval \|= QSPI_CMD_READ_DUAL;
	462	memval \|= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
	463	memval \|= QSPI_SETUP0_READ_DUAL;
	464	break;
	465	default:
	466	memval \|= QSPI_CMD_READ;
	467	memval \|= QSPI_SETUP0_NUM_D_BYTES_NO_BITS;
	468	memval \|= QSPI_SETUP0_READ_NORMAL;
	469	break;
	470	}
	471
	472	writel(memval, &priv->base->setup0);
	473	}
	474
	475
	476	static int ti_qspi_set_speed(struct udevice *bus, uint max_hz)
	477	{
	478	struct ti_qspi_priv *priv = dev_get_priv(bus);
	479
	480	ti_spi_set_speed(priv, max_hz);
	481
	482	return 0;
	483	}
	484
	485	static int ti_qspi_set_mode(struct udevice *bus, uint mode)
	486	{
	487	struct ti_qspi_priv *priv = dev_get_priv(bus);
	488	return __ti_qspi_set_mode(priv, mode);
	489	}
	490
	491	static int ti_qspi_claim_bus(struct udevice *dev)
	492	{
	493	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
	494	struct spi_slave *slave = dev_get_parent_priv(dev);
	495	struct ti_qspi_priv *priv;
	496	struct udevice *bus;
	497
	498	bus = dev->parent;
	499	priv = dev_get_priv(bus);
	500
	501	if (slave_plat->cs > priv->num_cs) {
	502	debug("invalid qspi chip select\n");
	503	return -EINVAL;
	504	}
	505
	506	__ti_qspi_setup_memorymap(priv, slave, true);
	507
	508	return __ti_qspi_claim_bus(priv, slave_plat->cs);
	509	}
	510
	511	static int ti_qspi_release_bus(struct udevice *dev)
	512	{
	513	struct spi_slave *slave = dev_get_parent_priv(dev);
	514	struct ti_qspi_priv *priv;
	515	struct udevice *bus;
	516
	517	bus = dev->parent;
	518	priv = dev_get_priv(bus);
	519
	520	__ti_qspi_setup_memorymap(priv, slave, false);
	521	__ti_qspi_release_bus(priv);
	522
523	return 0;
524	}
525
526	static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
527	const void dout, void din, unsigned long flags)
528	{
529	struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
530	struct ti_qspi_priv *priv;
531	struct udevice *bus;
532
533	bus = dev->parent;
534	priv = dev_get_priv(bus);
535
536	if (slave->cs > priv->num_cs) {
537	debug("invalid qspi chip select\n");
538	return -EINVAL;
539	}
540
541	return __ti_qspi_xfer(priv, bitlen, dout, din, flags, slave->cs);
542	}
543
544	static int ti_qspi_probe(struct udevice *bus)
545	{
a6f56ad1 V	546	struct ti_qspi_priv *priv = dev_get_priv(bus);
	547
	548	priv->fclk = dev_get_driver_data(bus);
	549
106f8139 M	550	return 0;
	551	}
	552
b06a381a JJH	553	static void map_syscon_chipselects(struct udevice bus)
	554	{
	555	#if CONFIG_IS_ENABLED(SYSCON)
	556	struct udevice *syscon;
	557	struct regmap *regmap;
	558	const fdt32_t *cell;
	559	int len, err;
	560
	561	err = uclass_get_device_by_phandle(UCLASS_SYSCON, bus,
	562	"syscon-chipselects", &syscon);
	563	if (err) {
	564	debug("%s: unable to find syscon device (%d)\n", __func__,
	565	err);
	566	return NULL;
	567	}
	568
	569	regmap = syscon_get_regmap(syscon);
	570	if (IS_ERR(regmap)) {
	571	debug("%s: unable to find regmap (%ld)\n", __func__,
	572	PTR_ERR(regmap));
	573	return NULL;
	574	}
	575
da409ccc SG	576	cell = fdt_getprop(gd->fdt_blob, dev_of_offset(bus),
da409ccc SG	577	"syscon-chipselects", &len);
b06a381a JJH	578	if (len < 2*sizeof(fdt32_t)) {
	579	debug("%s: offset not available\n", __func__);
	580	return NULL;
	581	}
	582
	583	return fdtdec_get_number(cell + 1, 1) + regmap_get_range(regmap, 0);
	584	#else
	585	fdt_addr_t addr;
a821c4af	586	addr = devfdt_get_addr_index(bus, 2);
b06a381a JJH	587	return (addr == FDT_ADDR_T_NONE) ? NULL :
	588	map_physmem(addr, 0, MAP_NOCACHE);
	589	#endif
	590	}
	591
106f8139 M	592	static int ti_qspi_ofdata_to_platdata(struct udevice *bus)
	593	{
	594	struct ti_qspi_priv *priv = dev_get_priv(bus);
	595	const void *blob = gd->fdt_blob;
e160f7d4	596	int node = dev_of_offset(bus);
106f8139	597
b06a381a	598	priv->ctrl_mod_mmap = map_syscon_chipselects(bus);
a821c4af SG	599	priv->base = map_physmem(devfdt_get_addr(bus),
	600	sizeof(struct ti_qspi_regs), MAP_NOCACHE);
	601	priv->memory_map = map_physmem(devfdt_get_addr_index(bus, 1), 0,
e6601df8	602	MAP_NOCACHE);
106f8139 M	603
	604	priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
	605	if (priv->max_hz < 0) {
	606	debug("Error: Max frequency missing\n");
	607	return -ENODEV;
	608	}
	609	priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
	610
	611	debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__,
	612	(int)priv->base, priv->max_hz);
	613
	614	return 0;
	615	}
	616
	617	static int ti_qspi_child_pre_probe(struct udevice *dev)
	618	{
	619	struct spi_slave *slave = dev_get_parent_priv(dev);
	620	struct udevice *bus = dev_get_parent(dev);
	621	struct ti_qspi_priv *priv = dev_get_priv(bus);
	622
	623	slave->memory_map = priv->memory_map;
	624	return 0;
	625	}
	626
	627	static const struct dm_spi_ops ti_qspi_ops = {
	628	.claim_bus = ti_qspi_claim_bus,
	629	.release_bus = ti_qspi_release_bus,
	630	.xfer = ti_qspi_xfer,
	631	.set_speed = ti_qspi_set_speed,
	632	.set_mode = ti_qspi_set_mode,
	633	};
	634
	635	static const struct udevice_id ti_qspi_ids[] = {
a6f56ad1 V	636	{ .compatible = "ti,dra7xxx-qspi", .data = QSPI_DRA7XX_FCLK},
a6f56ad1 V	637	{ .compatible = "ti,am4372-qspi", .data = QSPI_FCLK},
106f8139 M	638	{ }
	639	};
	640
	641	U_BOOT_DRIVER(ti_qspi) = {
	642	.name = "ti_qspi",
	643	.id = UCLASS_SPI,
	644	.of_match = ti_qspi_ids,
	645	.ops = &ti_qspi_ops,
	646	.ofdata_to_platdata = ti_qspi_ofdata_to_platdata,
	647	.priv_auto_alloc_size = sizeof(struct ti_qspi_priv),
	648	.probe = ti_qspi_probe,
	649	.child_pre_probe = ti_qspi_child_pre_probe,
	650	};
	651	#endif /* CONFIG_DM_SPI */