[people/ms/u-boot.git] / drivers / spi / ti_qspi.c

/*
 * TI QSPI driver
 *
 * Copyright (C) 2013, Texas Instruments, Incorporated
 *
 * SPDX-License-Identifier: GPL-2.0+
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/omap.h>
#include <malloc.h>
#include <spi.h>
#include <dm.h>
#include <asm/gpio.h>
#include <asm/omap_gpio.h>
#include <asm/omap_common.h>
#include <asm/ti-common/ti-edma3.h>
#include <linux/kernel.h>
#include <regmap.h>
#include <syscon.h>

DECLARE_GLOBAL_DATA_PTR;

/* ti qpsi register bit masks */
#define QSPI_TIMEOUT                    2000000
#define QSPI_FCLK			192000000
#define QSPI_DRA7XX_FCLK                76800000
#define QSPI_WLEN_MAX_BITS		128
#define QSPI_WLEN_MAX_BYTES		(QSPI_WLEN_MAX_BITS >> 3)
#define QSPI_WLEN_MASK			QSPI_WLEN(QSPI_WLEN_MAX_BITS)
/* clock control */
#define QSPI_CLK_EN                     BIT(31)
#define QSPI_CLK_DIV_MAX                0xffff
/* command */
#define QSPI_EN_CS(n)                   (n << 28)
#define QSPI_WLEN(n)                    ((n-1) << 19)
#define QSPI_3_PIN                      BIT(18)
#define QSPI_RD_SNGL                    BIT(16)
#define QSPI_WR_SNGL                    (2 << 16)
#define QSPI_INVAL                      (4 << 16)
#define QSPI_RD_QUAD                    (7 << 16)
/* device control */
#define QSPI_DD(m, n)                   (m << (3 + n*8))
#define QSPI_CKPHA(n)                   (1 << (2 + n*8))
#define QSPI_CSPOL(n)                   (1 << (1 + n*8))
#define QSPI_CKPOL(n)                   (1 << (n*8))
/* status */
#define QSPI_WC                         BIT(1)
#define QSPI_BUSY                       BIT(0)
#define QSPI_WC_BUSY                    (QSPI_WC | QSPI_BUSY)
#define QSPI_XFER_DONE                  QSPI_WC
#define MM_SWITCH                       0x01
#define MEM_CS(cs)                      ((cs + 1) << 8)
#define MEM_CS_UNSELECT                 0xfffff8ff
#define MMAP_START_ADDR_DRA		0x5c000000
#define MMAP_START_ADDR_AM43x		0x30000000
#define CORE_CTRL_IO                    0x4a002558

#define QSPI_CMD_READ                   (0x3 << 0)
#define QSPI_CMD_READ_DUAL		(0x6b << 0)
#define QSPI_CMD_READ_QUAD              (0x6c << 0)
#define QSPI_CMD_READ_FAST              (0x0b << 0)
#define QSPI_SETUP0_NUM_A_BYTES         (0x3 << 8)
#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10)
#define QSPI_SETUP0_NUM_D_BYTES_8_BITS  (0x1 << 10)
#define QSPI_SETUP0_READ_NORMAL         (0x0 << 12)
#define QSPI_SETUP0_READ_DUAL           (0x1 << 12)
#define QSPI_SETUP0_READ_QUAD           (0x3 << 12)
#define QSPI_CMD_WRITE                  (0x12 << 16)
#define QSPI_NUM_DUMMY_BITS             (0x0 << 24)

/* ti qspi register set */
struct ti_qspi_regs {
	u32 pid;
	u32 pad0[3];
	u32 sysconfig;
	u32 pad1[3];
	u32 int_stat_raw;
	u32 int_stat_en;
	u32 int_en_set;
	u32 int_en_ctlr;
	u32 intc_eoi;
	u32 pad2[3];
	u32 clk_ctrl;
	u32 dc;
	u32 cmd;
	u32 status;
	u32 data;
	u32 setup0;
	u32 setup1;
	u32 setup2;
	u32 setup3;
	u32 memswitch;
	u32 data1;
	u32 data2;
	u32 data3;
};

/* ti qspi priv */
struct ti_qspi_priv {
#ifndef CONFIG_DM_SPI
	struct spi_slave slave;
#else
	void *memory_map;
	uint max_hz;
	u32 num_cs;
#endif
	struct ti_qspi_regs *base;
	void *ctrl_mod_mmap;
	ulong fclk;
	unsigned int mode;
	u32 cmd;
	u32 dc;
};

static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
{
	uint clk_div;

	if (!hz)
		clk_div = 0;
	else
		clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1;

	/* truncate clk_div value to QSPI_CLK_DIV_MAX */
	if (clk_div > QSPI_CLK_DIV_MAX)
		clk_div = QSPI_CLK_DIV_MAX;

	debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);

	/* disable SCLK */
	writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
	       &priv->base->clk_ctrl);
	/* enable SCLK and program the clk divider */
	writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
}

static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
{
	writel(priv->cmd | QSPI_INVAL, &priv->base->cmd);
	/* dummy readl to ensure bus sync */
	readl(&priv->base->cmd);
}

static int __ti_qspi_set_mode(struct ti_qspi_priv *priv, unsigned int mode)
{
	priv->dc = 0;
	if (mode & SPI_CPHA)
		priv->dc |= QSPI_CKPHA(0);
	if (mode & SPI_CPOL)
		priv->dc |= QSPI_CKPOL(0);
	if (mode & SPI_CS_HIGH)
		priv->dc |= QSPI_CSPOL(0);

	return 0;
}

static int __ti_qspi_claim_bus(struct ti_qspi_priv *priv, int cs)
{
	writel(priv->dc, &priv->base->dc);
	writel(0, &priv->base->cmd);
	writel(0, &priv->base->data);

	priv->dc <<= cs * 8;
	writel(priv->dc, &priv->base->dc);

	return 0;
}

static void __ti_qspi_release_bus(struct ti_qspi_priv *priv)
{
	writel(0, &priv->base->dc);
	writel(0, &priv->base->cmd);
	writel(0, &priv->base->data);
}

static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
{
	u32 val;

	val = readl(ctrl_mod_mmap);
	if (enable)
		val |= MEM_CS(cs);
	else
		val &= MEM_CS_UNSELECT;
	writel(val, ctrl_mod_mmap);
}

static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen,
			const void *dout, void *din, unsigned long flags,
			u32 cs)
{
	uint words = bitlen >> 3; /* fixed 8-bit word length */
	const uchar *txp = dout;
	uchar *rxp = din;
	uint status;
	int timeout;

	/* Setup mmap flags */
	if (flags & SPI_XFER_MMAP) {
		writel(MM_SWITCH, &priv->base->memswitch);
		if (priv->ctrl_mod_mmap)
			ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, true);
		return 0;
	} else if (flags & SPI_XFER_MMAP_END) {
		writel(~MM_SWITCH, &priv->base->memswitch);
		if (priv->ctrl_mod_mmap)
			ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, false);
		return 0;
	}

	if (bitlen == 0)
		return -1;

	if (bitlen % 8) {
		debug("spi_xfer: Non byte aligned SPI transfer\n");
		return -1;
	}

	/* Setup command reg */
	priv->cmd = 0;
	priv->cmd |= QSPI_WLEN(8);
	priv->cmd |= QSPI_EN_CS(cs);
	if (priv->mode & SPI_3WIRE)
		priv->cmd |= QSPI_3_PIN;
	priv->cmd |= 0xfff;

	while (words) {
		u8 xfer_len = 0;

		if (txp) {
			u32 cmd = priv->cmd;

			if (words >= QSPI_WLEN_MAX_BYTES) {
				u32 *txbuf = (u32 *)txp;
				u32 data;

				data = cpu_to_be32(*txbuf++);
				writel(data, &priv->base->data3);
				data = cpu_to_be32(*txbuf++);
				writel(data, &priv->base->data2);
				data = cpu_to_be32(*txbuf++);
				writel(data, &priv->base->data1);
				data = cpu_to_be32(*txbuf++);
				writel(data, &priv->base->data);
				cmd &= ~QSPI_WLEN_MASK;
				cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
				xfer_len = QSPI_WLEN_MAX_BYTES;
			} else {
				writeb(*txp, &priv->base->data);
				xfer_len = 1;
			}
			debug("tx cmd %08x dc %08x\n",
			      cmd | QSPI_WR_SNGL, priv->dc);
			writel(cmd | QSPI_WR_SNGL, &priv->base->cmd);
			status = readl(&priv->base->status);
			timeout = QSPI_TIMEOUT;
			while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
				if (--timeout < 0) {
					printf("spi_xfer: TX timeout!\n");
					return -1;
				}
				status = readl(&priv->base->status);
			}
			txp += xfer_len;
			debug("tx done, status %08x\n", status);
		}
		if (rxp) {
			debug("rx cmd %08x dc %08x\n",
			      ((u32)(priv->cmd | QSPI_RD_SNGL)), priv->dc);
			writel(priv->cmd | QSPI_RD_SNGL, &priv->base->cmd);
			status = readl(&priv->base->status);
			timeout = QSPI_TIMEOUT;
			while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
				if (--timeout < 0) {
					printf("spi_xfer: RX timeout!\n");
					return -1;
				}
				status = readl(&priv->base->status);
			}
			*rxp++ = readl(&priv->base->data);
			xfer_len = 1;
			debug("rx done, status %08x, read %02x\n",
			      status, *(rxp-1));
		}
		words -= xfer_len;
	}

	/* Terminate frame */
	if (flags & SPI_XFER_END)
		ti_qspi_cs_deactivate(priv);

	return 0;
}

/* TODO: control from sf layer to here through dm-spi */
#if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
void spi_flash_copy_mmap(void *data, void *offset, size_t len)
{
	unsigned int			addr = (unsigned int) (data);
	unsigned int			edma_slot_num = 1;

	/* Invalidate the area, so no writeback into the RAM races with DMA */
	invalidate_dcache_range(addr, addr + roundup(len, ARCH_DMA_MINALIGN));

	/* enable edma3 clocks */
	enable_edma3_clocks();

	/* Call edma3 api to do actual DMA transfer	*/
	edma3_transfer(EDMA3_BASE, edma_slot_num, data, offset, len);

	/* disable edma3 clocks */
	disable_edma3_clocks();

	*((unsigned int *)offset) += len;
}
#endif

#ifndef CONFIG_DM_SPI

static inline struct ti_qspi_priv *to_ti_qspi_priv(struct spi_slave *slave)
{
	return container_of(slave, struct ti_qspi_priv, slave);
}

int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
	return 1;
}

void spi_cs_activate(struct spi_slave *slave)
{
	/* CS handled in xfer */
	return;
}

void spi_cs_deactivate(struct spi_slave *slave)
{
	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
	ti_qspi_cs_deactivate(priv);
}

void spi_init(void)
{
	/* nothing to do */
}

static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv)
{
	u32 memval = 0;

#ifdef CONFIG_QSPI_QUAD_SUPPORT
	struct spi_slave *slave = &priv->slave;
	memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES |
			QSPI_SETUP0_NUM_D_BYTES_8_BITS |
			QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE |
			QSPI_NUM_DUMMY_BITS);
	slave->mode |= SPI_RX_QUAD;
#else
	memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
			QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
			QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE |
			QSPI_NUM_DUMMY_BITS;
#endif

	writel(memval, &priv->base->setup0);
}

struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
				  unsigned int max_hz, unsigned int mode)
{
	struct ti_qspi_priv *priv;

#ifdef CONFIG_AM43XX
	gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio");
	gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
#endif

	priv = spi_alloc_slave(struct ti_qspi_priv, bus, cs);
	if (!priv) {
		printf("SPI_error: Fail to allocate ti_qspi_priv\n");
		return NULL;
	}

	priv->base = (struct ti_qspi_regs *)QSPI_BASE;
	priv->mode = mode;
#if defined(CONFIG_DRA7XX)
	priv->ctrl_mod_mmap = (void *)CORE_CTRL_IO;
	priv->slave.memory_map = (void *)MMAP_START_ADDR_DRA;
	priv->fclk = QSPI_DRA7XX_FCLK;
#else
	priv->slave.memory_map = (void *)MMAP_START_ADDR_AM43x;
	priv->fclk = QSPI_FCLK;
#endif

	ti_spi_set_speed(priv, max_hz);

#ifdef CONFIG_TI_SPI_MMAP
	ti_spi_setup_spi_register(priv);
#endif

	return &priv->slave;
}

void spi_free_slave(struct spi_slave *slave)
{
	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
	free(priv);
}

int spi_claim_bus(struct spi_slave *slave)
{
	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);

	debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
	__ti_qspi_set_mode(priv, priv->mode);
	return __ti_qspi_claim_bus(priv, priv->slave.cs);
}
void spi_release_bus(struct spi_slave *slave)
{
	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);

	debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
	__ti_qspi_release_bus(priv);
}

int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
	     void *din, unsigned long flags)
{
	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);

	debug("spi_xfer: bus:%i cs:%i bitlen:%i flags:%lx\n",
	      priv->slave.bus, priv->slave.cs, bitlen, flags);
	return __ti_qspi_xfer(priv, bitlen, dout, din, flags, priv->slave.cs);
}

#else /* CONFIG_DM_SPI */

static void __ti_qspi_setup_memorymap(struct ti_qspi_priv *priv,
				      struct spi_slave *slave,
				      bool enable)
{
	u32 memval;
	u32 mode = slave->mode & (SPI_RX_QUAD | SPI_RX_DUAL);

	if (!enable) {
		writel(0, &priv->base->setup0);
		return;
	}

	memval = QSPI_SETUP0_NUM_A_BYTES | QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS;

	switch (mode) {
	case SPI_RX_QUAD:
		memval |= QSPI_CMD_READ_QUAD;
		memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
		memval |= QSPI_SETUP0_READ_QUAD;
		slave->mode |= SPI_RX_QUAD;
		break;
	case SPI_RX_DUAL:
		memval |= QSPI_CMD_READ_DUAL;
		memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
		memval |= QSPI_SETUP0_READ_DUAL;
		break;
	default:
		memval |= QSPI_CMD_READ;
		memval |= QSPI_SETUP0_NUM_D_BYTES_NO_BITS;
		memval |= QSPI_SETUP0_READ_NORMAL;
		break;
	}

	writel(memval, &priv->base->setup0);
}


static int ti_qspi_set_speed(struct udevice *bus, uint max_hz)
{
	struct ti_qspi_priv *priv = dev_get_priv(bus);

	ti_spi_set_speed(priv, max_hz);

	return 0;
}

static int ti_qspi_set_mode(struct udevice *bus, uint mode)
{
	struct ti_qspi_priv *priv = dev_get_priv(bus);
	return __ti_qspi_set_mode(priv, mode);
}

static int ti_qspi_claim_bus(struct udevice *dev)
{
	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
	struct spi_slave *slave = dev_get_parent_priv(dev);
	struct ti_qspi_priv *priv;
	struct udevice *bus;

	bus = dev->parent;
	priv = dev_get_priv(bus);

	if (slave_plat->cs > priv->num_cs) {
		debug("invalid qspi chip select\n");
		return -EINVAL;
	}

	__ti_qspi_setup_memorymap(priv, slave, true);

	return __ti_qspi_claim_bus(priv, slave_plat->cs);
}

static int ti_qspi_release_bus(struct udevice *dev)
{
	struct spi_slave *slave = dev_get_parent_priv(dev);
	struct ti_qspi_priv *priv;
	struct udevice *bus;

	bus = dev->parent;
	priv = dev_get_priv(bus);

	__ti_qspi_setup_memorymap(priv, slave, false);
	__ti_qspi_release_bus(priv);

	return 0;
}

static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
			const void *dout, void *din, unsigned long flags)
{
	struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
	struct ti_qspi_priv *priv;
	struct udevice *bus;

	bus = dev->parent;
	priv = dev_get_priv(bus);

	if (slave->cs > priv->num_cs) {
		debug("invalid qspi chip select\n");
		return -EINVAL;
	}

	return __ti_qspi_xfer(priv, bitlen, dout, din, flags, slave->cs);
}

static int ti_qspi_probe(struct udevice *bus)
{
	struct ti_qspi_priv *priv = dev_get_priv(bus);

	priv->fclk = dev_get_driver_data(bus);

	return 0;
}

static void *map_syscon_chipselects(struct udevice *bus)
{
#if CONFIG_IS_ENABLED(SYSCON)
	struct udevice *syscon;
	struct regmap *regmap;
	const fdt32_t *cell;
	int len, err;

	err = uclass_get_device_by_phandle(UCLASS_SYSCON, bus,
					   "syscon-chipselects", &syscon);
	if (err) {
		debug("%s: unable to find syscon device (%d)\n", __func__,
		      err);
		return NULL;
	}

	regmap = syscon_get_regmap(syscon);
	if (IS_ERR(regmap)) {
		debug("%s: unable to find regmap (%ld)\n", __func__,
		      PTR_ERR(regmap));
		return NULL;
	}

	cell = fdt_getprop(gd->fdt_blob, dev_of_offset(bus),
			   "syscon-chipselects", &len);
	if (len < 2*sizeof(fdt32_t)) {
		debug("%s: offset not available\n", __func__);
		return NULL;
	}

	return fdtdec_get_number(cell + 1, 1) + regmap_get_range(regmap, 0);
#else
	fdt_addr_t addr;
	addr = devfdt_get_addr_index(bus, 2);
	return (addr == FDT_ADDR_T_NONE) ? NULL :
		map_physmem(addr, 0, MAP_NOCACHE);
#endif
}

static int ti_qspi_ofdata_to_platdata(struct udevice *bus)
{
	struct ti_qspi_priv *priv = dev_get_priv(bus);
	const void *blob = gd->fdt_blob;
	int node = dev_of_offset(bus);

	priv->ctrl_mod_mmap = map_syscon_chipselects(bus);
	priv->base = map_physmem(devfdt_get_addr(bus),
				 sizeof(struct ti_qspi_regs), MAP_NOCACHE);
	priv->memory_map = map_physmem(devfdt_get_addr_index(bus, 1), 0,
				       MAP_NOCACHE);

	priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
	if (priv->max_hz < 0) {
		debug("Error: Max frequency missing\n");
		return -ENODEV;
	}
	priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);

	debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__,
	      (int)priv->base, priv->max_hz);

	return 0;
}

static int ti_qspi_child_pre_probe(struct udevice *dev)
{
	struct spi_slave *slave = dev_get_parent_priv(dev);
	struct udevice *bus = dev_get_parent(dev);
	struct ti_qspi_priv *priv = dev_get_priv(bus);

	slave->memory_map = priv->memory_map;
	return 0;
}

static const struct dm_spi_ops ti_qspi_ops = {
	.claim_bus	= ti_qspi_claim_bus,
	.release_bus	= ti_qspi_release_bus,
	.xfer		= ti_qspi_xfer,
	.set_speed	= ti_qspi_set_speed,
	.set_mode	= ti_qspi_set_mode,
};

static const struct udevice_id ti_qspi_ids[] = {
	{ .compatible = "ti,dra7xxx-qspi",	.data = QSPI_DRA7XX_FCLK},
	{ .compatible = "ti,am4372-qspi",	.data = QSPI_FCLK},
	{ }
};

U_BOOT_DRIVER(ti_qspi) = {
	.name	= "ti_qspi",
	.id	= UCLASS_SPI,
	.of_match = ti_qspi_ids,
	.ops	= &ti_qspi_ops,
	.ofdata_to_platdata = ti_qspi_ofdata_to_platdata,
	.priv_auto_alloc_size = sizeof(struct ti_qspi_priv),
	.probe	= ti_qspi_probe,
	.child_pre_probe = ti_qspi_child_pre_probe,
};
#endif /* CONFIG_DM_SPI */
Commit	Line	Data
1d0933ea MP	1	/*
	2	* TI QSPI driver
	3	*
	4	* Copyright (C) 2013, Texas Instruments, Incorporated
	5	*
	6	* SPDX-License-Identifier: GPL-2.0+
	7	*/
	8
	9	#include <common.h>
	10	#include <asm/io.h>
	11	#include <asm/arch/omap.h>
	12	#include <malloc.h>
	13	#include <spi.h>
106f8139	14	#include <dm.h>
570533b8 SP	15	#include <asm/gpio.h>
570533b8 SP	16	#include <asm/omap_gpio.h>
8ddd9c48 V	17	#include <asm/omap_common.h>
8ddd9c48 V	18	#include <asm/ti-common/ti-edma3.h>
948b8bbd	19	#include <linux/kernel.h>
b06a381a JJH	20	#include <regmap.h>
b06a381a JJH	21	#include <syscon.h>
1d0933ea	22
106f8139 M	23	DECLARE_GLOBAL_DATA_PTR;
106f8139 M	24
1d0933ea MP	25	/* ti qpsi register bit masks */
1d0933ea MP	26	#define QSPI_TIMEOUT 2000000
a6f56ad1 V	27	#define QSPI_FCLK 192000000
a6f56ad1 V	28	#define QSPI_DRA7XX_FCLK 76800000
26036850 V	29	#define QSPI_WLEN_MAX_BITS 128
	30	#define QSPI_WLEN_MAX_BYTES (QSPI_WLEN_MAX_BITS >> 3)
	31	#define QSPI_WLEN_MASK QSPI_WLEN(QSPI_WLEN_MAX_BITS)
1d0933ea	32	/* clock control */
847720c4	33	#define QSPI_CLK_EN BIT(31)
1d0933ea MP	34	#define QSPI_CLK_DIV_MAX 0xffff
	35	/* command */
	36	#define QSPI_EN_CS(n) (n << 28)
	37	#define QSPI_WLEN(n) ((n-1) << 19)
847720c4 JT	38	#define QSPI_3_PIN BIT(18)
847720c4 JT	39	#define QSPI_RD_SNGL BIT(16)
1d0933ea MP	40	#define QSPI_WR_SNGL (2 << 16)
	41	#define QSPI_INVAL (4 << 16)
	42	#define QSPI_RD_QUAD (7 << 16)
	43	/* device control */
	44	#define QSPI_DD(m, n) (m << (3 + n*8))
	45	#define QSPI_CKPHA(n) (1 << (2 + n*8))
	46	#define QSPI_CSPOL(n) (1 << (1 + n*8))
	47	#define QSPI_CKPOL(n) (1 << (n*8))
	48	/* status */
847720c4 JT	49	#define QSPI_WC BIT(1)
847720c4 JT	50	#define QSPI_BUSY BIT(0)
1d0933ea MP	51	#define QSPI_WC_BUSY (QSPI_WC \| QSPI_BUSY)
	52	#define QSPI_XFER_DONE QSPI_WC
	53	#define MM_SWITCH 0x01
ec712f49	54	#define MEM_CS(cs) ((cs + 1) << 8)
8dfd6e21	55	#define MEM_CS_UNSELECT 0xfffff8ff
570533b8 SP	56	#define MMAP_START_ADDR_DRA 0x5c000000
570533b8 SP	57	#define MMAP_START_ADDR_AM43x 0x30000000
1d0933ea MP	58	#define CORE_CTRL_IO 0x4a002558
	59
	60	#define QSPI_CMD_READ (0x3 << 0)
106f8139	61	#define QSPI_CMD_READ_DUAL (0x6b << 0)
74d49bfd	62	#define QSPI_CMD_READ_QUAD (0x6c << 0)
1d0933ea	63	#define QSPI_CMD_READ_FAST (0x0b << 0)
74d49bfd	64	#define QSPI_SETUP0_NUM_A_BYTES (0x3 << 8)
1d0933ea MP	65	#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10)
	66	#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10)
	67	#define QSPI_SETUP0_READ_NORMAL (0x0 << 12)
106f8139	68	#define QSPI_SETUP0_READ_DUAL (0x1 << 12)
1d0933ea	69	#define QSPI_SETUP0_READ_QUAD (0x3 << 12)
74d49bfd	70	#define QSPI_CMD_WRITE (0x12 << 16)
1d0933ea MP	71	#define QSPI_NUM_DUMMY_BITS (0x0 << 24)
	72
	73	/* ti qspi register set */
	74	struct ti_qspi_regs {
	75	u32 pid;
	76	u32 pad0[3];
	77	u32 sysconfig;
	78	u32 pad1[3];
	79	u32 int_stat_raw;
	80	u32 int_stat_en;
	81	u32 int_en_set;
	82	u32 int_en_ctlr;
	83	u32 intc_eoi;
	84	u32 pad2[3];
	85	u32 clk_ctrl;
	86	u32 dc;
	87	u32 cmd;
	88	u32 status;
	89	u32 data;
	90	u32 setup0;
	91	u32 setup1;
	92	u32 setup2;
	93	u32 setup3;
	94	u32 memswitch;
	95	u32 data1;
	96	u32 data2;
	97	u32 data3;
	98	};
	99
9c42558a M	100	/* ti qspi priv */
9c42558a M	101	struct ti_qspi_priv {
106f8139	102	#ifndef CONFIG_DM_SPI
1d0933ea	103	struct spi_slave slave;
106f8139 M	104	#else
	105	void *memory_map;
	106	uint max_hz;
	107	u32 num_cs;
	108	#endif
1d0933ea	109	struct ti_qspi_regs *base;
22309144	110	void *ctrl_mod_mmap;
a6f56ad1	111	ulong fclk;
1d0933ea MP	112	unsigned int mode;
	113	u32 cmd;
	114	u32 dc;
	115	};
	116
22309144	117	static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
1d0933ea	118	{
1d0933ea MP	119	uint clk_div;
1d0933ea MP	120
1d0933ea MP	121	if (!hz)
	122	clk_div = 0;
	123	else
948b8bbd V	124	clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1;
	125
	126	/* truncate clk_div value to QSPI_CLK_DIV_MAX */
	127	if (clk_div > QSPI_CLK_DIV_MAX)
	128	clk_div = QSPI_CLK_DIV_MAX;
1d0933ea	129
c595a285 V	130	debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
c595a285 V	131
1d0933ea	132	/* disable SCLK */
9c42558a M	133	writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
9c42558a M	134	&priv->base->clk_ctrl);
948b8bbd	135	/* enable SCLK and program the clk divider */
9c42558a	136	writel(QSPI_CLK_EN \| clk_div, &priv->base->clk_ctrl);
1d0933ea MP	137	}
1d0933ea MP	138
22309144	139	static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
1d0933ea	140	{
9c42558a	141	writel(priv->cmd \| QSPI_INVAL, &priv->base->cmd);
857db48e	142	/* dummy readl to ensure bus sync */
22309144	143	readl(&priv->base->cmd);
1d0933ea MP	144	}
1d0933ea MP	145
22309144	146	static int __ti_qspi_set_mode(struct ti_qspi_priv *priv, unsigned int mode)
1d0933ea	147	{
22309144 M	148	priv->dc = 0;
	149	if (mode & SPI_CPHA)
	150	priv->dc \|= QSPI_CKPHA(0);
	151	if (mode & SPI_CPOL)
	152	priv->dc \|= QSPI_CKPOL(0);
	153	if (mode & SPI_CS_HIGH)
	154	priv->dc \|= QSPI_CSPOL(0);
1d0933ea	155
22309144	156	return 0;
1d0933ea MP	157	}
1d0933ea MP	158
22309144	159	static int __ti_qspi_claim_bus(struct ti_qspi_priv *priv, int cs)
1d0933ea	160	{
9c42558a M	161	writel(priv->dc, &priv->base->dc);
	162	writel(0, &priv->base->cmd);
	163	writel(0, &priv->base->data);
1d0933ea	164
22309144 M	165	priv->dc <<= cs * 8;
	166	writel(priv->dc, &priv->base->dc);
	167
1d0933ea MP	168	return 0;
	169	}
	170
22309144	171	static void __ti_qspi_release_bus(struct ti_qspi_priv *priv)
1d0933ea	172	{
9c42558a M	173	writel(0, &priv->base->dc);
	174	writel(0, &priv->base->cmd);
	175	writel(0, &priv->base->data);
1d0933ea MP	176	}
1d0933ea MP	177
22309144 M	178	static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
	179	{
	180	u32 val;
	181
	182	val = readl(ctrl_mod_mmap);
	183	if (enable)
	184	val \|= MEM_CS(cs);
	185	else
	186	val &= MEM_CS_UNSELECT;
	187	writel(val, ctrl_mod_mmap);
	188	}
	189
	190	static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen,
	191	const void dout, void din, unsigned long flags,
	192	u32 cs)
1d0933ea	193	{
1d0933ea MP	194	uint words = bitlen >> 3; /* fixed 8-bit word length */
	195	const uchar *txp = dout;
	196	uchar *rxp = din;
	197	uint status;
570533b8 SP	198	int timeout;
570533b8 SP	199
1d0933ea MP	200	/* Setup mmap flags */
1d0933ea MP	201	if (flags & SPI_XFER_MMAP) {
9c42558a	202	writel(MM_SWITCH, &priv->base->memswitch);
22309144 M	203	if (priv->ctrl_mod_mmap)
22309144 M	204	ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, true);
1d0933ea MP	205	return 0;
1d0933ea MP	206	} else if (flags & SPI_XFER_MMAP_END) {
9c42558a	207	writel(~MM_SWITCH, &priv->base->memswitch);
22309144 M	208	if (priv->ctrl_mod_mmap)
22309144 M	209	ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, false);
1d0933ea MP	210	return 0;
	211	}
	212
	213	if (bitlen == 0)
	214	return -1;
	215
	216	if (bitlen % 8) {
	217	debug("spi_xfer: Non byte aligned SPI transfer\n");
	218	return -1;
	219	}
	220
	221	/* Setup command reg */
9c42558a M	222	priv->cmd = 0;
9c42558a M	223	priv->cmd \|= QSPI_WLEN(8);
22309144	224	priv->cmd \|= QSPI_EN_CS(cs);
9c42558a M	225	if (priv->mode & SPI_3WIRE)
	226	priv->cmd \|= QSPI_3_PIN;
	227	priv->cmd \|= 0xfff;
1d0933ea	228
26036850 V	229	while (words) {
	230	u8 xfer_len = 0;
	231
1d0933ea	232	if (txp) {
26036850 V	233	u32 cmd = priv->cmd;
	234
	235	if (words >= QSPI_WLEN_MAX_BYTES) {
	236	u32 txbuf = (u32 )txp;
	237	u32 data;
	238
	239	data = cpu_to_be32(*txbuf++);
	240	writel(data, &priv->base->data3);
	241	data = cpu_to_be32(*txbuf++);
	242	writel(data, &priv->base->data2);
	243	data = cpu_to_be32(*txbuf++);
	244	writel(data, &priv->base->data1);
	245	data = cpu_to_be32(*txbuf++);
	246	writel(data, &priv->base->data);
	247	cmd &= ~QSPI_WLEN_MASK;
	248	cmd \|= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
	249	xfer_len = QSPI_WLEN_MAX_BYTES;
	250	} else {
	251	writeb(*txp, &priv->base->data);
	252	xfer_len = 1;
	253	}
	254	debug("tx cmd %08x dc %08x\n",
	255	cmd \| QSPI_WR_SNGL, priv->dc);
	256	writel(cmd \| QSPI_WR_SNGL, &priv->base->cmd);
9c42558a	257	status = readl(&priv->base->status);
1d0933ea MP	258	timeout = QSPI_TIMEOUT;
	259	while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
	260	if (--timeout < 0) {
	261	printf("spi_xfer: TX timeout!\n");
	262	return -1;
	263	}
9c42558a	264	status = readl(&priv->base->status);
1d0933ea	265	}
26036850	266	txp += xfer_len;
1d0933ea MP	267	debug("tx done, status %08x\n", status);
	268	}
	269	if (rxp) {
1d0933ea	270	debug("rx cmd %08x dc %08x\n",
69eeefaa	271	((u32)(priv->cmd \| QSPI_RD_SNGL)), priv->dc);
69eeefaa	272	writel(priv->cmd \| QSPI_RD_SNGL, &priv->base->cmd);
9c42558a	273	status = readl(&priv->base->status);
1d0933ea MP	274	timeout = QSPI_TIMEOUT;
	275	while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
	276	if (--timeout < 0) {
	277	printf("spi_xfer: RX timeout!\n");
	278	return -1;
	279	}
9c42558a	280	status = readl(&priv->base->status);
1d0933ea	281	}
9c42558a	282	*rxp++ = readl(&priv->base->data);
26036850	283	xfer_len = 1;
1d0933ea MP	284	debug("rx done, status %08x, read %02x\n",
	285	status, *(rxp-1));
	286	}
26036850	287	words -= xfer_len;
1d0933ea MP	288	}
	289
	290	/* Terminate frame */
	291	if (flags & SPI_XFER_END)
22309144	292	ti_qspi_cs_deactivate(priv);
1d0933ea MP	293
	294	return 0;
	295	}
8ddd9c48 V	296
8ddd9c48 V	297	/* TODO: control from sf layer to here through dm-spi */
518b0afc	298	#if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
8ddd9c48 V	299	void spi_flash_copy_mmap(void data, void offset, size_t len)
	300	{
	301	unsigned int addr = (unsigned int) (data);
	302	unsigned int edma_slot_num = 1;
	303
	304	/* Invalidate the area, so no writeback into the RAM races with DMA */
	305	invalidate_dcache_range(addr, addr + roundup(len, ARCH_DMA_MINALIGN));
	306
	307	/* enable edma3 clocks */
	308	enable_edma3_clocks();
	309
	310	/* Call edma3 api to do actual DMA transfer */
	311	edma3_transfer(EDMA3_BASE, edma_slot_num, data, offset, len);
	312
	313	/* disable edma3 clocks */
	314	disable_edma3_clocks();
	315
	316	((unsigned int )offset) += len;
	317	}
	318	#endif
22309144	319
106f8139 M	320	#ifndef CONFIG_DM_SPI
106f8139 M	321
22309144 M	322	static inline struct ti_qspi_priv to_ti_qspi_priv(struct spi_slave slave)
	323	{
	324	return container_of(slave, struct ti_qspi_priv, slave);
	325	}
	326
	327	int spi_cs_is_valid(unsigned int bus, unsigned int cs)
	328	{
	329	return 1;
	330	}
	331
	332	void spi_cs_activate(struct spi_slave *slave)
	333	{
	334	/* CS handled in xfer */
	335	return;
	336	}
	337
	338	void spi_cs_deactivate(struct spi_slave *slave)
	339	{
	340	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
	341	ti_qspi_cs_deactivate(priv);
	342	}
	343
	344	void spi_init(void)
	345	{
	346	/* nothing to do */
	347	}
	348
	349	static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv)
	350	{
	351	u32 memval = 0;
	352
	353	#ifdef CONFIG_QSPI_QUAD_SUPPORT
	354	struct spi_slave *slave = &priv->slave;
	355	memval \|= (QSPI_CMD_READ_QUAD \| QSPI_SETUP0_NUM_A_BYTES \|
	356	QSPI_SETUP0_NUM_D_BYTES_8_BITS \|
	357	QSPI_SETUP0_READ_QUAD \| QSPI_CMD_WRITE \|
	358	QSPI_NUM_DUMMY_BITS);
08fe9c29	359	slave->mode \|= SPI_RX_QUAD;
22309144 M	360	#else
	361	memval \|= QSPI_CMD_READ \| QSPI_SETUP0_NUM_A_BYTES \|
	362	QSPI_SETUP0_NUM_D_BYTES_NO_BITS \|
	363	QSPI_SETUP0_READ_NORMAL \| QSPI_CMD_WRITE \|
	364	QSPI_NUM_DUMMY_BITS;
	365	#endif
	366
	367	writel(memval, &priv->base->setup0);
	368	}
	369
	370	struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
	371	unsigned int max_hz, unsigned int mode)
	372	{
	373	struct ti_qspi_priv *priv;
	374
	375	#ifdef CONFIG_AM43XX
	376	gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio");
	377	gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
	378	#endif
	379
	380	priv = spi_alloc_slave(struct ti_qspi_priv, bus, cs);
	381	if (!priv) {
	382	printf("SPI_error: Fail to allocate ti_qspi_priv\n");
	383	return NULL;
	384	}
	385
	386	priv->base = (struct ti_qspi_regs *)QSPI_BASE;
	387	priv->mode = mode;
3891a54f	388	#if defined(CONFIG_DRA7XX)
22309144 M	389	priv->ctrl_mod_mmap = (void *)CORE_CTRL_IO;
22309144 M	390	priv->slave.memory_map = (void *)MMAP_START_ADDR_DRA;
a6f56ad1	391	priv->fclk = QSPI_DRA7XX_FCLK;
22309144 M	392	#else
22309144 M	393	priv->slave.memory_map = (void *)MMAP_START_ADDR_AM43x;
a6f56ad1	394	priv->fclk = QSPI_FCLK;
22309144 M	395	#endif
	396
	397	ti_spi_set_speed(priv, max_hz);
	398
	399	#ifdef CONFIG_TI_SPI_MMAP
	400	ti_spi_setup_spi_register(priv);
	401	#endif
	402
	403	return &priv->slave;
	404	}
	405
	406	void spi_free_slave(struct spi_slave *slave)
	407	{
	408	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
	409	free(priv);
	410	}
	411
	412	int spi_claim_bus(struct spi_slave *slave)
	413	{
	414	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
	415
	416	debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
	417	__ti_qspi_set_mode(priv, priv->mode);
	418	return __ti_qspi_claim_bus(priv, priv->slave.cs);
	419	}
	420	void spi_release_bus(struct spi_slave *slave)
	421	{
	422	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
	423
	424	debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
	425	__ti_qspi_release_bus(priv);
	426	}
	427
	428	int spi_xfer(struct spi_slave slave, unsigned int bitlen, const void dout,
	429	void *din, unsigned long flags)
	430	{
	431	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
	432
	433	debug("spi_xfer: bus:%i cs:%i bitlen:%i flags:%lx\n",
	434	priv->slave.bus, priv->slave.cs, bitlen, flags);
	435	return __ti_qspi_xfer(priv, bitlen, dout, din, flags, priv->slave.cs);
	436	}
106f8139 M	437
	438	#else /* CONFIG_DM_SPI */
	439
	440	static void __ti_qspi_setup_memorymap(struct ti_qspi_priv *priv,
	441	struct spi_slave *slave,
	442	bool enable)
	443	{
	444	u32 memval;
08fe9c29	445	u32 mode = slave->mode & (SPI_RX_QUAD \| SPI_RX_DUAL);
106f8139 M	446
	447	if (!enable) {
	448	writel(0, &priv->base->setup0);
	449	return;
	450	}
	451
	452	memval = QSPI_SETUP0_NUM_A_BYTES \| QSPI_CMD_WRITE \| QSPI_NUM_DUMMY_BITS;
	453
	454	switch (mode) {
	455	case SPI_RX_QUAD:
	456	memval \|= QSPI_CMD_READ_QUAD;
	457	memval \|= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
	458	memval \|= QSPI_SETUP0_READ_QUAD;
08fe9c29	459	slave->mode \|= SPI_RX_QUAD;
106f8139 M	460	break;
	461	case SPI_RX_DUAL:
	462	memval \|= QSPI_CMD_READ_DUAL;
	463	memval \|= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
	464	memval \|= QSPI_SETUP0_READ_DUAL;
	465	break;
	466	default:
	467	memval \|= QSPI_CMD_READ;
	468	memval \|= QSPI_SETUP0_NUM_D_BYTES_NO_BITS;
	469	memval \|= QSPI_SETUP0_READ_NORMAL;
	470	break;
	471	}
	472
	473	writel(memval, &priv->base->setup0);
	474	}
	475
	476
	477	static int ti_qspi_set_speed(struct udevice *bus, uint max_hz)
	478	{
	479	struct ti_qspi_priv *priv = dev_get_priv(bus);
	480
	481	ti_spi_set_speed(priv, max_hz);
	482
	483	return 0;
	484	}
	485
	486	static int ti_qspi_set_mode(struct udevice *bus, uint mode)
	487	{
	488	struct ti_qspi_priv *priv = dev_get_priv(bus);
	489	return __ti_qspi_set_mode(priv, mode);
	490	}
	491
	492	static int ti_qspi_claim_bus(struct udevice *dev)
	493	{
	494	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
	495	struct spi_slave *slave = dev_get_parent_priv(dev);
	496	struct ti_qspi_priv *priv;
	497	struct udevice *bus;
	498
	499	bus = dev->parent;
	500	priv = dev_get_priv(bus);
	501
	502	if (slave_plat->cs > priv->num_cs) {
	503	debug("invalid qspi chip select\n");
	504	return -EINVAL;
	505	}
	506
	507	__ti_qspi_setup_memorymap(priv, slave, true);
	508
	509	return __ti_qspi_claim_bus(priv, slave_plat->cs);
	510	}
	511
	512	static int ti_qspi_release_bus(struct udevice *dev)
	513	{
	514	struct spi_slave *slave = dev_get_parent_priv(dev);
	515	struct ti_qspi_priv *priv;
	516	struct udevice *bus;
	517
	518	bus = dev->parent;
	519	priv = dev_get_priv(bus);
	520
	521	__ti_qspi_setup_memorymap(priv, slave, false);
	522	__ti_qspi_release_bus(priv);
	523
524	return 0;
525	}
526
527	static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
528	const void dout, void din, unsigned long flags)
529	{
530	struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
531	struct ti_qspi_priv *priv;
532	struct udevice *bus;
533
534	bus = dev->parent;
535	priv = dev_get_priv(bus);
536
537	if (slave->cs > priv->num_cs) {
538	debug("invalid qspi chip select\n");
539	return -EINVAL;
540	}
541
542	return __ti_qspi_xfer(priv, bitlen, dout, din, flags, slave->cs);
543	}
544
545	static int ti_qspi_probe(struct udevice *bus)
546	{
a6f56ad1 V	547	struct ti_qspi_priv *priv = dev_get_priv(bus);
	548
	549	priv->fclk = dev_get_driver_data(bus);
	550
106f8139 M	551	return 0;
	552	}
	553
b06a381a JJH	554	static void map_syscon_chipselects(struct udevice bus)
	555	{
	556	#if CONFIG_IS_ENABLED(SYSCON)
	557	struct udevice *syscon;
	558	struct regmap *regmap;
	559	const fdt32_t *cell;
	560	int len, err;
	561
	562	err = uclass_get_device_by_phandle(UCLASS_SYSCON, bus,
	563	"syscon-chipselects", &syscon);
	564	if (err) {
	565	debug("%s: unable to find syscon device (%d)\n", __func__,
	566	err);
	567	return NULL;
	568	}
	569
	570	regmap = syscon_get_regmap(syscon);
	571	if (IS_ERR(regmap)) {
	572	debug("%s: unable to find regmap (%ld)\n", __func__,
	573	PTR_ERR(regmap));
	574	return NULL;
	575	}
	576
da409ccc SG	577	cell = fdt_getprop(gd->fdt_blob, dev_of_offset(bus),
da409ccc SG	578	"syscon-chipselects", &len);
b06a381a JJH	579	if (len < 2*sizeof(fdt32_t)) {
	580	debug("%s: offset not available\n", __func__);
	581	return NULL;
	582	}
	583
	584	return fdtdec_get_number(cell + 1, 1) + regmap_get_range(regmap, 0);
	585	#else
	586	fdt_addr_t addr;
a821c4af	587	addr = devfdt_get_addr_index(bus, 2);
b06a381a JJH	588	return (addr == FDT_ADDR_T_NONE) ? NULL :
	589	map_physmem(addr, 0, MAP_NOCACHE);
	590	#endif
	591	}
	592
106f8139 M	593	static int ti_qspi_ofdata_to_platdata(struct udevice *bus)
	594	{
	595	struct ti_qspi_priv *priv = dev_get_priv(bus);
	596	const void *blob = gd->fdt_blob;
e160f7d4	597	int node = dev_of_offset(bus);
106f8139	598
b06a381a	599	priv->ctrl_mod_mmap = map_syscon_chipselects(bus);
a821c4af SG	600	priv->base = map_physmem(devfdt_get_addr(bus),
	601	sizeof(struct ti_qspi_regs), MAP_NOCACHE);
	602	priv->memory_map = map_physmem(devfdt_get_addr_index(bus, 1), 0,
e6601df8	603	MAP_NOCACHE);
106f8139 M	604
	605	priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
	606	if (priv->max_hz < 0) {
	607	debug("Error: Max frequency missing\n");
	608	return -ENODEV;
	609	}
	610	priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
	611
	612	debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__,
	613	(int)priv->base, priv->max_hz);
	614
	615	return 0;
	616	}
	617
	618	static int ti_qspi_child_pre_probe(struct udevice *dev)
	619	{
	620	struct spi_slave *slave = dev_get_parent_priv(dev);
	621	struct udevice *bus = dev_get_parent(dev);
	622	struct ti_qspi_priv *priv = dev_get_priv(bus);
	623
	624	slave->memory_map = priv->memory_map;
	625	return 0;
	626	}
	627
	628	static const struct dm_spi_ops ti_qspi_ops = {
	629	.claim_bus = ti_qspi_claim_bus,
	630	.release_bus = ti_qspi_release_bus,
	631	.xfer = ti_qspi_xfer,
	632	.set_speed = ti_qspi_set_speed,
	633	.set_mode = ti_qspi_set_mode,
	634	};
	635
	636	static const struct udevice_id ti_qspi_ids[] = {
a6f56ad1 V	637	{ .compatible = "ti,dra7xxx-qspi", .data = QSPI_DRA7XX_FCLK},
a6f56ad1 V	638	{ .compatible = "ti,am4372-qspi", .data = QSPI_FCLK},
106f8139 M	639	{ }
	640	};
	641
	642	U_BOOT_DRIVER(ti_qspi) = {
	643	.name = "ti_qspi",
	644	.id = UCLASS_SPI,
	645	.of_match = ti_qspi_ids,
	646	.ops = &ti_qspi_ops,
	647	.ofdata_to_platdata = ti_qspi_ofdata_to_platdata,
	648	.priv_auto_alloc_size = sizeof(struct ti_qspi_priv),
	649	.probe = ti_qspi_probe,
	650	.child_pre_probe = ti_qspi_child_pre_probe,
	651	};
	652	#endif /* CONFIG_DM_SPI */