[people/ms/u-boot.git] / drivers / spi / ti_qspi.c

/*
 * TI QSPI driver
 *
 * Copyright (C) 2013, Texas Instruments, Incorporated
 *
 * SPDX-License-Identifier: GPL-2.0+
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/omap.h>
#include <malloc.h>
#include <spi.h>
#include <dm.h>
#include <asm/gpio.h>
#include <asm/omap_gpio.h>
#include <asm/omap_common.h>
#include <asm/ti-common/ti-edma3.h>

DECLARE_GLOBAL_DATA_PTR;

/* ti qpsi register bit masks */
#define QSPI_TIMEOUT                    2000000
#define QSPI_FCLK                       192000000
/* clock control */
#define QSPI_CLK_EN                     BIT(31)
#define QSPI_CLK_DIV_MAX                0xffff
/* command */
#define QSPI_EN_CS(n)                   (n << 28)
#define QSPI_WLEN(n)                    ((n-1) << 19)
#define QSPI_3_PIN                      BIT(18)
#define QSPI_RD_SNGL                    BIT(16)
#define QSPI_WR_SNGL                    (2 << 16)
#define QSPI_INVAL                      (4 << 16)
#define QSPI_RD_QUAD                    (7 << 16)
/* device control */
#define QSPI_DD(m, n)                   (m << (3 + n*8))
#define QSPI_CKPHA(n)                   (1 << (2 + n*8))
#define QSPI_CSPOL(n)                   (1 << (1 + n*8))
#define QSPI_CKPOL(n)                   (1 << (n*8))
/* status */
#define QSPI_WC                         BIT(1)
#define QSPI_BUSY                       BIT(0)
#define QSPI_WC_BUSY                    (QSPI_WC | QSPI_BUSY)
#define QSPI_XFER_DONE                  QSPI_WC
#define MM_SWITCH                       0x01
#define MEM_CS(cs)                      ((cs + 1) << 8)
#define MEM_CS_UNSELECT                 0xfffff8ff
#define MMAP_START_ADDR_DRA		0x5c000000
#define MMAP_START_ADDR_AM43x		0x30000000
#define CORE_CTRL_IO                    0x4a002558

#define QSPI_CMD_READ                   (0x3 << 0)
#define QSPI_CMD_READ_DUAL		(0x6b << 0)
#define QSPI_CMD_READ_QUAD              (0x6c << 0)
#define QSPI_CMD_READ_FAST              (0x0b << 0)
#define QSPI_SETUP0_NUM_A_BYTES         (0x3 << 8)
#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10)
#define QSPI_SETUP0_NUM_D_BYTES_8_BITS  (0x1 << 10)
#define QSPI_SETUP0_READ_NORMAL         (0x0 << 12)
#define QSPI_SETUP0_READ_DUAL           (0x1 << 12)
#define QSPI_SETUP0_READ_QUAD           (0x3 << 12)
#define QSPI_CMD_WRITE                  (0x12 << 16)
#define QSPI_NUM_DUMMY_BITS             (0x0 << 24)

/* ti qspi register set */
struct ti_qspi_regs {
	u32 pid;
	u32 pad0[3];
	u32 sysconfig;
	u32 pad1[3];
	u32 int_stat_raw;
	u32 int_stat_en;
	u32 int_en_set;
	u32 int_en_ctlr;
	u32 intc_eoi;
	u32 pad2[3];
	u32 clk_ctrl;
	u32 dc;
	u32 cmd;
	u32 status;
	u32 data;
	u32 setup0;
	u32 setup1;
	u32 setup2;
	u32 setup3;
	u32 memswitch;
	u32 data1;
	u32 data2;
	u32 data3;
};

/* ti qspi priv */
struct ti_qspi_priv {
#ifndef CONFIG_DM_SPI
	struct spi_slave slave;
#else
	void *memory_map;
	uint max_hz;
	u32 num_cs;
#endif
	struct ti_qspi_regs *base;
	void *ctrl_mod_mmap;
	unsigned int mode;
	u32 cmd;
	u32 dc;
};

static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
{
	uint clk_div;

	debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);

	if (!hz)
		clk_div = 0;
	else
		clk_div = (QSPI_FCLK / hz) - 1;

	/* disable SCLK */
	writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
	       &priv->base->clk_ctrl);

	/* assign clk_div values */
	if (clk_div < 0)
		clk_div = 0;
	else if (clk_div > QSPI_CLK_DIV_MAX)
		clk_div = QSPI_CLK_DIV_MAX;

	/* enable SCLK */
	writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
}

static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
{
	writel(priv->cmd | QSPI_INVAL, &priv->base->cmd);
	/* dummy readl to ensure bus sync */
	readl(&priv->base->cmd);
}

static int __ti_qspi_set_mode(struct ti_qspi_priv *priv, unsigned int mode)
{
	priv->dc = 0;
	if (mode & SPI_CPHA)
		priv->dc |= QSPI_CKPHA(0);
	if (mode & SPI_CPOL)
		priv->dc |= QSPI_CKPOL(0);
	if (mode & SPI_CS_HIGH)
		priv->dc |= QSPI_CSPOL(0);

	return 0;
}

static int __ti_qspi_claim_bus(struct ti_qspi_priv *priv, int cs)
{
	writel(priv->dc, &priv->base->dc);
	writel(0, &priv->base->cmd);
	writel(0, &priv->base->data);

	priv->dc <<= cs * 8;
	writel(priv->dc, &priv->base->dc);

	return 0;
}

static void __ti_qspi_release_bus(struct ti_qspi_priv *priv)
{
	writel(0, &priv->base->dc);
	writel(0, &priv->base->cmd);
	writel(0, &priv->base->data);
}

static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
{
	u32 val;

	val = readl(ctrl_mod_mmap);
	if (enable)
		val |= MEM_CS(cs);
	else
		val &= MEM_CS_UNSELECT;
	writel(val, ctrl_mod_mmap);
}

static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen,
			const void *dout, void *din, unsigned long flags,
			u32 cs)
{
	uint words = bitlen >> 3; /* fixed 8-bit word length */
	const uchar *txp = dout;
	uchar *rxp = din;
	uint status;
	int timeout;

	/* Setup mmap flags */
	if (flags & SPI_XFER_MMAP) {
		writel(MM_SWITCH, &priv->base->memswitch);
		if (priv->ctrl_mod_mmap)
			ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, true);
		return 0;
	} else if (flags & SPI_XFER_MMAP_END) {
		writel(~MM_SWITCH, &priv->base->memswitch);
		if (priv->ctrl_mod_mmap)
			ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, false);
		return 0;
	}

	if (bitlen == 0)
		return -1;

	if (bitlen % 8) {
		debug("spi_xfer: Non byte aligned SPI transfer\n");
		return -1;
	}

	/* Setup command reg */
	priv->cmd = 0;
	priv->cmd |= QSPI_WLEN(8);
	priv->cmd |= QSPI_EN_CS(cs);
	if (priv->mode & SPI_3WIRE)
		priv->cmd |= QSPI_3_PIN;
	priv->cmd |= 0xfff;

/* FIXME: This delay is required for successfull
 * completion of read/write/erase. Once its root
 * caused, it will be remove from the driver.
 */
#ifdef CONFIG_AM43XX
	udelay(100);
#endif
	while (words--) {
		if (txp) {
			debug("tx cmd %08x dc %08x data %02x\n",
			      priv->cmd | QSPI_WR_SNGL, priv->dc, *txp);
			writel(*txp++, &priv->base->data);
			writel(priv->cmd | QSPI_WR_SNGL,
			       &priv->base->cmd);
			status = readl(&priv->base->status);
			timeout = QSPI_TIMEOUT;
			while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
				if (--timeout < 0) {
					printf("spi_xfer: TX timeout!\n");
					return -1;
				}
				status = readl(&priv->base->status);
			}
			debug("tx done, status %08x\n", status);
		}
		if (rxp) {
			debug("rx cmd %08x dc %08x\n",
			      ((u32)(priv->cmd | QSPI_RD_SNGL)), priv->dc);
			#ifdef CONFIG_DRA7XX
				udelay(500);
			#endif
			writel(priv->cmd | QSPI_RD_SNGL, &priv->base->cmd);
			status = readl(&priv->base->status);
			timeout = QSPI_TIMEOUT;
			while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
				if (--timeout < 0) {
					printf("spi_xfer: RX timeout!\n");
					return -1;
				}
				status = readl(&priv->base->status);
			}
			*rxp++ = readl(&priv->base->data);
			debug("rx done, status %08x, read %02x\n",
			      status, *(rxp-1));
		}
	}

	/* Terminate frame */
	if (flags & SPI_XFER_END)
		ti_qspi_cs_deactivate(priv);

	return 0;
}

/* TODO: control from sf layer to here through dm-spi */
#if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
void spi_flash_copy_mmap(void *data, void *offset, size_t len)
{
	unsigned int			addr = (unsigned int) (data);
	unsigned int			edma_slot_num = 1;

	/* Invalidate the area, so no writeback into the RAM races with DMA */
	invalidate_dcache_range(addr, addr + roundup(len, ARCH_DMA_MINALIGN));

	/* enable edma3 clocks */
	enable_edma3_clocks();

	/* Call edma3 api to do actual DMA transfer	*/
	edma3_transfer(EDMA3_BASE, edma_slot_num, data, offset, len);

	/* disable edma3 clocks */
	disable_edma3_clocks();

	*((unsigned int *)offset) += len;
}
#endif

#ifndef CONFIG_DM_SPI

static inline struct ti_qspi_priv *to_ti_qspi_priv(struct spi_slave *slave)
{
	return container_of(slave, struct ti_qspi_priv, slave);
}

int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
	return 1;
}

void spi_cs_activate(struct spi_slave *slave)
{
	/* CS handled in xfer */
	return;
}

void spi_cs_deactivate(struct spi_slave *slave)
{
	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
	ti_qspi_cs_deactivate(priv);
}

void spi_init(void)
{
	/* nothing to do */
}

static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv)
{
	u32 memval = 0;

#ifdef CONFIG_QSPI_QUAD_SUPPORT
	struct spi_slave *slave = &priv->slave;
	memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES |
			QSPI_SETUP0_NUM_D_BYTES_8_BITS |
			QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE |
			QSPI_NUM_DUMMY_BITS);
	slave->mode_rx = SPI_RX_QUAD;
#else
	memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
			QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
			QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE |
			QSPI_NUM_DUMMY_BITS;
#endif

	writel(memval, &priv->base->setup0);
}

struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
				  unsigned int max_hz, unsigned int mode)
{
	struct ti_qspi_priv *priv;

#ifdef CONFIG_AM43XX
	gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio");
	gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
#endif

	priv = spi_alloc_slave(struct ti_qspi_priv, bus, cs);
	if (!priv) {
		printf("SPI_error: Fail to allocate ti_qspi_priv\n");
		return NULL;
	}

	priv->base = (struct ti_qspi_regs *)QSPI_BASE;
	priv->mode = mode;
#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
	priv->ctrl_mod_mmap = (void *)CORE_CTRL_IO;
	priv->slave.memory_map = (void *)MMAP_START_ADDR_DRA;
#else
	priv->slave.memory_map = (void *)MMAP_START_ADDR_AM43x;
#endif

	ti_spi_set_speed(priv, max_hz);

#ifdef CONFIG_TI_SPI_MMAP
	ti_spi_setup_spi_register(priv);
#endif

	return &priv->slave;
}

void spi_free_slave(struct spi_slave *slave)
{
	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
	free(priv);
}

int spi_claim_bus(struct spi_slave *slave)
{
	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);

	debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
	__ti_qspi_set_mode(priv, priv->mode);
	return __ti_qspi_claim_bus(priv, priv->slave.cs);
}
void spi_release_bus(struct spi_slave *slave)
{
	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);

	debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
	__ti_qspi_release_bus(priv);
}

int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
	     void *din, unsigned long flags)
{
	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);

	debug("spi_xfer: bus:%i cs:%i bitlen:%i flags:%lx\n",
	      priv->slave.bus, priv->slave.cs, bitlen, flags);
	return __ti_qspi_xfer(priv, bitlen, dout, din, flags, priv->slave.cs);
}

#else /* CONFIG_DM_SPI */

static void __ti_qspi_setup_memorymap(struct ti_qspi_priv *priv,
				      struct spi_slave *slave,
				      bool enable)
{
	u32 memval;
	u32 mode = slave->mode_rx & (SPI_RX_QUAD | SPI_RX_DUAL);

	if (!enable) {
		writel(0, &priv->base->setup0);
		return;
	}

	memval = QSPI_SETUP0_NUM_A_BYTES | QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS;

	switch (mode) {
	case SPI_RX_QUAD:
		memval |= QSPI_CMD_READ_QUAD;
		memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
		memval |= QSPI_SETUP0_READ_QUAD;
		slave->mode_rx = SPI_RX_QUAD;
		break;
	case SPI_RX_DUAL:
		memval |= QSPI_CMD_READ_DUAL;
		memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
		memval |= QSPI_SETUP0_READ_DUAL;
		break;
	default:
		memval |= QSPI_CMD_READ;
		memval |= QSPI_SETUP0_NUM_D_BYTES_NO_BITS;
		memval |= QSPI_SETUP0_READ_NORMAL;
		break;
	}

	writel(memval, &priv->base->setup0);
}


static int ti_qspi_set_speed(struct udevice *bus, uint max_hz)
{
	struct ti_qspi_priv *priv = dev_get_priv(bus);

	ti_spi_set_speed(priv, max_hz);

	return 0;
}

static int ti_qspi_set_mode(struct udevice *bus, uint mode)
{
	struct ti_qspi_priv *priv = dev_get_priv(bus);
	return __ti_qspi_set_mode(priv, mode);
}

static int ti_qspi_claim_bus(struct udevice *dev)
{
	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
	struct spi_slave *slave = dev_get_parent_priv(dev);
	struct ti_qspi_priv *priv;
	struct udevice *bus;

	bus = dev->parent;
	priv = dev_get_priv(bus);

	if (slave_plat->cs > priv->num_cs) {
		debug("invalid qspi chip select\n");
		return -EINVAL;
	}

	__ti_qspi_setup_memorymap(priv, slave, true);

	return __ti_qspi_claim_bus(priv, slave_plat->cs);
}

static int ti_qspi_release_bus(struct udevice *dev)
{
	struct spi_slave *slave = dev_get_parent_priv(dev);
	struct ti_qspi_priv *priv;
	struct udevice *bus;

	bus = dev->parent;
	priv = dev_get_priv(bus);

	__ti_qspi_setup_memorymap(priv, slave, false);
	__ti_qspi_release_bus(priv);

	return 0;
}

static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
			const void *dout, void *din, unsigned long flags)
{
	struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
	struct ti_qspi_priv *priv;
	struct udevice *bus;

	bus = dev->parent;
	priv = dev_get_priv(bus);

	if (slave->cs > priv->num_cs) {
		debug("invalid qspi chip select\n");
		return -EINVAL;
	}

	return __ti_qspi_xfer(priv, bitlen, dout, din, flags, slave->cs);
}

static int ti_qspi_probe(struct udevice *bus)
{
	/* Nothing to do in probe */
	return 0;
}

static int ti_qspi_ofdata_to_platdata(struct udevice *bus)
{
	struct ti_qspi_priv *priv = dev_get_priv(bus);
	const void *blob = gd->fdt_blob;
	int node = bus->of_offset;
	fdt_addr_t addr;
	void *mmap;

	priv->base = map_physmem(dev_get_addr(bus), sizeof(struct ti_qspi_regs),
				 MAP_NOCACHE);
	priv->memory_map = map_physmem(dev_get_addr_index(bus, 1), 0,
				       MAP_NOCACHE);
	addr = dev_get_addr_index(bus, 2);
	mmap = map_physmem(dev_get_addr_index(bus, 2), 0, MAP_NOCACHE);
	priv->ctrl_mod_mmap = (addr == FDT_ADDR_T_NONE) ? NULL : mmap;

	priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
	if (priv->max_hz < 0) {
		debug("Error: Max frequency missing\n");
		return -ENODEV;
	}
	priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);

	debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__,
	      (int)priv->base, priv->max_hz);

	return 0;
}

static int ti_qspi_child_pre_probe(struct udevice *dev)
{
	struct spi_slave *slave = dev_get_parent_priv(dev);
	struct udevice *bus = dev_get_parent(dev);
	struct ti_qspi_priv *priv = dev_get_priv(bus);

	slave->memory_map = priv->memory_map;
	return 0;
}

static const struct dm_spi_ops ti_qspi_ops = {
	.claim_bus	= ti_qspi_claim_bus,
	.release_bus	= ti_qspi_release_bus,
	.xfer		= ti_qspi_xfer,
	.set_speed	= ti_qspi_set_speed,
	.set_mode	= ti_qspi_set_mode,
};

static const struct udevice_id ti_qspi_ids[] = {
	{ .compatible = "ti,dra7xxx-qspi" },
	{ .compatible = "ti,am4372-qspi" },
	{ }
};

U_BOOT_DRIVER(ti_qspi) = {
	.name	= "ti_qspi",
	.id	= UCLASS_SPI,
	.of_match = ti_qspi_ids,
	.ops	= &ti_qspi_ops,
	.ofdata_to_platdata = ti_qspi_ofdata_to_platdata,
	.priv_auto_alloc_size = sizeof(struct ti_qspi_priv),
	.probe	= ti_qspi_probe,
	.child_pre_probe = ti_qspi_child_pre_probe,
};
#endif /* CONFIG_DM_SPI */
Commit	Line	Data
1d0933ea MP	1	/*
	2	* TI QSPI driver
	3	*
	4	* Copyright (C) 2013, Texas Instruments, Incorporated
	5	*
	6	* SPDX-License-Identifier: GPL-2.0+
	7	*/
	8
	9	#include <common.h>
	10	#include <asm/io.h>
	11	#include <asm/arch/omap.h>
	12	#include <malloc.h>
	13	#include <spi.h>
106f8139	14	#include <dm.h>
570533b8 SP	15	#include <asm/gpio.h>
570533b8 SP	16	#include <asm/omap_gpio.h>
8ddd9c48 V	17	#include <asm/omap_common.h>
8ddd9c48 V	18	#include <asm/ti-common/ti-edma3.h>
1d0933ea	19
106f8139 M	20	DECLARE_GLOBAL_DATA_PTR;
106f8139 M	21
1d0933ea MP	22	/* ti qpsi register bit masks */
	23	#define QSPI_TIMEOUT 2000000
	24	#define QSPI_FCLK 192000000
	25	/* clock control */
847720c4	26	#define QSPI_CLK_EN BIT(31)
1d0933ea MP	27	#define QSPI_CLK_DIV_MAX 0xffff
	28	/* command */
	29	#define QSPI_EN_CS(n) (n << 28)
	30	#define QSPI_WLEN(n) ((n-1) << 19)
847720c4 JT	31	#define QSPI_3_PIN BIT(18)
847720c4 JT	32	#define QSPI_RD_SNGL BIT(16)
1d0933ea MP	33	#define QSPI_WR_SNGL (2 << 16)
	34	#define QSPI_INVAL (4 << 16)
	35	#define QSPI_RD_QUAD (7 << 16)
	36	/* device control */
	37	#define QSPI_DD(m, n) (m << (3 + n*8))
	38	#define QSPI_CKPHA(n) (1 << (2 + n*8))
	39	#define QSPI_CSPOL(n) (1 << (1 + n*8))
	40	#define QSPI_CKPOL(n) (1 << (n*8))
	41	/* status */
847720c4 JT	42	#define QSPI_WC BIT(1)
847720c4 JT	43	#define QSPI_BUSY BIT(0)
1d0933ea MP	44	#define QSPI_WC_BUSY (QSPI_WC \| QSPI_BUSY)
	45	#define QSPI_XFER_DONE QSPI_WC
	46	#define MM_SWITCH 0x01
ec712f49	47	#define MEM_CS(cs) ((cs + 1) << 8)
8dfd6e21	48	#define MEM_CS_UNSELECT 0xfffff8ff
570533b8 SP	49	#define MMAP_START_ADDR_DRA 0x5c000000
570533b8 SP	50	#define MMAP_START_ADDR_AM43x 0x30000000
1d0933ea MP	51	#define CORE_CTRL_IO 0x4a002558
	52
	53	#define QSPI_CMD_READ (0x3 << 0)
106f8139	54	#define QSPI_CMD_READ_DUAL (0x6b << 0)
74d49bfd	55	#define QSPI_CMD_READ_QUAD (0x6c << 0)
1d0933ea	56	#define QSPI_CMD_READ_FAST (0x0b << 0)
74d49bfd	57	#define QSPI_SETUP0_NUM_A_BYTES (0x3 << 8)
1d0933ea MP	58	#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10)
	59	#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10)
	60	#define QSPI_SETUP0_READ_NORMAL (0x0 << 12)
106f8139	61	#define QSPI_SETUP0_READ_DUAL (0x1 << 12)
1d0933ea	62	#define QSPI_SETUP0_READ_QUAD (0x3 << 12)
74d49bfd	63	#define QSPI_CMD_WRITE (0x12 << 16)
1d0933ea MP	64	#define QSPI_NUM_DUMMY_BITS (0x0 << 24)
	65
	66	/* ti qspi register set */
	67	struct ti_qspi_regs {
	68	u32 pid;
	69	u32 pad0[3];
	70	u32 sysconfig;
	71	u32 pad1[3];
	72	u32 int_stat_raw;
	73	u32 int_stat_en;
	74	u32 int_en_set;
	75	u32 int_en_ctlr;
	76	u32 intc_eoi;
	77	u32 pad2[3];
	78	u32 clk_ctrl;
	79	u32 dc;
	80	u32 cmd;
	81	u32 status;
	82	u32 data;
	83	u32 setup0;
	84	u32 setup1;
	85	u32 setup2;
	86	u32 setup3;
	87	u32 memswitch;
	88	u32 data1;
	89	u32 data2;
	90	u32 data3;
	91	};
	92
9c42558a M	93	/* ti qspi priv */
9c42558a M	94	struct ti_qspi_priv {
106f8139	95	#ifndef CONFIG_DM_SPI
1d0933ea	96	struct spi_slave slave;
106f8139 M	97	#else
	98	void *memory_map;
	99	uint max_hz;
	100	u32 num_cs;
	101	#endif
1d0933ea	102	struct ti_qspi_regs *base;
22309144	103	void *ctrl_mod_mmap;
1d0933ea MP	104	unsigned int mode;
	105	u32 cmd;
	106	u32 dc;
	107	};
	108
22309144	109	static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
1d0933ea	110	{
1d0933ea MP	111	uint clk_div;
	112
	113	debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
	114
	115	if (!hz)
	116	clk_div = 0;
	117	else
	118	clk_div = (QSPI_FCLK / hz) - 1;
	119
	120	/* disable SCLK */
9c42558a M	121	writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
9c42558a M	122	&priv->base->clk_ctrl);
1d0933ea MP	123
	124	/* assign clk_div values */
	125	if (clk_div < 0)
	126	clk_div = 0;
	127	else if (clk_div > QSPI_CLK_DIV_MAX)
	128	clk_div = QSPI_CLK_DIV_MAX;
	129
	130	/* enable SCLK */
9c42558a	131	writel(QSPI_CLK_EN \| clk_div, &priv->base->clk_ctrl);
1d0933ea MP	132	}
1d0933ea MP	133
22309144	134	static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
1d0933ea	135	{
9c42558a	136	writel(priv->cmd \| QSPI_INVAL, &priv->base->cmd);
857db48e	137	/* dummy readl to ensure bus sync */
22309144	138	readl(&priv->base->cmd);
1d0933ea MP	139	}
1d0933ea MP	140
22309144	141	static int __ti_qspi_set_mode(struct ti_qspi_priv *priv, unsigned int mode)
1d0933ea	142	{
22309144 M	143	priv->dc = 0;
	144	if (mode & SPI_CPHA)
	145	priv->dc \|= QSPI_CKPHA(0);
	146	if (mode & SPI_CPOL)
	147	priv->dc \|= QSPI_CKPOL(0);
	148	if (mode & SPI_CS_HIGH)
	149	priv->dc \|= QSPI_CSPOL(0);
1d0933ea	150
22309144	151	return 0;
1d0933ea MP	152	}
1d0933ea MP	153
22309144	154	static int __ti_qspi_claim_bus(struct ti_qspi_priv *priv, int cs)
1d0933ea	155	{
9c42558a M	156	writel(priv->dc, &priv->base->dc);
	157	writel(0, &priv->base->cmd);
	158	writel(0, &priv->base->data);
1d0933ea	159
22309144 M	160	priv->dc <<= cs * 8;
	161	writel(priv->dc, &priv->base->dc);
	162
1d0933ea MP	163	return 0;
	164	}
	165
22309144	166	static void __ti_qspi_release_bus(struct ti_qspi_priv *priv)
1d0933ea	167	{
9c42558a M	168	writel(0, &priv->base->dc);
	169	writel(0, &priv->base->cmd);
	170	writel(0, &priv->base->data);
1d0933ea MP	171	}
1d0933ea MP	172
22309144 M	173	static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
	174	{
	175	u32 val;
	176
	177	val = readl(ctrl_mod_mmap);
	178	if (enable)
	179	val \|= MEM_CS(cs);
	180	else
	181	val &= MEM_CS_UNSELECT;
	182	writel(val, ctrl_mod_mmap);
	183	}
	184
	185	static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen,
	186	const void dout, void din, unsigned long flags,
	187	u32 cs)
1d0933ea	188	{
1d0933ea MP	189	uint words = bitlen >> 3; /* fixed 8-bit word length */
	190	const uchar *txp = dout;
	191	uchar *rxp = din;
	192	uint status;
570533b8 SP	193	int timeout;
570533b8 SP	194
1d0933ea MP	195	/* Setup mmap flags */
1d0933ea MP	196	if (flags & SPI_XFER_MMAP) {
9c42558a	197	writel(MM_SWITCH, &priv->base->memswitch);
22309144 M	198	if (priv->ctrl_mod_mmap)
22309144 M	199	ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, true);
1d0933ea MP	200	return 0;
1d0933ea MP	201	} else if (flags & SPI_XFER_MMAP_END) {
9c42558a	202	writel(~MM_SWITCH, &priv->base->memswitch);
22309144 M	203	if (priv->ctrl_mod_mmap)
22309144 M	204	ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, false);
1d0933ea MP	205	return 0;
	206	}
	207
	208	if (bitlen == 0)
	209	return -1;
	210
	211	if (bitlen % 8) {
	212	debug("spi_xfer: Non byte aligned SPI transfer\n");
	213	return -1;
	214	}
	215
	216	/* Setup command reg */
9c42558a M	217	priv->cmd = 0;
9c42558a M	218	priv->cmd \|= QSPI_WLEN(8);
22309144	219	priv->cmd \|= QSPI_EN_CS(cs);
9c42558a M	220	if (priv->mode & SPI_3WIRE)
	221	priv->cmd \|= QSPI_3_PIN;
	222	priv->cmd \|= 0xfff;
1d0933ea	223
bb7cd0dd SP	224	/* FIXME: This delay is required for successfull
	225	* completion of read/write/erase. Once its root
	226	* caused, it will be remove from the driver.
	227	*/
	228	#ifdef CONFIG_AM43XX
	229	udelay(100);
	230	#endif
1d0933ea MP	231	while (words--) {
	232	if (txp) {
	233	debug("tx cmd %08x dc %08x data %02x\n",
9c42558a M	234	priv->cmd \| QSPI_WR_SNGL, priv->dc, *txp);
	235	writel(*txp++, &priv->base->data);
	236	writel(priv->cmd \| QSPI_WR_SNGL,
	237	&priv->base->cmd);
	238	status = readl(&priv->base->status);
1d0933ea MP	239	timeout = QSPI_TIMEOUT;
	240	while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
	241	if (--timeout < 0) {
	242	printf("spi_xfer: TX timeout!\n");
	243	return -1;
	244	}
9c42558a	245	status = readl(&priv->base->status);
1d0933ea MP	246	}
	247	debug("tx done, status %08x\n", status);
	248	}
	249	if (rxp) {
1d0933ea	250	debug("rx cmd %08x dc %08x\n",
69eeefaa	251	((u32)(priv->cmd \| QSPI_RD_SNGL)), priv->dc);
b545a98f PS	252	#ifdef CONFIG_DRA7XX
	253	udelay(500);
	254	#endif
69eeefaa	255	writel(priv->cmd \| QSPI_RD_SNGL, &priv->base->cmd);
9c42558a	256	status = readl(&priv->base->status);
1d0933ea MP	257	timeout = QSPI_TIMEOUT;
	258	while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
	259	if (--timeout < 0) {
	260	printf("spi_xfer: RX timeout!\n");
	261	return -1;
	262	}
9c42558a	263	status = readl(&priv->base->status);
1d0933ea	264	}
9c42558a	265	*rxp++ = readl(&priv->base->data);
1d0933ea MP	266	debug("rx done, status %08x, read %02x\n",
	267	status, *(rxp-1));
	268	}
	269	}
	270
	271	/* Terminate frame */
	272	if (flags & SPI_XFER_END)
22309144	273	ti_qspi_cs_deactivate(priv);
1d0933ea MP	274
	275	return 0;
	276	}
8ddd9c48 V	277
8ddd9c48 V	278	/* TODO: control from sf layer to here through dm-spi */
518b0afc	279	#if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
8ddd9c48 V	280	void spi_flash_copy_mmap(void data, void offset, size_t len)
	281	{
	282	unsigned int addr = (unsigned int) (data);
	283	unsigned int edma_slot_num = 1;
	284
	285	/* Invalidate the area, so no writeback into the RAM races with DMA */
	286	invalidate_dcache_range(addr, addr + roundup(len, ARCH_DMA_MINALIGN));
	287
	288	/* enable edma3 clocks */
	289	enable_edma3_clocks();
	290
	291	/* Call edma3 api to do actual DMA transfer */
	292	edma3_transfer(EDMA3_BASE, edma_slot_num, data, offset, len);
	293
	294	/* disable edma3 clocks */
	295	disable_edma3_clocks();
	296
	297	((unsigned int )offset) += len;
	298	}
	299	#endif
22309144	300
106f8139 M	301	#ifndef CONFIG_DM_SPI
106f8139 M	302
22309144 M	303	static inline struct ti_qspi_priv to_ti_qspi_priv(struct spi_slave slave)
	304	{
	305	return container_of(slave, struct ti_qspi_priv, slave);
	306	}
	307
	308	int spi_cs_is_valid(unsigned int bus, unsigned int cs)
	309	{
	310	return 1;
	311	}
	312
	313	void spi_cs_activate(struct spi_slave *slave)
	314	{
	315	/* CS handled in xfer */
	316	return;
	317	}
	318
	319	void spi_cs_deactivate(struct spi_slave *slave)
	320	{
	321	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
	322	ti_qspi_cs_deactivate(priv);
	323	}
	324
	325	void spi_init(void)
	326	{
	327	/* nothing to do */
	328	}
	329
	330	static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv)
	331	{
	332	u32 memval = 0;
	333
	334	#ifdef CONFIG_QSPI_QUAD_SUPPORT
	335	struct spi_slave *slave = &priv->slave;
	336	memval \|= (QSPI_CMD_READ_QUAD \| QSPI_SETUP0_NUM_A_BYTES \|
	337	QSPI_SETUP0_NUM_D_BYTES_8_BITS \|
	338	QSPI_SETUP0_READ_QUAD \| QSPI_CMD_WRITE \|
	339	QSPI_NUM_DUMMY_BITS);
	340	slave->mode_rx = SPI_RX_QUAD;
	341	#else
	342	memval \|= QSPI_CMD_READ \| QSPI_SETUP0_NUM_A_BYTES \|
	343	QSPI_SETUP0_NUM_D_BYTES_NO_BITS \|
	344	QSPI_SETUP0_READ_NORMAL \| QSPI_CMD_WRITE \|
	345	QSPI_NUM_DUMMY_BITS;
	346	#endif
	347
	348	writel(memval, &priv->base->setup0);
	349	}
	350
	351	struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
	352	unsigned int max_hz, unsigned int mode)
	353	{
	354	struct ti_qspi_priv *priv;
	355
	356	#ifdef CONFIG_AM43XX
	357	gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio");
	358	gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
	359	#endif
	360
	361	priv = spi_alloc_slave(struct ti_qspi_priv, bus, cs);
	362	if (!priv) {
	363	printf("SPI_error: Fail to allocate ti_qspi_priv\n");
	364	return NULL;
	365	}
	366
367	priv->base = (struct ti_qspi_regs *)QSPI_BASE;
368	priv->mode = mode;
369	#if defined(CONFIG_DRA7XX) \|\| defined(CONFIG_AM57XX)
370	priv->ctrl_mod_mmap = (void *)CORE_CTRL_IO;
371	priv->slave.memory_map = (void *)MMAP_START_ADDR_DRA;
372	#else
373	priv->slave.memory_map = (void *)MMAP_START_ADDR_AM43x;
374	#endif
375
376	ti_spi_set_speed(priv, max_hz);
377
378	#ifdef CONFIG_TI_SPI_MMAP
379	ti_spi_setup_spi_register(priv);
380	#endif
381
382	return &priv->slave;
383	}
384
385	void spi_free_slave(struct spi_slave *slave)
386	{
387	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
388	free(priv);
389	}
390
391	int spi_claim_bus(struct spi_slave *slave)
392	{
393	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
394
395	debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
396	__ti_qspi_set_mode(priv, priv->mode);
397	return __ti_qspi_claim_bus(priv, priv->slave.cs);
398	}
399	void spi_release_bus(struct spi_slave *slave)
400	{
401	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
402
403	debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
404	__ti_qspi_release_bus(priv);
405	}
406
407	int spi_xfer(struct spi_slave slave, unsigned int bitlen, const void dout,
408	void *din, unsigned long flags)
409	{
410	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
411
412	debug("spi_xfer: bus:%i cs:%i bitlen:%i flags:%lx\n",
413	priv->slave.bus, priv->slave.cs, bitlen, flags);
414	return __ti_qspi_xfer(priv, bitlen, dout, din, flags, priv->slave.cs);
415	}
106f8139 M	416
	417	#else /* CONFIG_DM_SPI */
	418
	419	static void __ti_qspi_setup_memorymap(struct ti_qspi_priv *priv,
	420	struct spi_slave *slave,
	421	bool enable)
	422	{
	423	u32 memval;
	424	u32 mode = slave->mode_rx & (SPI_RX_QUAD \| SPI_RX_DUAL);
	425
	426	if (!enable) {
	427	writel(0, &priv->base->setup0);
	428	return;
	429	}
	430
	431	memval = QSPI_SETUP0_NUM_A_BYTES \| QSPI_CMD_WRITE \| QSPI_NUM_DUMMY_BITS;
	432
	433	switch (mode) {
	434	case SPI_RX_QUAD:
	435	memval \|= QSPI_CMD_READ_QUAD;
	436	memval \|= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
	437	memval \|= QSPI_SETUP0_READ_QUAD;
	438	slave->mode_rx = SPI_RX_QUAD;
	439	break;
	440	case SPI_RX_DUAL:
	441	memval \|= QSPI_CMD_READ_DUAL;
	442	memval \|= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
	443	memval \|= QSPI_SETUP0_READ_DUAL;
	444	break;
	445	default:
	446	memval \|= QSPI_CMD_READ;
	447	memval \|= QSPI_SETUP0_NUM_D_BYTES_NO_BITS;
	448	memval \|= QSPI_SETUP0_READ_NORMAL;
	449	break;
	450	}
	451
	452	writel(memval, &priv->base->setup0);
	453	}
	454
	455
	456	static int ti_qspi_set_speed(struct udevice *bus, uint max_hz)
	457	{
	458	struct ti_qspi_priv *priv = dev_get_priv(bus);
	459
	460	ti_spi_set_speed(priv, max_hz);
	461
	462	return 0;
	463	}
	464
	465	static int ti_qspi_set_mode(struct udevice *bus, uint mode)
	466	{
	467	struct ti_qspi_priv *priv = dev_get_priv(bus);
	468	return __ti_qspi_set_mode(priv, mode);
	469	}
	470
	471	static int ti_qspi_claim_bus(struct udevice *dev)
	472	{
	473	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
	474	struct spi_slave *slave = dev_get_parent_priv(dev);
	475	struct ti_qspi_priv *priv;
	476	struct udevice *bus;
	477
	478	bus = dev->parent;
	479	priv = dev_get_priv(bus);
480
481	if (slave_plat->cs > priv->num_cs) {
482	debug("invalid qspi chip select\n");
483	return -EINVAL;
484	}
485
486	__ti_qspi_setup_memorymap(priv, slave, true);
487
488	return __ti_qspi_claim_bus(priv, slave_plat->cs);
489	}
490
491	static int ti_qspi_release_bus(struct udevice *dev)
492	{
493	struct spi_slave *slave = dev_get_parent_priv(dev);
494	struct ti_qspi_priv *priv;
495	struct udevice *bus;
496
497	bus = dev->parent;
498	priv = dev_get_priv(bus);
499
500	__ti_qspi_setup_memorymap(priv, slave, false);
501	__ti_qspi_release_bus(priv);
502
503	return 0;
504	}
505
506	static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
507	const void dout, void din, unsigned long flags)
508	{
509	struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
510	struct ti_qspi_priv *priv;
511	struct udevice *bus;
512
513	bus = dev->parent;
514	priv = dev_get_priv(bus);
515
516	if (slave->cs > priv->num_cs) {
517	debug("invalid qspi chip select\n");
518	return -EINVAL;
519	}
520
521	return __ti_qspi_xfer(priv, bitlen, dout, din, flags, slave->cs);
522	}
523
524	static int ti_qspi_probe(struct udevice *bus)
525	{
526	/* Nothing to do in probe */
527	return 0;
528	}
529
530	static int ti_qspi_ofdata_to_platdata(struct udevice *bus)
531	{
532	struct ti_qspi_priv *priv = dev_get_priv(bus);
533	const void *blob = gd->fdt_blob;
534	int node = bus->of_offset;
535	fdt_addr_t addr;
e6601df8	536	void *mmap;
106f8139	537
e6601df8 LV	538	priv->base = map_physmem(dev_get_addr(bus), sizeof(struct ti_qspi_regs),
	539	MAP_NOCACHE);
	540	priv->memory_map = map_physmem(dev_get_addr_index(bus, 1), 0,
	541	MAP_NOCACHE);
106f8139	542	addr = dev_get_addr_index(bus, 2);
e6601df8 LV	543	mmap = map_physmem(dev_get_addr_index(bus, 2), 0, MAP_NOCACHE);
e6601df8 LV	544	priv->ctrl_mod_mmap = (addr == FDT_ADDR_T_NONE) ? NULL : mmap;
106f8139 M	545
	546	priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
	547	if (priv->max_hz < 0) {
	548	debug("Error: Max frequency missing\n");
	549	return -ENODEV;
	550	}
	551	priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
	552
	553	debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__,
	554	(int)priv->base, priv->max_hz);
	555
	556	return 0;
	557	}
	558
	559	static int ti_qspi_child_pre_probe(struct udevice *dev)
	560	{
	561	struct spi_slave *slave = dev_get_parent_priv(dev);
	562	struct udevice *bus = dev_get_parent(dev);
	563	struct ti_qspi_priv *priv = dev_get_priv(bus);
	564
	565	slave->memory_map = priv->memory_map;
	566	return 0;
	567	}
	568
	569	static const struct dm_spi_ops ti_qspi_ops = {
	570	.claim_bus = ti_qspi_claim_bus,
	571	.release_bus = ti_qspi_release_bus,
	572	.xfer = ti_qspi_xfer,
	573	.set_speed = ti_qspi_set_speed,
	574	.set_mode = ti_qspi_set_mode,
	575	};
	576
	577	static const struct udevice_id ti_qspi_ids[] = {
	578	{ .compatible = "ti,dra7xxx-qspi" },
	579	{ .compatible = "ti,am4372-qspi" },
	580	{ }
	581	};
	582
	583	U_BOOT_DRIVER(ti_qspi) = {
	584	.name = "ti_qspi",
	585	.id = UCLASS_SPI,
	586	.of_match = ti_qspi_ids,
	587	.ops = &ti_qspi_ops,
	588	.ofdata_to_platdata = ti_qspi_ofdata_to_platdata,
	589	.priv_auto_alloc_size = sizeof(struct ti_qspi_priv),
	590	.probe = ti_qspi_probe,
	591	.child_pre_probe = ti_qspi_child_pre_probe,
	592	};
	593	#endif /* CONFIG_DM_SPI */