[thirdparty/u-boot.git] / drivers / spi / xilinx_spi.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Xilinx SPI driver
 *
 * Supports 8 bit SPI transfers only, with or w/o FIFO
 *
 * Based on bfin_spi.c, by way of altera_spi.c
 * Copyright (c) 2015 Jagan Teki <jteki@openedev.com>
 * Copyright (c) 2012 Stephan Linz <linz@li-pro.net>
 * Copyright (c) 2010 Graeme Smecher <graeme.smecher@mail.mcgill.ca>
 * Copyright (c) 2010 Thomas Chou <thomas@wytron.com.tw>
 * Copyright (c) 2005-2008 Analog Devices Inc.
 */

#include <config.h>
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <malloc.h>
#include <spi.h>
#include <asm/io.h>
#include <wait_bit.h>

/*
 * [0]: http://www.xilinx.com/support/documentation
 *
 * Xilinx SPI Register Definitions
 * [1]:	[0]/ip_documentation/xps_spi.pdf
 *	page 8, Register Descriptions
 * [2]:	[0]/ip_documentation/axi_spi_ds742.pdf
 *	page 7, Register Overview Table
 */

/* SPI Control Register (spicr), [1] p9, [2] p8 */
#define SPICR_LSB_FIRST		BIT(9)
#define SPICR_MASTER_INHIBIT	BIT(8)
#define SPICR_MANUAL_SS		BIT(7)
#define SPICR_RXFIFO_RESEST	BIT(6)
#define SPICR_TXFIFO_RESEST	BIT(5)
#define SPICR_CPHA		BIT(4)
#define SPICR_CPOL		BIT(3)
#define SPICR_MASTER_MODE	BIT(2)
#define SPICR_SPE		BIT(1)
#define SPICR_LOOP		BIT(0)

/* SPI Status Register (spisr), [1] p11, [2] p10 */
#define SPISR_SLAVE_MODE_SELECT	BIT(5)
#define SPISR_MODF		BIT(4)
#define SPISR_TX_FULL		BIT(3)
#define SPISR_TX_EMPTY		BIT(2)
#define SPISR_RX_FULL		BIT(1)
#define SPISR_RX_EMPTY		BIT(0)

/* SPI Data Transmit Register (spidtr), [1] p12, [2] p12 */
#define SPIDTR_8BIT_MASK	GENMASK(7, 0)
#define SPIDTR_16BIT_MASK	GENMASK(15, 0)
#define SPIDTR_32BIT_MASK	GENMASK(31, 0)

/* SPI Data Receive Register (spidrr), [1] p12, [2] p12 */
#define SPIDRR_8BIT_MASK	GENMASK(7, 0)
#define SPIDRR_16BIT_MASK	GENMASK(15, 0)
#define SPIDRR_32BIT_MASK	GENMASK(31, 0)

/* SPI Slave Select Register (spissr), [1] p13, [2] p13 */
#define SPISSR_MASK(cs)		(1 << (cs))
#define SPISSR_ACT(cs)		~SPISSR_MASK(cs)
#define SPISSR_OFF		~0UL

/* SPI Software Reset Register (ssr) */
#define SPISSR_RESET_VALUE	0x0a

#define XILSPI_MAX_XFER_BITS	8
#define XILSPI_SPICR_DFLT_ON	(SPICR_MANUAL_SS | SPICR_MASTER_MODE | \
				SPICR_SPE)
#define XILSPI_SPICR_DFLT_OFF	(SPICR_MASTER_INHIBIT | SPICR_MANUAL_SS)

#ifndef CONFIG_XILINX_SPI_IDLE_VAL
#define CONFIG_XILINX_SPI_IDLE_VAL	GENMASK(7, 0)
#endif

#define XILINX_SPISR_TIMEOUT	10000 /* in milliseconds */

/* xilinx spi register set */
struct xilinx_spi_regs {
	u32 __space0__[7];
	u32 dgier;	/* Device Global Interrupt Enable Register (DGIER) */
	u32 ipisr;	/* IP Interrupt Status Register (IPISR) */
	u32 __space1__;
	u32 ipier;	/* IP Interrupt Enable Register (IPIER) */
	u32 __space2__[5];
	u32 srr;	/* Softare Reset Register (SRR) */
	u32 __space3__[7];
	u32 spicr;	/* SPI Control Register (SPICR) */
	u32 spisr;	/* SPI Status Register (SPISR) */
	u32 spidtr;	/* SPI Data Transmit Register (SPIDTR) */
	u32 spidrr;	/* SPI Data Receive Register (SPIDRR) */
	u32 spissr;	/* SPI Slave Select Register (SPISSR) */
	u32 spitfor;	/* SPI Transmit FIFO Occupancy Register (SPITFOR) */
	u32 spirfor;	/* SPI Receive FIFO Occupancy Register (SPIRFOR) */
};

/* xilinx spi priv */
struct xilinx_spi_priv {
	struct xilinx_spi_regs *regs;
	unsigned int freq;
	unsigned int mode;
	unsigned int fifo_depth;
	u8 startup;
};

static int xilinx_spi_probe(struct udevice *bus)
{
	struct xilinx_spi_priv *priv = dev_get_priv(bus);
	struct xilinx_spi_regs *regs = priv->regs;

	priv->regs = (struct xilinx_spi_regs *)dev_read_addr(bus);

	priv->fifo_depth = dev_read_u32_default(bus, "fifo-size", 0);

	writel(SPISSR_RESET_VALUE, &regs->srr);

	return 0;
}

static void spi_cs_activate(struct udevice *dev, uint cs)
{
	struct udevice *bus = dev_get_parent(dev);
	struct xilinx_spi_priv *priv = dev_get_priv(bus);
	struct xilinx_spi_regs *regs = priv->regs;

	writel(SPISSR_ACT(cs), &regs->spissr);
}

static void spi_cs_deactivate(struct udevice *dev)
{
	struct udevice *bus = dev_get_parent(dev);
	struct xilinx_spi_priv *priv = dev_get_priv(bus);
	struct xilinx_spi_regs *regs = priv->regs;

	writel(SPISSR_OFF, &regs->spissr);
}

static int xilinx_spi_claim_bus(struct udevice *dev)
{
	struct udevice *bus = dev_get_parent(dev);
	struct xilinx_spi_priv *priv = dev_get_priv(bus);
	struct xilinx_spi_regs *regs = priv->regs;

	writel(SPISSR_OFF, &regs->spissr);
	writel(XILSPI_SPICR_DFLT_ON, &regs->spicr);

	return 0;
}

static int xilinx_spi_release_bus(struct udevice *dev)
{
	struct udevice *bus = dev_get_parent(dev);
	struct xilinx_spi_priv *priv = dev_get_priv(bus);
	struct xilinx_spi_regs *regs = priv->regs;

	writel(SPISSR_OFF, &regs->spissr);
	writel(XILSPI_SPICR_DFLT_OFF, &regs->spicr);

	return 0;
}

static u32 xilinx_spi_fill_txfifo(struct udevice *bus, const u8 *txp,
				  u32 txbytes)
{
	struct xilinx_spi_priv *priv = dev_get_priv(bus);
	struct xilinx_spi_regs *regs = priv->regs;
	unsigned char d;
	u32 i = 0;

	while (txbytes && !(readl(&regs->spisr) & SPISR_TX_FULL) &&
	       i < priv->fifo_depth) {
		d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL;
		debug("spi_xfer: tx:%x ", d);
		/* write out and wait for processing (receive data) */
		writel(d & SPIDTR_8BIT_MASK, &regs->spidtr);
		txbytes--;
		i++;
	}

	return i;
}

static u32 xilinx_spi_read_rxfifo(struct udevice *bus, u8 *rxp, u32 rxbytes)
{
	struct xilinx_spi_priv *priv = dev_get_priv(bus);
	struct xilinx_spi_regs *regs = priv->regs;
	unsigned char d;
	unsigned int i = 0;

	while (rxbytes && !(readl(&regs->spisr) & SPISR_RX_EMPTY)) {
		d = readl(&regs->spidrr) & SPIDRR_8BIT_MASK;
		if (rxp)
			*rxp++ = d;
		debug("spi_xfer: rx:%x\n", d);
		rxbytes--;
		i++;
	}
	debug("Rx_done\n");

	return i;
}

static void xilinx_spi_startup_block(struct udevice *dev, unsigned int bytes,
				     const void *dout, void *din)
{
	struct udevice *bus = dev_get_parent(dev);
	struct xilinx_spi_priv *priv = dev_get_priv(bus);
	struct xilinx_spi_regs *regs = priv->regs;
	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
	const unsigned char *txp = dout;
	unsigned char *rxp = din;
	u32 reg, count;
	u32 txbytes = bytes;
	u32 rxbytes = bytes;

	/*
	 * This loop runs two times. First time to send the command.
	 * Second time to transfer data. After transferring data,
	 * it sets txp to the initial value for the normal operation.
	 */
	for ( ; priv->startup < 2; priv->startup++) {
		count = xilinx_spi_fill_txfifo(bus, txp, txbytes);
		reg = readl(&regs->spicr) & ~SPICR_MASTER_INHIBIT;
		writel(reg, &regs->spicr);
		count = xilinx_spi_read_rxfifo(bus, rxp, rxbytes);
		txp = din;

		if (priv->startup) {
			spi_cs_deactivate(dev);
			spi_cs_activate(dev, slave_plat->cs);
			txp = dout;
		}
	}
}

static int xilinx_spi_xfer(struct udevice *dev, unsigned int bitlen,
			    const void *dout, void *din, unsigned long flags)
{
	struct udevice *bus = dev_get_parent(dev);
	struct xilinx_spi_priv *priv = dev_get_priv(bus);
	struct xilinx_spi_regs *regs = priv->regs;
	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
	/* assume spi core configured to do 8 bit transfers */
	unsigned int bytes = bitlen / XILSPI_MAX_XFER_BITS;
	const unsigned char *txp = dout;
	unsigned char *rxp = din;
	u32 txbytes = bytes;
	u32 rxbytes = bytes;
	u32 reg, count, timeout;
	int ret;

	debug("spi_xfer: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n",
	      bus->seq, slave_plat->cs, bitlen, bytes, flags);

	if (bitlen == 0)
		goto done;

	if (bitlen % XILSPI_MAX_XFER_BITS) {
		printf("XILSPI warning: Not a multiple of %d bits\n",
		       XILSPI_MAX_XFER_BITS);
		flags |= SPI_XFER_END;
		goto done;
	}

	if (flags & SPI_XFER_BEGIN)
		spi_cs_activate(dev, slave_plat->cs);

	/*
	 * This is the work around for the startup block issue in
	 * the spi controller. SPI clock is passing through STARTUP
	 * block to FLASH. STARTUP block don't provide clock as soon
	 * as QSPI provides command. So first command fails.
	 */
	xilinx_spi_startup_block(dev, bytes, dout, din);

	while (txbytes && rxbytes) {
		count = xilinx_spi_fill_txfifo(bus, txp, txbytes);
		reg = readl(&regs->spicr) & ~SPICR_MASTER_INHIBIT;
		writel(reg, &regs->spicr);
		txbytes -= count;
		if (txp)
			txp += count;

		ret = wait_for_bit_le32(&regs->spisr, SPISR_TX_EMPTY, true,
					XILINX_SPISR_TIMEOUT, false);
		if (ret < 0) {
			printf("XILSPI error: Xfer timeout\n");
			return ret;
		}

		debug("txbytes:0x%x,txp:0x%p\n", txbytes, txp);
		count = xilinx_spi_read_rxfifo(bus, rxp, rxbytes);
		rxbytes -= count;
		if (rxp)
			rxp += count;
		debug("rxbytes:0x%x rxp:0x%p\n", rxbytes, rxp);
	}

 done:
	if (flags & SPI_XFER_END)
		spi_cs_deactivate(dev);

	return 0;
}

static int xilinx_spi_set_speed(struct udevice *bus, uint speed)
{
	struct xilinx_spi_priv *priv = dev_get_priv(bus);

	priv->freq = speed;

	debug("xilinx_spi_set_speed: regs=%p, speed=%d\n", priv->regs,
	      priv->freq);

	return 0;
}

static int xilinx_spi_set_mode(struct udevice *bus, uint mode)
{
	struct xilinx_spi_priv *priv = dev_get_priv(bus);
	struct xilinx_spi_regs *regs = priv->regs;
	uint32_t spicr;

	spicr = readl(&regs->spicr);
	if (mode & SPI_LSB_FIRST)
		spicr |= SPICR_LSB_FIRST;
	if (mode & SPI_CPHA)
		spicr |= SPICR_CPHA;
	if (mode & SPI_CPOL)
		spicr |= SPICR_CPOL;
	if (mode & SPI_LOOP)
		spicr |= SPICR_LOOP;

	writel(spicr, &regs->spicr);
	priv->mode = mode;

	debug("xilinx_spi_set_mode: regs=%p, mode=%d\n", priv->regs,
	      priv->mode);

	return 0;
}

static const struct dm_spi_ops xilinx_spi_ops = {
	.claim_bus	= xilinx_spi_claim_bus,
	.release_bus	= xilinx_spi_release_bus,
	.xfer		= xilinx_spi_xfer,
	.set_speed	= xilinx_spi_set_speed,
	.set_mode	= xilinx_spi_set_mode,
};

static const struct udevice_id xilinx_spi_ids[] = {
	{ .compatible = "xlnx,xps-spi-2.00.a" },
	{ .compatible = "xlnx,xps-spi-2.00.b" },
	{ }
};

U_BOOT_DRIVER(xilinx_spi) = {
	.name	= "xilinx_spi",
	.id	= UCLASS_SPI,
	.of_match = xilinx_spi_ids,
	.ops	= &xilinx_spi_ops,
	.priv_auto_alloc_size = sizeof(struct xilinx_spi_priv),
	.probe	= xilinx_spi_probe,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
09aac75e SL	2	/*
	3	* Xilinx SPI driver
	4	*
a7b6ef05	5	* Supports 8 bit SPI transfers only, with or w/o FIFO
09aac75e	6	*
a7b6ef05	7	* Based on bfin_spi.c, by way of altera_spi.c
9505c36e	8	* Copyright (c) 2015 Jagan Teki <jteki@openedev.com>
09aac75e	9	* Copyright (c) 2012 Stephan Linz <linz@li-pro.net>
a7b6ef05 JT	10	* Copyright (c) 2010 Graeme Smecher <graeme.smecher@mail.mcgill.ca>
	11	* Copyright (c) 2010 Thomas Chou <thomas@wytron.com.tw>
	12	* Copyright (c) 2005-2008 Analog Devices Inc.
09aac75e	13	*/
a7b6ef05	14
09aac75e SL	15	#include <config.h>
09aac75e SL	16	#include <common.h>
9505c36e JT	17	#include <dm.h>
9505c36e JT	18	#include <errno.h>
09aac75e SL	19	#include <malloc.h>
09aac75e SL	20	#include <spi.h>
5f24d123	21	#include <asm/io.h>
0c0de58f	22	#include <wait_bit.h>
09aac75e	23
f93542a8	24	/*
a7b6ef05	25	* [0]: http://www.xilinx.com/support/documentation
f93542a8	26	*
a7b6ef05	27	* Xilinx SPI Register Definitions
f93542a8 JT	28	* [1]: [0]/ip_documentation/xps_spi.pdf
	29	* page 8, Register Descriptions
	30	* [2]: [0]/ip_documentation/axi_spi_ds742.pdf
	31	* page 7, Register Overview Table
	32	*/
f93542a8 JT	33
f93542a8 JT	34	/* SPI Control Register (spicr), [1] p9, [2] p8 */
5ea392d4 JT	35	#define SPICR_LSB_FIRST BIT(9)
	36	#define SPICR_MASTER_INHIBIT BIT(8)
	37	#define SPICR_MANUAL_SS BIT(7)
	38	#define SPICR_RXFIFO_RESEST BIT(6)
	39	#define SPICR_TXFIFO_RESEST BIT(5)
	40	#define SPICR_CPHA BIT(4)
	41	#define SPICR_CPOL BIT(3)
	42	#define SPICR_MASTER_MODE BIT(2)
	43	#define SPICR_SPE BIT(1)
	44	#define SPICR_LOOP BIT(0)
f93542a8 JT	45
f93542a8 JT	46	/* SPI Status Register (spisr), [1] p11, [2] p10 */
5ea392d4 JT	47	#define SPISR_SLAVE_MODE_SELECT BIT(5)
	48	#define SPISR_MODF BIT(4)
	49	#define SPISR_TX_FULL BIT(3)
	50	#define SPISR_TX_EMPTY BIT(2)
	51	#define SPISR_RX_FULL BIT(1)
	52	#define SPISR_RX_EMPTY BIT(0)
f93542a8 JT	53
f93542a8 JT	54	/* SPI Data Transmit Register (spidtr), [1] p12, [2] p12 */
d2436301 JT	55	#define SPIDTR_8BIT_MASK GENMASK(7, 0)
	56	#define SPIDTR_16BIT_MASK GENMASK(15, 0)
	57	#define SPIDTR_32BIT_MASK GENMASK(31, 0)
f93542a8 JT	58
f93542a8 JT	59	/* SPI Data Receive Register (spidrr), [1] p12, [2] p12 */
d2436301 JT	60	#define SPIDRR_8BIT_MASK GENMASK(7, 0)
	61	#define SPIDRR_16BIT_MASK GENMASK(15, 0)
	62	#define SPIDRR_32BIT_MASK GENMASK(31, 0)
f93542a8 JT	63
	64	/* SPI Slave Select Register (spissr), [1] p13, [2] p13 */
	65	#define SPISSR_MASK(cs) (1 << (cs))
	66	#define SPISSR_ACT(cs) ~SPISSR_MASK(cs)
	67	#define SPISSR_OFF ~0UL
	68
f93542a8 JT	69	/* SPI Software Reset Register (ssr) */
	70	#define SPISSR_RESET_VALUE 0x0a
	71
a7b6ef05 JT	72	#define XILSPI_MAX_XFER_BITS 8
	73	#define XILSPI_SPICR_DFLT_ON (SPICR_MANUAL_SS \| SPICR_MASTER_MODE \| \
	74	SPICR_SPE)
	75	#define XILSPI_SPICR_DFLT_OFF (SPICR_MASTER_INHIBIT \| SPICR_MANUAL_SS)
	76
	77	#ifndef CONFIG_XILINX_SPI_IDLE_VAL
d2436301	78	#define CONFIG_XILINX_SPI_IDLE_VAL GENMASK(7, 0)
a7b6ef05 JT	79	#endif
a7b6ef05 JT	80
0c0de58f VK	81	#define XILINX_SPISR_TIMEOUT 10000 /* in milliseconds */
0c0de58f VK	82
a7b6ef05	83	/* xilinx spi register set */
9505c36e	84	struct xilinx_spi_regs {
a7b6ef05 JT	85	u32 __space0__[7];
	86	u32 dgier; /* Device Global Interrupt Enable Register (DGIER) */
	87	u32 ipisr; /* IP Interrupt Status Register (IPISR) */
	88	u32 __space1__;
	89	u32 ipier; /* IP Interrupt Enable Register (IPIER) */
	90	u32 __space2__[5];
	91	u32 srr; /* Softare Reset Register (SRR) */
	92	u32 __space3__[7];
	93	u32 spicr; /* SPI Control Register (SPICR) */
	94	u32 spisr; /* SPI Status Register (SPISR) */
	95	u32 spidtr; /* SPI Data Transmit Register (SPIDTR) */
	96	u32 spidrr; /* SPI Data Receive Register (SPIDRR) */
	97	u32 spissr; /* SPI Slave Select Register (SPISSR) */
	98	u32 spitfor; /* SPI Transmit FIFO Occupancy Register (SPITFOR) */
	99	u32 spirfor; /* SPI Receive FIFO Occupancy Register (SPIRFOR) */
	100	};
	101
9505c36e JT	102	/* xilinx spi priv */
	103	struct xilinx_spi_priv {
	104	struct xilinx_spi_regs *regs;
f93542a8 JT	105	unsigned int freq;
f93542a8 JT	106	unsigned int mode;
0c0de58f	107	unsigned int fifo_depth;
83ce6469	108	u8 startup;
f93542a8 JT	109	};
f93542a8 JT	110
9505c36e	111	static int xilinx_spi_probe(struct udevice *bus)
09aac75e	112	{
9505c36e JT	113	struct xilinx_spi_priv *priv = dev_get_priv(bus);
9505c36e JT	114	struct xilinx_spi_regs *regs = priv->regs;
09aac75e	115
6e9d9fcb	116	priv->regs = (struct xilinx_spi_regs *)dev_read_addr(bus);
09aac75e	117
6e9d9fcb	118	priv->fifo_depth = dev_read_u32_default(bus, "fifo-size", 0);
0c0de58f	119
9505c36e	120	writel(SPISSR_RESET_VALUE, &regs->srr);
09aac75e	121
9505c36e	122	return 0;
09aac75e SL	123	}
09aac75e SL	124
9505c36e	125	static void spi_cs_activate(struct udevice *dev, uint cs)
09aac75e	126	{
9505c36e JT	127	struct udevice *bus = dev_get_parent(dev);
	128	struct xilinx_spi_priv *priv = dev_get_priv(bus);
	129	struct xilinx_spi_regs *regs = priv->regs;
09aac75e	130
9505c36e	131	writel(SPISSR_ACT(cs), &regs->spissr);
09aac75e SL	132	}
09aac75e SL	133
9505c36e	134	static void spi_cs_deactivate(struct udevice *dev)
09aac75e	135	{
9505c36e JT	136	struct udevice *bus = dev_get_parent(dev);
	137	struct xilinx_spi_priv *priv = dev_get_priv(bus);
	138	struct xilinx_spi_regs *regs = priv->regs;
09aac75e	139
9505c36e	140	writel(SPISSR_OFF, &regs->spissr);
09aac75e SL	141	}
09aac75e SL	142
9505c36e	143	static int xilinx_spi_claim_bus(struct udevice *dev)
09aac75e	144	{
9505c36e JT	145	struct udevice *bus = dev_get_parent(dev);
	146	struct xilinx_spi_priv *priv = dev_get_priv(bus);
	147	struct xilinx_spi_regs *regs = priv->regs;
09aac75e	148
9505c36e JT	149	writel(SPISSR_OFF, &regs->spissr);
9505c36e JT	150	writel(XILSPI_SPICR_DFLT_ON, &regs->spicr);
09aac75e	151
09aac75e SL	152	return 0;
	153	}
	154
9505c36e	155	static int xilinx_spi_release_bus(struct udevice *dev)
09aac75e	156	{
9505c36e JT	157	struct udevice *bus = dev_get_parent(dev);
	158	struct xilinx_spi_priv *priv = dev_get_priv(bus);
	159	struct xilinx_spi_regs *regs = priv->regs;
09aac75e	160
9505c36e JT	161	writel(SPISSR_OFF, &regs->spissr);
	162	writel(XILSPI_SPICR_DFLT_OFF, &regs->spicr);
	163
	164	return 0;
09aac75e SL	165	}
09aac75e SL	166
0c0de58f VK	167	static u32 xilinx_spi_fill_txfifo(struct udevice bus, const u8 txp,
	168	u32 txbytes)
	169	{
	170	struct xilinx_spi_priv *priv = dev_get_priv(bus);
	171	struct xilinx_spi_regs *regs = priv->regs;
	172	unsigned char d;
	173	u32 i = 0;
	174
	175	while (txbytes && !(readl(&regs->spisr) & SPISR_TX_FULL) &&
	176	i < priv->fifo_depth) {
	177	d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL;
	178	debug("spi_xfer: tx:%x ", d);
	179	/* write out and wait for processing (receive data) */
	180	writel(d & SPIDTR_8BIT_MASK, &regs->spidtr);
	181	txbytes--;
	182	i++;
	183	}
	184
	185	return i;
	186	}
	187
	188	static u32 xilinx_spi_read_rxfifo(struct udevice bus, u8 rxp, u32 rxbytes)
	189	{
	190	struct xilinx_spi_priv *priv = dev_get_priv(bus);
	191	struct xilinx_spi_regs *regs = priv->regs;
	192	unsigned char d;
	193	unsigned int i = 0;
	194
	195	while (rxbytes && !(readl(&regs->spisr) & SPISR_RX_EMPTY)) {
	196	d = readl(&regs->spidrr) & SPIDRR_8BIT_MASK;
	197	if (rxp)
	198	*rxp++ = d;
	199	debug("spi_xfer: rx:%x\n", d);
	200	rxbytes--;
	201	i++;
	202	}
	203	debug("Rx_done\n");
	204
	205	return i;
	206	}
	207
83ce6469 VK	208	static void xilinx_spi_startup_block(struct udevice *dev, unsigned int bytes,
	209	const void dout, void din)
	210	{
	211	struct udevice *bus = dev_get_parent(dev);
	212	struct xilinx_spi_priv *priv = dev_get_priv(bus);
	213	struct xilinx_spi_regs *regs = priv->regs;
	214	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
	215	const unsigned char *txp = dout;
	216	unsigned char *rxp = din;
	217	u32 reg, count;
	218	u32 txbytes = bytes;
	219	u32 rxbytes = bytes;
	220
	221	/*
	222	* This loop runs two times. First time to send the command.
	223	* Second time to transfer data. After transferring data,
	224	* it sets txp to the initial value for the normal operation.
	225	*/
	226	for ( ; priv->startup < 2; priv->startup++) {
	227	count = xilinx_spi_fill_txfifo(bus, txp, txbytes);
	228	reg = readl(&regs->spicr) & ~SPICR_MASTER_INHIBIT;
	229	writel(reg, &regs->spicr);
	230	count = xilinx_spi_read_rxfifo(bus, rxp, rxbytes);
	231	txp = din;
	232
	233	if (priv->startup) {
	234	spi_cs_deactivate(dev);
	235	spi_cs_activate(dev, slave_plat->cs);
	236	txp = dout;
	237	}
	238	}
	239	}
	240
9505c36e JT	241	static int xilinx_spi_xfer(struct udevice *dev, unsigned int bitlen,
9505c36e JT	242	const void dout, void din, unsigned long flags)
09aac75e	243	{
9505c36e JT	244	struct udevice *bus = dev_get_parent(dev);
	245	struct xilinx_spi_priv *priv = dev_get_priv(bus);
	246	struct xilinx_spi_regs *regs = priv->regs;
	247	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
09aac75e SL	248	/* assume spi core configured to do 8 bit transfers */
	249	unsigned int bytes = bitlen / XILSPI_MAX_XFER_BITS;
	250	const unsigned char *txp = dout;
	251	unsigned char *rxp = din;
0c0de58f VK	252	u32 txbytes = bytes;
	253	u32 rxbytes = bytes;
	254	u32 reg, count, timeout;
	255	int ret;
09aac75e	256
a7b6ef05	257	debug("spi_xfer: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n",
9505c36e	258	bus->seq, slave_plat->cs, bitlen, bytes, flags);
a7b6ef05	259
09aac75e SL	260	if (bitlen == 0)
	261	goto done;
	262
	263	if (bitlen % XILSPI_MAX_XFER_BITS) {
a7b6ef05 JT	264	printf("XILSPI warning: Not a multiple of %d bits\n",
a7b6ef05 JT	265	XILSPI_MAX_XFER_BITS);
09aac75e SL	266	flags \|= SPI_XFER_END;
	267	goto done;
	268	}
	269
09aac75e	270	if (flags & SPI_XFER_BEGIN)
9505c36e	271	spi_cs_activate(dev, slave_plat->cs);
09aac75e	272
83ce6469 VK	273	/*
	274	* This is the work around for the startup block issue in
	275	* the spi controller. SPI clock is passing through STARTUP
	276	* block to FLASH. STARTUP block don't provide clock as soon
	277	* as QSPI provides command. So first command fails.
	278	*/
	279	xilinx_spi_startup_block(dev, bytes, dout, din);
09aac75e	280
0c0de58f VK	281	while (txbytes && rxbytes) {
	282	count = xilinx_spi_fill_txfifo(bus, txp, txbytes);
	283	reg = readl(&regs->spicr) & ~SPICR_MASTER_INHIBIT;
	284	writel(reg, &regs->spicr);
	285	txbytes -= count;
	286	if (txp)
	287	txp += count;
09aac75e	288
0c0de58f VK	289	ret = wait_for_bit_le32(&regs->spisr, SPISR_TX_EMPTY, true,
	290	XILINX_SPISR_TIMEOUT, false);
	291	if (ret < 0) {
a7b6ef05	292	printf("XILSPI error: Xfer timeout\n");
0c0de58f	293	return ret;
09aac75e SL	294	}
09aac75e SL	295
0c0de58f VK	296	debug("txbytes:0x%x,txp:0x%p\n", txbytes, txp);
	297	count = xilinx_spi_read_rxfifo(bus, rxp, rxbytes);
	298	rxbytes -= count;
09aac75e	299	if (rxp)
0c0de58f VK	300	rxp += count;
0c0de58f VK	301	debug("rxbytes:0x%x rxp:0x%p\n", rxbytes, rxp);
09aac75e SL	302	}
	303
	304	done:
	305	if (flags & SPI_XFER_END)
9505c36e	306	spi_cs_deactivate(dev);
09aac75e SL	307
	308	return 0;
	309	}
9505c36e JT	310
	311	static int xilinx_spi_set_speed(struct udevice *bus, uint speed)
	312	{
	313	struct xilinx_spi_priv *priv = dev_get_priv(bus);
	314
	315	priv->freq = speed;
	316
d5f60737	317	debug("xilinx_spi_set_speed: regs=%p, speed=%d\n", priv->regs,
9505c36e JT	318	priv->freq);
	319
	320	return 0;
	321	}
	322
	323	static int xilinx_spi_set_mode(struct udevice *bus, uint mode)
	324	{
	325	struct xilinx_spi_priv *priv = dev_get_priv(bus);
	326	struct xilinx_spi_regs *regs = priv->regs;
	327	uint32_t spicr;
	328
	329	spicr = readl(&regs->spicr);
d5f60737	330	if (mode & SPI_LSB_FIRST)
9505c36e	331	spicr \|= SPICR_LSB_FIRST;
d5f60737	332	if (mode & SPI_CPHA)
9505c36e	333	spicr \|= SPICR_CPHA;
d5f60737	334	if (mode & SPI_CPOL)
9505c36e	335	spicr \|= SPICR_CPOL;
d5f60737	336	if (mode & SPI_LOOP)
9505c36e JT	337	spicr \|= SPICR_LOOP;
	338
	339	writel(spicr, &regs->spicr);
	340	priv->mode = mode;
	341
	342	debug("xilinx_spi_set_mode: regs=%p, mode=%d\n", priv->regs,
	343	priv->mode);
	344
	345	return 0;
	346	}
	347
	348	static const struct dm_spi_ops xilinx_spi_ops = {
	349	.claim_bus = xilinx_spi_claim_bus,
	350	.release_bus = xilinx_spi_release_bus,
	351	.xfer = xilinx_spi_xfer,
	352	.set_speed = xilinx_spi_set_speed,
	353	.set_mode = xilinx_spi_set_mode,
	354	};
	355
	356	static const struct udevice_id xilinx_spi_ids[] = {
76de51a6 MS	357	{ .compatible = "xlnx,xps-spi-2.00.a" },
76de51a6 MS	358	{ .compatible = "xlnx,xps-spi-2.00.b" },
9505c36e JT	359	{ }
	360	};
	361
	362	U_BOOT_DRIVER(xilinx_spi) = {
	363	.name = "xilinx_spi",
	364	.id = UCLASS_SPI,
	365	.of_match = xilinx_spi_ids,
	366	.ops = &xilinx_spi_ops,
	367	.priv_auto_alloc_size = sizeof(struct xilinx_spi_priv),
	368	.probe = xilinx_spi_probe,
	369	};