[people/ms/u-boot.git] / drivers / spi / xilinx_spi.c

/*
 * Xilinx SPI driver
 *
 * supports 8 bit SPI transfers only, with or w/o FIFO
 *
 * based on bfin_spi.c, by way of altera_spi.c
 * Copyright (c) 2005-2008 Analog Devices Inc.
 * Copyright (c) 2010 Thomas Chou <thomas@wytron.com.tw>
 * Copyright (c) 2010 Graeme Smecher <graeme.smecher@mail.mcgill.ca>
 * Copyright (c) 2012 Stephan Linz <linz@li-pro.net>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 *
 * [0]: http://www.xilinx.com/support/documentation
 *
 * [S]:	[0]/ip_documentation/xps_spi.pdf
 *	[0]/ip_documentation/axi_spi_ds742.pdf
 */
#include <config.h>
#include <common.h>
#include <malloc.h>
#include <spi.h>

#include "xilinx_spi.h"

#ifndef CONFIG_SYS_XILINX_SPI_LIST
#define CONFIG_SYS_XILINX_SPI_LIST	{ CONFIG_SYS_SPI_BASE }
#endif

#ifndef CONFIG_XILINX_SPI_IDLE_VAL
#define CONFIG_XILINX_SPI_IDLE_VAL	0xff
#endif

#define XILSPI_SPICR_DFLT_ON		(SPICR_MANUAL_SS | \
					 SPICR_MASTER_MODE | \
					 SPICR_SPE)

#define XILSPI_SPICR_DFLT_OFF		(SPICR_MASTER_INHIBIT | \
					 SPICR_MANUAL_SS)

#define XILSPI_MAX_XFER_BITS		8

static unsigned long xilinx_spi_base_list[] = CONFIG_SYS_XILINX_SPI_LIST;

__attribute__((weak))
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
	return bus < ARRAY_SIZE(xilinx_spi_base_list) && cs < 32;
}

__attribute__((weak))
void spi_cs_activate(struct spi_slave *slave)
{
	struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);

	writel(SPISSR_ACT(slave->cs), &xilspi->regs->spissr);
}

__attribute__((weak))
void spi_cs_deactivate(struct spi_slave *slave)
{
	struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);

	writel(SPISSR_OFF, &xilspi->regs->spissr);
}

void spi_init(void)
{
	/* do nothing */
}

void spi_set_speed(struct spi_slave *slave, uint hz)
{
	/* xilinx spi core does not support programmable speed */
}

struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
				  unsigned int max_hz, unsigned int mode)
{
	struct xilinx_spi_slave *xilspi;

	if (!spi_cs_is_valid(bus, cs)) {
		printf("XILSPI error: %s: unsupported bus %d / cs %d\n",
				__func__, bus, cs);
		return NULL;
	}

	xilspi = spi_alloc_slave(struct xilinx_spi_slave, bus, cs);
	if (!xilspi) {
		printf("XILSPI error: %s: malloc of SPI structure failed\n",
				__func__);
		return NULL;
	}
	xilspi->regs = (struct xilinx_spi_reg *)xilinx_spi_base_list[bus];
	xilspi->freq = max_hz;
	xilspi->mode = mode;
	debug("%s: bus:%i cs:%i base:%p mode:%x max_hz:%d\n", __func__,
		bus, cs, xilspi->regs, xilspi->mode, xilspi->freq);

	writel(SPISSR_RESET_VALUE, &xilspi->regs->srr);

	return &xilspi->slave;
}

void spi_free_slave(struct spi_slave *slave)
{
	struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);

	free(xilspi);
}

int spi_claim_bus(struct spi_slave *slave)
{
	struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
	u32 spicr;

	debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
	writel(SPISSR_OFF, &xilspi->regs->spissr);

	spicr = XILSPI_SPICR_DFLT_ON;
	if (xilspi->mode & SPI_LSB_FIRST)
		spicr |= SPICR_LSB_FIRST;
	if (xilspi->mode & SPI_CPHA)
		spicr |= SPICR_CPHA;
	if (xilspi->mode & SPI_CPOL)
		spicr |= SPICR_CPOL;
	if (xilspi->mode & SPI_LOOP)
		spicr |= SPICR_LOOP;

	writel(spicr, &xilspi->regs->spicr);
	return 0;
}

void spi_release_bus(struct spi_slave *slave)
{
	struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);

	debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
	writel(SPISSR_OFF, &xilspi->regs->spissr);
	writel(XILSPI_SPICR_DFLT_OFF, &xilspi->regs->spicr);
}

int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
	     void *din, unsigned long flags)
{
	struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
	/* assume spi core configured to do 8 bit transfers */
	unsigned int bytes = bitlen / XILSPI_MAX_XFER_BITS;
	const unsigned char *txp = dout;
	unsigned char *rxp = din;
	unsigned rxecount = 17;	/* max. 16 elements in FIFO, leftover 1 */
	unsigned global_timeout;

	debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__,
		slave->bus, slave->cs, bitlen, bytes, flags);
	if (bitlen == 0)
		goto done;

	if (bitlen % XILSPI_MAX_XFER_BITS) {
		printf("XILSPI warning: %s: Not a multiple of %d bits\n",
				__func__, XILSPI_MAX_XFER_BITS);
		flags |= SPI_XFER_END;
		goto done;
	}

	/* empty read buffer */
	while (rxecount && !(readl(&xilspi->regs->spisr) & SPISR_RX_EMPTY)) {
		readl(&xilspi->regs->spidrr);
		rxecount--;
	}

	if (!rxecount) {
		printf("XILSPI error: %s: Rx buffer not empty\n", __func__);
		return -1;
	}

	if (flags & SPI_XFER_BEGIN)
		spi_cs_activate(slave);

	/* at least 1usec or greater, leftover 1 */
	global_timeout = xilspi->freq > XILSPI_MAX_XFER_BITS * 1000000 ? 2 :
			(XILSPI_MAX_XFER_BITS * 1000000 / xilspi->freq) + 1;

	while (bytes--) {
		unsigned timeout = global_timeout;
		/* get Tx element from data out buffer and count up */
		unsigned char d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL;
		debug("%s: tx:%x ", __func__, d);

		/* write out and wait for processing (receive data) */
		writel(d & SPIDTR_8BIT_MASK, &xilspi->regs->spidtr);
		while (timeout && readl(&xilspi->regs->spisr)
						& SPISR_RX_EMPTY) {
			timeout--;
			udelay(1);
		}

		if (!timeout) {
			printf("XILSPI error: %s: Xfer timeout\n", __func__);
			return -1;
		}

		/* read Rx element and push into data in buffer */
		d = readl(&xilspi->regs->spidrr) & SPIDRR_8BIT_MASK;
		if (rxp)
			*rxp++ = d;
		debug("rx:%x\n", d);
	}

 done:
	if (flags & SPI_XFER_END)
		spi_cs_deactivate(slave);

	return 0;
}
Commit	Line	Data
09aac75e SL	1	/*
	2	* Xilinx SPI driver
	3	*
	4	* supports 8 bit SPI transfers only, with or w/o FIFO
	5	*
	6	* based on bfin_spi.c, by way of altera_spi.c
	7	* Copyright (c) 2005-2008 Analog Devices Inc.
	8	* Copyright (c) 2010 Thomas Chou <thomas@wytron.com.tw>
	9	* Copyright (c) 2010 Graeme Smecher <graeme.smecher@mail.mcgill.ca>
	10	* Copyright (c) 2012 Stephan Linz <linz@li-pro.net>
	11	*
e7b1e452	12	* SPDX-License-Identifier: GPL-2.0+
09aac75e SL	13	*
	14	* [0]: http://www.xilinx.com/support/documentation
	15	*
	16	* [S]: [0]/ip_documentation/xps_spi.pdf
	17	* [0]/ip_documentation/axi_spi_ds742.pdf
	18	*/
	19	#include <config.h>
	20	#include <common.h>
	21	#include <malloc.h>
	22	#include <spi.h>
	23
	24	#include "xilinx_spi.h"
	25
	26	#ifndef CONFIG_SYS_XILINX_SPI_LIST
	27	#define CONFIG_SYS_XILINX_SPI_LIST { CONFIG_SYS_SPI_BASE }
	28	#endif
	29
	30	#ifndef CONFIG_XILINX_SPI_IDLE_VAL
	31	#define CONFIG_XILINX_SPI_IDLE_VAL 0xff
	32	#endif
	33
	34	#define XILSPI_SPICR_DFLT_ON (SPICR_MANUAL_SS \| \
	35	SPICR_MASTER_MODE \| \
	36	SPICR_SPE)
	37
	38	#define XILSPI_SPICR_DFLT_OFF (SPICR_MASTER_INHIBIT \| \
	39	SPICR_MANUAL_SS)
	40
	41	#define XILSPI_MAX_XFER_BITS 8
	42
	43	static unsigned long xilinx_spi_base_list[] = CONFIG_SYS_XILINX_SPI_LIST;
	44
	45	__attribute__((weak))
	46	int spi_cs_is_valid(unsigned int bus, unsigned int cs)
	47	{
	48	return bus < ARRAY_SIZE(xilinx_spi_base_list) && cs < 32;
	49	}
	50
	51	__attribute__((weak))
	52	void spi_cs_activate(struct spi_slave *slave)
	53	{
	54	struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
	55
	56	writel(SPISSR_ACT(slave->cs), &xilspi->regs->spissr);
	57	}
	58
	59	__attribute__((weak))
	60	void spi_cs_deactivate(struct spi_slave *slave)
	61	{
	62	struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
	63
	64	writel(SPISSR_OFF, &xilspi->regs->spissr);
	65	}
	66
	67	void spi_init(void)
	68	{
	69	/* do nothing */
	70	}
	71
	72	void spi_set_speed(struct spi_slave *slave, uint hz)
	73	{
	74	/* xilinx spi core does not support programmable speed */
	75	}
	76
77	struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
78	unsigned int max_hz, unsigned int mode)
79	{
80	struct xilinx_spi_slave *xilspi;
09aac75e SL	81
	82	if (!spi_cs_is_valid(bus, cs)) {
	83	printf("XILSPI error: %s: unsupported bus %d / cs %d\n",
	84	__func__, bus, cs);
	85	return NULL;
	86	}
	87
d3504fee	88	xilspi = spi_alloc_slave(struct xilinx_spi_slave, bus, cs);
09aac75e SL	89	if (!xilspi) {
	90	printf("XILSPI error: %s: malloc of SPI structure failed\n",
	91	__func__);
	92	return NULL;
	93	}
09aac75e SL	94	xilspi->regs = (struct xilinx_spi_reg *)xilinx_spi_base_list[bus];
	95	xilspi->freq = max_hz;
	96	xilspi->mode = mode;
	97	debug("%s: bus:%i cs:%i base:%p mode:%x max_hz:%d\n", __func__,
	98	bus, cs, xilspi->regs, xilspi->mode, xilspi->freq);
	99
85e9c65f JW	100	writel(SPISSR_RESET_VALUE, &xilspi->regs->srr);
85e9c65f JW	101
09aac75e SL	102	return &xilspi->slave;
	103	}
	104
	105	void spi_free_slave(struct spi_slave *slave)
	106	{
	107	struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
	108
	109	free(xilspi);
	110	}
	111
	112	int spi_claim_bus(struct spi_slave *slave)
	113	{
	114	struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
	115	u32 spicr;
	116
	117	debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
	118	writel(SPISSR_OFF, &xilspi->regs->spissr);
	119
	120	spicr = XILSPI_SPICR_DFLT_ON;
	121	if (xilspi->mode & SPI_LSB_FIRST)
	122	spicr \|= SPICR_LSB_FIRST;
	123	if (xilspi->mode & SPI_CPHA)
	124	spicr \|= SPICR_CPHA;
	125	if (xilspi->mode & SPI_CPOL)
	126	spicr \|= SPICR_CPOL;
	127	if (xilspi->mode & SPI_LOOP)
	128	spicr \|= SPICR_LOOP;
	129
	130	writel(spicr, &xilspi->regs->spicr);
	131	return 0;
	132	}
	133
	134	void spi_release_bus(struct spi_slave *slave)
	135	{
	136	struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
	137
	138	debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
	139	writel(SPISSR_OFF, &xilspi->regs->spissr);
	140	writel(XILSPI_SPICR_DFLT_OFF, &xilspi->regs->spicr);
	141	}
	142
	143	int spi_xfer(struct spi_slave slave, unsigned int bitlen, const void dout,
	144	void *din, unsigned long flags)
	145	{
	146	struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
	147	/* assume spi core configured to do 8 bit transfers */
	148	unsigned int bytes = bitlen / XILSPI_MAX_XFER_BITS;
	149	const unsigned char *txp = dout;
	150	unsigned char *rxp = din;
	151	unsigned rxecount = 17; /* max. 16 elements in FIFO, leftover 1 */
999c39a4	152	unsigned global_timeout;
09aac75e SL	153
	154	debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__,
	155	slave->bus, slave->cs, bitlen, bytes, flags);
	156	if (bitlen == 0)
	157	goto done;
	158
	159	if (bitlen % XILSPI_MAX_XFER_BITS) {
	160	printf("XILSPI warning: %s: Not a multiple of %d bits\n",
	161	__func__, XILSPI_MAX_XFER_BITS);
	162	flags \|= SPI_XFER_END;
	163	goto done;
	164	}
	165
	166	/* empty read buffer */
	167	while (rxecount && !(readl(&xilspi->regs->spisr) & SPISR_RX_EMPTY)) {
	168	readl(&xilspi->regs->spidrr);
	169	rxecount--;
	170	}
	171
	172	if (!rxecount) {
	173	printf("XILSPI error: %s: Rx buffer not empty\n", __func__);
	174	return -1;
	175	}
	176
	177	if (flags & SPI_XFER_BEGIN)
	178	spi_cs_activate(slave);
	179
999c39a4 MS	180	/* at least 1usec or greater, leftover 1 */
999c39a4 MS	181	global_timeout = xilspi->freq > XILSPI_MAX_XFER_BITS * 1000000 ? 2 :
09aac75e SL	182	(XILSPI_MAX_XFER_BITS * 1000000 / xilspi->freq) + 1;
09aac75e SL	183
999c39a4 MS	184	while (bytes--) {
999c39a4 MS	185	unsigned timeout = global_timeout;
09aac75e SL	186	/* get Tx element from data out buffer and count up */
	187	unsigned char d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL;
	188	debug("%s: tx:%x ", __func__, d);
	189
	190	/* write out and wait for processing (receive data) */
	191	writel(d & SPIDTR_8BIT_MASK, &xilspi->regs->spidtr);
	192	while (timeout && readl(&xilspi->regs->spisr)
	193	& SPISR_RX_EMPTY) {
	194	timeout--;
	195	udelay(1);
	196	}
	197
	198	if (!timeout) {
	199	printf("XILSPI error: %s: Xfer timeout\n", __func__);
	200	return -1;
	201	}
	202
	203	/* read Rx element and push into data in buffer */
	204	d = readl(&xilspi->regs->spidrr) & SPIDRR_8BIT_MASK;
	205	if (rxp)
	206	*rxp++ = d;
	207	debug("rx:%x\n", d);
	208	}
	209
	210	done:
	211	if (flags & SPI_XFER_END)
	212	spi_cs_deactivate(slave);
	213
	214	return 0;
	215	}