[thirdparty/u-boot.git] / drivers / spi / xilinx_spi.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Xilinx SPI driver
 *
 * Supports 8 bit SPI transfers only, with or w/o FIFO
 *
 * Based on bfin_spi.c, by way of altera_spi.c
 * Copyright (c) 2015 Jagan Teki <jteki@openedev.com>
 * Copyright (c) 2012 Stephan Linz <linz@li-pro.net>
 * Copyright (c) 2010 Graeme Smecher <graeme.smecher@mail.mcgill.ca>
 * Copyright (c) 2010 Thomas Chou <thomas@wytron.com.tw>
 * Copyright (c) 2005-2008 Analog Devices Inc.
 */

#include <config.h>
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <malloc.h>
#include <spi.h>
#include <asm/io.h>

/*
 * [0]: http://www.xilinx.com/support/documentation
 *
 * Xilinx SPI Register Definitions
 * [1]:	[0]/ip_documentation/xps_spi.pdf
 *	page 8, Register Descriptions
 * [2]:	[0]/ip_documentation/axi_spi_ds742.pdf
 *	page 7, Register Overview Table
 */

/* SPI Control Register (spicr), [1] p9, [2] p8 */
#define SPICR_LSB_FIRST		BIT(9)
#define SPICR_MASTER_INHIBIT	BIT(8)
#define SPICR_MANUAL_SS		BIT(7)
#define SPICR_RXFIFO_RESEST	BIT(6)
#define SPICR_TXFIFO_RESEST	BIT(5)
#define SPICR_CPHA		BIT(4)
#define SPICR_CPOL		BIT(3)
#define SPICR_MASTER_MODE	BIT(2)
#define SPICR_SPE		BIT(1)
#define SPICR_LOOP		BIT(0)

/* SPI Status Register (spisr), [1] p11, [2] p10 */
#define SPISR_SLAVE_MODE_SELECT	BIT(5)
#define SPISR_MODF		BIT(4)
#define SPISR_TX_FULL		BIT(3)
#define SPISR_TX_EMPTY		BIT(2)
#define SPISR_RX_FULL		BIT(1)
#define SPISR_RX_EMPTY		BIT(0)

/* SPI Data Transmit Register (spidtr), [1] p12, [2] p12 */
#define SPIDTR_8BIT_MASK	GENMASK(7, 0)
#define SPIDTR_16BIT_MASK	GENMASK(15, 0)
#define SPIDTR_32BIT_MASK	GENMASK(31, 0)

/* SPI Data Receive Register (spidrr), [1] p12, [2] p12 */
#define SPIDRR_8BIT_MASK	GENMASK(7, 0)
#define SPIDRR_16BIT_MASK	GENMASK(15, 0)
#define SPIDRR_32BIT_MASK	GENMASK(31, 0)

/* SPI Slave Select Register (spissr), [1] p13, [2] p13 */
#define SPISSR_MASK(cs)		(1 << (cs))
#define SPISSR_ACT(cs)		~SPISSR_MASK(cs)
#define SPISSR_OFF		~0UL

/* SPI Software Reset Register (ssr) */
#define SPISSR_RESET_VALUE	0x0a

#define XILSPI_MAX_XFER_BITS	8
#define XILSPI_SPICR_DFLT_ON	(SPICR_MANUAL_SS | SPICR_MASTER_MODE | \
				SPICR_SPE)
#define XILSPI_SPICR_DFLT_OFF	(SPICR_MASTER_INHIBIT | SPICR_MANUAL_SS)

#ifndef CONFIG_XILINX_SPI_IDLE_VAL
#define CONFIG_XILINX_SPI_IDLE_VAL	GENMASK(7, 0)
#endif

#ifndef CONFIG_SYS_XILINX_SPI_LIST
#define CONFIG_SYS_XILINX_SPI_LIST	{ CONFIG_SYS_SPI_BASE }
#endif

/* xilinx spi register set */
struct xilinx_spi_regs {
	u32 __space0__[7];
	u32 dgier;	/* Device Global Interrupt Enable Register (DGIER) */
	u32 ipisr;	/* IP Interrupt Status Register (IPISR) */
	u32 __space1__;
	u32 ipier;	/* IP Interrupt Enable Register (IPIER) */
	u32 __space2__[5];
	u32 srr;	/* Softare Reset Register (SRR) */
	u32 __space3__[7];
	u32 spicr;	/* SPI Control Register (SPICR) */
	u32 spisr;	/* SPI Status Register (SPISR) */
	u32 spidtr;	/* SPI Data Transmit Register (SPIDTR) */
	u32 spidrr;	/* SPI Data Receive Register (SPIDRR) */
	u32 spissr;	/* SPI Slave Select Register (SPISSR) */
	u32 spitfor;	/* SPI Transmit FIFO Occupancy Register (SPITFOR) */
	u32 spirfor;	/* SPI Receive FIFO Occupancy Register (SPIRFOR) */
};

/* xilinx spi priv */
struct xilinx_spi_priv {
	struct xilinx_spi_regs *regs;
	unsigned int freq;
	unsigned int mode;
};

static unsigned long xilinx_spi_base_list[] = CONFIG_SYS_XILINX_SPI_LIST;
static int xilinx_spi_probe(struct udevice *bus)
{
	struct xilinx_spi_priv *priv = dev_get_priv(bus);
	struct xilinx_spi_regs *regs = priv->regs;

	priv->regs = (struct xilinx_spi_regs *)xilinx_spi_base_list[bus->seq];

	writel(SPISSR_RESET_VALUE, &regs->srr);

	return 0;
}

static void spi_cs_activate(struct udevice *dev, uint cs)
{
	struct udevice *bus = dev_get_parent(dev);
	struct xilinx_spi_priv *priv = dev_get_priv(bus);
	struct xilinx_spi_regs *regs = priv->regs;

	writel(SPISSR_ACT(cs), &regs->spissr);
}

static void spi_cs_deactivate(struct udevice *dev)
{
	struct udevice *bus = dev_get_parent(dev);
	struct xilinx_spi_priv *priv = dev_get_priv(bus);
	struct xilinx_spi_regs *regs = priv->regs;

	writel(SPISSR_OFF, &regs->spissr);
}

static int xilinx_spi_claim_bus(struct udevice *dev)
{
	struct udevice *bus = dev_get_parent(dev);
	struct xilinx_spi_priv *priv = dev_get_priv(bus);
	struct xilinx_spi_regs *regs = priv->regs;

	writel(SPISSR_OFF, &regs->spissr);
	writel(XILSPI_SPICR_DFLT_ON, &regs->spicr);

	return 0;
}

static int xilinx_spi_release_bus(struct udevice *dev)
{
	struct udevice *bus = dev_get_parent(dev);
	struct xilinx_spi_priv *priv = dev_get_priv(bus);
	struct xilinx_spi_regs *regs = priv->regs;

	writel(SPISSR_OFF, &regs->spissr);
	writel(XILSPI_SPICR_DFLT_OFF, &regs->spicr);

	return 0;
}

static int xilinx_spi_xfer(struct udevice *dev, unsigned int bitlen,
			    const void *dout, void *din, unsigned long flags)
{
	struct udevice *bus = dev_get_parent(dev);
	struct xilinx_spi_priv *priv = dev_get_priv(bus);
	struct xilinx_spi_regs *regs = priv->regs;
	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
	/* assume spi core configured to do 8 bit transfers */
	unsigned int bytes = bitlen / XILSPI_MAX_XFER_BITS;
	const unsigned char *txp = dout;
	unsigned char *rxp = din;
	unsigned rxecount = 17;	/* max. 16 elements in FIFO, leftover 1 */
	unsigned global_timeout;

	debug("spi_xfer: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n",
	      bus->seq, slave_plat->cs, bitlen, bytes, flags);

	if (bitlen == 0)
		goto done;

	if (bitlen % XILSPI_MAX_XFER_BITS) {
		printf("XILSPI warning: Not a multiple of %d bits\n",
		       XILSPI_MAX_XFER_BITS);
		flags |= SPI_XFER_END;
		goto done;
	}

	/* empty read buffer */
	while (rxecount && !(readl(&regs->spisr) & SPISR_RX_EMPTY)) {
		readl(&regs->spidrr);
		rxecount--;
	}

	if (!rxecount) {
		printf("XILSPI error: Rx buffer not empty\n");
		return -1;
	}

	if (flags & SPI_XFER_BEGIN)
		spi_cs_activate(dev, slave_plat->cs);

	/* at least 1usec or greater, leftover 1 */
	global_timeout = priv->freq > XILSPI_MAX_XFER_BITS * 1000000 ? 2 :
			(XILSPI_MAX_XFER_BITS * 1000000 / priv->freq) + 1;

	while (bytes--) {
		unsigned timeout = global_timeout;
		/* get Tx element from data out buffer and count up */
		unsigned char d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL;
		debug("spi_xfer: tx:%x ", d);

		/* write out and wait for processing (receive data) */
		writel(d & SPIDTR_8BIT_MASK, &regs->spidtr);
		while (timeout && readl(&regs->spisr)
						& SPISR_RX_EMPTY) {
			timeout--;
			udelay(1);
		}

		if (!timeout) {
			printf("XILSPI error: Xfer timeout\n");
			return -1;
		}

		/* read Rx element and push into data in buffer */
		d = readl(&regs->spidrr) & SPIDRR_8BIT_MASK;
		if (rxp)
			*rxp++ = d;
		debug("spi_xfer: rx:%x\n", d);
	}

 done:
	if (flags & SPI_XFER_END)
		spi_cs_deactivate(dev);

	return 0;
}

static int xilinx_spi_set_speed(struct udevice *bus, uint speed)
{
	struct xilinx_spi_priv *priv = dev_get_priv(bus);

	priv->freq = speed;

	debug("xilinx_spi_set_speed: regs=%p, speed=%d\n", priv->regs,
	      priv->freq);

	return 0;
}

static int xilinx_spi_set_mode(struct udevice *bus, uint mode)
{
	struct xilinx_spi_priv *priv = dev_get_priv(bus);
	struct xilinx_spi_regs *regs = priv->regs;
	uint32_t spicr;

	spicr = readl(&regs->spicr);
	if (mode & SPI_LSB_FIRST)
		spicr |= SPICR_LSB_FIRST;
	if (mode & SPI_CPHA)
		spicr |= SPICR_CPHA;
	if (mode & SPI_CPOL)
		spicr |= SPICR_CPOL;
	if (mode & SPI_LOOP)
		spicr |= SPICR_LOOP;

	writel(spicr, &regs->spicr);
	priv->mode = mode;

	debug("xilinx_spi_set_mode: regs=%p, mode=%d\n", priv->regs,
	      priv->mode);

	return 0;
}

static const struct dm_spi_ops xilinx_spi_ops = {
	.claim_bus	= xilinx_spi_claim_bus,
	.release_bus	= xilinx_spi_release_bus,
	.xfer		= xilinx_spi_xfer,
	.set_speed	= xilinx_spi_set_speed,
	.set_mode	= xilinx_spi_set_mode,
};

static const struct udevice_id xilinx_spi_ids[] = {
	{ .compatible = "xlnx,xps-spi-2.00.a" },
	{ .compatible = "xlnx,xps-spi-2.00.b" },
	{ }
};

U_BOOT_DRIVER(xilinx_spi) = {
	.name	= "xilinx_spi",
	.id	= UCLASS_SPI,
	.of_match = xilinx_spi_ids,
	.ops	= &xilinx_spi_ops,
	.priv_auto_alloc_size = sizeof(struct xilinx_spi_priv),
	.probe	= xilinx_spi_probe,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
09aac75e SL	2	/*
	3	* Xilinx SPI driver
	4	*
a7b6ef05	5	* Supports 8 bit SPI transfers only, with or w/o FIFO
09aac75e	6	*
a7b6ef05	7	* Based on bfin_spi.c, by way of altera_spi.c
9505c36e	8	* Copyright (c) 2015 Jagan Teki <jteki@openedev.com>
09aac75e	9	* Copyright (c) 2012 Stephan Linz <linz@li-pro.net>
a7b6ef05 JT	10	* Copyright (c) 2010 Graeme Smecher <graeme.smecher@mail.mcgill.ca>
	11	* Copyright (c) 2010 Thomas Chou <thomas@wytron.com.tw>
	12	* Copyright (c) 2005-2008 Analog Devices Inc.
09aac75e	13	*/
a7b6ef05	14
09aac75e SL	15	#include <config.h>
09aac75e SL	16	#include <common.h>
9505c36e JT	17	#include <dm.h>
9505c36e JT	18	#include <errno.h>
09aac75e SL	19	#include <malloc.h>
09aac75e SL	20	#include <spi.h>
5f24d123	21	#include <asm/io.h>
09aac75e	22
f93542a8	23	/*
a7b6ef05	24	* [0]: http://www.xilinx.com/support/documentation
f93542a8	25	*
a7b6ef05	26	* Xilinx SPI Register Definitions
f93542a8 JT	27	* [1]: [0]/ip_documentation/xps_spi.pdf
	28	* page 8, Register Descriptions
	29	* [2]: [0]/ip_documentation/axi_spi_ds742.pdf
	30	* page 7, Register Overview Table
	31	*/
f93542a8 JT	32
f93542a8 JT	33	/* SPI Control Register (spicr), [1] p9, [2] p8 */
5ea392d4 JT	34	#define SPICR_LSB_FIRST BIT(9)
	35	#define SPICR_MASTER_INHIBIT BIT(8)
	36	#define SPICR_MANUAL_SS BIT(7)
	37	#define SPICR_RXFIFO_RESEST BIT(6)
	38	#define SPICR_TXFIFO_RESEST BIT(5)
	39	#define SPICR_CPHA BIT(4)
	40	#define SPICR_CPOL BIT(3)
	41	#define SPICR_MASTER_MODE BIT(2)
	42	#define SPICR_SPE BIT(1)
	43	#define SPICR_LOOP BIT(0)
f93542a8 JT	44
f93542a8 JT	45	/* SPI Status Register (spisr), [1] p11, [2] p10 */
5ea392d4 JT	46	#define SPISR_SLAVE_MODE_SELECT BIT(5)
	47	#define SPISR_MODF BIT(4)
	48	#define SPISR_TX_FULL BIT(3)
	49	#define SPISR_TX_EMPTY BIT(2)
	50	#define SPISR_RX_FULL BIT(1)
	51	#define SPISR_RX_EMPTY BIT(0)
f93542a8 JT	52
f93542a8 JT	53	/* SPI Data Transmit Register (spidtr), [1] p12, [2] p12 */
d2436301 JT	54	#define SPIDTR_8BIT_MASK GENMASK(7, 0)
	55	#define SPIDTR_16BIT_MASK GENMASK(15, 0)
	56	#define SPIDTR_32BIT_MASK GENMASK(31, 0)
f93542a8 JT	57
f93542a8 JT	58	/* SPI Data Receive Register (spidrr), [1] p12, [2] p12 */
d2436301 JT	59	#define SPIDRR_8BIT_MASK GENMASK(7, 0)
	60	#define SPIDRR_16BIT_MASK GENMASK(15, 0)
	61	#define SPIDRR_32BIT_MASK GENMASK(31, 0)
f93542a8 JT	62
	63	/* SPI Slave Select Register (spissr), [1] p13, [2] p13 */
	64	#define SPISSR_MASK(cs) (1 << (cs))
	65	#define SPISSR_ACT(cs) ~SPISSR_MASK(cs)
	66	#define SPISSR_OFF ~0UL
	67
f93542a8 JT	68	/* SPI Software Reset Register (ssr) */
	69	#define SPISSR_RESET_VALUE 0x0a
	70
a7b6ef05 JT	71	#define XILSPI_MAX_XFER_BITS 8
	72	#define XILSPI_SPICR_DFLT_ON (SPICR_MANUAL_SS \| SPICR_MASTER_MODE \| \
	73	SPICR_SPE)
	74	#define XILSPI_SPICR_DFLT_OFF (SPICR_MASTER_INHIBIT \| SPICR_MANUAL_SS)
	75
	76	#ifndef CONFIG_XILINX_SPI_IDLE_VAL
d2436301	77	#define CONFIG_XILINX_SPI_IDLE_VAL GENMASK(7, 0)
a7b6ef05 JT	78	#endif
	79
	80	#ifndef CONFIG_SYS_XILINX_SPI_LIST
	81	#define CONFIG_SYS_XILINX_SPI_LIST { CONFIG_SYS_SPI_BASE }
	82	#endif
	83
	84	/* xilinx spi register set */
9505c36e	85	struct xilinx_spi_regs {
a7b6ef05 JT	86	u32 __space0__[7];
	87	u32 dgier; /* Device Global Interrupt Enable Register (DGIER) */
	88	u32 ipisr; /* IP Interrupt Status Register (IPISR) */
	89	u32 __space1__;
	90	u32 ipier; /* IP Interrupt Enable Register (IPIER) */
	91	u32 __space2__[5];
	92	u32 srr; /* Softare Reset Register (SRR) */
	93	u32 __space3__[7];
	94	u32 spicr; /* SPI Control Register (SPICR) */
	95	u32 spisr; /* SPI Status Register (SPISR) */
	96	u32 spidtr; /* SPI Data Transmit Register (SPIDTR) */
	97	u32 spidrr; /* SPI Data Receive Register (SPIDRR) */
	98	u32 spissr; /* SPI Slave Select Register (SPISSR) */
	99	u32 spitfor; /* SPI Transmit FIFO Occupancy Register (SPITFOR) */
	100	u32 spirfor; /* SPI Receive FIFO Occupancy Register (SPIRFOR) */
	101	};
	102
9505c36e JT	103	/* xilinx spi priv */
	104	struct xilinx_spi_priv {
	105	struct xilinx_spi_regs *regs;
f93542a8 JT	106	unsigned int freq;
	107	unsigned int mode;
	108	};
	109
09aac75e	110	static unsigned long xilinx_spi_base_list[] = CONFIG_SYS_XILINX_SPI_LIST;
9505c36e	111	static int xilinx_spi_probe(struct udevice *bus)
09aac75e	112	{
9505c36e JT	113	struct xilinx_spi_priv *priv = dev_get_priv(bus);
9505c36e JT	114	struct xilinx_spi_regs *regs = priv->regs;
09aac75e	115
9505c36e	116	priv->regs = (struct xilinx_spi_regs *)xilinx_spi_base_list[bus->seq];
09aac75e	117
9505c36e	118	writel(SPISSR_RESET_VALUE, &regs->srr);
09aac75e	119
9505c36e	120	return 0;
09aac75e SL	121	}
09aac75e SL	122
9505c36e	123	static void spi_cs_activate(struct udevice *dev, uint cs)
09aac75e	124	{
9505c36e JT	125	struct udevice *bus = dev_get_parent(dev);
	126	struct xilinx_spi_priv *priv = dev_get_priv(bus);
	127	struct xilinx_spi_regs *regs = priv->regs;
09aac75e	128
9505c36e	129	writel(SPISSR_ACT(cs), &regs->spissr);
09aac75e SL	130	}
09aac75e SL	131
9505c36e	132	static void spi_cs_deactivate(struct udevice *dev)
09aac75e	133	{
9505c36e JT	134	struct udevice *bus = dev_get_parent(dev);
	135	struct xilinx_spi_priv *priv = dev_get_priv(bus);
	136	struct xilinx_spi_regs *regs = priv->regs;
09aac75e	137
9505c36e	138	writel(SPISSR_OFF, &regs->spissr);
09aac75e SL	139	}
09aac75e SL	140
9505c36e	141	static int xilinx_spi_claim_bus(struct udevice *dev)
09aac75e	142	{
9505c36e JT	143	struct udevice *bus = dev_get_parent(dev);
	144	struct xilinx_spi_priv *priv = dev_get_priv(bus);
	145	struct xilinx_spi_regs *regs = priv->regs;
09aac75e	146
9505c36e JT	147	writel(SPISSR_OFF, &regs->spissr);
9505c36e JT	148	writel(XILSPI_SPICR_DFLT_ON, &regs->spicr);
09aac75e	149
09aac75e SL	150	return 0;
	151	}
	152
9505c36e	153	static int xilinx_spi_release_bus(struct udevice *dev)
09aac75e	154	{
9505c36e JT	155	struct udevice *bus = dev_get_parent(dev);
	156	struct xilinx_spi_priv *priv = dev_get_priv(bus);
	157	struct xilinx_spi_regs *regs = priv->regs;
09aac75e	158
9505c36e JT	159	writel(SPISSR_OFF, &regs->spissr);
	160	writel(XILSPI_SPICR_DFLT_OFF, &regs->spicr);
	161
	162	return 0;
09aac75e SL	163	}
09aac75e SL	164
9505c36e JT	165	static int xilinx_spi_xfer(struct udevice *dev, unsigned int bitlen,
9505c36e JT	166	const void dout, void din, unsigned long flags)
09aac75e	167	{
9505c36e JT	168	struct udevice *bus = dev_get_parent(dev);
	169	struct xilinx_spi_priv *priv = dev_get_priv(bus);
	170	struct xilinx_spi_regs *regs = priv->regs;
	171	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
09aac75e SL	172	/* assume spi core configured to do 8 bit transfers */
	173	unsigned int bytes = bitlen / XILSPI_MAX_XFER_BITS;
	174	const unsigned char *txp = dout;
	175	unsigned char *rxp = din;
	176	unsigned rxecount = 17; /* max. 16 elements in FIFO, leftover 1 */
999c39a4	177	unsigned global_timeout;
09aac75e	178
a7b6ef05	179	debug("spi_xfer: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n",
9505c36e	180	bus->seq, slave_plat->cs, bitlen, bytes, flags);
a7b6ef05	181
09aac75e SL	182	if (bitlen == 0)
	183	goto done;
	184
	185	if (bitlen % XILSPI_MAX_XFER_BITS) {
a7b6ef05 JT	186	printf("XILSPI warning: Not a multiple of %d bits\n",
a7b6ef05 JT	187	XILSPI_MAX_XFER_BITS);
09aac75e SL	188	flags \|= SPI_XFER_END;
	189	goto done;
	190	}
	191
	192	/* empty read buffer */
9505c36e JT	193	while (rxecount && !(readl(&regs->spisr) & SPISR_RX_EMPTY)) {
9505c36e JT	194	readl(&regs->spidrr);
09aac75e SL	195	rxecount--;
	196	}
	197
	198	if (!rxecount) {
a7b6ef05	199	printf("XILSPI error: Rx buffer not empty\n");
09aac75e SL	200	return -1;
	201	}
	202
	203	if (flags & SPI_XFER_BEGIN)
9505c36e	204	spi_cs_activate(dev, slave_plat->cs);
09aac75e	205
999c39a4	206	/* at least 1usec or greater, leftover 1 */
9505c36e JT	207	global_timeout = priv->freq > XILSPI_MAX_XFER_BITS * 1000000 ? 2 :
9505c36e JT	208	(XILSPI_MAX_XFER_BITS * 1000000 / priv->freq) + 1;
09aac75e	209
999c39a4 MS	210	while (bytes--) {
999c39a4 MS	211	unsigned timeout = global_timeout;
09aac75e SL	212	/* get Tx element from data out buffer and count up */
09aac75e SL	213	unsigned char d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL;
a7b6ef05	214	debug("spi_xfer: tx:%x ", d);
09aac75e SL	215
09aac75e SL	216	/* write out and wait for processing (receive data) */
9505c36e JT	217	writel(d & SPIDTR_8BIT_MASK, &regs->spidtr);
9505c36e JT	218	while (timeout && readl(&regs->spisr)
09aac75e SL	219	& SPISR_RX_EMPTY) {
	220	timeout--;
	221	udelay(1);
	222	}
	223
	224	if (!timeout) {
a7b6ef05	225	printf("XILSPI error: Xfer timeout\n");
09aac75e SL	226	return -1;
	227	}
	228
	229	/* read Rx element and push into data in buffer */
9505c36e	230	d = readl(&regs->spidrr) & SPIDRR_8BIT_MASK;
09aac75e SL	231	if (rxp)
09aac75e SL	232	*rxp++ = d;
a7b6ef05	233	debug("spi_xfer: rx:%x\n", d);
09aac75e SL	234	}
	235
	236	done:
	237	if (flags & SPI_XFER_END)
9505c36e	238	spi_cs_deactivate(dev);
09aac75e SL	239
	240	return 0;
	241	}
9505c36e JT	242
	243	static int xilinx_spi_set_speed(struct udevice *bus, uint speed)
	244	{
	245	struct xilinx_spi_priv *priv = dev_get_priv(bus);
	246
	247	priv->freq = speed;
	248
d5f60737	249	debug("xilinx_spi_set_speed: regs=%p, speed=%d\n", priv->regs,
9505c36e JT	250	priv->freq);
	251
	252	return 0;
	253	}
	254
	255	static int xilinx_spi_set_mode(struct udevice *bus, uint mode)
	256	{
	257	struct xilinx_spi_priv *priv = dev_get_priv(bus);
	258	struct xilinx_spi_regs *regs = priv->regs;
	259	uint32_t spicr;
	260
	261	spicr = readl(&regs->spicr);
d5f60737	262	if (mode & SPI_LSB_FIRST)
9505c36e	263	spicr \|= SPICR_LSB_FIRST;
d5f60737	264	if (mode & SPI_CPHA)
9505c36e	265	spicr \|= SPICR_CPHA;
d5f60737	266	if (mode & SPI_CPOL)
9505c36e	267	spicr \|= SPICR_CPOL;
d5f60737	268	if (mode & SPI_LOOP)
9505c36e JT	269	spicr \|= SPICR_LOOP;
	270
	271	writel(spicr, &regs->spicr);
	272	priv->mode = mode;
	273
	274	debug("xilinx_spi_set_mode: regs=%p, mode=%d\n", priv->regs,
	275	priv->mode);
	276
	277	return 0;
	278	}
	279
	280	static const struct dm_spi_ops xilinx_spi_ops = {
	281	.claim_bus = xilinx_spi_claim_bus,
	282	.release_bus = xilinx_spi_release_bus,
	283	.xfer = xilinx_spi_xfer,
	284	.set_speed = xilinx_spi_set_speed,
	285	.set_mode = xilinx_spi_set_mode,
	286	};
	287
	288	static const struct udevice_id xilinx_spi_ids[] = {
76de51a6 MS	289	{ .compatible = "xlnx,xps-spi-2.00.a" },
76de51a6 MS	290	{ .compatible = "xlnx,xps-spi-2.00.b" },
9505c36e JT	291	{ }
	292	};
	293
	294	U_BOOT_DRIVER(xilinx_spi) = {
	295	.name = "xilinx_spi",
	296	.id = UCLASS_SPI,
	297	.of_match = xilinx_spi_ids,
	298	.ops = &xilinx_spi_ops,
	299	.priv_auto_alloc_size = sizeof(struct xilinx_spi_priv),
	300	.probe = xilinx_spi_probe,
	301	};