]>
Commit | Line | Data |
---|---|---|
1465d055 | 1 | /* |
86e99b98 | 2 | * (C) Copyright 2013 Xilinx, Inc. |
b1c82da2 | 3 | * (C) Copyright 2015 Jagan Teki <jteki@openedev.com> |
1465d055 JT |
4 | * |
5 | * Xilinx Zynq PS SPI controller driver (master mode only) | |
6 | * | |
7 | * SPDX-License-Identifier: GPL-2.0+ | |
8 | */ | |
9 | ||
1465d055 | 10 | #include <common.h> |
b1c82da2 | 11 | #include <dm.h> |
1465d055 JT |
12 | #include <malloc.h> |
13 | #include <spi.h> | |
14 | #include <asm/io.h> | |
1465d055 | 15 | |
cdc9dd07 JT |
16 | DECLARE_GLOBAL_DATA_PTR; |
17 | ||
1465d055 | 18 | /* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */ |
736b4df1 JT |
19 | #define ZYNQ_SPI_CR_MSA_MASK BIT(15) /* Manual start enb */ |
20 | #define ZYNQ_SPI_CR_MCS_MASK BIT(14) /* Manual chip select */ | |
9cf2ffb3 JT |
21 | #define ZYNQ_SPI_CR_CS_MASK GENMASK(13, 10) /* Chip select */ |
22 | #define ZYNQ_SPI_CR_BAUD_MASK GENMASK(5, 3) /* Baud rate div */ | |
736b4df1 JT |
23 | #define ZYNQ_SPI_CR_CPHA_MASK BIT(2) /* Clock phase */ |
24 | #define ZYNQ_SPI_CR_CPOL_MASK BIT(1) /* Clock polarity */ | |
25 | #define ZYNQ_SPI_CR_MSTREN_MASK BIT(0) /* Mode select */ | |
26 | #define ZYNQ_SPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */ | |
27 | #define ZYNQ_SPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */ | |
9cf2ffb3 | 28 | #define ZYNQ_SPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */ |
736b4df1 | 29 | #define ZYNQ_SPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */ |
1465d055 | 30 | |
46ab8a6a JT |
31 | #define ZYNQ_SPI_CR_BAUD_MAX 8 /* Baud rate divisor max val */ |
32 | #define ZYNQ_SPI_CR_BAUD_SHIFT 3 /* Baud rate divisor shift */ | |
33 | #define ZYNQ_SPI_CR_SS_SHIFT 10 /* Slave select shift */ | |
34 | ||
1465d055 JT |
35 | #define ZYNQ_SPI_FIFO_DEPTH 128 |
36 | #ifndef CONFIG_SYS_ZYNQ_SPI_WAIT | |
37 | #define CONFIG_SYS_ZYNQ_SPI_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */ | |
38 | #endif | |
39 | ||
40 | /* zynq spi register set */ | |
41 | struct zynq_spi_regs { | |
42 | u32 cr; /* 0x00 */ | |
43 | u32 isr; /* 0x04 */ | |
44 | u32 ier; /* 0x08 */ | |
45 | u32 idr; /* 0x0C */ | |
46 | u32 imr; /* 0x10 */ | |
47 | u32 enr; /* 0x14 */ | |
48 | u32 dr; /* 0x18 */ | |
49 | u32 txdr; /* 0x1C */ | |
50 | u32 rxdr; /* 0x20 */ | |
51 | }; | |
52 | ||
b1c82da2 JT |
53 | |
54 | /* zynq spi platform data */ | |
55 | struct zynq_spi_platdata { | |
56 | struct zynq_spi_regs *regs; | |
57 | u32 frequency; /* input frequency */ | |
1465d055 | 58 | u32 speed_hz; |
1465d055 JT |
59 | }; |
60 | ||
b1c82da2 JT |
61 | /* zynq spi priv */ |
62 | struct zynq_spi_priv { | |
63 | struct zynq_spi_regs *regs; | |
19126998 | 64 | u8 cs; |
b1c82da2 JT |
65 | u8 mode; |
66 | u8 fifo_depth; | |
67 | u32 freq; /* required frequency */ | |
68 | }; | |
1465d055 | 69 | |
b1c82da2 | 70 | static int zynq_spi_ofdata_to_platdata(struct udevice *bus) |
1465d055 | 71 | { |
b1c82da2 | 72 | struct zynq_spi_platdata *plat = bus->platdata; |
cdc9dd07 JT |
73 | const void *blob = gd->fdt_blob; |
74 | int node = bus->of_offset; | |
75 | ||
4e9838c1 | 76 | plat->regs = (struct zynq_spi_regs *)dev_get_addr(bus); |
b1c82da2 | 77 | |
cdc9dd07 JT |
78 | /* FIXME: Use 250MHz as a suitable default */ |
79 | plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", | |
80 | 250000000); | |
b1c82da2 JT |
81 | plat->speed_hz = plat->frequency / 2; |
82 | ||
80fd9792 | 83 | debug("%s: regs=%p max-frequency=%d\n", __func__, |
cdc9dd07 JT |
84 | plat->regs, plat->frequency); |
85 | ||
b1c82da2 JT |
86 | return 0; |
87 | } | |
88 | ||
89 | static void zynq_spi_init_hw(struct zynq_spi_priv *priv) | |
90 | { | |
91 | struct zynq_spi_regs *regs = priv->regs; | |
1465d055 JT |
92 | u32 confr; |
93 | ||
94 | /* Disable SPI */ | |
b1c82da2 | 95 | writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, ®s->enr); |
1465d055 JT |
96 | |
97 | /* Disable Interrupts */ | |
b1c82da2 | 98 | writel(ZYNQ_SPI_IXR_ALL_MASK, ®s->idr); |
1465d055 JT |
99 | |
100 | /* Clear RX FIFO */ | |
b1c82da2 | 101 | while (readl(®s->isr) & |
1465d055 | 102 | ZYNQ_SPI_IXR_RXNEMPTY_MASK) |
b1c82da2 | 103 | readl(®s->rxdr); |
1465d055 JT |
104 | |
105 | /* Clear Interrupts */ | |
b1c82da2 | 106 | writel(ZYNQ_SPI_IXR_ALL_MASK, ®s->isr); |
1465d055 JT |
107 | |
108 | /* Manual slave select and Auto start */ | |
109 | confr = ZYNQ_SPI_CR_MCS_MASK | ZYNQ_SPI_CR_CS_MASK | | |
110 | ZYNQ_SPI_CR_MSTREN_MASK; | |
111 | confr &= ~ZYNQ_SPI_CR_MSA_MASK; | |
b1c82da2 | 112 | writel(confr, ®s->cr); |
1465d055 JT |
113 | |
114 | /* Enable SPI */ | |
b1c82da2 | 115 | writel(ZYNQ_SPI_ENR_SPI_EN_MASK, ®s->enr); |
1465d055 JT |
116 | } |
117 | ||
b1c82da2 | 118 | static int zynq_spi_probe(struct udevice *bus) |
1465d055 | 119 | { |
b1c82da2 JT |
120 | struct zynq_spi_platdata *plat = dev_get_platdata(bus); |
121 | struct zynq_spi_priv *priv = dev_get_priv(bus); | |
122 | ||
123 | priv->regs = plat->regs; | |
124 | priv->fifo_depth = ZYNQ_SPI_FIFO_DEPTH; | |
125 | ||
126 | /* init the zynq spi hw */ | |
127 | zynq_spi_init_hw(priv); | |
128 | ||
129 | return 0; | |
1465d055 JT |
130 | } |
131 | ||
19126998 | 132 | static void spi_cs_activate(struct udevice *dev) |
1465d055 | 133 | { |
b1c82da2 JT |
134 | struct udevice *bus = dev->parent; |
135 | struct zynq_spi_priv *priv = dev_get_priv(bus); | |
136 | struct zynq_spi_regs *regs = priv->regs; | |
1465d055 JT |
137 | u32 cr; |
138 | ||
b1c82da2 JT |
139 | clrbits_le32(®s->cr, ZYNQ_SPI_CR_CS_MASK); |
140 | cr = readl(®s->cr); | |
1465d055 JT |
141 | /* |
142 | * CS cal logic: CS[13:10] | |
143 | * xxx0 - cs0 | |
144 | * xx01 - cs1 | |
145 | * x011 - cs2 | |
146 | */ | |
19126998 | 147 | cr |= (~(1 << priv->cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK; |
b1c82da2 | 148 | writel(cr, ®s->cr); |
1465d055 JT |
149 | } |
150 | ||
b1c82da2 | 151 | static void spi_cs_deactivate(struct udevice *dev) |
1465d055 | 152 | { |
b1c82da2 JT |
153 | struct udevice *bus = dev->parent; |
154 | struct zynq_spi_priv *priv = dev_get_priv(bus); | |
155 | struct zynq_spi_regs *regs = priv->regs; | |
1465d055 | 156 | |
b1c82da2 | 157 | setbits_le32(®s->cr, ZYNQ_SPI_CR_CS_MASK); |
1465d055 JT |
158 | } |
159 | ||
b1c82da2 | 160 | static int zynq_spi_claim_bus(struct udevice *dev) |
1465d055 | 161 | { |
b1c82da2 JT |
162 | struct udevice *bus = dev->parent; |
163 | struct zynq_spi_priv *priv = dev_get_priv(bus); | |
164 | struct zynq_spi_regs *regs = priv->regs; | |
1465d055 | 165 | |
b1c82da2 | 166 | writel(ZYNQ_SPI_ENR_SPI_EN_MASK, ®s->enr); |
1465d055 | 167 | |
b1c82da2 | 168 | return 0; |
1465d055 JT |
169 | } |
170 | ||
b1c82da2 | 171 | static int zynq_spi_release_bus(struct udevice *dev) |
1465d055 | 172 | { |
b1c82da2 JT |
173 | struct udevice *bus = dev->parent; |
174 | struct zynq_spi_priv *priv = dev_get_priv(bus); | |
175 | struct zynq_spi_regs *regs = priv->regs; | |
1465d055 | 176 | |
b1c82da2 | 177 | writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, ®s->enr); |
1465d055 JT |
178 | |
179 | return 0; | |
180 | } | |
181 | ||
b1c82da2 JT |
182 | static int zynq_spi_xfer(struct udevice *dev, unsigned int bitlen, |
183 | const void *dout, void *din, unsigned long flags) | |
1465d055 | 184 | { |
b1c82da2 JT |
185 | struct udevice *bus = dev->parent; |
186 | struct zynq_spi_priv *priv = dev_get_priv(bus); | |
187 | struct zynq_spi_regs *regs = priv->regs; | |
188 | struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); | |
1465d055 JT |
189 | u32 len = bitlen / 8; |
190 | u32 tx_len = len, rx_len = len, tx_tvl; | |
191 | const u8 *tx_buf = dout; | |
192 | u8 *rx_buf = din, buf; | |
193 | u32 ts, status; | |
194 | ||
195 | debug("spi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n", | |
b1c82da2 | 196 | bus->seq, slave_plat->cs, bitlen, len, flags); |
1465d055 | 197 | |
1465d055 JT |
198 | if (bitlen % 8) { |
199 | debug("spi_xfer: Non byte aligned SPI transfer\n"); | |
200 | return -1; | |
201 | } | |
202 | ||
19126998 | 203 | priv->cs = slave_plat->cs; |
1465d055 | 204 | if (flags & SPI_XFER_BEGIN) |
19126998 | 205 | spi_cs_activate(dev); |
1465d055 JT |
206 | |
207 | while (rx_len > 0) { | |
208 | /* Write the data into TX FIFO - tx threshold is fifo_depth */ | |
209 | tx_tvl = 0; | |
b1c82da2 | 210 | while ((tx_tvl < priv->fifo_depth) && tx_len) { |
1465d055 JT |
211 | if (tx_buf) |
212 | buf = *tx_buf++; | |
213 | else | |
214 | buf = 0; | |
b1c82da2 | 215 | writel(buf, ®s->txdr); |
1465d055 JT |
216 | tx_len--; |
217 | tx_tvl++; | |
218 | } | |
219 | ||
220 | /* Check TX FIFO completion */ | |
221 | ts = get_timer(0); | |
b1c82da2 | 222 | status = readl(®s->isr); |
1465d055 JT |
223 | while (!(status & ZYNQ_SPI_IXR_TXOW_MASK)) { |
224 | if (get_timer(ts) > CONFIG_SYS_ZYNQ_SPI_WAIT) { | |
225 | printf("spi_xfer: Timeout! TX FIFO not full\n"); | |
226 | return -1; | |
227 | } | |
b1c82da2 | 228 | status = readl(®s->isr); |
1465d055 JT |
229 | } |
230 | ||
231 | /* Read the data from RX FIFO */ | |
b1c82da2 | 232 | status = readl(®s->isr); |
1465d055 | 233 | while (status & ZYNQ_SPI_IXR_RXNEMPTY_MASK) { |
b1c82da2 | 234 | buf = readl(®s->rxdr); |
1465d055 JT |
235 | if (rx_buf) |
236 | *rx_buf++ = buf; | |
b1c82da2 | 237 | status = readl(®s->isr); |
1465d055 JT |
238 | rx_len--; |
239 | } | |
240 | } | |
241 | ||
242 | if (flags & SPI_XFER_END) | |
b1c82da2 JT |
243 | spi_cs_deactivate(dev); |
244 | ||
245 | return 0; | |
246 | } | |
247 | ||
248 | static int zynq_spi_set_speed(struct udevice *bus, uint speed) | |
249 | { | |
250 | struct zynq_spi_platdata *plat = bus->platdata; | |
251 | struct zynq_spi_priv *priv = dev_get_priv(bus); | |
252 | struct zynq_spi_regs *regs = priv->regs; | |
253 | uint32_t confr; | |
254 | u8 baud_rate_val = 0; | |
255 | ||
256 | if (speed > plat->frequency) | |
257 | speed = plat->frequency; | |
258 | ||
259 | /* Set the clock frequency */ | |
260 | confr = readl(®s->cr); | |
261 | if (speed == 0) { | |
262 | /* Set baudrate x8, if the freq is 0 */ | |
263 | baud_rate_val = 0x2; | |
264 | } else if (plat->speed_hz != speed) { | |
46ab8a6a | 265 | while ((baud_rate_val < ZYNQ_SPI_CR_BAUD_MAX) && |
b1c82da2 JT |
266 | ((plat->frequency / |
267 | (2 << baud_rate_val)) > speed)) | |
268 | baud_rate_val++; | |
269 | plat->speed_hz = speed / (2 << baud_rate_val); | |
270 | } | |
dda6241a | 271 | confr &= ~ZYNQ_SPI_CR_BAUD_MASK; |
46ab8a6a | 272 | confr |= (baud_rate_val << ZYNQ_SPI_CR_BAUD_SHIFT); |
b1c82da2 JT |
273 | |
274 | writel(confr, ®s->cr); | |
275 | priv->freq = speed; | |
276 | ||
a22bba81 JT |
277 | debug("zynq_spi_set_speed: regs=%p, speed=%d\n", |
278 | priv->regs, priv->freq); | |
b1c82da2 JT |
279 | |
280 | return 0; | |
281 | } | |
282 | ||
283 | static int zynq_spi_set_mode(struct udevice *bus, uint mode) | |
284 | { | |
285 | struct zynq_spi_priv *priv = dev_get_priv(bus); | |
286 | struct zynq_spi_regs *regs = priv->regs; | |
287 | uint32_t confr; | |
288 | ||
289 | /* Set the SPI Clock phase and polarities */ | |
290 | confr = readl(®s->cr); | |
291 | confr &= ~(ZYNQ_SPI_CR_CPHA_MASK | ZYNQ_SPI_CR_CPOL_MASK); | |
292 | ||
a22bba81 | 293 | if (mode & SPI_CPHA) |
b1c82da2 | 294 | confr |= ZYNQ_SPI_CR_CPHA_MASK; |
a22bba81 | 295 | if (mode & SPI_CPOL) |
b1c82da2 JT |
296 | confr |= ZYNQ_SPI_CR_CPOL_MASK; |
297 | ||
298 | writel(confr, ®s->cr); | |
299 | priv->mode = mode; | |
300 | ||
301 | debug("zynq_spi_set_mode: regs=%p, mode=%d\n", priv->regs, priv->mode); | |
1465d055 JT |
302 | |
303 | return 0; | |
304 | } | |
b1c82da2 JT |
305 | |
306 | static const struct dm_spi_ops zynq_spi_ops = { | |
307 | .claim_bus = zynq_spi_claim_bus, | |
308 | .release_bus = zynq_spi_release_bus, | |
309 | .xfer = zynq_spi_xfer, | |
310 | .set_speed = zynq_spi_set_speed, | |
311 | .set_mode = zynq_spi_set_mode, | |
312 | }; | |
313 | ||
314 | static const struct udevice_id zynq_spi_ids[] = { | |
40b383fa | 315 | { .compatible = "xlnx,zynq-spi-r1p6" }, |
23ef5aea | 316 | { .compatible = "cdns,spi-r1p6" }, |
b1c82da2 JT |
317 | { } |
318 | }; | |
319 | ||
320 | U_BOOT_DRIVER(zynq_spi) = { | |
321 | .name = "zynq_spi", | |
322 | .id = UCLASS_SPI, | |
323 | .of_match = zynq_spi_ids, | |
324 | .ops = &zynq_spi_ops, | |
325 | .ofdata_to_platdata = zynq_spi_ofdata_to_platdata, | |
326 | .platdata_auto_alloc_size = sizeof(struct zynq_spi_platdata), | |
327 | .priv_auto_alloc_size = sizeof(struct zynq_spi_priv), | |
328 | .probe = zynq_spi_probe, | |
329 | }; |