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Commit | Line | Data |
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eb4afe30 JC |
1 | Mediatek Gigabit Switch |
2 | ======================= | |
3 | ||
4 | The mediatek gigabit switch can be found on Mediatek SoCs. | |
5 | ||
6 | Required properties: | |
7 | - compatible: Should be "mediatek,mt7620-gsw", "mediatek,mt7621-gsw", | |
8 | "mediatek,mt7623-gsw" | |
9 | - reg: Address and length of the register set for the device | |
10 | - interrupts: Should contain the gigabit switches interrupt | |
11 | ||
12 | ||
13 | Additional required properties for ARM based SoCs: | |
14 | - mediatek,reset-pin: phandle describing the reset GPIO | |
15 | - clocks: the clocks used by the switch | |
16 | - clock-names: the names of the clocks listed in the clocks property | |
17 | these should be "trgpll", "esw", "gp2", "gp1" | |
18 | - mt7530-supply: the phandle of the regulator used to power the switch | |
19 | - mediatek,pctl-regmap: phandle to the port control regmap. this is used to | |
20 | setup the drive current | |
21 | ||
22 | ||
23 | Optional properties: | |
24 | - interrupt-parent: Should be the phandle for the interrupt controller | |
25 | that services interrupts for this device | |
26 | ||
27 | Example: | |
28 | ||
29 | gsw: switch@1b100000 { | |
30 | compatible = "mediatek,mt7623-gsw"; | |
31 | reg = <0 0x1b110000 0 0x300000>; | |
32 | ||
33 | interrupt-parent = <&pio>; | |
34 | interrupts = <168 IRQ_TYPE_EDGE_RISING>; | |
35 | ||
36 | clocks = <&apmixedsys CLK_APMIXED_TRGPLL>, | |
37 | <ðsys CLK_ETHSYS_ESW>, | |
38 | <ðsys CLK_ETHSYS_GP2>, | |
39 | <ðsys CLK_ETHSYS_GP1>; | |
40 | clock-names = "trgpll", "esw", "gp2", "gp1"; | |
41 | ||
42 | mt7530-supply = <&mt6323_vpa_reg>; | |
43 | ||
44 | mediatek,pctl-regmap = <&syscfg_pctl_a>; | |
45 | mediatek,reset-pin = <&pio 15 0>; | |
46 | ||
47 | status = "okay"; | |
48 | }; |