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1ab7f2a4 JC |
1 | /* |
2 | * spi-mt7621.c -- MediaTek MT7621 SPI controller driver | |
3 | * | |
4 | * Copyright (C) 2011 Sergiy <piratfm@gmail.com> | |
5 | * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org> | |
6 | * Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name> | |
7 | * | |
8 | * Some parts are based on spi-orion.c: | |
9 | * Author: Shadi Ammouri <shadi@marvell.com> | |
10 | * Copyright (C) 2007-2008 Marvell Ltd. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | */ | |
16 | ||
17 | #include <linux/init.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/clk.h> | |
20 | #include <linux/err.h> | |
21 | #include <linux/delay.h> | |
22 | #include <linux/io.h> | |
23 | #include <linux/reset.h> | |
24 | #include <linux/spi/spi.h> | |
25 | #include <linux/of_device.h> | |
26 | #include <linux/platform_device.h> | |
27 | #include <linux/swab.h> | |
28 | ||
29 | #include <ralink_regs.h> | |
30 | ||
31 | #define SPI_BPW_MASK(bits) BIT((bits) - 1) | |
32 | ||
33 | #define DRIVER_NAME "spi-mt7621" | |
34 | /* in usec */ | |
35 | #define RALINK_SPI_WAIT_MAX_LOOP 2000 | |
36 | ||
37 | /* SPISTAT register bit field */ | |
38 | #define SPISTAT_BUSY BIT(0) | |
39 | ||
40 | #define MT7621_SPI_TRANS 0x00 | |
41 | #define SPITRANS_BUSY BIT(16) | |
42 | ||
43 | #define MT7621_SPI_OPCODE 0x04 | |
44 | #define MT7621_SPI_DATA0 0x08 | |
45 | #define MT7621_SPI_DATA4 0x18 | |
46 | #define SPI_CTL_TX_RX_CNT_MASK 0xff | |
47 | #define SPI_CTL_START BIT(8) | |
48 | ||
49 | #define MT7621_SPI_POLAR 0x38 | |
50 | #define MT7621_SPI_MASTER 0x28 | |
51 | #define MT7621_SPI_MOREBUF 0x2c | |
52 | #define MT7621_SPI_SPACE 0x3c | |
53 | ||
54 | #define MT7621_CPHA BIT(5) | |
55 | #define MT7621_CPOL BIT(4) | |
56 | #define MT7621_LSB_FIRST BIT(3) | |
57 | ||
b8a95278 SN |
58 | #define RT2880_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | \ |
59 | SPI_LSB_FIRST | SPI_CS_HIGH) | |
1ab7f2a4 JC |
60 | |
61 | struct mt7621_spi; | |
62 | ||
63 | struct mt7621_spi { | |
64 | struct spi_master *master; | |
65 | void __iomem *base; | |
66 | unsigned int sys_freq; | |
67 | unsigned int speed; | |
68 | struct clk *clk; | |
bf732c6b | 69 | int pending_write; |
1ab7f2a4 JC |
70 | |
71 | struct mt7621_spi_ops *ops; | |
72 | }; | |
73 | ||
74 | static inline struct mt7621_spi *spidev_to_mt7621_spi(struct spi_device *spi) | |
75 | { | |
76 | return spi_master_get_devdata(spi->master); | |
77 | } | |
78 | ||
79 | static inline u32 mt7621_spi_read(struct mt7621_spi *rs, u32 reg) | |
80 | { | |
81 | return ioread32(rs->base + reg); | |
82 | } | |
83 | ||
84 | static inline void mt7621_spi_write(struct mt7621_spi *rs, u32 reg, u32 val) | |
85 | { | |
86 | iowrite32(val, rs->base + reg); | |
87 | } | |
88 | ||
89 | static void mt7621_spi_reset(struct mt7621_spi *rs, int duplex) | |
90 | { | |
91 | u32 master = mt7621_spi_read(rs, MT7621_SPI_MASTER); | |
92 | ||
93 | master |= 7 << 29; | |
94 | master |= 1 << 2; | |
95 | if (duplex) | |
96 | master |= 1 << 10; | |
97 | else | |
98 | master &= ~(1 << 10); | |
99 | ||
100 | mt7621_spi_write(rs, MT7621_SPI_MASTER, master); | |
bf732c6b | 101 | rs->pending_write = 0; |
1ab7f2a4 JC |
102 | } |
103 | ||
104 | static void mt7621_spi_set_cs(struct spi_device *spi, int enable) | |
105 | { | |
106 | struct mt7621_spi *rs = spidev_to_mt7621_spi(spi); | |
107 | int cs = spi->chip_select; | |
108 | u32 polar = 0; | |
109 | ||
110 | mt7621_spi_reset(rs, cs); | |
111 | if (enable) | |
112 | polar = BIT(cs); | |
113 | mt7621_spi_write(rs, MT7621_SPI_POLAR, polar); | |
114 | } | |
115 | ||
116 | static int mt7621_spi_prepare(struct spi_device *spi, unsigned int speed) | |
117 | { | |
118 | struct mt7621_spi *rs = spidev_to_mt7621_spi(spi); | |
119 | u32 rate; | |
120 | u32 reg; | |
121 | ||
122 | dev_dbg(&spi->dev, "speed:%u\n", speed); | |
123 | ||
124 | rate = DIV_ROUND_UP(rs->sys_freq, speed); | |
125 | dev_dbg(&spi->dev, "rate-1:%u\n", rate); | |
126 | ||
127 | if (rate > 4097) | |
128 | return -EINVAL; | |
129 | ||
130 | if (rate < 2) | |
131 | rate = 2; | |
132 | ||
133 | reg = mt7621_spi_read(rs, MT7621_SPI_MASTER); | |
134 | reg &= ~(0xfff << 16); | |
135 | reg |= (rate - 2) << 16; | |
136 | rs->speed = speed; | |
137 | ||
138 | reg &= ~MT7621_LSB_FIRST; | |
139 | if (spi->mode & SPI_LSB_FIRST) | |
140 | reg |= MT7621_LSB_FIRST; | |
141 | ||
142 | reg &= ~(MT7621_CPHA | MT7621_CPOL); | |
143 | switch(spi->mode & (SPI_CPOL | SPI_CPHA)) { | |
d42fd96a SN |
144 | case SPI_MODE_0: |
145 | break; | |
146 | case SPI_MODE_1: | |
147 | reg |= MT7621_CPHA; | |
148 | break; | |
149 | case SPI_MODE_2: | |
150 | reg |= MT7621_CPOL; | |
151 | break; | |
152 | case SPI_MODE_3: | |
153 | reg |= MT7621_CPOL | MT7621_CPHA; | |
154 | break; | |
1ab7f2a4 JC |
155 | } |
156 | mt7621_spi_write(rs, MT7621_SPI_MASTER, reg); | |
157 | ||
158 | return 0; | |
159 | } | |
160 | ||
a83834c1 | 161 | static inline int mt7621_spi_wait_till_ready(struct mt7621_spi *rs) |
1ab7f2a4 | 162 | { |
1ab7f2a4 JC |
163 | int i; |
164 | ||
165 | for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) { | |
166 | u32 status; | |
167 | ||
168 | status = mt7621_spi_read(rs, MT7621_SPI_TRANS); | |
169 | if ((status & SPITRANS_BUSY) == 0) { | |
170 | return 0; | |
171 | } | |
172 | cpu_relax(); | |
173 | udelay(1); | |
174 | } | |
175 | ||
176 | return -ETIMEDOUT; | |
177 | } | |
178 | ||
bf732c6b N |
179 | static void mt7621_spi_read_half_duplex(struct mt7621_spi *rs, |
180 | int rx_len, u8 *buf) | |
1ab7f2a4 | 181 | { |
bf732c6b N |
182 | /* Combine with any pending write, and perform one or |
183 | * more half-duplex transactions reading 'len' bytes. | |
184 | * Data to be written is already in MT7621_SPI_DATA* | |
185 | */ | |
186 | int tx_len = rs->pending_write; | |
1ab7f2a4 | 187 | |
bf732c6b | 188 | rs->pending_write = 0; |
1ab7f2a4 | 189 | |
bf732c6b N |
190 | while (rx_len || tx_len) { |
191 | int i; | |
192 | u32 val = (min(tx_len, 4) * 8) << 24; | |
193 | int rx = min(rx_len, 32); | |
1ab7f2a4 | 194 | |
bf732c6b N |
195 | if (tx_len > 4) |
196 | val |= (tx_len - 4) * 8; | |
197 | val |= (rx * 8) << 12; | |
198 | mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val); | |
1ab7f2a4 | 199 | |
bf732c6b | 200 | tx_len = 0; |
1ab7f2a4 | 201 | |
bf732c6b N |
202 | val = mt7621_spi_read(rs, MT7621_SPI_TRANS); |
203 | val |= SPI_CTL_START; | |
204 | mt7621_spi_write(rs, MT7621_SPI_TRANS, val); | |
1ab7f2a4 | 205 | |
bf732c6b | 206 | mt7621_spi_wait_till_ready(rs); |
1ab7f2a4 | 207 | |
bf732c6b N |
208 | for (i = 0; i < rx; i++) { |
209 | if ((i % 4) == 0) | |
210 | val = mt7621_spi_read(rs, MT7621_SPI_DATA0 + i); | |
211 | *buf++ = val & 0xff; | |
212 | val >>= 8; | |
213 | } | |
214 | rx_len -= i; | |
1ab7f2a4 | 215 | } |
bf732c6b | 216 | } |
1ab7f2a4 | 217 | |
bf732c6b N |
218 | static inline void mt7621_spi_flush(struct mt7621_spi *rs) |
219 | { | |
220 | mt7621_spi_read_half_duplex(rs, 0, NULL); | |
221 | } | |
1ab7f2a4 | 222 | |
bf732c6b N |
223 | static void mt7621_spi_write_half_duplex(struct mt7621_spi *rs, |
224 | int tx_len, const u8 *buf) | |
225 | { | |
226 | int val = 0; | |
227 | int len = rs->pending_write; | |
228 | ||
229 | if (len & 3) { | |
230 | val = mt7621_spi_read(rs, MT7621_SPI_OPCODE + (len & ~3)); | |
231 | if (len < 4) { | |
232 | val <<= (4 - len) * 8; | |
233 | val = swab32(val); | |
234 | } | |
1ab7f2a4 | 235 | } |
1ab7f2a4 | 236 | |
bf732c6b N |
237 | while (tx_len > 0) { |
238 | if (len >= 36) { | |
239 | rs->pending_write = len; | |
240 | mt7621_spi_flush(rs); | |
241 | len = 0; | |
242 | } | |
1ab7f2a4 | 243 | |
bf732c6b N |
244 | val |= *buf++ << (8 * (len & 3)); |
245 | len++; | |
246 | if ((len & 3) == 0) { | |
247 | if (len == 4) | |
248 | /* The byte-order of the opcode is weird! */ | |
249 | val = swab32(val); | |
250 | mt7621_spi_write(rs, MT7621_SPI_OPCODE + len - 4, val); | |
251 | val = 0; | |
252 | } | |
253 | tx_len -= 1; | |
254 | } | |
255 | if (len & 3) { | |
256 | if (len < 4) { | |
257 | val = swab32(val); | |
258 | val >>= (4 - len) * 8; | |
259 | } | |
260 | mt7621_spi_write(rs, MT7621_SPI_OPCODE + (len & ~3), val); | |
261 | } | |
262 | rs->pending_write = len; | |
263 | } | |
1ab7f2a4 | 264 | |
bf732c6b N |
265 | static int mt7621_spi_transfer_half_duplex(struct spi_master *master, |
266 | struct spi_message *m) | |
267 | { | |
268 | struct mt7621_spi *rs = spi_master_get_devdata(master); | |
269 | struct spi_device *spi = m->spi; | |
270 | unsigned int speed = spi->max_speed_hz; | |
271 | struct spi_transfer *t = NULL; | |
272 | int status = 0; | |
1ab7f2a4 | 273 | |
a83834c1 | 274 | mt7621_spi_wait_till_ready(rs); |
1ab7f2a4 | 275 | |
bf732c6b N |
276 | list_for_each_entry(t, &m->transfers, transfer_list) |
277 | if (t->speed_hz < speed) | |
278 | speed = t->speed_hz; | |
1ab7f2a4 | 279 | |
bf732c6b N |
280 | if (mt7621_spi_prepare(spi, speed)) { |
281 | status = -EIO; | |
282 | goto msg_done; | |
283 | } | |
1ab7f2a4 | 284 | |
bf732c6b N |
285 | mt7621_spi_set_cs(spi, 1); |
286 | m->actual_length = 0; | |
1ab7f2a4 | 287 | list_for_each_entry(t, &m->transfers, transfer_list) { |
bf732c6b N |
288 | if (t->rx_buf) |
289 | mt7621_spi_read_half_duplex(rs, t->len, t->rx_buf); | |
290 | else if (t->tx_buf) | |
291 | mt7621_spi_write_half_duplex(rs, t->len, t->tx_buf); | |
292 | m->actual_length += t->len; | |
1ab7f2a4 | 293 | } |
bf732c6b | 294 | mt7621_spi_flush(rs); |
1ab7f2a4 | 295 | |
bf732c6b | 296 | mt7621_spi_set_cs(spi, 0); |
1ab7f2a4 JC |
297 | msg_done: |
298 | m->status = status; | |
299 | spi_finalize_current_message(master); | |
300 | ||
301 | return 0; | |
302 | } | |
303 | ||
304 | static int mt7621_spi_transfer_full_duplex(struct spi_master *master, | |
305 | struct spi_message *m) | |
306 | { | |
307 | struct mt7621_spi *rs = spi_master_get_devdata(master); | |
308 | struct spi_device *spi = m->spi; | |
309 | unsigned int speed = spi->max_speed_hz; | |
310 | struct spi_transfer *t = NULL; | |
311 | int status = 0; | |
312 | int i, len = 0; | |
313 | int rx_len = 0; | |
314 | u32 data[9] = { 0 }; | |
315 | u32 val = 0; | |
316 | ||
a83834c1 | 317 | mt7621_spi_wait_till_ready(rs); |
1ab7f2a4 JC |
318 | |
319 | list_for_each_entry(t, &m->transfers, transfer_list) { | |
320 | const u8 *buf = t->tx_buf; | |
321 | ||
322 | if (t->rx_buf) | |
323 | rx_len += t->len; | |
324 | ||
325 | if (!buf) | |
326 | continue; | |
327 | ||
328 | if (WARN_ON(len + t->len > 16)) { | |
329 | status = -EIO; | |
330 | goto msg_done; | |
331 | } | |
332 | ||
333 | for (i = 0; i < t->len; i++, len++) | |
334 | data[len / 4] |= buf[i] << (8 * (len & 3)); | |
335 | if (speed > t->speed_hz) | |
336 | speed = t->speed_hz; | |
337 | } | |
338 | ||
339 | if (WARN_ON(rx_len > 16)) { | |
340 | status = -EIO; | |
341 | goto msg_done; | |
342 | } | |
343 | ||
344 | if (mt7621_spi_prepare(spi, speed)) { | |
345 | status = -EIO; | |
346 | goto msg_done; | |
347 | } | |
348 | ||
349 | for (i = 0; i < len; i += 4) | |
350 | mt7621_spi_write(rs, MT7621_SPI_DATA0 + i, data[i / 4]); | |
351 | ||
352 | val |= len * 8; | |
353 | val |= (rx_len * 8) << 12; | |
354 | mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val); | |
355 | ||
356 | mt7621_spi_set_cs(spi, 1); | |
357 | ||
358 | val = mt7621_spi_read(rs, MT7621_SPI_TRANS); | |
359 | val |= SPI_CTL_START; | |
360 | mt7621_spi_write(rs, MT7621_SPI_TRANS, val); | |
361 | ||
a83834c1 | 362 | mt7621_spi_wait_till_ready(rs); |
1ab7f2a4 JC |
363 | |
364 | mt7621_spi_set_cs(spi, 0); | |
365 | ||
366 | for (i = 0; i < rx_len; i += 4) | |
367 | data[i / 4] = mt7621_spi_read(rs, MT7621_SPI_DATA4 + i); | |
368 | ||
369 | m->actual_length = rx_len; | |
370 | ||
371 | len = 0; | |
372 | list_for_each_entry(t, &m->transfers, transfer_list) { | |
373 | u8 *buf = t->rx_buf; | |
374 | ||
375 | if (!buf) | |
376 | continue; | |
377 | ||
378 | for (i = 0; i < t->len; i++, len++) | |
379 | buf[i] = data[len / 4] >> (8 * (len & 3)); | |
380 | } | |
381 | ||
382 | msg_done: | |
383 | m->status = status; | |
384 | spi_finalize_current_message(master); | |
385 | ||
386 | return 0; | |
387 | } | |
388 | ||
389 | static int mt7621_spi_transfer_one_message(struct spi_master *master, | |
390 | struct spi_message *m) | |
391 | { | |
392 | struct spi_device *spi = m->spi; | |
393 | int cs = spi->chip_select; | |
394 | ||
395 | if (cs) | |
396 | return mt7621_spi_transfer_full_duplex(master, m); | |
397 | return mt7621_spi_transfer_half_duplex(master, m); | |
398 | } | |
399 | ||
400 | static int mt7621_spi_setup(struct spi_device *spi) | |
401 | { | |
402 | struct mt7621_spi *rs = spidev_to_mt7621_spi(spi); | |
403 | ||
404 | if ((spi->max_speed_hz == 0) || | |
405 | (spi->max_speed_hz > (rs->sys_freq / 2))) | |
406 | spi->max_speed_hz = (rs->sys_freq / 2); | |
407 | ||
408 | if (spi->max_speed_hz < (rs->sys_freq / 4097)) { | |
409 | dev_err(&spi->dev, "setup: requested speed is too low %d Hz\n", | |
410 | spi->max_speed_hz); | |
411 | return -EINVAL; | |
412 | } | |
413 | ||
414 | return 0; | |
415 | } | |
416 | ||
417 | static const struct of_device_id mt7621_spi_match[] = { | |
418 | { .compatible = "ralink,mt7621-spi" }, | |
419 | {}, | |
420 | }; | |
421 | MODULE_DEVICE_TABLE(of, mt7621_spi_match); | |
422 | ||
1ab7f2a4 JC |
423 | static int mt7621_spi_probe(struct platform_device *pdev) |
424 | { | |
425 | const struct of_device_id *match; | |
426 | struct spi_master *master; | |
427 | struct mt7621_spi *rs; | |
1ab7f2a4 JC |
428 | void __iomem *base; |
429 | struct resource *r; | |
430 | int status = 0; | |
431 | struct clk *clk; | |
432 | struct mt7621_spi_ops *ops; | |
433 | ||
434 | match = of_match_device(mt7621_spi_match, &pdev->dev); | |
435 | if (!match) | |
436 | return -EINVAL; | |
437 | ops = (struct mt7621_spi_ops *)match->data; | |
438 | ||
439 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
440 | base = devm_ioremap_resource(&pdev->dev, r); | |
441 | if (IS_ERR(base)) | |
442 | return PTR_ERR(base); | |
443 | ||
444 | clk = devm_clk_get(&pdev->dev, NULL); | |
445 | if (IS_ERR(clk)) { | |
446 | dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n", | |
447 | status); | |
448 | return PTR_ERR(clk); | |
449 | } | |
450 | ||
451 | status = clk_prepare_enable(clk); | |
452 | if (status) | |
453 | return status; | |
454 | ||
455 | master = spi_alloc_master(&pdev->dev, sizeof(*rs)); | |
456 | if (master == NULL) { | |
457 | dev_info(&pdev->dev, "master allocation failed\n"); | |
458 | return -ENOMEM; | |
459 | } | |
460 | ||
461 | master->mode_bits = RT2880_SPI_MODE_BITS; | |
462 | ||
463 | master->setup = mt7621_spi_setup; | |
464 | master->transfer_one_message = mt7621_spi_transfer_one_message; | |
465 | master->bits_per_word_mask = SPI_BPW_MASK(8); | |
466 | master->dev.of_node = pdev->dev.of_node; | |
467 | master->num_chipselect = 2; | |
1ab7f2a4 JC |
468 | |
469 | dev_set_drvdata(&pdev->dev, master); | |
470 | ||
471 | rs = spi_master_get_devdata(master); | |
472 | rs->base = base; | |
473 | rs->clk = clk; | |
474 | rs->master = master; | |
475 | rs->sys_freq = clk_get_rate(rs->clk); | |
476 | rs->ops = ops; | |
bf732c6b | 477 | rs->pending_write = 0; |
1ab7f2a4 | 478 | dev_info(&pdev->dev, "sys_freq: %u\n", rs->sys_freq); |
1ab7f2a4 JC |
479 | |
480 | device_reset(&pdev->dev); | |
481 | ||
482 | mt7621_spi_reset(rs, 0); | |
483 | ||
484 | return spi_register_master(master); | |
485 | } | |
486 | ||
487 | static int mt7621_spi_remove(struct platform_device *pdev) | |
488 | { | |
489 | struct spi_master *master; | |
490 | struct mt7621_spi *rs; | |
491 | ||
492 | master = dev_get_drvdata(&pdev->dev); | |
493 | rs = spi_master_get_devdata(master); | |
494 | ||
495 | clk_disable(rs->clk); | |
496 | spi_unregister_master(master); | |
497 | ||
498 | return 0; | |
499 | } | |
500 | ||
501 | MODULE_ALIAS("platform:" DRIVER_NAME); | |
502 | ||
503 | static struct platform_driver mt7621_spi_driver = { | |
504 | .driver = { | |
505 | .name = DRIVER_NAME, | |
1ab7f2a4 JC |
506 | .of_match_table = mt7621_spi_match, |
507 | }, | |
508 | .probe = mt7621_spi_probe, | |
509 | .remove = mt7621_spi_remove, | |
510 | }; | |
511 | ||
512 | module_platform_driver(mt7621_spi_driver); | |
513 | ||
514 | MODULE_DESCRIPTION("MT7621 SPI driver"); | |
515 | MODULE_AUTHOR("Felix Fietkau <nbd@nbd.name>"); | |
516 | MODULE_LICENSE("GPL"); |