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77d89b08 | 1 | /* Driver for Realtek PCI-Express card reader |
2 | * | |
3 | * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License as published by the | |
7 | * Free Software Foundation; either version 2, or (at your option) any | |
8 | * later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | * General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along | |
16 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
17 | * | |
18 | * Author: | |
19 | * wwang (wei_wang@realsil.com.cn) | |
20 | * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China | |
21 | */ | |
22 | ||
23 | #include <linux/blkdev.h> | |
24 | #include <linux/kthread.h> | |
25 | #include <linux/sched.h> | |
26 | ||
27 | #include "rtsx.h" | |
28 | #include "rtsx_transport.h" | |
29 | #include "rtsx_scsi.h" | |
30 | #include "rtsx_card.h" | |
31 | #include "sd.h" | |
32 | ||
33 | #define SD_MAX_RETRY_COUNT 3 | |
34 | ||
6680d2ca | 35 | static u16 REG_SD_CFG1; |
36 | static u16 REG_SD_CFG2; | |
37 | static u16 REG_SD_CFG3; | |
38 | static u16 REG_SD_STAT1; | |
39 | static u16 REG_SD_STAT2; | |
40 | static u16 REG_SD_BUS_STAT; | |
41 | static u16 REG_SD_PAD_CTL; | |
42 | static u16 REG_SD_SAMPLE_POINT_CTL; | |
43 | static u16 REG_SD_PUSH_POINT_CTL; | |
44 | static u16 REG_SD_CMD0; | |
45 | static u16 REG_SD_CMD1; | |
46 | static u16 REG_SD_CMD2; | |
47 | static u16 REG_SD_CMD3; | |
48 | static u16 REG_SD_CMD4; | |
49 | static u16 REG_SD_CMD5; | |
50 | static u16 REG_SD_BYTE_CNT_L; | |
51 | static u16 REG_SD_BYTE_CNT_H; | |
52 | static u16 REG_SD_BLOCK_CNT_L; | |
53 | static u16 REG_SD_BLOCK_CNT_H; | |
54 | static u16 REG_SD_TRANSFER; | |
55 | static u16 REG_SD_VPCLK0_CTL; | |
56 | static u16 REG_SD_VPCLK1_CTL; | |
57 | static u16 REG_SD_DCMPS0_CTL; | |
58 | static u16 REG_SD_DCMPS1_CTL; | |
77d89b08 | 59 | |
60 | static inline void sd_set_err_code(struct rtsx_chip *chip, u8 err_code) | |
61 | { | |
62 | struct sd_info *sd_card = &(chip->sd_card); | |
63 | ||
64 | sd_card->err_code |= err_code; | |
65 | } | |
66 | ||
67 | static inline void sd_clr_err_code(struct rtsx_chip *chip) | |
68 | { | |
69 | struct sd_info *sd_card = &(chip->sd_card); | |
70 | ||
71 | sd_card->err_code = 0; | |
72 | } | |
73 | ||
74 | static inline int sd_check_err_code(struct rtsx_chip *chip, u8 err_code) | |
75 | { | |
76 | struct sd_info *sd_card = &(chip->sd_card); | |
77 | ||
78 | return sd_card->err_code & err_code; | |
79 | } | |
80 | ||
81 | static void sd_init_reg_addr(struct rtsx_chip *chip) | |
82 | { | |
83 | if (CHECK_PID(chip, 0x5209)) { | |
84 | REG_SD_CFG1 = SD_CFG1; | |
85 | REG_SD_CFG2 = SD_CFG2; | |
86 | REG_SD_CFG3 = SD_CFG3; | |
87 | REG_SD_STAT1 = SD_STAT1; | |
88 | REG_SD_STAT2 = SD_STAT2; | |
89 | REG_SD_BUS_STAT = SD_BUS_STAT; | |
90 | REG_SD_PAD_CTL = SD_PAD_CTL; | |
91 | REG_SD_SAMPLE_POINT_CTL = SD_SAMPLE_POINT_CTL; | |
92 | REG_SD_PUSH_POINT_CTL = SD_PUSH_POINT_CTL; | |
93 | REG_SD_CMD0 = SD_CMD0; | |
94 | REG_SD_CMD1 = SD_CMD1; | |
95 | REG_SD_CMD2 = SD_CMD2; | |
96 | REG_SD_CMD3 = SD_CMD3; | |
97 | REG_SD_CMD4 = SD_CMD4; | |
98 | REG_SD_CMD5 = SD_CMD5; | |
99 | REG_SD_BYTE_CNT_L = SD_BYTE_CNT_L; | |
100 | REG_SD_BYTE_CNT_H = SD_BYTE_CNT_H; | |
101 | REG_SD_BLOCK_CNT_L = SD_BLOCK_CNT_L; | |
102 | REG_SD_BLOCK_CNT_H = SD_BLOCK_CNT_H; | |
103 | REG_SD_TRANSFER = SD_TRANSFER; | |
104 | REG_SD_VPCLK0_CTL = SD_VPCLK0_CTL; | |
105 | REG_SD_VPCLK1_CTL = SD_VPCLK1_CTL; | |
106 | REG_SD_DCMPS0_CTL = SD_DCMPS0_CTL; | |
107 | REG_SD_DCMPS1_CTL = SD_DCMPS1_CTL; | |
108 | } else { | |
109 | REG_SD_CFG1 = 0xFD31; | |
110 | REG_SD_CFG2 = 0xFD33; | |
111 | REG_SD_CFG3 = 0xFD3E; | |
112 | REG_SD_STAT1 = 0xFD30; | |
113 | REG_SD_STAT2 = 0; | |
114 | REG_SD_BUS_STAT = 0; | |
115 | REG_SD_PAD_CTL = 0; | |
116 | REG_SD_SAMPLE_POINT_CTL = 0; | |
117 | REG_SD_PUSH_POINT_CTL = 0; | |
118 | REG_SD_CMD0 = 0xFD34; | |
119 | REG_SD_CMD1 = 0xFD35; | |
120 | REG_SD_CMD2 = 0xFD36; | |
121 | REG_SD_CMD3 = 0xFD37; | |
122 | REG_SD_CMD4 = 0xFD38; | |
123 | REG_SD_CMD5 = 0xFD5A; | |
124 | REG_SD_BYTE_CNT_L = 0xFD39; | |
125 | REG_SD_BYTE_CNT_H = 0xFD3A; | |
126 | REG_SD_BLOCK_CNT_L = 0xFD3B; | |
127 | REG_SD_BLOCK_CNT_H = 0xFD3C; | |
128 | REG_SD_TRANSFER = 0xFD32; | |
129 | REG_SD_VPCLK0_CTL = 0; | |
130 | REG_SD_VPCLK1_CTL = 0; | |
131 | REG_SD_DCMPS0_CTL = 0; | |
132 | REG_SD_DCMPS1_CTL = 0; | |
133 | } | |
134 | } | |
135 | ||
136 | static int sd_check_data0_status(struct rtsx_chip *chip) | |
137 | { | |
138 | u8 stat; | |
139 | ||
140 | if (CHECK_PID(chip, 0x5209)) { | |
141 | RTSX_READ_REG(chip, REG_SD_BUS_STAT, &stat); | |
142 | } else { | |
143 | RTSX_READ_REG(chip, REG_SD_STAT1, &stat); | |
144 | } | |
145 | ||
146 | if (!(stat & SD_DAT0_STATUS)) { | |
147 | sd_set_err_code(chip, SD_BUSY); | |
148 | TRACE_RET(chip, STATUS_FAIL); | |
149 | } | |
150 | ||
151 | return STATUS_SUCCESS; | |
152 | } | |
153 | ||
154 | static int sd_send_cmd_get_rsp(struct rtsx_chip *chip, u8 cmd_idx, | |
155 | u32 arg, u8 rsp_type, u8 *rsp, int rsp_len) | |
156 | { | |
157 | struct sd_info *sd_card = &(chip->sd_card); | |
158 | int retval; | |
159 | int timeout = 100; | |
160 | u16 reg_addr; | |
161 | u8 *ptr; | |
162 | int stat_idx = 0; | |
163 | int rty_cnt = 0; | |
164 | ||
165 | sd_clr_err_code(chip); | |
166 | ||
167 | RTSX_DEBUGP("SD/MMC CMD %d, arg = 0x%08x\n", cmd_idx, arg); | |
168 | ||
169 | if (rsp_type == SD_RSP_TYPE_R1b) | |
170 | timeout = 3000; | |
171 | ||
172 | RTY_SEND_CMD: | |
173 | ||
174 | rtsx_init_cmd(chip); | |
175 | ||
176 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | cmd_idx); | |
177 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, (u8)(arg >> 24)); | |
178 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, (u8)(arg >> 16)); | |
179 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, (u8)(arg >> 8)); | |
180 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, (u8)arg); | |
181 | ||
182 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type); | |
183 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, | |
184 | 0x01, PINGPONG_BUFFER); | |
185 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, | |
186 | 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START); | |
187 | rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, | |
188 | SD_TRANSFER_END | SD_STAT_IDLE, SD_TRANSFER_END | SD_STAT_IDLE); | |
189 | ||
190 | if (rsp_type == SD_RSP_TYPE_R2) { | |
191 | for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16; reg_addr++) { | |
192 | rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0); | |
193 | } | |
194 | stat_idx = 16; | |
195 | } else if (rsp_type != SD_RSP_TYPE_R0) { | |
196 | for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4; reg_addr++) { | |
197 | rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0); | |
198 | } | |
199 | stat_idx = 5; | |
200 | } | |
201 | ||
202 | rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_STAT1, 0, 0); | |
203 | ||
204 | retval = rtsx_send_cmd(chip, SD_CARD, timeout); | |
205 | if (retval < 0) { | |
206 | u8 val; | |
207 | ||
208 | rtsx_read_register(chip, REG_SD_STAT1, &val); | |
209 | RTSX_DEBUGP("SD_STAT1: 0x%x\n", val); | |
210 | ||
211 | if (CHECK_PID(chip, 0x5209)) { | |
212 | rtsx_read_register(chip, REG_SD_STAT2, &val); | |
213 | RTSX_DEBUGP("SD_STAT2: 0x%x\n", val); | |
214 | ||
215 | if (val & SD_RSP_80CLK_TIMEOUT) { | |
216 | rtsx_clear_sd_error(chip); | |
217 | sd_set_err_code(chip, SD_RSP_TIMEOUT); | |
218 | TRACE_RET(chip, STATUS_FAIL); | |
219 | } | |
220 | ||
221 | rtsx_read_register(chip, REG_SD_BUS_STAT, &val); | |
222 | RTSX_DEBUGP("SD_BUS_STAT: 0x%x\n", val); | |
223 | } else { | |
224 | rtsx_read_register(chip, REG_SD_CFG3, &val); | |
225 | RTSX_DEBUGP("SD_CFG3: 0x%x\n", val); | |
226 | } | |
227 | ||
228 | if (retval == -ETIMEDOUT) { | |
229 | if (rsp_type & SD_WAIT_BUSY_END) { | |
230 | retval = sd_check_data0_status(chip); | |
231 | if (retval != STATUS_SUCCESS) { | |
232 | rtsx_clear_sd_error(chip); | |
233 | TRACE_RET(chip, retval); | |
234 | } | |
235 | } else { | |
236 | sd_set_err_code(chip, SD_TO_ERR); | |
237 | } | |
238 | retval = STATUS_TIMEDOUT; | |
239 | } else { | |
240 | retval = STATUS_FAIL; | |
241 | } | |
242 | rtsx_clear_sd_error(chip); | |
243 | ||
244 | TRACE_RET(chip, retval); | |
245 | } | |
246 | ||
247 | if (rsp_type == SD_RSP_TYPE_R0) | |
248 | return STATUS_SUCCESS; | |
249 | ||
250 | ptr = rtsx_get_cmd_data(chip) + 1; | |
251 | ||
252 | if ((ptr[0] & 0xC0) != 0) { | |
253 | sd_set_err_code(chip, SD_STS_ERR); | |
254 | TRACE_RET(chip, STATUS_FAIL); | |
255 | } | |
256 | ||
257 | if (!(rsp_type & SD_NO_CHECK_CRC7)) { | |
258 | if (ptr[stat_idx] & SD_CRC7_ERR) { | |
259 | if (cmd_idx == WRITE_MULTIPLE_BLOCK) { | |
260 | sd_set_err_code(chip, SD_CRC_ERR); | |
261 | TRACE_RET(chip, STATUS_FAIL); | |
262 | } | |
263 | if (rty_cnt < SD_MAX_RETRY_COUNT) { | |
264 | wait_timeout(20); | |
265 | rty_cnt++; | |
266 | goto RTY_SEND_CMD; | |
267 | } else { | |
268 | sd_set_err_code(chip, SD_CRC_ERR); | |
269 | TRACE_RET(chip, STATUS_FAIL); | |
270 | } | |
271 | } | |
272 | } | |
273 | ||
274 | if ((rsp_type == SD_RSP_TYPE_R1) || (rsp_type == SD_RSP_TYPE_R1b)) { | |
275 | if ((cmd_idx != SEND_RELATIVE_ADDR) && (cmd_idx != SEND_IF_COND)) { | |
276 | if (cmd_idx != STOP_TRANSMISSION) { | |
277 | if (ptr[1] & 0x80) { | |
278 | TRACE_RET(chip, STATUS_FAIL); | |
279 | } | |
280 | } | |
281 | #ifdef SUPPORT_SD_LOCK | |
282 | if (ptr[1] & 0x7D) | |
283 | #else | |
284 | if (ptr[1] & 0x7F) | |
285 | #endif | |
286 | { | |
287 | RTSX_DEBUGP("ptr[1]: 0x%02x\n", ptr[1]); | |
288 | TRACE_RET(chip, STATUS_FAIL); | |
289 | } | |
290 | if (ptr[2] & 0xFF) { | |
291 | RTSX_DEBUGP("ptr[2]: 0x%02x\n", ptr[2]); | |
292 | TRACE_RET(chip, STATUS_FAIL); | |
293 | } | |
294 | if (ptr[3] & 0x80) { | |
295 | RTSX_DEBUGP("ptr[3]: 0x%02x\n", ptr[3]); | |
296 | TRACE_RET(chip, STATUS_FAIL); | |
297 | } | |
298 | if (ptr[3] & 0x01) { | |
299 | sd_card->sd_data_buf_ready = 1; | |
300 | } else { | |
301 | sd_card->sd_data_buf_ready = 0; | |
302 | } | |
303 | } | |
304 | } | |
305 | ||
306 | if (rsp && rsp_len) | |
307 | memcpy(rsp, ptr, rsp_len); | |
308 | ||
309 | return STATUS_SUCCESS; | |
310 | } | |
311 | ||
312 | static int sd_read_data(struct rtsx_chip *chip, | |
313 | u8 trans_mode, u8 *cmd, int cmd_len, u16 byte_cnt, | |
314 | u16 blk_cnt, u8 bus_width, u8 *buf, int buf_len, | |
315 | int timeout) | |
316 | { | |
317 | struct sd_info *sd_card = &(chip->sd_card); | |
318 | int retval; | |
319 | int i; | |
320 | ||
321 | sd_clr_err_code(chip); | |
322 | ||
323 | if (!buf) | |
324 | buf_len = 0; | |
325 | ||
326 | if (buf_len > 512) { | |
327 | TRACE_RET(chip, STATUS_FAIL); | |
328 | } | |
329 | ||
330 | rtsx_init_cmd(chip); | |
331 | ||
332 | if (cmd_len) { | |
333 | RTSX_DEBUGP("SD/MMC CMD %d\n", cmd[0] - 0x40); | |
334 | for (i = 0; i < (cmd_len < 6 ? cmd_len : 6); i++) { | |
335 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0 + i, 0xFF, cmd[i]); | |
336 | } | |
337 | } | |
338 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt); | |
339 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, (u8)(byte_cnt >> 8)); | |
340 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, (u8)blk_cnt); | |
341 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, (u8)(blk_cnt >> 8)); | |
342 | ||
343 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width); | |
344 | ||
345 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, | |
346 | SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END | | |
347 | SD_CHECK_CRC7 | SD_RSP_LEN_6); | |
348 | if (trans_mode != SD_TM_AUTO_TUNING) { | |
349 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER); | |
350 | } | |
351 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, trans_mode | SD_TRANSFER_START); | |
352 | rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END); | |
353 | ||
354 | retval = rtsx_send_cmd(chip, SD_CARD, timeout); | |
355 | if (retval < 0) { | |
356 | if (retval == -ETIMEDOUT) { | |
357 | sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, | |
358 | SD_RSP_TYPE_R1, NULL, 0); | |
359 | } | |
360 | ||
361 | TRACE_RET(chip, STATUS_FAIL); | |
362 | } | |
363 | ||
364 | if (buf && buf_len) { | |
365 | retval = rtsx_read_ppbuf(chip, buf, buf_len); | |
366 | if (retval != STATUS_SUCCESS) { | |
367 | TRACE_RET(chip, STATUS_FAIL); | |
368 | } | |
369 | } | |
370 | ||
371 | return STATUS_SUCCESS; | |
372 | } | |
373 | ||
374 | static int sd_write_data(struct rtsx_chip *chip, u8 trans_mode, | |
375 | u8 *cmd, int cmd_len, u16 byte_cnt, u16 blk_cnt, u8 bus_width, | |
376 | u8 *buf, int buf_len, int timeout) | |
377 | { | |
378 | struct sd_info *sd_card = &(chip->sd_card); | |
379 | int retval; | |
380 | int i; | |
381 | ||
382 | sd_clr_err_code(chip); | |
383 | ||
384 | if (!buf) | |
385 | buf_len = 0; | |
386 | ||
387 | if (buf_len > 512) { | |
388 | /* This function can't write data more than one page */ | |
389 | TRACE_RET(chip, STATUS_FAIL); | |
390 | } | |
391 | ||
392 | if (buf && buf_len) { | |
393 | retval = rtsx_write_ppbuf(chip, buf, buf_len); | |
394 | if (retval != STATUS_SUCCESS) { | |
395 | TRACE_RET(chip, STATUS_FAIL); | |
396 | } | |
397 | } | |
398 | ||
399 | rtsx_init_cmd(chip); | |
400 | ||
401 | if (cmd_len) { | |
402 | RTSX_DEBUGP("SD/MMC CMD %d\n", cmd[0] - 0x40); | |
403 | for (i = 0; i < (cmd_len < 6 ? cmd_len : 6); i++) { | |
404 | rtsx_add_cmd(chip, WRITE_REG_CMD, | |
405 | REG_SD_CMD0 + i, 0xFF, cmd[i]); | |
406 | } | |
407 | } | |
408 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt); | |
409 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, (u8)(byte_cnt >> 8)); | |
410 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, (u8)blk_cnt); | |
411 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, (u8)(blk_cnt >> 8)); | |
412 | ||
413 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width); | |
414 | ||
415 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, | |
416 | SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END | | |
417 | SD_CHECK_CRC7 | SD_RSP_LEN_6); | |
418 | ||
419 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, trans_mode | SD_TRANSFER_START); | |
420 | rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END); | |
421 | ||
422 | retval = rtsx_send_cmd(chip, SD_CARD, timeout); | |
423 | if (retval < 0) { | |
424 | if (retval == -ETIMEDOUT) { | |
425 | sd_send_cmd_get_rsp(chip, SEND_STATUS, | |
426 | sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0); | |
427 | } | |
428 | ||
429 | TRACE_RET(chip, STATUS_FAIL); | |
430 | } | |
431 | ||
432 | return STATUS_SUCCESS; | |
433 | } | |
434 | ||
435 | static int sd_check_csd(struct rtsx_chip *chip, char check_wp) | |
436 | { | |
437 | struct sd_info *sd_card = &(chip->sd_card); | |
438 | int retval; | |
439 | int i; | |
440 | u8 csd_ver, trans_speed; | |
441 | u8 rsp[16]; | |
442 | ||
443 | for (i = 0; i < 6; i++) { | |
444 | if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) { | |
445 | sd_set_err_code(chip, SD_NO_CARD); | |
446 | TRACE_RET(chip, STATUS_FAIL); | |
447 | } | |
448 | ||
449 | retval = sd_send_cmd_get_rsp(chip, SEND_CSD, sd_card->sd_addr, SD_RSP_TYPE_R2, rsp, 16); | |
450 | if (retval == STATUS_SUCCESS) | |
451 | break; | |
452 | } | |
453 | ||
454 | if (i == 6) { | |
455 | TRACE_RET(chip, STATUS_FAIL); | |
456 | } | |
457 | ||
458 | memcpy(sd_card->raw_csd, rsp + 1, 15); | |
459 | ||
460 | if (CHECK_PID(chip, 0x5209)) { | |
461 | RTSX_READ_REG(chip, REG_SD_CMD5, sd_card->raw_csd + 15); | |
462 | } | |
463 | ||
464 | RTSX_DEBUGP("CSD Response:\n"); | |
465 | RTSX_DUMP(sd_card->raw_csd, 16); | |
466 | ||
467 | csd_ver = (rsp[1] & 0xc0) >> 6; | |
468 | RTSX_DEBUGP("csd_ver = %d\n", csd_ver); | |
469 | ||
470 | trans_speed = rsp[4]; | |
471 | if ((trans_speed & 0x07) == 0x02) { | |
472 | if ((trans_speed & 0xf8) >= 0x30) { | |
473 | if (chip->asic_code) { | |
474 | sd_card->sd_clock = 47; | |
475 | } else { | |
476 | sd_card->sd_clock = CLK_50; | |
477 | } | |
478 | } else if ((trans_speed & 0xf8) == 0x28) { | |
479 | if (chip->asic_code) { | |
480 | sd_card->sd_clock = 39; | |
481 | } else { | |
482 | sd_card->sd_clock = CLK_40; | |
483 | } | |
484 | } else if ((trans_speed & 0xf8) == 0x20) { | |
485 | if (chip->asic_code) { | |
486 | sd_card->sd_clock = 29; | |
487 | } else { | |
488 | sd_card->sd_clock = CLK_30; | |
489 | } | |
490 | } else if ((trans_speed & 0xf8) >= 0x10) { | |
491 | if (chip->asic_code) { | |
492 | sd_card->sd_clock = 23; | |
493 | } else { | |
494 | sd_card->sd_clock = CLK_20; | |
495 | } | |
496 | } else if ((trans_speed & 0x08) >= 0x08) { | |
497 | if (chip->asic_code) { | |
498 | sd_card->sd_clock = 19; | |
499 | } else { | |
500 | sd_card->sd_clock = CLK_20; | |
501 | } | |
502 | } else { | |
503 | TRACE_RET(chip, STATUS_FAIL); | |
504 | } | |
505 | } else { | |
506 | TRACE_RET(chip, STATUS_FAIL); | |
507 | } | |
508 | ||
509 | if (CHK_MMC_SECTOR_MODE(sd_card)) { | |
510 | sd_card->capacity = 0; | |
511 | } else { | |
512 | if ((!CHK_SD_HCXC(sd_card)) || (csd_ver == 0)) { | |
513 | u8 blk_size, c_size_mult; | |
514 | u16 c_size; | |
515 | blk_size = rsp[6] & 0x0F; | |
516 | c_size = ((u16)(rsp[7] & 0x03) << 10) | |
517 | + ((u16)rsp[8] << 2) | |
518 | + ((u16)(rsp[9] & 0xC0) >> 6); | |
519 | c_size_mult = (u8)((rsp[10] & 0x03) << 1); | |
520 | c_size_mult += (rsp[11] & 0x80) >> 7; | |
521 | sd_card->capacity = (((u32)(c_size + 1)) * (1 << (c_size_mult + 2))) << (blk_size - 9); | |
522 | } else { | |
523 | u32 total_sector = 0; | |
524 | total_sector = (((u32)rsp[8] & 0x3f) << 16) | | |
525 | ((u32)rsp[9] << 8) | (u32)rsp[10]; | |
526 | sd_card->capacity = (total_sector + 1) << 10; | |
527 | } | |
528 | } | |
529 | ||
530 | if (check_wp) { | |
531 | if (rsp[15] & 0x30) { | |
532 | chip->card_wp |= SD_CARD; | |
533 | } | |
534 | RTSX_DEBUGP("CSD WP Status: 0x%x\n", rsp[15]); | |
535 | } | |
536 | ||
537 | return STATUS_SUCCESS; | |
538 | } | |
539 | ||
540 | static int sd_set_sample_push_timing(struct rtsx_chip *chip) | |
541 | { | |
542 | struct sd_info *sd_card = &(chip->sd_card); | |
543 | ||
544 | if (CHECK_PID(chip, 0x5209)) { | |
545 | if (CHK_SD_SDR104(sd_card) || CHK_SD_SDR50(sd_card)) { | |
546 | RTSX_WRITE_REG(chip, SD_CFG1, 0x0C | SD_ASYNC_FIFO_NOT_RST, | |
547 | SD_30_MODE | SD_ASYNC_FIFO_NOT_RST); | |
548 | RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ); | |
549 | RTSX_WRITE_REG(chip, CARD_CLK_SOURCE, 0xFF, | |
550 | CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1); | |
551 | RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, 0); | |
552 | } else if (CHK_SD_DDR50(sd_card) || CHK_MMC_DDR52(sd_card)) { | |
553 | RTSX_WRITE_REG(chip, SD_CFG1, 0x0C | SD_ASYNC_FIFO_NOT_RST, | |
554 | SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST); | |
555 | RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ); | |
556 | RTSX_WRITE_REG(chip, CARD_CLK_SOURCE, 0xFF, | |
557 | CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1); | |
558 | RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, 0); | |
559 | RTSX_WRITE_REG(chip, SD_PUSH_POINT_CTL, DDR_VAR_TX_CMD_DAT, | |
560 | DDR_VAR_TX_CMD_DAT); | |
561 | RTSX_WRITE_REG(chip, SD_SAMPLE_POINT_CTL, DDR_VAR_RX_DAT | DDR_VAR_RX_CMD, | |
562 | DDR_VAR_RX_DAT | DDR_VAR_RX_CMD); | |
563 | } else { | |
564 | u8 val = 0; | |
565 | ||
566 | RTSX_WRITE_REG(chip, SD_CFG1, 0x0C, SD_20_MODE); | |
567 | RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ); | |
568 | RTSX_WRITE_REG(chip, CARD_CLK_SOURCE, 0xFF, | |
569 | CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1); | |
570 | RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, 0); | |
571 | ||
572 | if ((chip->sd_ctl & SD_PUSH_POINT_CTL_MASK) == SD_PUSH_POINT_AUTO) { | |
573 | val = SD20_TX_NEG_EDGE; | |
574 | } else if ((chip->sd_ctl & SD_PUSH_POINT_CTL_MASK) == SD_PUSH_POINT_DELAY) { | |
575 | val = SD20_TX_14_AHEAD; | |
576 | } else { | |
577 | val = SD20_TX_NEG_EDGE; | |
578 | } | |
579 | RTSX_WRITE_REG(chip, SD_PUSH_POINT_CTL, SD20_TX_SEL_MASK, val); | |
580 | ||
581 | if ((chip->sd_ctl & SD_SAMPLE_POINT_CTL_MASK) == SD_SAMPLE_POINT_AUTO) { | |
582 | if (chip->asic_code) { | |
583 | if (CHK_SD_HS(sd_card) || CHK_MMC_52M(sd_card)) { | |
584 | val = SD20_RX_14_DELAY; | |
585 | } else { | |
586 | val = SD20_RX_POS_EDGE; | |
587 | } | |
588 | } else { | |
589 | val = SD20_RX_14_DELAY; | |
590 | } | |
591 | } else if ((chip->sd_ctl & SD_SAMPLE_POINT_CTL_MASK) == SD_SAMPLE_POINT_DELAY) { | |
592 | val = SD20_RX_14_DELAY; | |
593 | } else { | |
594 | val = SD20_RX_POS_EDGE; | |
595 | } | |
596 | RTSX_WRITE_REG(chip, SD_SAMPLE_POINT_CTL, SD20_RX_SEL_MASK, val); | |
597 | } | |
598 | } else { | |
599 | u8 val = 0; | |
600 | ||
601 | if ((chip->sd_ctl & SD_PUSH_POINT_CTL_MASK) == SD_PUSH_POINT_DELAY) { | |
602 | val |= 0x10; | |
603 | } | |
604 | ||
605 | if ((chip->sd_ctl & SD_SAMPLE_POINT_CTL_MASK) == SD_SAMPLE_POINT_AUTO) { | |
606 | if (chip->asic_code) { | |
607 | if (CHK_SD_HS(sd_card) || CHK_MMC_52M(sd_card)) { | |
608 | if (val & 0x10) { | |
609 | val |= 0x04; | |
610 | } else { | |
611 | val |= 0x08; | |
612 | } | |
613 | } | |
614 | } else { | |
615 | if (val & 0x10) { | |
616 | val |= 0x04; | |
617 | } else { | |
618 | val |= 0x08; | |
619 | } | |
620 | } | |
621 | } else if ((chip->sd_ctl & SD_SAMPLE_POINT_CTL_MASK) == SD_SAMPLE_POINT_DELAY) { | |
622 | if (val & 0x10) { | |
623 | val |= 0x04; | |
624 | } else { | |
625 | val |= 0x08; | |
626 | } | |
627 | } | |
628 | ||
629 | RTSX_WRITE_REG(chip, REG_SD_CFG1, 0x1C, val); | |
630 | } | |
631 | ||
632 | return STATUS_SUCCESS; | |
633 | } | |
634 | ||
635 | static void sd_choose_proper_clock(struct rtsx_chip *chip) | |
636 | { | |
637 | struct sd_info *sd_card = &(chip->sd_card); | |
638 | ||
639 | if (CHK_SD_SDR104(sd_card)) { | |
640 | if (chip->asic_code) { | |
641 | sd_card->sd_clock = chip->asic_sd_sdr104_clk; | |
642 | } else { | |
643 | sd_card->sd_clock = chip->fpga_sd_sdr104_clk; | |
644 | } | |
645 | } else if (CHK_SD_DDR50(sd_card)) { | |
646 | if (chip->asic_code) { | |
647 | sd_card->sd_clock = chip->asic_sd_ddr50_clk; | |
648 | } else { | |
649 | sd_card->sd_clock = chip->fpga_sd_ddr50_clk; | |
650 | } | |
651 | } else if (CHK_SD_SDR50(sd_card)) { | |
652 | if (chip->asic_code) { | |
653 | sd_card->sd_clock = chip->asic_sd_sdr50_clk; | |
654 | } else { | |
655 | sd_card->sd_clock = chip->fpga_sd_sdr50_clk; | |
656 | } | |
657 | } else if (CHK_SD_HS(sd_card)) { | |
658 | if (chip->asic_code) { | |
659 | sd_card->sd_clock = chip->asic_sd_hs_clk; | |
660 | } else { | |
661 | sd_card->sd_clock = chip->fpga_sd_hs_clk; | |
662 | } | |
663 | } else if (CHK_MMC_52M(sd_card) || CHK_MMC_DDR52(sd_card)) { | |
664 | if (chip->asic_code) { | |
665 | sd_card->sd_clock = chip->asic_mmc_52m_clk; | |
666 | } else { | |
667 | sd_card->sd_clock = chip->fpga_mmc_52m_clk; | |
668 | } | |
669 | } else if (CHK_MMC_26M(sd_card)) { | |
670 | if (chip->asic_code) { | |
671 | sd_card->sd_clock = 48; | |
672 | } else { | |
673 | sd_card->sd_clock = CLK_50; | |
674 | } | |
675 | } | |
676 | } | |
677 | ||
678 | static int sd_set_clock_divider(struct rtsx_chip *chip, u8 clk_div) | |
679 | { | |
680 | u8 mask = 0, val = 0; | |
681 | ||
682 | if (CHECK_PID(chip, 0x5209)) { | |
683 | mask = SD_CLK_DIVIDE_MASK; | |
684 | val = clk_div; | |
685 | } else { | |
686 | mask = 0x60; | |
687 | if (clk_div == SD_CLK_DIVIDE_0) { | |
688 | val = 0x00; | |
689 | } else if (clk_div == SD_CLK_DIVIDE_128) { | |
690 | val = 0x40; | |
691 | } else if (clk_div == SD_CLK_DIVIDE_256) { | |
692 | val = 0x20; | |
693 | } | |
694 | } | |
695 | ||
696 | RTSX_WRITE_REG(chip, REG_SD_CFG1, mask, val); | |
697 | ||
698 | return STATUS_SUCCESS; | |
699 | } | |
700 | ||
701 | static int sd_set_init_para(struct rtsx_chip *chip) | |
702 | { | |
703 | struct sd_info *sd_card = &(chip->sd_card); | |
704 | int retval; | |
705 | ||
706 | retval = sd_set_sample_push_timing(chip); | |
707 | if (retval != STATUS_SUCCESS) { | |
708 | TRACE_RET(chip, STATUS_FAIL); | |
709 | } | |
710 | ||
711 | sd_choose_proper_clock(chip); | |
712 | ||
713 | retval = switch_clock(chip, sd_card->sd_clock); | |
714 | if (retval != STATUS_SUCCESS) { | |
715 | TRACE_RET(chip, STATUS_FAIL); | |
716 | } | |
717 | ||
718 | return STATUS_SUCCESS; | |
719 | } | |
720 | ||
721 | int sd_select_card(struct rtsx_chip *chip, int select) | |
722 | { | |
723 | struct sd_info *sd_card = &(chip->sd_card); | |
724 | int retval; | |
725 | u8 cmd_idx, cmd_type; | |
726 | u32 addr; | |
727 | ||
728 | if (select) { | |
729 | cmd_idx = SELECT_CARD; | |
730 | cmd_type = SD_RSP_TYPE_R1; | |
731 | addr = sd_card->sd_addr; | |
732 | } else { | |
733 | cmd_idx = DESELECT_CARD; | |
734 | cmd_type = SD_RSP_TYPE_R0; | |
735 | addr = 0; | |
736 | } | |
737 | ||
738 | retval = sd_send_cmd_get_rsp(chip, cmd_idx, addr, cmd_type, NULL, 0); | |
739 | if (retval != STATUS_SUCCESS) { | |
740 | TRACE_RET(chip, STATUS_FAIL); | |
741 | } | |
742 | ||
743 | return STATUS_SUCCESS; | |
744 | } | |
745 | ||
746 | #ifdef SUPPORT_SD_LOCK | |
747 | static int sd_update_lock_status(struct rtsx_chip *chip) | |
748 | { | |
749 | struct sd_info *sd_card = &(chip->sd_card); | |
750 | int retval; | |
751 | u8 rsp[5]; | |
752 | ||
753 | retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1, rsp, 5); | |
754 | if (retval != STATUS_SUCCESS) { | |
755 | TRACE_RET(chip, STATUS_FAIL); | |
756 | } | |
757 | ||
758 | if (rsp[1] & 0x02) { | |
759 | sd_card->sd_lock_status |= SD_LOCKED; | |
760 | } else { | |
761 | sd_card->sd_lock_status &= ~SD_LOCKED; | |
762 | } | |
763 | ||
764 | RTSX_DEBUGP("sd_card->sd_lock_status = 0x%x\n", sd_card->sd_lock_status); | |
765 | ||
766 | if (rsp[1] & 0x01) { | |
767 | TRACE_RET(chip, STATUS_FAIL); | |
768 | } | |
769 | ||
770 | return STATUS_SUCCESS; | |
771 | } | |
772 | #endif | |
773 | ||
774 | static int sd_wait_state_data_ready(struct rtsx_chip *chip, u8 state, u8 data_ready, int polling_cnt) | |
775 | { | |
776 | struct sd_info *sd_card = &(chip->sd_card); | |
777 | int retval, i; | |
778 | u8 rsp[5]; | |
779 | ||
780 | for (i = 0; i < polling_cnt; i++) { | |
781 | retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, | |
782 | sd_card->sd_addr, SD_RSP_TYPE_R1, rsp, 5); | |
783 | if (retval != STATUS_SUCCESS) { | |
784 | TRACE_RET(chip, STATUS_FAIL); | |
785 | } | |
786 | ||
787 | if (((rsp[3] & 0x1E) == state) && ((rsp[3] & 0x01) == data_ready)) { | |
788 | return STATUS_SUCCESS; | |
789 | } | |
790 | } | |
791 | ||
792 | TRACE_RET(chip, STATUS_FAIL); | |
793 | } | |
794 | ||
795 | static int sd_change_bank_voltage(struct rtsx_chip *chip, u8 voltage) | |
796 | { | |
797 | int retval; | |
798 | ||
799 | if (voltage == SD_IO_3V3) { | |
800 | if (chip->asic_code) { | |
801 | retval = rtsx_write_phy_register(chip, 0x08, 0x4FC0 | chip->phy_voltage); | |
802 | if (retval != STATUS_SUCCESS) { | |
803 | TRACE_RET(chip, STATUS_FAIL); | |
804 | } | |
805 | } else { | |
806 | RTSX_WRITE_REG(chip, SD_PAD_CTL, SD_IO_USING_1V8, 0); | |
807 | } | |
808 | } else if (voltage == SD_IO_1V8) { | |
809 | if (chip->asic_code) { | |
810 | retval = rtsx_write_phy_register(chip, 0x08, 0x4C40 | chip->phy_voltage); | |
811 | if (retval != STATUS_SUCCESS) { | |
812 | TRACE_RET(chip, STATUS_FAIL); | |
813 | } | |
814 | } else { | |
815 | RTSX_WRITE_REG(chip, SD_PAD_CTL, SD_IO_USING_1V8, SD_IO_USING_1V8); | |
816 | } | |
817 | } else { | |
818 | TRACE_RET(chip, STATUS_FAIL); | |
819 | } | |
820 | ||
821 | return STATUS_SUCCESS; | |
822 | } | |
823 | ||
824 | static int sd_voltage_switch(struct rtsx_chip *chip) | |
825 | { | |
826 | int retval; | |
827 | u8 stat; | |
828 | ||
829 | RTSX_WRITE_REG(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, SD_CLK_TOGGLE_EN); | |
830 | ||
831 | retval = sd_send_cmd_get_rsp(chip, VOLTAGE_SWITCH, 0, SD_RSP_TYPE_R1, NULL, 0); | |
832 | if (retval != STATUS_SUCCESS) { | |
833 | TRACE_RET(chip, STATUS_FAIL); | |
834 | } | |
835 | ||
836 | udelay(chip->sd_voltage_switch_delay); | |
837 | ||
838 | RTSX_READ_REG(chip, SD_BUS_STAT, &stat); | |
839 | if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | | |
840 | SD_DAT1_STATUS | SD_DAT0_STATUS)) { | |
841 | TRACE_RET(chip, STATUS_FAIL); | |
842 | } | |
843 | ||
844 | RTSX_WRITE_REG(chip, SD_BUS_STAT, 0xFF, SD_CLK_FORCE_STOP); | |
845 | retval = sd_change_bank_voltage(chip, SD_IO_1V8); | |
846 | if (retval != STATUS_SUCCESS) { | |
847 | TRACE_RET(chip, STATUS_FAIL); | |
848 | } | |
849 | wait_timeout(50); | |
850 | ||
851 | RTSX_WRITE_REG(chip, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN); | |
852 | wait_timeout(10); | |
853 | ||
854 | RTSX_READ_REG(chip, SD_BUS_STAT, &stat); | |
855 | if ((stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | | |
856 | SD_DAT1_STATUS | SD_DAT0_STATUS)) != | |
857 | (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | | |
858 | SD_DAT1_STATUS | SD_DAT0_STATUS)) { | |
859 | RTSX_DEBUGP("SD_BUS_STAT: 0x%x\n", stat); | |
860 | rtsx_write_register(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); | |
861 | rtsx_write_register(chip, CARD_CLK_EN, 0xFF, 0); | |
862 | TRACE_RET(chip, STATUS_FAIL); | |
863 | } | |
864 | ||
865 | RTSX_WRITE_REG(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); | |
866 | ||
867 | return STATUS_SUCCESS; | |
868 | } | |
869 | ||
870 | static int sd_reset_dcm(struct rtsx_chip *chip, u8 tune_dir) | |
871 | { | |
872 | if (tune_dir == TUNE_RX) { | |
873 | RTSX_WRITE_REG(chip, DCM_DRP_CTL, 0xFF, DCM_RESET | DCM_RX); | |
874 | RTSX_WRITE_REG(chip, DCM_DRP_CTL, 0xFF, DCM_RX); | |
875 | } else { | |
876 | RTSX_WRITE_REG(chip, DCM_DRP_CTL, 0xFF, DCM_RESET | DCM_TX); | |
877 | RTSX_WRITE_REG(chip, DCM_DRP_CTL, 0xFF, DCM_TX); | |
878 | } | |
879 | ||
880 | return STATUS_SUCCESS; | |
881 | } | |
882 | ||
883 | static int sd_change_phase(struct rtsx_chip *chip, u8 sample_point, u8 tune_dir) | |
884 | { | |
885 | struct sd_info *sd_card = &(chip->sd_card); | |
886 | u16 SD_VP_CTL, SD_DCMPS_CTL; | |
887 | u8 val; | |
888 | int retval; | |
889 | int ddr_rx = 0; | |
890 | ||
891 | RTSX_DEBUGP("sd_change_phase (sample_point = %d, tune_dir = %d)\n", | |
892 | sample_point, tune_dir); | |
893 | ||
894 | if (tune_dir == TUNE_RX) { | |
895 | SD_VP_CTL = SD_VPRX_CTL; | |
896 | SD_DCMPS_CTL = SD_DCMPS_RX_CTL; | |
897 | if (CHK_SD_DDR50(sd_card)) { | |
898 | ddr_rx = 1; | |
899 | } | |
900 | } else { | |
901 | SD_VP_CTL = SD_VPTX_CTL; | |
902 | SD_DCMPS_CTL = SD_DCMPS_TX_CTL; | |
903 | } | |
904 | ||
905 | if (chip->asic_code) { | |
906 | RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, CHANGE_CLK); | |
907 | RTSX_WRITE_REG(chip, SD_VP_CTL, 0x1F, sample_point); | |
908 | RTSX_WRITE_REG(chip, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0); | |
909 | RTSX_WRITE_REG(chip, SD_VPCLK0_CTL, PHASE_NOT_RESET, PHASE_NOT_RESET); | |
910 | RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, 0); | |
911 | } else { | |
912 | #if CONFIG_RTS_PSTOR_DEBUG | |
913 | rtsx_read_register(chip, SD_VP_CTL, &val); | |
914 | RTSX_DEBUGP("SD_VP_CTL: 0x%x\n", val); | |
915 | rtsx_read_register(chip, SD_DCMPS_CTL, &val); | |
916 | RTSX_DEBUGP("SD_DCMPS_CTL: 0x%x\n", val); | |
917 | #endif | |
918 | ||
919 | if (ddr_rx) { | |
920 | RTSX_WRITE_REG(chip, SD_VP_CTL, PHASE_CHANGE, PHASE_CHANGE); | |
921 | udelay(50); | |
922 | RTSX_WRITE_REG(chip, SD_VP_CTL, 0xFF, | |
923 | PHASE_CHANGE | PHASE_NOT_RESET | sample_point); | |
924 | } else { | |
925 | RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, CHANGE_CLK); | |
926 | udelay(50); | |
927 | RTSX_WRITE_REG(chip, SD_VP_CTL, 0xFF, | |
928 | PHASE_NOT_RESET | sample_point); | |
929 | } | |
930 | udelay(100); | |
931 | ||
932 | rtsx_init_cmd(chip); | |
933 | rtsx_add_cmd(chip, WRITE_REG_CMD, SD_DCMPS_CTL, DCMPS_CHANGE, DCMPS_CHANGE); | |
934 | rtsx_add_cmd(chip, CHECK_REG_CMD, SD_DCMPS_CTL, DCMPS_CHANGE_DONE, DCMPS_CHANGE_DONE); | |
935 | retval = rtsx_send_cmd(chip, SD_CARD, 100); | |
936 | if (retval != STATUS_SUCCESS) { | |
937 | TRACE_GOTO(chip, Fail); | |
938 | } | |
939 | ||
940 | val = *rtsx_get_cmd_data(chip); | |
941 | if (val & DCMPS_ERROR) { | |
942 | TRACE_GOTO(chip, Fail); | |
943 | } | |
944 | if ((val & DCMPS_CURRENT_PHASE) != sample_point) { | |
945 | TRACE_GOTO(chip, Fail); | |
946 | } | |
947 | RTSX_WRITE_REG(chip, SD_DCMPS_CTL, DCMPS_CHANGE, 0); | |
948 | if (ddr_rx) { | |
949 | RTSX_WRITE_REG(chip, SD_VP_CTL, PHASE_CHANGE, 0); | |
950 | } else { | |
951 | RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, 0); | |
952 | } | |
953 | udelay(50); | |
954 | } | |
955 | ||
956 | RTSX_WRITE_REG(chip, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0); | |
957 | ||
958 | return STATUS_SUCCESS; | |
959 | ||
960 | Fail: | |
961 | #if CONFIG_RTS_PSTOR_DEBUG | |
962 | rtsx_read_register(chip, SD_VP_CTL, &val); | |
963 | RTSX_DEBUGP("SD_VP_CTL: 0x%x\n", val); | |
964 | rtsx_read_register(chip, SD_DCMPS_CTL, &val); | |
965 | RTSX_DEBUGP("SD_DCMPS_CTL: 0x%x\n", val); | |
966 | #endif | |
967 | ||
968 | rtsx_write_register(chip, SD_DCMPS_CTL, DCMPS_CHANGE, 0); | |
969 | rtsx_write_register(chip, SD_VP_CTL, PHASE_CHANGE, 0); | |
970 | wait_timeout(10); | |
971 | sd_reset_dcm(chip, tune_dir); | |
972 | return STATUS_FAIL; | |
973 | } | |
974 | ||
975 | static int sd_check_spec(struct rtsx_chip *chip, u8 bus_width) | |
976 | { | |
977 | struct sd_info *sd_card = &(chip->sd_card); | |
978 | int retval; | |
979 | u8 cmd[5], buf[8]; | |
980 | ||
981 | retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0); | |
982 | if (retval != STATUS_SUCCESS) { | |
983 | TRACE_RET(chip, STATUS_FAIL); | |
984 | } | |
985 | ||
986 | cmd[0] = 0x40 | SEND_SCR; | |
987 | cmd[1] = 0; | |
988 | cmd[2] = 0; | |
989 | cmd[3] = 0; | |
990 | cmd[4] = 0; | |
991 | ||
992 | retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 8, 1, bus_width, buf, 8, 250); | |
993 | if (retval != STATUS_SUCCESS) { | |
994 | rtsx_clear_sd_error(chip); | |
995 | TRACE_RET(chip, STATUS_FAIL); | |
996 | } | |
997 | ||
998 | memcpy(sd_card->raw_scr, buf, 8); | |
999 | ||
1000 | if ((buf[0] & 0x0F) == 0) { | |
1001 | TRACE_RET(chip, STATUS_FAIL); | |
1002 | } | |
1003 | ||
1004 | return STATUS_SUCCESS; | |
1005 | } | |
1006 | ||
1007 | static int sd_query_switch_result(struct rtsx_chip *chip, u8 func_group, u8 func_to_switch, | |
1008 | u8 *buf, int buf_len) | |
1009 | { | |
1010 | u8 support_mask = 0, query_switch = 0, switch_busy = 0; | |
1011 | int support_offset = 0, query_switch_offset = 0, check_busy_offset = 0; | |
1012 | ||
1013 | if (func_group == SD_FUNC_GROUP_1) { | |
1014 | support_offset = FUNCTION_GROUP1_SUPPORT_OFFSET; | |
1015 | query_switch_offset = FUNCTION_GROUP1_QUERY_SWITCH_OFFSET; | |
1016 | check_busy_offset = FUNCTION_GROUP1_CHECK_BUSY_OFFSET; | |
1017 | ||
1018 | switch (func_to_switch) { | |
1019 | case HS_SUPPORT: | |
1020 | support_mask = HS_SUPPORT_MASK; | |
1021 | query_switch = HS_QUERY_SWITCH_OK; | |
1022 | switch_busy = HS_SWITCH_BUSY; | |
1023 | break; | |
1024 | ||
1025 | case SDR50_SUPPORT: | |
1026 | support_mask = SDR50_SUPPORT_MASK; | |
1027 | query_switch = SDR50_QUERY_SWITCH_OK; | |
1028 | switch_busy = SDR50_SWITCH_BUSY; | |
1029 | break; | |
1030 | ||
1031 | case SDR104_SUPPORT: | |
1032 | support_mask = SDR104_SUPPORT_MASK; | |
1033 | query_switch = SDR104_QUERY_SWITCH_OK; | |
1034 | switch_busy = SDR104_SWITCH_BUSY; | |
1035 | break; | |
1036 | ||
1037 | case DDR50_SUPPORT: | |
1038 | support_mask = DDR50_SUPPORT_MASK; | |
1039 | query_switch = DDR50_QUERY_SWITCH_OK; | |
1040 | switch_busy = DDR50_SWITCH_BUSY; | |
1041 | break; | |
1042 | ||
1043 | default: | |
1044 | TRACE_RET(chip, STATUS_FAIL); | |
1045 | } | |
1046 | } else if (func_group == SD_FUNC_GROUP_3) { | |
1047 | support_offset = FUNCTION_GROUP3_SUPPORT_OFFSET; | |
1048 | query_switch_offset = FUNCTION_GROUP3_QUERY_SWITCH_OFFSET; | |
1049 | check_busy_offset = FUNCTION_GROUP3_CHECK_BUSY_OFFSET; | |
1050 | ||
1051 | switch (func_to_switch) { | |
1052 | case DRIVING_TYPE_A: | |
1053 | support_mask = DRIVING_TYPE_A_MASK; | |
1054 | query_switch = TYPE_A_QUERY_SWITCH_OK; | |
1055 | switch_busy = TYPE_A_SWITCH_BUSY; | |
1056 | break; | |
1057 | ||
1058 | case DRIVING_TYPE_C: | |
1059 | support_mask = DRIVING_TYPE_C_MASK; | |
1060 | query_switch = TYPE_C_QUERY_SWITCH_OK; | |
1061 | switch_busy = TYPE_C_SWITCH_BUSY; | |
1062 | break; | |
1063 | ||
1064 | case DRIVING_TYPE_D: | |
1065 | support_mask = DRIVING_TYPE_D_MASK; | |
1066 | query_switch = TYPE_D_QUERY_SWITCH_OK; | |
1067 | switch_busy = TYPE_D_SWITCH_BUSY; | |
1068 | break; | |
1069 | ||
1070 | default: | |
1071 | TRACE_RET(chip, STATUS_FAIL); | |
1072 | } | |
1073 | } else if (func_group == SD_FUNC_GROUP_4) { | |
1074 | support_offset = FUNCTION_GROUP4_SUPPORT_OFFSET; | |
1075 | query_switch_offset = FUNCTION_GROUP4_QUERY_SWITCH_OFFSET; | |
1076 | check_busy_offset = FUNCTION_GROUP4_CHECK_BUSY_OFFSET; | |
1077 | ||
1078 | switch (func_to_switch) { | |
1079 | case CURRENT_LIMIT_400: | |
1080 | support_mask = CURRENT_LIMIT_400_MASK; | |
1081 | query_switch = CURRENT_LIMIT_400_QUERY_SWITCH_OK; | |
1082 | switch_busy = CURRENT_LIMIT_400_SWITCH_BUSY; | |
1083 | break; | |
1084 | ||
1085 | case CURRENT_LIMIT_600: | |
1086 | support_mask = CURRENT_LIMIT_600_MASK; | |
1087 | query_switch = CURRENT_LIMIT_600_QUERY_SWITCH_OK; | |
1088 | switch_busy = CURRENT_LIMIT_600_SWITCH_BUSY; | |
1089 | break; | |
1090 | ||
1091 | case CURRENT_LIMIT_800: | |
1092 | support_mask = CURRENT_LIMIT_800_MASK; | |
1093 | query_switch = CURRENT_LIMIT_800_QUERY_SWITCH_OK; | |
1094 | switch_busy = CURRENT_LIMIT_800_SWITCH_BUSY; | |
1095 | break; | |
1096 | ||
1097 | default: | |
1098 | TRACE_RET(chip, STATUS_FAIL); | |
1099 | } | |
1100 | } else { | |
1101 | TRACE_RET(chip, STATUS_FAIL); | |
1102 | } | |
1103 | ||
1104 | if (func_group == SD_FUNC_GROUP_1) { | |
1105 | if (!(buf[support_offset] & support_mask) || | |
1106 | ((buf[query_switch_offset] & 0x0F) != query_switch)) { | |
1107 | TRACE_RET(chip, STATUS_FAIL); | |
1108 | } | |
1109 | } | |
1110 | ||
1111 | /* Check 'Busy Status' */ | |
1112 | if ((buf[DATA_STRUCTURE_VER_OFFSET] == 0x01) && | |
1113 | ((buf[check_busy_offset] & switch_busy) == switch_busy)) { | |
1114 | TRACE_RET(chip, STATUS_FAIL); | |
1115 | } | |
1116 | ||
1117 | return STATUS_SUCCESS; | |
1118 | } | |
1119 | ||
1120 | static int sd_check_switch_mode(struct rtsx_chip *chip, u8 mode, | |
1121 | u8 func_group, u8 func_to_switch, u8 bus_width) | |
1122 | { | |
1123 | struct sd_info *sd_card = &(chip->sd_card); | |
1124 | int retval; | |
1125 | u8 cmd[5], buf[64]; | |
1126 | ||
1127 | RTSX_DEBUGP("sd_check_switch_mode (mode = %d, func_group = %d, func_to_switch = %d)\n", | |
1128 | mode, func_group, func_to_switch); | |
1129 | ||
1130 | cmd[0] = 0x40 | SWITCH; | |
1131 | cmd[1] = mode; | |
1132 | ||
1133 | if (func_group == SD_FUNC_GROUP_1) { | |
1134 | cmd[2] = 0xFF; | |
1135 | cmd[3] = 0xFF; | |
1136 | cmd[4] = 0xF0 + func_to_switch; | |
1137 | } else if (func_group == SD_FUNC_GROUP_3) { | |
1138 | cmd[2] = 0xFF; | |
1139 | cmd[3] = 0xF0 + func_to_switch; | |
1140 | cmd[4] = 0xFF; | |
1141 | } else if (func_group == SD_FUNC_GROUP_4) { | |
1142 | cmd[2] = 0xFF; | |
1143 | cmd[3] = 0x0F + (func_to_switch << 4); | |
1144 | cmd[4] = 0xFF; | |
1145 | } else { | |
1146 | cmd[1] = SD_CHECK_MODE; | |
1147 | cmd[2] = 0xFF; | |
1148 | cmd[3] = 0xFF; | |
1149 | cmd[4] = 0xFF; | |
1150 | } | |
1151 | ||
1152 | retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 64, 1, bus_width, buf, 64, 250); | |
1153 | if (retval != STATUS_SUCCESS) { | |
1154 | rtsx_clear_sd_error(chip); | |
1155 | TRACE_RET(chip, STATUS_FAIL); | |
1156 | } | |
1157 | ||
1158 | RTSX_DUMP(buf, 64); | |
1159 | ||
1160 | if (func_group == NO_ARGUMENT) { | |
1161 | sd_card->func_group1_mask = buf[0x0D]; | |
1162 | sd_card->func_group2_mask = buf[0x0B]; | |
1163 | sd_card->func_group3_mask = buf[0x09]; | |
1164 | sd_card->func_group4_mask = buf[0x07]; | |
1165 | ||
1166 | RTSX_DEBUGP("func_group1_mask = 0x%02x\n", buf[0x0D]); | |
1167 | RTSX_DEBUGP("func_group2_mask = 0x%02x\n", buf[0x0B]); | |
1168 | RTSX_DEBUGP("func_group3_mask = 0x%02x\n", buf[0x09]); | |
1169 | RTSX_DEBUGP("func_group4_mask = 0x%02x\n", buf[0x07]); | |
1170 | } else { | |
1171 | /* Maximum current consumption, check whether current is acceptable; | |
1172 | * bit[511:496] = 0x0000 means some error happaned. | |
1173 | */ | |
1174 | u16 cc = ((u16)buf[0] << 8) | buf[1]; | |
1175 | RTSX_DEBUGP("Maximum current consumption: %dmA\n", cc); | |
1176 | if ((cc == 0) || (cc > 800)) { | |
1177 | TRACE_RET(chip, STATUS_FAIL); | |
1178 | } | |
1179 | retval = sd_query_switch_result(chip, func_group, func_to_switch, buf, 64); | |
1180 | if (retval != STATUS_SUCCESS) { | |
1181 | TRACE_RET(chip, STATUS_FAIL); | |
1182 | } | |
1183 | ||
1184 | if ((cc > 400) || (func_to_switch > CURRENT_LIMIT_400)) { | |
1185 | RTSX_WRITE_REG(chip, OCPPARA2, SD_OCP_THD_MASK, chip->sd_800mA_ocp_thd); | |
1186 | RTSX_WRITE_REG(chip, CARD_PWR_CTL, PMOS_STRG_MASK, PMOS_STRG_800mA); | |
1187 | } | |
1188 | } | |
1189 | ||
1190 | return STATUS_SUCCESS; | |
1191 | } | |
1192 | ||
1193 | static u8 downgrade_switch_mode(u8 func_group, u8 func_to_switch) | |
1194 | { | |
1195 | if (func_group == SD_FUNC_GROUP_1) { | |
1196 | if (func_to_switch > HS_SUPPORT) { | |
1197 | func_to_switch--; | |
1198 | } | |
1199 | } else if (func_group == SD_FUNC_GROUP_4) { | |
1200 | if (func_to_switch > CURRENT_LIMIT_200) { | |
1201 | func_to_switch--; | |
1202 | } | |
1203 | } | |
1204 | ||
1205 | return func_to_switch; | |
1206 | } | |
1207 | ||
1208 | static int sd_check_switch(struct rtsx_chip *chip, | |
1209 | u8 func_group, u8 func_to_switch, u8 bus_width) | |
1210 | { | |
1211 | int retval; | |
1212 | int i; | |
1213 | int switch_good = 0; | |
1214 | ||
1215 | for (i = 0; i < 3; i++) { | |
1216 | if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) { | |
1217 | sd_set_err_code(chip, SD_NO_CARD); | |
1218 | TRACE_RET(chip, STATUS_FAIL); | |
1219 | } | |
1220 | ||
1221 | retval = sd_check_switch_mode(chip, SD_CHECK_MODE, func_group, | |
1222 | func_to_switch, bus_width); | |
1223 | if (retval == STATUS_SUCCESS) { | |
1224 | u8 stat; | |
1225 | ||
1226 | retval = sd_check_switch_mode(chip, SD_SWITCH_MODE, | |
1227 | func_group, func_to_switch, bus_width); | |
1228 | if (retval == STATUS_SUCCESS) { | |
1229 | switch_good = 1; | |
1230 | break; | |
1231 | } | |
1232 | ||
1233 | RTSX_READ_REG(chip, SD_STAT1, &stat); | |
1234 | if (stat & SD_CRC16_ERR) { | |
1235 | RTSX_DEBUGP("SD CRC16 error when switching mode\n"); | |
1236 | TRACE_RET(chip, STATUS_FAIL); | |
1237 | } | |
1238 | } | |
1239 | ||
1240 | func_to_switch = downgrade_switch_mode(func_group, func_to_switch); | |
1241 | ||
1242 | wait_timeout(20); | |
1243 | } | |
1244 | ||
1245 | if (!switch_good) { | |
1246 | TRACE_RET(chip, STATUS_FAIL); | |
1247 | } | |
1248 | ||
1249 | return STATUS_SUCCESS; | |
1250 | } | |
1251 | ||
1252 | static int sd_switch_function(struct rtsx_chip *chip, u8 bus_width) | |
1253 | { | |
1254 | struct sd_info *sd_card = &(chip->sd_card); | |
1255 | int retval; | |
1256 | int i; | |
1257 | u8 func_to_switch = 0; | |
1258 | ||
1259 | /* Get supported functions */ | |
1260 | retval = sd_check_switch_mode(chip, SD_CHECK_MODE, | |
1261 | NO_ARGUMENT, NO_ARGUMENT, bus_width); | |
1262 | if (retval != STATUS_SUCCESS) { | |
1263 | TRACE_RET(chip, STATUS_FAIL); | |
1264 | } | |
1265 | ||
1266 | sd_card->func_group1_mask &= ~(sd_card->sd_switch_fail); | |
1267 | ||
2d2322b2 | 1268 | /* Function Group 1: Access Mode */ |
77d89b08 | 1269 | for (i = 0; i < 4; i++) { |
1270 | switch ((u8)(chip->sd_speed_prior >> (i*8))) { | |
1271 | case SDR104_SUPPORT: | |
1272 | if ((sd_card->func_group1_mask & SDR104_SUPPORT_MASK) | |
1273 | && chip->sdr104_en) { | |
1274 | func_to_switch = SDR104_SUPPORT; | |
1275 | } | |
1276 | break; | |
1277 | ||
1278 | case DDR50_SUPPORT: | |
1279 | if ((sd_card->func_group1_mask & DDR50_SUPPORT_MASK) | |
1280 | && chip->ddr50_en) { | |
1281 | func_to_switch = DDR50_SUPPORT; | |
1282 | } | |
1283 | break; | |
1284 | ||
1285 | case SDR50_SUPPORT: | |
1286 | if ((sd_card->func_group1_mask & SDR50_SUPPORT_MASK) | |
1287 | && chip->sdr50_en) { | |
1288 | func_to_switch = SDR50_SUPPORT; | |
1289 | } | |
1290 | break; | |
1291 | ||
1292 | case HS_SUPPORT: | |
1293 | if (sd_card->func_group1_mask & HS_SUPPORT_MASK) { | |
1294 | func_to_switch = HS_SUPPORT; | |
1295 | } | |
1296 | break; | |
1297 | ||
1298 | default: | |
1299 | continue; | |
1300 | } | |
1301 | ||
1302 | ||
1303 | if (func_to_switch) { | |
1304 | break; | |
1305 | } | |
1306 | } | |
1307 | RTSX_DEBUGP("SD_FUNC_GROUP_1: func_to_switch = 0x%02x", func_to_switch); | |
1308 | ||
1309 | #ifdef SUPPORT_SD_LOCK | |
1310 | if ((sd_card->sd_lock_status & SD_SDR_RST) | |
1311 | && (DDR50_SUPPORT == func_to_switch) | |
1312 | && (sd_card->func_group1_mask & SDR50_SUPPORT_MASK)) { | |
1313 | func_to_switch = SDR50_SUPPORT; | |
1314 | RTSX_DEBUGP("Using SDR50 instead of DDR50 for SD Lock\n"); | |
1315 | } | |
1316 | #endif | |
1317 | ||
1318 | if (func_to_switch) { | |
1319 | retval = sd_check_switch(chip, SD_FUNC_GROUP_1, func_to_switch, bus_width); | |
1320 | if (retval != STATUS_SUCCESS) { | |
1321 | if (func_to_switch == SDR104_SUPPORT) { | |
1322 | sd_card->sd_switch_fail = SDR104_SUPPORT_MASK; | |
1323 | } else if (func_to_switch == DDR50_SUPPORT) { | |
1324 | sd_card->sd_switch_fail = | |
1325 | SDR104_SUPPORT_MASK | DDR50_SUPPORT_MASK; | |
1326 | } else if (func_to_switch == SDR50_SUPPORT) { | |
1327 | sd_card->sd_switch_fail = | |
1328 | SDR104_SUPPORT_MASK | DDR50_SUPPORT_MASK | | |
1329 | SDR50_SUPPORT_MASK; | |
1330 | } | |
1331 | TRACE_RET(chip, STATUS_FAIL); | |
1332 | } | |
1333 | ||
1334 | if (func_to_switch == SDR104_SUPPORT) { | |
1335 | SET_SD_SDR104(sd_card); | |
1336 | } else if (func_to_switch == DDR50_SUPPORT) { | |
1337 | SET_SD_DDR50(sd_card); | |
1338 | } else if (func_to_switch == SDR50_SUPPORT) { | |
1339 | SET_SD_SDR50(sd_card); | |
1340 | } else { | |
1341 | SET_SD_HS(sd_card); | |
1342 | } | |
1343 | } | |
1344 | ||
1345 | if (CHK_SD_DDR50(sd_card)) { | |
1346 | RTSX_WRITE_REG(chip, SD_PUSH_POINT_CTL, 0x06, 0x04); | |
1347 | retval = sd_set_sample_push_timing(chip); | |
1348 | if (retval != STATUS_SUCCESS) { | |
1349 | TRACE_RET(chip, STATUS_FAIL); | |
1350 | } | |
1351 | } | |
1352 | ||
2d2322b2 | 1353 | if (!func_to_switch || (func_to_switch == HS_SUPPORT)) { |
1354 | /* Do not try to switch current limit if the card doesn't | |
1355 | * support UHS mode or we don't want it to support UHS mode | |
1356 | */ | |
1357 | return STATUS_SUCCESS; | |
1358 | } | |
1359 | ||
1360 | /* Function Group 4: Current Limit */ | |
77d89b08 | 1361 | func_to_switch = 0xFF; |
1362 | ||
1363 | for (i = 0; i < 4; i++) { | |
1364 | switch ((u8)(chip->sd_current_prior >> (i*8))) { | |
1365 | case CURRENT_LIMIT_800: | |
1366 | if (sd_card->func_group4_mask & CURRENT_LIMIT_800_MASK) { | |
1367 | func_to_switch = CURRENT_LIMIT_800; | |
1368 | } | |
1369 | break; | |
1370 | ||
1371 | case CURRENT_LIMIT_600: | |
1372 | if (sd_card->func_group4_mask & CURRENT_LIMIT_600_MASK) { | |
1373 | func_to_switch = CURRENT_LIMIT_600; | |
1374 | } | |
1375 | break; | |
1376 | ||
1377 | case CURRENT_LIMIT_400: | |
1378 | if (sd_card->func_group4_mask & CURRENT_LIMIT_400_MASK) { | |
1379 | func_to_switch = CURRENT_LIMIT_400; | |
1380 | } | |
1381 | break; | |
1382 | ||
1383 | case CURRENT_LIMIT_200: | |
1384 | if (sd_card->func_group4_mask & CURRENT_LIMIT_200_MASK) { | |
1385 | func_to_switch = CURRENT_LIMIT_200; | |
1386 | } | |
1387 | break; | |
1388 | ||
1389 | default: | |
1390 | continue; | |
1391 | } | |
1392 | ||
1393 | if (func_to_switch != 0xFF) { | |
1394 | break; | |
1395 | } | |
1396 | } | |
1397 | ||
1398 | RTSX_DEBUGP("SD_FUNC_GROUP_4: func_to_switch = 0x%02x", func_to_switch); | |
1399 | ||
1400 | if (func_to_switch <= CURRENT_LIMIT_800) { | |
1401 | retval = sd_check_switch(chip, SD_FUNC_GROUP_4, func_to_switch, bus_width); | |
1402 | if (retval != STATUS_SUCCESS) { | |
1403 | if (sd_check_err_code(chip, SD_NO_CARD)) { | |
1404 | TRACE_RET(chip, STATUS_FAIL); | |
1405 | } | |
1406 | } | |
1407 | RTSX_DEBUGP("Switch current limit finished! (%d)\n", retval); | |
1408 | } | |
1409 | ||
1410 | if (CHK_SD_DDR50(sd_card)) { | |
1411 | RTSX_WRITE_REG(chip, SD_PUSH_POINT_CTL, 0x06, 0); | |
1412 | } | |
1413 | ||
1414 | return STATUS_SUCCESS; | |
1415 | } | |
1416 | ||
1417 | static int sd_wait_data_idle(struct rtsx_chip *chip) | |
1418 | { | |
1419 | int retval = STATUS_TIMEDOUT; | |
1420 | int i; | |
1421 | u8 val = 0; | |
1422 | ||
1423 | for (i = 0; i < 100; i++) { | |
1424 | RTSX_READ_REG(chip, SD_DATA_STATE, &val); | |
1425 | if (val & SD_DATA_IDLE) { | |
1426 | retval = STATUS_SUCCESS; | |
1427 | break; | |
1428 | } | |
1429 | udelay(100); | |
1430 | } | |
1431 | RTSX_DEBUGP("SD_DATA_STATE: 0x%02x\n", val); | |
1432 | ||
1433 | return retval; | |
1434 | } | |
1435 | ||
1436 | static int sd_sdr_tuning_rx_cmd(struct rtsx_chip *chip, u8 sample_point) | |
1437 | { | |
1438 | int retval; | |
1439 | u8 cmd[5]; | |
1440 | ||
1441 | retval = sd_change_phase(chip, sample_point, TUNE_RX); | |
1442 | if (retval != STATUS_SUCCESS) { | |
1443 | TRACE_RET(chip, STATUS_FAIL); | |
1444 | } | |
1445 | ||
1446 | cmd[0] = 0x40 | SEND_TUNING_PATTERN; | |
1447 | cmd[1] = 0; | |
1448 | cmd[2] = 0; | |
1449 | cmd[3] = 0; | |
1450 | cmd[4] = 0; | |
1451 | ||
1452 | retval = sd_read_data(chip, SD_TM_AUTO_TUNING, | |
1453 | cmd, 5, 0x40, 1, SD_BUS_WIDTH_4, NULL, 0, 100); | |
1454 | if (retval != STATUS_SUCCESS) { | |
1455 | (void)sd_wait_data_idle(chip); | |
1456 | ||
1457 | rtsx_clear_sd_error(chip); | |
1458 | TRACE_RET(chip, STATUS_FAIL); | |
1459 | } | |
1460 | ||
1461 | return STATUS_SUCCESS; | |
1462 | } | |
1463 | ||
1464 | static int sd_ddr_tuning_rx_cmd(struct rtsx_chip *chip, u8 sample_point) | |
1465 | { | |
1466 | struct sd_info *sd_card = &(chip->sd_card); | |
1467 | int retval; | |
1468 | u8 cmd[5]; | |
1469 | ||
1470 | retval = sd_change_phase(chip, sample_point, TUNE_RX); | |
1471 | if (retval != STATUS_SUCCESS) { | |
1472 | TRACE_RET(chip, STATUS_FAIL); | |
1473 | } | |
1474 | ||
1475 | RTSX_DEBUGP("sd ddr tuning rx\n"); | |
1476 | ||
1477 | retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0); | |
1478 | if (retval != STATUS_SUCCESS) { | |
1479 | TRACE_RET(chip, STATUS_FAIL); | |
1480 | } | |
1481 | ||
1482 | cmd[0] = 0x40 | SD_STATUS; | |
1483 | cmd[1] = 0; | |
1484 | cmd[2] = 0; | |
1485 | cmd[3] = 0; | |
1486 | cmd[4] = 0; | |
1487 | ||
1488 | retval = sd_read_data(chip, SD_TM_NORMAL_READ, | |
1489 | cmd, 5, 64, 1, SD_BUS_WIDTH_4, NULL, 0, 100); | |
1490 | if (retval != STATUS_SUCCESS) { | |
1491 | (void)sd_wait_data_idle(chip); | |
1492 | ||
1493 | rtsx_clear_sd_error(chip); | |
1494 | TRACE_RET(chip, STATUS_FAIL); | |
1495 | } | |
1496 | ||
1497 | return STATUS_SUCCESS; | |
1498 | } | |
1499 | ||
1500 | static int mmc_ddr_tunning_rx_cmd(struct rtsx_chip *chip, u8 sample_point) | |
1501 | { | |
1502 | struct sd_info *sd_card = &(chip->sd_card); | |
1503 | int retval; | |
1504 | u8 cmd[5], bus_width; | |
1505 | ||
1506 | if (CHK_MMC_8BIT(sd_card)) { | |
1507 | bus_width = SD_BUS_WIDTH_8; | |
1508 | } else if (CHK_MMC_4BIT(sd_card)) { | |
1509 | bus_width = SD_BUS_WIDTH_4; | |
1510 | } else { | |
1511 | bus_width = SD_BUS_WIDTH_1; | |
1512 | } | |
1513 | ||
1514 | retval = sd_change_phase(chip, sample_point, TUNE_RX); | |
1515 | if (retval != STATUS_SUCCESS) { | |
1516 | TRACE_RET(chip, STATUS_FAIL); | |
1517 | } | |
1518 | ||
1519 | RTSX_DEBUGP("mmc ddr tuning rx\n"); | |
1520 | ||
1521 | cmd[0] = 0x40 | SEND_EXT_CSD; | |
1522 | cmd[1] = 0; | |
1523 | cmd[2] = 0; | |
1524 | cmd[3] = 0; | |
1525 | cmd[4] = 0; | |
1526 | ||
1527 | retval = sd_read_data(chip, SD_TM_NORMAL_READ, | |
1528 | cmd, 5, 0x200, 1, bus_width, NULL, 0, 100); | |
1529 | if (retval != STATUS_SUCCESS) { | |
1530 | (void)sd_wait_data_idle(chip); | |
1531 | ||
1532 | rtsx_clear_sd_error(chip); | |
1533 | TRACE_RET(chip, STATUS_FAIL); | |
1534 | } | |
1535 | ||
1536 | return STATUS_SUCCESS; | |
1537 | } | |
1538 | ||
1539 | static int sd_sdr_tuning_tx_cmd(struct rtsx_chip *chip, u8 sample_point) | |
1540 | { | |
1541 | struct sd_info *sd_card = &(chip->sd_card); | |
1542 | int retval; | |
1543 | ||
1544 | retval = sd_change_phase(chip, sample_point, TUNE_TX); | |
1545 | if (retval != STATUS_SUCCESS) { | |
1546 | TRACE_RET(chip, STATUS_FAIL); | |
1547 | } | |
1548 | ||
1549 | RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, SD_RSP_80CLK_TIMEOUT_EN); | |
1550 | ||
1551 | retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, | |
1552 | SD_RSP_TYPE_R1, NULL, 0); | |
1553 | if (retval != STATUS_SUCCESS) { | |
1554 | if (sd_check_err_code(chip, SD_RSP_TIMEOUT)) { | |
1555 | rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0); | |
1556 | TRACE_RET(chip, STATUS_FAIL); | |
1557 | } | |
1558 | } | |
1559 | ||
1560 | RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0); | |
1561 | ||
1562 | return STATUS_SUCCESS; | |
1563 | } | |
1564 | ||
1565 | static int sd_ddr_tuning_tx_cmd(struct rtsx_chip *chip, u8 sample_point) | |
1566 | { | |
1567 | struct sd_info *sd_card = &(chip->sd_card); | |
1568 | int retval; | |
1569 | u8 cmd[5], bus_width; | |
1570 | ||
1571 | retval = sd_change_phase(chip, sample_point, TUNE_TX); | |
1572 | if (retval != STATUS_SUCCESS) { | |
1573 | TRACE_RET(chip, STATUS_FAIL); | |
1574 | } | |
1575 | ||
1576 | if (CHK_SD(sd_card)) { | |
1577 | bus_width = SD_BUS_WIDTH_4; | |
1578 | } else { | |
1579 | if (CHK_MMC_8BIT(sd_card)) { | |
1580 | bus_width = SD_BUS_WIDTH_8; | |
1581 | } else if (CHK_MMC_4BIT(sd_card)) { | |
1582 | bus_width = SD_BUS_WIDTH_4; | |
1583 | } else { | |
1584 | bus_width = SD_BUS_WIDTH_1; | |
1585 | } | |
1586 | } | |
1587 | ||
1588 | retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000); | |
1589 | if (retval != STATUS_SUCCESS) { | |
1590 | TRACE_RET(chip, STATUS_FAIL); | |
1591 | } | |
1592 | ||
1593 | RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, SD_RSP_80CLK_TIMEOUT_EN); | |
1594 | ||
1595 | cmd[0] = 0x40 | PROGRAM_CSD; | |
1596 | cmd[1] = 0; | |
1597 | cmd[2] = 0; | |
1598 | cmd[3] = 0; | |
1599 | cmd[4] = 0; | |
1600 | ||
1601 | retval = sd_write_data(chip, SD_TM_AUTO_WRITE_2, | |
1602 | cmd, 5, 16, 1, bus_width, sd_card->raw_csd, 16, 100); | |
1603 | if (retval != STATUS_SUCCESS) { | |
1604 | rtsx_clear_sd_error(chip); | |
1605 | rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0); | |
1606 | TRACE_RET(chip, STATUS_FAIL); | |
1607 | } | |
1608 | ||
1609 | RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0); | |
1610 | ||
1611 | sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0); | |
1612 | ||
1613 | return STATUS_SUCCESS; | |
1614 | } | |
1615 | ||
1616 | static u8 sd_search_final_phase(struct rtsx_chip *chip, u32 phase_map, u8 tune_dir) | |
1617 | { | |
1618 | struct sd_info *sd_card = &(chip->sd_card); | |
1619 | struct timing_phase_path path[MAX_PHASE + 1]; | |
1620 | int i, j, cont_path_cnt; | |
1621 | int new_block, max_len, final_path_idx; | |
1622 | u8 final_phase = 0xFF; | |
1623 | ||
1624 | if (phase_map == 0xFFFFFFFF) { | |
1625 | if (tune_dir == TUNE_RX) { | |
1626 | final_phase = (u8)chip->sd_default_rx_phase; | |
1627 | } else { | |
1628 | final_phase = (u8)chip->sd_default_tx_phase; | |
1629 | } | |
1630 | ||
1631 | goto Search_Finish; | |
1632 | } | |
1633 | ||
1634 | cont_path_cnt = 0; | |
1635 | new_block = 1; | |
1636 | j = 0; | |
1637 | for (i = 0; i < MAX_PHASE + 1; i++) { | |
1638 | if (phase_map & (1 << i)) { | |
1639 | if (new_block) { | |
1640 | new_block = 0; | |
1641 | j = cont_path_cnt++; | |
1642 | path[j].start = i; | |
1643 | path[j].end = i; | |
1644 | } else { | |
1645 | path[j].end = i; | |
1646 | } | |
1647 | } else { | |
1648 | new_block = 1; | |
1649 | if (cont_path_cnt) { | |
1650 | int idx = cont_path_cnt - 1; | |
1651 | path[idx].len = path[idx].end - path[idx].start + 1; | |
1652 | path[idx].mid = path[idx].start + path[idx].len / 2; | |
1653 | } | |
1654 | } | |
1655 | } | |
1656 | ||
1657 | if (cont_path_cnt == 0) { | |
1658 | RTSX_DEBUGP("No continuous phase path\n"); | |
1659 | goto Search_Finish; | |
1660 | } else { | |
1661 | int idx = cont_path_cnt - 1; | |
1662 | path[idx].len = path[idx].end - path[idx].start + 1; | |
1663 | path[idx].mid = path[idx].start + path[idx].len / 2; | |
1664 | } | |
1665 | ||
1666 | if ((path[0].start == 0) && (path[cont_path_cnt - 1].end == MAX_PHASE)) { | |
1667 | path[0].start = path[cont_path_cnt - 1].start - MAX_PHASE - 1; | |
1668 | path[0].len += path[cont_path_cnt - 1].len; | |
1669 | path[0].mid = path[0].start + path[0].len / 2; | |
1670 | if (path[0].mid < 0) { | |
1671 | path[0].mid += MAX_PHASE + 1; | |
1672 | } | |
1673 | cont_path_cnt--; | |
1674 | } | |
1675 | ||
1676 | max_len = 0; | |
1677 | final_phase = 0; | |
1678 | final_path_idx = 0; | |
1679 | for (i = 0; i < cont_path_cnt; i++) { | |
1680 | if (path[i].len > max_len) { | |
1681 | max_len = path[i].len; | |
1682 | final_phase = (u8)path[i].mid; | |
1683 | final_path_idx = i; | |
1684 | } | |
1685 | ||
1686 | RTSX_DEBUGP("path[%d].start = %d\n", i, path[i].start); | |
1687 | RTSX_DEBUGP("path[%d].end = %d\n", i, path[i].end); | |
1688 | RTSX_DEBUGP("path[%d].len = %d\n", i, path[i].len); | |
1689 | RTSX_DEBUGP("path[%d].mid = %d\n", i, path[i].mid); | |
1690 | RTSX_DEBUGP("\n"); | |
1691 | } | |
1692 | ||
1693 | if (tune_dir == TUNE_TX) { | |
1694 | if (CHK_SD_SDR104(sd_card)) { | |
1695 | if (max_len > 15) { | |
1696 | int temp_mid = (max_len - 16) / 2; | |
1697 | int temp_final_phase = | |
1698 | path[final_path_idx].end - (max_len - (6 + temp_mid)); | |
1699 | ||
1700 | if (temp_final_phase < 0) { | |
1701 | final_phase = (u8)(temp_final_phase + MAX_PHASE + 1); | |
1702 | } else { | |
1703 | final_phase = (u8)temp_final_phase; | |
1704 | } | |
1705 | } | |
1706 | } else if (CHK_SD_SDR50(sd_card)) { | |
1707 | if (max_len > 12) { | |
1708 | int temp_mid = (max_len - 13) / 2; | |
1709 | int temp_final_phase = | |
1710 | path[final_path_idx].end - (max_len - (3 + temp_mid)); | |
1711 | ||
1712 | if (temp_final_phase < 0) { | |
1713 | final_phase = (u8)(temp_final_phase + MAX_PHASE + 1); | |
1714 | } else { | |
1715 | final_phase = (u8)temp_final_phase; | |
1716 | } | |
1717 | } | |
1718 | } | |
1719 | } | |
1720 | ||
1721 | Search_Finish: | |
25985edc | 1722 | RTSX_DEBUGP("Final chosen phase: %d\n", final_phase); |
77d89b08 | 1723 | return final_phase; |
1724 | } | |
1725 | ||
1726 | static int sd_tuning_rx(struct rtsx_chip *chip) | |
1727 | { | |
1728 | struct sd_info *sd_card = &(chip->sd_card); | |
1729 | int retval; | |
1730 | int i, j; | |
1731 | u32 raw_phase_map[3], phase_map; | |
1732 | u8 final_phase; | |
1733 | int (*tuning_cmd)(struct rtsx_chip *chip, u8 sample_point); | |
1734 | ||
1735 | if (CHK_SD(sd_card)) { | |
1736 | if (CHK_SD_DDR50(sd_card)) { | |
1737 | tuning_cmd = sd_ddr_tuning_rx_cmd; | |
1738 | } else { | |
1739 | tuning_cmd = sd_sdr_tuning_rx_cmd; | |
1740 | } | |
1741 | } else { | |
1742 | if (CHK_MMC_DDR52(sd_card)) { | |
1743 | tuning_cmd = mmc_ddr_tunning_rx_cmd; | |
1744 | } else { | |
1745 | TRACE_RET(chip, STATUS_FAIL); | |
1746 | } | |
1747 | } | |
1748 | ||
1749 | for (i = 0; i < 3; i++) { | |
1750 | raw_phase_map[i] = 0; | |
1751 | for (j = MAX_PHASE; j >= 0; j--) { | |
1752 | if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) { | |
1753 | sd_set_err_code(chip, SD_NO_CARD); | |
1754 | TRACE_RET(chip, STATUS_FAIL); | |
1755 | } | |
1756 | ||
1757 | retval = tuning_cmd(chip, (u8)j); | |
1758 | if (retval == STATUS_SUCCESS) { | |
1759 | raw_phase_map[i] |= 1 << j; | |
1760 | } | |
1761 | } | |
1762 | } | |
1763 | ||
1764 | phase_map = raw_phase_map[0] & raw_phase_map[1] & raw_phase_map[2]; | |
1765 | for (i = 0; i < 3; i++) { | |
1766 | RTSX_DEBUGP("RX raw_phase_map[%d] = 0x%08x\n", i, raw_phase_map[i]); | |
1767 | } | |
1768 | RTSX_DEBUGP("RX phase_map = 0x%08x\n", phase_map); | |
1769 | ||
1770 | final_phase = sd_search_final_phase(chip, phase_map, TUNE_RX); | |
1771 | if (final_phase == 0xFF) { | |
1772 | TRACE_RET(chip, STATUS_FAIL); | |
1773 | } | |
1774 | ||
1775 | retval = sd_change_phase(chip, final_phase, TUNE_RX); | |
1776 | if (retval != STATUS_SUCCESS) { | |
1777 | TRACE_RET(chip, STATUS_FAIL); | |
1778 | } | |
1779 | ||
1780 | return STATUS_SUCCESS; | |
1781 | } | |
1782 | ||
1783 | static int sd_ddr_pre_tuning_tx(struct rtsx_chip *chip) | |
1784 | { | |
1785 | struct sd_info *sd_card = &(chip->sd_card); | |
1786 | int retval; | |
1787 | int i; | |
1788 | u32 phase_map; | |
1789 | u8 final_phase; | |
1790 | ||
1791 | RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, SD_RSP_80CLK_TIMEOUT_EN); | |
1792 | ||
1793 | phase_map = 0; | |
1794 | for (i = MAX_PHASE; i >= 0; i--) { | |
1795 | if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) { | |
1796 | sd_set_err_code(chip, SD_NO_CARD); | |
1797 | rtsx_write_register(chip, SD_CFG3, | |
1798 | SD_RSP_80CLK_TIMEOUT_EN, 0); | |
1799 | TRACE_RET(chip, STATUS_FAIL); | |
1800 | } | |
1801 | ||
1802 | retval = sd_change_phase(chip, (u8)i, TUNE_TX); | |
1803 | if (retval != STATUS_SUCCESS) { | |
1804 | continue; | |
1805 | } | |
1806 | ||
1807 | retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, | |
1808 | SD_RSP_TYPE_R1, NULL, 0); | |
1809 | if ((retval == STATUS_SUCCESS) || !sd_check_err_code(chip, SD_RSP_TIMEOUT)) { | |
1810 | phase_map |= 1 << i; | |
1811 | } | |
1812 | } | |
1813 | ||
1814 | RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0); | |
1815 | ||
1816 | RTSX_DEBUGP("DDR TX pre tune phase_map = 0x%08x\n", phase_map); | |
1817 | ||
1818 | final_phase = sd_search_final_phase(chip, phase_map, TUNE_TX); | |
1819 | if (final_phase == 0xFF) { | |
1820 | TRACE_RET(chip, STATUS_FAIL); | |
1821 | } | |
1822 | ||
1823 | retval = sd_change_phase(chip, final_phase, TUNE_TX); | |
1824 | if (retval != STATUS_SUCCESS) { | |
1825 | TRACE_RET(chip, STATUS_FAIL); | |
1826 | } | |
1827 | ||
1828 | RTSX_DEBUGP("DDR TX pre tune phase: %d\n", (int)final_phase); | |
1829 | ||
1830 | return STATUS_SUCCESS; | |
1831 | } | |
1832 | ||
1833 | static int sd_tuning_tx(struct rtsx_chip *chip) | |
1834 | { | |
1835 | struct sd_info *sd_card = &(chip->sd_card); | |
1836 | int retval; | |
1837 | int i, j; | |
1838 | u32 raw_phase_map[3], phase_map; | |
1839 | u8 final_phase; | |
1840 | int (*tuning_cmd)(struct rtsx_chip *chip, u8 sample_point); | |
1841 | ||
1842 | if (CHK_SD(sd_card)) { | |
1843 | if (CHK_SD_DDR50(sd_card)) { | |
1844 | tuning_cmd = sd_ddr_tuning_tx_cmd; | |
1845 | } else { | |
1846 | tuning_cmd = sd_sdr_tuning_tx_cmd; | |
1847 | } | |
1848 | } else { | |
1849 | if (CHK_MMC_DDR52(sd_card)) { | |
1850 | tuning_cmd = sd_ddr_tuning_tx_cmd; | |
1851 | } else { | |
1852 | TRACE_RET(chip, STATUS_FAIL); | |
1853 | } | |
1854 | } | |
1855 | ||
1856 | for (i = 0; i < 3; i++) { | |
1857 | raw_phase_map[i] = 0; | |
1858 | for (j = MAX_PHASE; j >= 0; j--) { | |
1859 | if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) { | |
1860 | sd_set_err_code(chip, SD_NO_CARD); | |
1861 | rtsx_write_register(chip, SD_CFG3, | |
1862 | SD_RSP_80CLK_TIMEOUT_EN, 0); | |
1863 | TRACE_RET(chip, STATUS_FAIL); | |
1864 | } | |
1865 | ||
1866 | retval = tuning_cmd(chip, (u8)j); | |
1867 | if (retval == STATUS_SUCCESS) { | |
1868 | raw_phase_map[i] |= 1 << j; | |
1869 | } | |
1870 | } | |
1871 | } | |
1872 | ||
1873 | phase_map = raw_phase_map[0] & raw_phase_map[1] & raw_phase_map[2]; | |
1874 | for (i = 0; i < 3; i++) { | |
1875 | RTSX_DEBUGP("TX raw_phase_map[%d] = 0x%08x\n", i, raw_phase_map[i]); | |
1876 | } | |
1877 | RTSX_DEBUGP("TX phase_map = 0x%08x\n", phase_map); | |
1878 | ||
1879 | final_phase = sd_search_final_phase(chip, phase_map, TUNE_TX); | |
1880 | if (final_phase == 0xFF) { | |
1881 | TRACE_RET(chip, STATUS_FAIL); | |
1882 | } | |
1883 | ||
1884 | retval = sd_change_phase(chip, final_phase, TUNE_TX); | |
1885 | if (retval != STATUS_SUCCESS) { | |
1886 | TRACE_RET(chip, STATUS_FAIL); | |
1887 | } | |
1888 | ||
1889 | return STATUS_SUCCESS; | |
1890 | } | |
1891 | ||
1892 | static int sd_sdr_tuning(struct rtsx_chip *chip) | |
1893 | { | |
1894 | int retval; | |
1895 | ||
1896 | retval = sd_tuning_tx(chip); | |
1897 | if (retval != STATUS_SUCCESS) { | |
1898 | TRACE_RET(chip, STATUS_FAIL); | |
1899 | } | |
1900 | ||
1901 | retval = sd_tuning_rx(chip); | |
1902 | if (retval != STATUS_SUCCESS) { | |
1903 | TRACE_RET(chip, STATUS_FAIL); | |
1904 | } | |
1905 | ||
1906 | return STATUS_SUCCESS; | |
1907 | } | |
1908 | ||
1909 | static int sd_ddr_tuning(struct rtsx_chip *chip) | |
1910 | { | |
1911 | int retval; | |
1912 | ||
1913 | if (!(chip->sd_ctl & SD_DDR_TX_PHASE_SET_BY_USER)) { | |
1914 | retval = sd_ddr_pre_tuning_tx(chip); | |
1915 | if (retval != STATUS_SUCCESS) { | |
1916 | TRACE_RET(chip, STATUS_FAIL); | |
1917 | } | |
1918 | } else { | |
1919 | retval = sd_change_phase(chip, (u8)chip->sd_ddr_tx_phase, TUNE_TX); | |
1920 | if (retval != STATUS_SUCCESS) { | |
1921 | TRACE_RET(chip, STATUS_FAIL); | |
1922 | } | |
1923 | } | |
1924 | ||
1925 | retval = sd_tuning_rx(chip); | |
1926 | if (retval != STATUS_SUCCESS) { | |
1927 | TRACE_RET(chip, STATUS_FAIL); | |
1928 | } | |
1929 | ||
1930 | if (!(chip->sd_ctl & SD_DDR_TX_PHASE_SET_BY_USER)) { | |
1931 | retval = sd_tuning_tx(chip); | |
1932 | if (retval != STATUS_SUCCESS) { | |
1933 | TRACE_RET(chip, STATUS_FAIL); | |
1934 | } | |
1935 | } | |
1936 | ||
1937 | return STATUS_SUCCESS; | |
1938 | } | |
1939 | ||
1940 | static int mmc_ddr_tuning(struct rtsx_chip *chip) | |
1941 | { | |
1942 | int retval; | |
1943 | ||
1944 | if (!(chip->sd_ctl & MMC_DDR_TX_PHASE_SET_BY_USER)) { | |
1945 | retval = sd_ddr_pre_tuning_tx(chip); | |
1946 | if (retval != STATUS_SUCCESS) { | |
1947 | TRACE_RET(chip, STATUS_FAIL); | |
1948 | } | |
1949 | } else { | |
1950 | retval = sd_change_phase(chip, (u8)chip->mmc_ddr_tx_phase, TUNE_TX); | |
1951 | if (retval != STATUS_SUCCESS) { | |
1952 | TRACE_RET(chip, STATUS_FAIL); | |
1953 | } | |
1954 | } | |
1955 | ||
1956 | retval = sd_tuning_rx(chip); | |
1957 | if (retval != STATUS_SUCCESS) { | |
1958 | TRACE_RET(chip, STATUS_FAIL); | |
1959 | } | |
1960 | ||
1961 | if (!(chip->sd_ctl & MMC_DDR_TX_PHASE_SET_BY_USER)) { | |
1962 | retval = sd_tuning_tx(chip); | |
1963 | if (retval != STATUS_SUCCESS) { | |
1964 | TRACE_RET(chip, STATUS_FAIL); | |
1965 | } | |
1966 | } | |
1967 | ||
1968 | return STATUS_SUCCESS; | |
1969 | } | |
1970 | ||
1971 | int sd_switch_clock(struct rtsx_chip *chip) | |
1972 | { | |
1973 | struct sd_info *sd_card = &(chip->sd_card); | |
1974 | int retval; | |
1975 | int re_tuning = 0; | |
1976 | ||
1977 | retval = select_card(chip, SD_CARD); | |
1978 | if (retval != STATUS_SUCCESS) { | |
1979 | TRACE_RET(chip, STATUS_FAIL); | |
1980 | } | |
1981 | ||
1982 | if (CHECK_PID(chip, 0x5209) && | |
1983 | (CHK_SD30_SPEED(sd_card) || CHK_MMC_DDR52(sd_card))) { | |
1984 | if (sd_card->need_retune && (sd_card->sd_clock != chip->cur_clk)) { | |
1985 | re_tuning = 1; | |
1986 | sd_card->need_retune = 0; | |
1987 | } | |
1988 | } | |
1989 | ||
1990 | retval = switch_clock(chip, sd_card->sd_clock); | |
1991 | if (retval != STATUS_SUCCESS) { | |
1992 | TRACE_RET(chip, STATUS_FAIL); | |
1993 | } | |
1994 | ||
1995 | if (re_tuning) { | |
1996 | if (CHK_SD(sd_card)) { | |
1997 | if (CHK_SD_DDR50(sd_card)) { | |
1998 | retval = sd_ddr_tuning(chip); | |
1999 | } else { | |
2000 | retval = sd_sdr_tuning(chip); | |
2001 | } | |
2002 | } else { | |
2003 | if (CHK_MMC_DDR52(sd_card)) { | |
2004 | retval = mmc_ddr_tuning(chip); | |
2005 | } | |
2006 | } | |
2007 | ||
2008 | if (retval != STATUS_SUCCESS) { | |
2009 | TRACE_RET(chip, STATUS_FAIL); | |
2010 | } | |
2011 | } | |
2012 | ||
2013 | return STATUS_SUCCESS; | |
2014 | } | |
2015 | ||
2016 | static int sd_prepare_reset(struct rtsx_chip *chip) | |
2017 | { | |
2018 | struct sd_info *sd_card = &(chip->sd_card); | |
2019 | int retval; | |
2020 | ||
2021 | if (chip->asic_code) { | |
2022 | sd_card->sd_clock = 29; | |
2023 | } else { | |
2024 | sd_card->sd_clock = CLK_30; | |
2025 | } | |
2026 | ||
2d2322b2 | 2027 | sd_card->sd_type = 0; |
2028 | sd_card->seq_mode = 0; | |
2029 | sd_card->sd_data_buf_ready = 0; | |
2030 | sd_card->capacity = 0; | |
2031 | ||
2032 | #ifdef SUPPORT_SD_LOCK | |
2033 | sd_card->sd_lock_status = 0; | |
2034 | sd_card->sd_erase_status = 0; | |
2035 | #endif | |
2036 | ||
2037 | chip->capacity[chip->card2lun[SD_CARD]] = 0; | |
77d89b08 | 2038 | chip->sd_io = 0; |
2039 | ||
2040 | retval = sd_set_init_para(chip); | |
2041 | if (retval != STATUS_SUCCESS) { | |
2042 | TRACE_RET(chip, retval); | |
2043 | } | |
2044 | ||
2045 | if (CHECK_PID(chip, 0x5209)) { | |
2046 | RTSX_WRITE_REG(chip, REG_SD_CFG1, 0xFF, | |
2047 | SD_CLK_DIVIDE_128 | SD_20_MODE | SD_BUS_WIDTH_1); | |
2048 | RTSX_WRITE_REG(chip, SD_SAMPLE_POINT_CTL, 0xFF, SD20_RX_POS_EDGE); | |
2049 | RTSX_WRITE_REG(chip, SD_PUSH_POINT_CTL, 0xFF, 0); | |
2050 | } else { | |
2051 | RTSX_WRITE_REG(chip, REG_SD_CFG1, 0xFF, 0x40); | |
2052 | } | |
2053 | ||
2054 | RTSX_WRITE_REG(chip, CARD_STOP, SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR); | |
2055 | ||
2056 | retval = select_card(chip, SD_CARD); | |
2057 | if (retval != STATUS_SUCCESS) { | |
2058 | TRACE_RET(chip, STATUS_FAIL); | |
2059 | } | |
2060 | ||
2061 | return STATUS_SUCCESS; | |
2062 | } | |
2063 | ||
2064 | static int sd_pull_ctl_disable(struct rtsx_chip *chip) | |
2065 | { | |
2066 | if (CHECK_PID(chip, 0x5209)) { | |
2067 | RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, 0x55); | |
2068 | RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF, 0x55); | |
2069 | RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF, 0xD5); | |
2070 | } else if (CHECK_PID(chip, 0x5208)) { | |
2071 | RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, | |
2072 | XD_D3_PD | SD_D7_PD | SD_CLK_PD | SD_D5_PD); | |
2073 | RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF, | |
2074 | SD_D6_PD | SD_D0_PD | SD_D1_PD | XD_D5_PD); | |
2075 | RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF, | |
2076 | SD_D4_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU); | |
2077 | RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF, | |
2078 | XD_RDY_PD | SD_D3_PD | SD_D2_PD | XD_ALE_PD); | |
2079 | RTSX_WRITE_REG(chip, CARD_PULL_CTL5, 0xFF, | |
2080 | MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD); | |
2081 | RTSX_WRITE_REG(chip, CARD_PULL_CTL6, 0xFF, MS_D5_PD | MS_D4_PD); | |
2082 | } else if (CHECK_PID(chip, 0x5288)) { | |
2083 | if (CHECK_BARO_PKG(chip, QFN)) { | |
2084 | RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, 0x55); | |
2085 | RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF, 0x55); | |
2086 | RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF, 0x4B); | |
2087 | RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF, 0x69); | |
2088 | } | |
2089 | } | |
2090 | ||
2091 | return STATUS_SUCCESS; | |
2092 | } | |
2093 | ||
2094 | int sd_pull_ctl_enable(struct rtsx_chip *chip) | |
2095 | { | |
2096 | int retval; | |
2097 | ||
2098 | rtsx_init_cmd(chip); | |
2099 | ||
2100 | if (CHECK_PID(chip, 0x5209)) { | |
2101 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0xAA); | |
2102 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0xAA); | |
2103 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0xE9); | |
2104 | } else if (CHECK_PID(chip, 0x5208)) { | |
2105 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, | |
2106 | XD_D3_PD | SD_DAT7_PU | SD_CLK_NP | SD_D5_PU); | |
2107 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, | |
2108 | SD_D6_PU | SD_D0_PU | SD_D1_PU | XD_D5_PD); | |
2109 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, | |
2110 | SD_D4_PU | XD_CE_PD | XD_CLE_PD | XD_CD_PU); | |
2111 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, | |
2112 | XD_RDY_PD | SD_D3_PU | SD_D2_PU | XD_ALE_PD); | |
2113 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, | |
2114 | MS_INS_PU | SD_WP_PU | SD_CD_PU | SD_CMD_PU); | |
2115 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, MS_D5_PD | MS_D4_PD); | |
2116 | } else if (CHECK_PID(chip, 0x5288)) { | |
2117 | if (CHECK_BARO_PKG(chip, QFN)) { | |
2118 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0xA8); | |
2119 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x5A); | |
2120 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95); | |
2121 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0xAA); | |
2122 | } | |
2123 | } | |
2124 | ||
2125 | retval = rtsx_send_cmd(chip, SD_CARD, 100); | |
2126 | if (retval < 0) { | |
2127 | TRACE_RET(chip, STATUS_FAIL); | |
2128 | } | |
2129 | ||
2130 | return STATUS_SUCCESS; | |
2131 | } | |
2132 | ||
2133 | static int sd_init_power(struct rtsx_chip *chip) | |
2134 | { | |
2135 | int retval; | |
2136 | ||
2137 | if (CHECK_PID(chip, 0x5209)) { | |
2138 | RTSX_WRITE_REG(chip, PWR_GATE_CTRL, LDO3318_PWR_MASK, LDO_OFF); | |
2139 | } | |
2140 | ||
2141 | retval = sd_power_off_card3v3(chip); | |
2142 | if (retval != STATUS_SUCCESS) { | |
2143 | TRACE_RET(chip, STATUS_FAIL); | |
2144 | } | |
2145 | ||
2146 | if (!chip->ft2_fast_mode) { | |
2147 | wait_timeout(250); | |
2148 | } | |
2149 | ||
2150 | retval = enable_card_clock(chip, SD_CARD); | |
2151 | if (retval != STATUS_SUCCESS) { | |
2152 | TRACE_RET(chip, STATUS_FAIL); | |
2153 | } | |
2154 | ||
2155 | if (chip->asic_code) { | |
2156 | retval = sd_pull_ctl_enable(chip); | |
2157 | if (retval != STATUS_SUCCESS) { | |
2158 | TRACE_RET(chip, STATUS_FAIL); | |
2159 | } | |
2160 | } else { | |
2161 | RTSX_WRITE_REG(chip, FPGA_PULL_CTL, FPGA_SD_PULL_CTL_BIT | 0x20, 0); | |
2162 | } | |
2163 | ||
2164 | if (chip->ft2_fast_mode) { | |
2165 | if (CHECK_PID(chip, 0x5209)) { | |
2166 | RTSX_WRITE_REG(chip, PWR_GATE_CTRL, LDO3318_PWR_MASK, LDO_ON); | |
2167 | } | |
2168 | } else { | |
2169 | retval = card_power_on(chip, SD_CARD); | |
2170 | if (retval != STATUS_SUCCESS) { | |
2171 | TRACE_RET(chip, STATUS_FAIL); | |
2172 | } | |
2173 | wait_timeout(260); | |
2174 | ||
2175 | #ifdef SUPPORT_OCP | |
2176 | if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) { | |
2177 | RTSX_DEBUGP("Over current, OCPSTAT is 0x%x\n", chip->ocp_stat); | |
2178 | TRACE_RET(chip, STATUS_FAIL); | |
2179 | } | |
2180 | #endif | |
2181 | } | |
2182 | ||
2183 | RTSX_WRITE_REG(chip, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN); | |
2184 | ||
2185 | return STATUS_SUCCESS; | |
2186 | } | |
2187 | ||
2188 | static int sd_dummy_clock(struct rtsx_chip *chip) | |
2189 | { | |
2190 | if (CHECK_PID(chip, 0x5209)) { | |
2191 | RTSX_WRITE_REG(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN, SD_CLK_TOGGLE_EN); | |
2192 | wait_timeout(5); | |
2193 | RTSX_WRITE_REG(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN, 0x00); | |
2194 | } else { | |
2195 | RTSX_WRITE_REG(chip, REG_SD_CFG3, 0x01, 0x01); | |
2196 | wait_timeout(5); | |
2197 | RTSX_WRITE_REG(chip, REG_SD_CFG3, 0x01, 0); | |
2198 | } | |
2199 | ||
2200 | return STATUS_SUCCESS; | |
2201 | } | |
2202 | ||
2203 | static int sd_read_lba0(struct rtsx_chip *chip) | |
2204 | { | |
2205 | struct sd_info *sd_card = &(chip->sd_card); | |
2206 | int retval; | |
2207 | u8 cmd[5], bus_width; | |
2208 | ||
2209 | cmd[0] = 0x40 | READ_SINGLE_BLOCK; | |
2210 | cmd[1] = 0; | |
2211 | cmd[2] = 0; | |
2212 | cmd[3] = 0; | |
2213 | cmd[4] = 0; | |
2214 | ||
2215 | if (CHK_SD(sd_card)) { | |
2216 | bus_width = SD_BUS_WIDTH_4; | |
2217 | } else { | |
2218 | if (CHK_MMC_8BIT(sd_card)) { | |
2219 | bus_width = SD_BUS_WIDTH_8; | |
2220 | } else if (CHK_MMC_4BIT(sd_card)) { | |
2221 | bus_width = SD_BUS_WIDTH_4; | |
2222 | } else { | |
2223 | bus_width = SD_BUS_WIDTH_1; | |
2224 | } | |
2225 | } | |
2226 | ||
2227 | retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, | |
2228 | 5, 512, 1, bus_width, NULL, 0, 100); | |
2229 | if (retval != STATUS_SUCCESS) { | |
2230 | TRACE_RET(chip, STATUS_FAIL); | |
2231 | } | |
2232 | ||
2233 | return STATUS_SUCCESS; | |
2234 | } | |
2235 | ||
2236 | static int sd_check_wp_state(struct rtsx_chip *chip) | |
2237 | { | |
2238 | struct sd_info *sd_card = &(chip->sd_card); | |
2239 | int retval; | |
2240 | u32 val; | |
2241 | u16 sd_card_type; | |
2242 | u8 cmd[5], buf[64]; | |
2243 | ||
2244 | retval = sd_send_cmd_get_rsp(chip, APP_CMD, | |
2245 | sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0); | |
2246 | if (retval != STATUS_SUCCESS) { | |
2247 | TRACE_RET(chip, STATUS_FAIL); | |
2248 | } | |
2249 | ||
2250 | cmd[0] = 0x40 | SD_STATUS; | |
2251 | cmd[1] = 0; | |
2252 | cmd[2] = 0; | |
2253 | cmd[3] = 0; | |
2254 | cmd[4] = 0; | |
2255 | ||
2256 | retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 64, 1, SD_BUS_WIDTH_4, buf, 64, 250); | |
2257 | if (retval != STATUS_SUCCESS) { | |
2258 | rtsx_clear_sd_error(chip); | |
2259 | ||
2260 | sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0); | |
2261 | TRACE_RET(chip, STATUS_FAIL); | |
2262 | } | |
2263 | ||
2264 | RTSX_DEBUGP("ACMD13:\n"); | |
2265 | RTSX_DUMP(buf, 64); | |
2266 | ||
2267 | sd_card_type = ((u16)buf[2] << 8) | buf[3]; | |
2268 | RTSX_DEBUGP("sd_card_type = 0x%04x\n", sd_card_type); | |
2269 | if ((sd_card_type == 0x0001) || (sd_card_type == 0x0002)) { | |
2270 | /* ROM card or OTP */ | |
2271 | chip->card_wp |= SD_CARD; | |
2272 | } | |
2273 | ||
2274 | /* Check SD Machanical Write-Protect Switch */ | |
2275 | val = rtsx_readl(chip, RTSX_BIPR); | |
2276 | if (val & SD_WRITE_PROTECT) { | |
2277 | chip->card_wp |= SD_CARD; | |
2278 | } | |
2279 | ||
2280 | return STATUS_SUCCESS; | |
2281 | } | |
2282 | ||
2283 | static int reset_sd(struct rtsx_chip *chip) | |
2284 | { | |
2285 | struct sd_info *sd_card = &(chip->sd_card); | |
2286 | int retval, i = 0, j = 0, k = 0, hi_cap_flow = 0; | |
2287 | int sd_dont_switch = 0; | |
2288 | int support_1v8 = 0; | |
2289 | int try_sdio = 1; | |
2290 | u8 rsp[16]; | |
2291 | u8 switch_bus_width; | |
2292 | u32 voltage = 0; | |
2293 | int sd20_mode = 0; | |
2294 | ||
2295 | SET_SD(sd_card); | |
2296 | ||
2297 | Switch_Fail: | |
2298 | ||
2299 | i = 0; | |
2300 | j = 0; | |
2301 | k = 0; | |
2302 | hi_cap_flow = 0; | |
2303 | ||
2304 | #ifdef SUPPORT_SD_LOCK | |
2305 | if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON) | |
2306 | goto SD_UNLOCK_ENTRY; | |
2307 | #endif | |
2308 | ||
2309 | retval = sd_prepare_reset(chip); | |
2310 | if (retval != STATUS_SUCCESS) { | |
2311 | TRACE_RET(chip, STATUS_FAIL); | |
2312 | } | |
2313 | ||
2314 | retval = sd_dummy_clock(chip); | |
2315 | if (retval != STATUS_SUCCESS) { | |
2316 | TRACE_RET(chip, STATUS_FAIL); | |
2317 | } | |
2318 | ||
2319 | if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip) && try_sdio) { | |
2320 | int rty_cnt = 0; | |
2321 | ||
2322 | for (; rty_cnt < chip->sdio_retry_cnt; rty_cnt++) { | |
2323 | if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) { | |
2324 | sd_set_err_code(chip, SD_NO_CARD); | |
2325 | TRACE_RET(chip, STATUS_FAIL); | |
2326 | } | |
2327 | ||
2328 | retval = sd_send_cmd_get_rsp(chip, IO_SEND_OP_COND, 0, SD_RSP_TYPE_R4, rsp, 5); | |
2329 | if (retval == STATUS_SUCCESS) { | |
2330 | int func_num = (rsp[1] >> 4) && 0x07; | |
2331 | if (func_num) { | |
2332 | RTSX_DEBUGP("SD_IO card (Function number: %d)!\n", func_num); | |
2333 | chip->sd_io = 1; | |
2334 | TRACE_RET(chip, STATUS_FAIL); | |
2335 | } | |
2336 | ||
2337 | break; | |
2338 | } | |
2339 | ||
2340 | sd_init_power(chip); | |
2341 | ||
2342 | sd_dummy_clock(chip); | |
2343 | } | |
2344 | ||
2345 | RTSX_DEBUGP("Normal card!\n"); | |
2346 | } | |
2347 | ||
2348 | /* Start Initialization Process of SD Card */ | |
2349 | RTY_SD_RST: | |
2350 | retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, SD_RSP_TYPE_R0, NULL, 0); | |
2351 | if (retval != STATUS_SUCCESS) { | |
2352 | TRACE_RET(chip, STATUS_FAIL); | |
2353 | } | |
2354 | ||
2355 | wait_timeout(20); | |
2356 | ||
2357 | retval = sd_send_cmd_get_rsp(chip, SEND_IF_COND, 0x000001AA, SD_RSP_TYPE_R7, rsp, 5); | |
2358 | if (retval == STATUS_SUCCESS) { | |
2359 | if ((rsp[4] == 0xAA) && ((rsp[3] & 0x0f) == 0x01)) { | |
2360 | hi_cap_flow = 1; | |
2361 | if (CHECK_PID(chip, 0x5209)) { | |
2362 | if (sd20_mode) { | |
2363 | voltage = SUPPORT_VOLTAGE | | |
2364 | SUPPORT_HIGH_AND_EXTENDED_CAPACITY; | |
2365 | } else { | |
2366 | voltage = SUPPORT_VOLTAGE | | |
2367 | SUPPORT_HIGH_AND_EXTENDED_CAPACITY | | |
2368 | SUPPORT_MAX_POWER_PERMANCE | SUPPORT_1V8; | |
2369 | } | |
2370 | } else { | |
2371 | voltage = SUPPORT_VOLTAGE | 0x40000000; | |
2372 | } | |
2373 | } | |
2374 | } | |
2375 | ||
2376 | if (!hi_cap_flow) { | |
2377 | voltage = SUPPORT_VOLTAGE; | |
2378 | ||
2379 | retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, SD_RSP_TYPE_R0, NULL, 0); | |
2380 | if (retval != STATUS_SUCCESS) { | |
2381 | TRACE_RET(chip, STATUS_FAIL); | |
2382 | } | |
2383 | ||
2384 | wait_timeout(20); | |
2385 | } | |
2386 | ||
2387 | do { | |
2388 | retval = sd_send_cmd_get_rsp(chip, APP_CMD, 0, SD_RSP_TYPE_R1, NULL, 0); | |
2389 | if (retval != STATUS_SUCCESS) { | |
2390 | if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) { | |
2391 | sd_set_err_code(chip, SD_NO_CARD); | |
2392 | TRACE_RET(chip, STATUS_FAIL); | |
2393 | } | |
2394 | ||
2395 | j++; | |
2396 | if (j < 3) { | |
2397 | goto RTY_SD_RST; | |
2398 | } else { | |
2399 | TRACE_RET(chip, STATUS_FAIL); | |
2400 | } | |
2401 | } | |
2402 | ||
2403 | retval = sd_send_cmd_get_rsp(chip, SD_APP_OP_COND, voltage, SD_RSP_TYPE_R3, rsp, 5); | |
2404 | if (retval != STATUS_SUCCESS) { | |
2405 | k++; | |
2406 | if (k < 3) { | |
2407 | goto RTY_SD_RST; | |
2408 | } else { | |
2409 | TRACE_RET(chip, STATUS_FAIL); | |
2410 | } | |
2411 | } | |
2412 | ||
2413 | i++; | |
2414 | wait_timeout(20); | |
2415 | } while (!(rsp[1] & 0x80) && (i < 255)); | |
2416 | ||
2417 | if (i == 255) { | |
2418 | TRACE_RET(chip, STATUS_FAIL); | |
2419 | } | |
2420 | ||
2421 | if (hi_cap_flow) { | |
2422 | if (rsp[1] & 0x40) { | |
2423 | SET_SD_HCXC(sd_card); | |
2424 | } else { | |
2425 | CLR_SD_HCXC(sd_card); | |
2426 | } | |
2427 | if (CHECK_PID(chip, 0x5209) && CHK_SD_HCXC(sd_card) && !sd20_mode) { | |
2428 | support_1v8 = (rsp[1] & 0x01) ? 1 : 0; | |
2429 | } else { | |
2430 | support_1v8 = 0; | |
2431 | } | |
2432 | } else { | |
2433 | CLR_SD_HCXC(sd_card); | |
2434 | support_1v8 = 0; | |
2435 | } | |
2436 | RTSX_DEBUGP("support_1v8 = %d\n", support_1v8); | |
2437 | ||
2438 | if (support_1v8) { | |
2439 | retval = sd_voltage_switch(chip); | |
2440 | if (retval != STATUS_SUCCESS) { | |
2441 | TRACE_RET(chip, STATUS_FAIL); | |
2442 | } | |
2443 | } | |
2444 | ||
2445 | retval = sd_send_cmd_get_rsp(chip, ALL_SEND_CID, 0, SD_RSP_TYPE_R2, NULL, 0); | |
2446 | if (retval != STATUS_SUCCESS) { | |
2447 | TRACE_RET(chip, STATUS_FAIL); | |
2448 | } | |
2449 | ||
2450 | for (i = 0; i < 3; i++) { | |
2451 | retval = sd_send_cmd_get_rsp(chip, SEND_RELATIVE_ADDR, 0, SD_RSP_TYPE_R6, rsp, 5); | |
2452 | if (retval != STATUS_SUCCESS) { | |
2453 | TRACE_RET(chip, STATUS_FAIL); | |
2454 | } | |
2455 | ||
2456 | sd_card->sd_addr = (u32)rsp[1] << 24; | |
2457 | sd_card->sd_addr += (u32)rsp[2] << 16; | |
2458 | ||
2459 | if (sd_card->sd_addr) { | |
2460 | break; | |
2461 | } | |
2462 | } | |
2463 | ||
2464 | retval = sd_check_csd(chip, 1); | |
2465 | if (retval != STATUS_SUCCESS) { | |
2466 | TRACE_RET(chip, STATUS_FAIL); | |
2467 | } | |
2468 | ||
2469 | retval = sd_select_card(chip, 1); | |
2470 | if (retval != STATUS_SUCCESS) { | |
2471 | TRACE_RET(chip, STATUS_FAIL); | |
2472 | } | |
2473 | ||
2474 | #ifdef SUPPORT_SD_LOCK | |
2475 | SD_UNLOCK_ENTRY: | |
2476 | retval = sd_update_lock_status(chip); | |
2477 | if (retval != STATUS_SUCCESS) { | |
2478 | TRACE_RET(chip, STATUS_FAIL); | |
2479 | } | |
2480 | ||
2481 | if (sd_card->sd_lock_status & SD_LOCKED) { | |
2482 | sd_card->sd_lock_status |= (SD_LOCK_1BIT_MODE | SD_PWD_EXIST); | |
2483 | return STATUS_SUCCESS; | |
2484 | } else if (!(sd_card->sd_lock_status & SD_UNLOCK_POW_ON)) { | |
2485 | sd_card->sd_lock_status &= ~SD_PWD_EXIST; | |
2486 | } | |
2487 | #endif | |
2488 | ||
2489 | retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0); | |
2490 | if (retval != STATUS_SUCCESS) { | |
2491 | TRACE_RET(chip, STATUS_FAIL); | |
2492 | } | |
2493 | retval = sd_send_cmd_get_rsp(chip, SET_CLR_CARD_DETECT, 0, SD_RSP_TYPE_R1, NULL, 0); | |
2494 | if (retval != STATUS_SUCCESS) { | |
2495 | TRACE_RET(chip, STATUS_FAIL); | |
2496 | } | |
2497 | ||
2498 | if (support_1v8) { | |
2499 | retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0); | |
2500 | if (retval != STATUS_SUCCESS) { | |
2501 | TRACE_RET(chip, STATUS_FAIL); | |
2502 | } | |
2503 | retval = sd_send_cmd_get_rsp(chip, SET_BUS_WIDTH, 2, SD_RSP_TYPE_R1, NULL, 0); | |
2504 | if (retval != STATUS_SUCCESS) { | |
2505 | TRACE_RET(chip, STATUS_FAIL); | |
2506 | } | |
2507 | ||
2508 | switch_bus_width = SD_BUS_WIDTH_4; | |
2509 | } else { | |
2510 | switch_bus_width = SD_BUS_WIDTH_1; | |
2511 | } | |
2512 | ||
2513 | retval = sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200, SD_RSP_TYPE_R1, NULL, 0); | |
2514 | if (retval != STATUS_SUCCESS) { | |
2515 | TRACE_RET(chip, STATUS_FAIL); | |
2516 | } | |
2517 | ||
2518 | retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0); | |
2519 | if (retval != STATUS_SUCCESS) { | |
2520 | TRACE_RET(chip, STATUS_FAIL); | |
2521 | } | |
2522 | ||
2523 | if (!(sd_card->raw_csd[4] & 0x40)) | |
2524 | sd_dont_switch = 1; | |
2525 | ||
2526 | if (!sd_dont_switch) { | |
2d2322b2 | 2527 | if (sd20_mode) { |
2528 | /* Set sd_switch_fail here, because we needn't | |
2529 | * switch to UHS mode | |
2530 | */ | |
2531 | sd_card->sd_switch_fail = SDR104_SUPPORT_MASK | | |
2532 | DDR50_SUPPORT_MASK | SDR50_SUPPORT_MASK; | |
2533 | } | |
2534 | ||
2535 | /* Check the card whether follow SD1.1 spec or higher */ | |
77d89b08 | 2536 | retval = sd_check_spec(chip, switch_bus_width); |
2537 | if (retval == STATUS_SUCCESS) { | |
2538 | retval = sd_switch_function(chip, switch_bus_width); | |
2539 | if (retval != STATUS_SUCCESS) { | |
2540 | if (CHECK_PID(chip, 0x5209)) { | |
2541 | sd_change_bank_voltage(chip, SD_IO_3V3); | |
2542 | } | |
2543 | sd_init_power(chip); | |
2544 | sd_dont_switch = 1; | |
2545 | try_sdio = 0; | |
2546 | ||
2547 | goto Switch_Fail; | |
2548 | } | |
2549 | } else { | |
2550 | if (support_1v8) { | |
2551 | if (CHECK_PID(chip, 0x5209)) { | |
2552 | sd_change_bank_voltage(chip, SD_IO_3V3); | |
2553 | } | |
2554 | sd_init_power(chip); | |
2555 | sd_dont_switch = 1; | |
2556 | try_sdio = 0; | |
2557 | ||
2558 | goto Switch_Fail; | |
2559 | } | |
2560 | } | |
2561 | } | |
2562 | ||
2563 | if (!support_1v8) { | |
2564 | retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0); | |
2565 | if (retval != STATUS_SUCCESS) { | |
2566 | TRACE_RET(chip, STATUS_FAIL); | |
2567 | } | |
2568 | retval = sd_send_cmd_get_rsp(chip, SET_BUS_WIDTH, 2, SD_RSP_TYPE_R1, NULL, 0); | |
2569 | if (retval != STATUS_SUCCESS) { | |
2570 | TRACE_RET(chip, STATUS_FAIL); | |
2571 | } | |
2572 | } | |
2573 | ||
2574 | #ifdef SUPPORT_SD_LOCK | |
2575 | sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE; | |
2576 | #endif | |
2577 | ||
2d2322b2 | 2578 | if (!sd20_mode && CHK_SD30_SPEED(sd_card)) { |
77d89b08 | 2579 | int read_lba0 = 1; |
2580 | ||
2581 | RTSX_WRITE_REG(chip, SD30_DRIVE_SEL, 0x07, chip->sd30_drive_sel_1v8); | |
2582 | ||
2583 | retval = sd_set_init_para(chip); | |
2584 | if (retval != STATUS_SUCCESS) { | |
2585 | TRACE_RET(chip, STATUS_FAIL); | |
2586 | } | |
2587 | ||
2588 | if (CHK_SD_DDR50(sd_card)) { | |
2589 | retval = sd_ddr_tuning(chip); | |
2590 | } else { | |
2591 | retval = sd_sdr_tuning(chip); | |
2592 | } | |
2593 | ||
2594 | if (retval != STATUS_SUCCESS) { | |
2595 | if (sd20_mode) { | |
2596 | TRACE_RET(chip, STATUS_FAIL); | |
2597 | } else { | |
2598 | retval = sd_init_power(chip); | |
2599 | if (retval != STATUS_SUCCESS) { | |
2600 | TRACE_RET(chip, STATUS_FAIL); | |
2601 | } | |
2602 | try_sdio = 0; | |
2603 | sd20_mode = 1; | |
2604 | goto Switch_Fail; | |
2605 | } | |
2606 | } | |
2607 | ||
2608 | sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0); | |
2609 | ||
2610 | if (CHK_SD_DDR50(sd_card)) { | |
2611 | retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000); | |
2612 | if (retval != STATUS_SUCCESS) { | |
2613 | read_lba0 = 0; | |
2614 | } | |
2615 | } | |
2616 | ||
2617 | if (read_lba0) { | |
2618 | retval = sd_read_lba0(chip); | |
2619 | if (retval != STATUS_SUCCESS) { | |
2620 | if (sd20_mode) { | |
2621 | TRACE_RET(chip, STATUS_FAIL); | |
2622 | } else { | |
2623 | retval = sd_init_power(chip); | |
2624 | if (retval != STATUS_SUCCESS) { | |
2625 | TRACE_RET(chip, STATUS_FAIL); | |
2626 | } | |
2627 | try_sdio = 0; | |
2628 | sd20_mode = 1; | |
2629 | goto Switch_Fail; | |
2630 | } | |
2631 | } | |
2632 | } | |
2633 | } | |
2634 | ||
2635 | retval = sd_check_wp_state(chip); | |
2636 | if (retval != STATUS_SUCCESS) { | |
2637 | TRACE_RET(chip, STATUS_FAIL); | |
2638 | } | |
2639 | ||
2640 | chip->card_bus_width[chip->card2lun[SD_CARD]] = 4; | |
2641 | ||
2642 | #ifdef SUPPORT_SD_LOCK | |
2643 | if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON) { | |
2644 | RTSX_WRITE_REG(chip, REG_SD_BLOCK_CNT_H, 0xFF, 0x02); | |
2645 | RTSX_WRITE_REG(chip, REG_SD_BLOCK_CNT_L, 0xFF, 0x00); | |
2646 | } | |
2647 | #endif | |
2648 | ||
2649 | return STATUS_SUCCESS; | |
2650 | } | |
2651 | ||
2652 | ||
2653 | static int mmc_test_switch_bus(struct rtsx_chip *chip, u8 width) | |
2654 | { | |
2655 | struct sd_info *sd_card = &(chip->sd_card); | |
2656 | int retval; | |
2657 | u8 buf[8] = {0}, bus_width, *ptr; | |
2658 | u16 byte_cnt; | |
2659 | int len; | |
2660 | ||
2661 | retval = sd_send_cmd_get_rsp(chip, BUSTEST_W, 0, SD_RSP_TYPE_R1, NULL, 0); | |
2662 | if (retval != STATUS_SUCCESS) { | |
2663 | TRACE_RET(chip, STATUS_FAIL); | |
2664 | } | |
2665 | ||
2666 | if (width == MMC_8BIT_BUS) { | |
2667 | buf[0] = 0x55; | |
2668 | buf[1] = 0xAA; | |
2669 | len = 8; | |
2670 | byte_cnt = 8; | |
2671 | bus_width = SD_BUS_WIDTH_8; | |
2672 | } else { | |
2673 | buf[0] = 0x5A; | |
2674 | len = 4; | |
2675 | byte_cnt = 4; | |
2676 | bus_width = SD_BUS_WIDTH_4; | |
2677 | } | |
2678 | ||
2679 | if (!CHECK_PID(chip, 0x5209)) { | |
2680 | RTSX_WRITE_REG(chip, REG_SD_CFG3, 0x02, 0x02); | |
2681 | } | |
2682 | ||
2683 | retval = sd_write_data(chip, SD_TM_AUTO_WRITE_3, | |
2684 | NULL, 0, byte_cnt, 1, bus_width, buf, len, 100); | |
2685 | if (retval != STATUS_SUCCESS) { | |
2686 | if (CHECK_PID(chip, 0x5209)) { | |
2687 | u8 val1 = 0, val2 = 0; | |
2688 | rtsx_read_register(chip, REG_SD_STAT1, &val1); | |
2689 | rtsx_read_register(chip, REG_SD_STAT2, &val2); | |
2690 | rtsx_clear_sd_error(chip); | |
2691 | if ((val1 & 0xE0) || val2) { | |
2692 | TRACE_RET(chip, STATUS_FAIL); | |
2693 | } | |
2694 | } else { | |
2695 | rtsx_clear_sd_error(chip); | |
2696 | rtsx_write_register(chip, REG_SD_CFG3, 0x02, 0); | |
2697 | TRACE_RET(chip, STATUS_FAIL); | |
2698 | } | |
2699 | } | |
2700 | ||
2701 | if (!CHECK_PID(chip, 0x5209)) { | |
2702 | RTSX_WRITE_REG(chip, REG_SD_CFG3, 0x02, 0); | |
2703 | } | |
2704 | ||
2705 | RTSX_DEBUGP("SD/MMC CMD %d\n", BUSTEST_R); | |
2706 | ||
2707 | rtsx_init_cmd(chip); | |
2708 | ||
2709 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | BUSTEST_R); | |
2710 | ||
2711 | if (width == MMC_8BIT_BUS) { | |
2712 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0x08); | |
2713 | } else { | |
2714 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0x04); | |
2715 | } | |
2716 | ||
2717 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, 1); | |
2718 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, 0); | |
2719 | ||
2720 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, | |
2721 | SD_CALCULATE_CRC7 | SD_NO_CHECK_CRC16 | SD_NO_WAIT_BUSY_END | | |
2722 | SD_CHECK_CRC7 | SD_RSP_LEN_6); | |
2723 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER); | |
2724 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, SD_TM_NORMAL_READ | SD_TRANSFER_START); | |
2725 | rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END); | |
2726 | ||
2727 | rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2, 0, 0); | |
2728 | if (width == MMC_8BIT_BUS) { | |
2729 | rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 1, 0, 0); | |
2730 | } | |
2731 | ||
2732 | retval = rtsx_send_cmd(chip, SD_CARD, 100); | |
2733 | if (retval < 0) { | |
2734 | rtsx_clear_sd_error(chip); | |
2735 | TRACE_RET(chip, STATUS_FAIL); | |
2736 | } | |
2737 | ||
2738 | ptr = rtsx_get_cmd_data(chip) + 1; | |
2739 | ||
2740 | if (width == MMC_8BIT_BUS) { | |
2741 | RTSX_DEBUGP("BUSTEST_R [8bits]: 0x%02x 0x%02x\n", ptr[0], ptr[1]); | |
2742 | if ((ptr[0] == 0xAA) && (ptr[1] == 0x55)) { | |
2743 | u8 rsp[5]; | |
2744 | u32 arg; | |
2745 | ||
2746 | if (CHK_MMC_DDR52(sd_card)) { | |
2747 | arg = 0x03B70600; | |
2748 | } else { | |
2749 | arg = 0x03B70200; | |
2750 | } | |
2751 | retval = sd_send_cmd_get_rsp(chip, SWITCH, arg, SD_RSP_TYPE_R1b, rsp, 5); | |
2752 | if ((retval == STATUS_SUCCESS) && !(rsp[4] & MMC_SWITCH_ERR)) { | |
2753 | return STATUS_SUCCESS; | |
2754 | } | |
2755 | } | |
2756 | } else { | |
2757 | RTSX_DEBUGP("BUSTEST_R [4bits]: 0x%02x\n", ptr[0]); | |
2758 | if (ptr[0] == 0xA5) { | |
2759 | u8 rsp[5]; | |
2760 | u32 arg; | |
2761 | ||
2762 | if (CHK_MMC_DDR52(sd_card)) { | |
2763 | arg = 0x03B70500; | |
2764 | } else { | |
2765 | arg = 0x03B70100; | |
2766 | } | |
2767 | retval = sd_send_cmd_get_rsp(chip, SWITCH, arg, SD_RSP_TYPE_R1b, rsp, 5); | |
2768 | if ((retval == STATUS_SUCCESS) && !(rsp[4] & MMC_SWITCH_ERR)) { | |
2769 | return STATUS_SUCCESS; | |
2770 | } | |
2771 | } | |
2772 | } | |
2773 | ||
2774 | TRACE_RET(chip, STATUS_FAIL); | |
2775 | } | |
2776 | ||
2777 | ||
2778 | static int mmc_switch_timing_bus(struct rtsx_chip *chip, int switch_ddr) | |
2779 | { | |
2780 | struct sd_info *sd_card = &(chip->sd_card); | |
2781 | int retval; | |
2782 | u8 *ptr, card_type, card_type_mask = 0; | |
2783 | ||
2784 | CLR_MMC_HS(sd_card); | |
2785 | ||
2786 | RTSX_DEBUGP("SD/MMC CMD %d\n", SEND_EXT_CSD); | |
2787 | ||
2788 | rtsx_init_cmd(chip); | |
2789 | ||
2790 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | SEND_EXT_CSD); | |
2791 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, 0); | |
2792 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, 0); | |
2793 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, 0); | |
2794 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, 0); | |
2795 | ||
2796 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0); | |
2797 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 2); | |
2798 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, 1); | |
2799 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, 0); | |
2800 | ||
2801 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, | |
2802 | SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END | | |
2803 | SD_CHECK_CRC7 | SD_RSP_LEN_6); | |
2804 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER); | |
2805 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, SD_TM_NORMAL_READ | SD_TRANSFER_START); | |
2806 | rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END); | |
2807 | ||
2808 | rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 196, 0xFF, 0); | |
2809 | rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 212, 0xFF, 0); | |
2810 | rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 213, 0xFF, 0); | |
2811 | rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 214, 0xFF, 0); | |
2812 | rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 215, 0xFF, 0); | |
2813 | ||
2814 | retval = rtsx_send_cmd(chip, SD_CARD, 1000); | |
2815 | if (retval < 0) { | |
2816 | if (retval == -ETIMEDOUT) { | |
2817 | rtsx_clear_sd_error(chip); | |
2818 | sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, | |
2819 | SD_RSP_TYPE_R1, NULL, 0); | |
2820 | } | |
2821 | TRACE_RET(chip, STATUS_FAIL); | |
2822 | } | |
2823 | ||
2824 | ptr = rtsx_get_cmd_data(chip); | |
2825 | if (ptr[0] & SD_TRANSFER_ERR) { | |
2826 | sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0); | |
2827 | TRACE_RET(chip, STATUS_FAIL); | |
2828 | } | |
2829 | ||
2830 | if (CHK_MMC_SECTOR_MODE(sd_card)) { | |
2831 | sd_card->capacity = ((u32)ptr[5] << 24) | ((u32)ptr[4] << 16) | | |
2832 | ((u32)ptr[3] << 8) | ((u32)ptr[2]); | |
2833 | } | |
2834 | ||
2835 | if (CHECK_PID(chip, 0x5209)) { | |
2836 | #ifdef SUPPORT_SD_LOCK | |
2837 | if (!(sd_card->sd_lock_status & SD_SDR_RST) && | |
2838 | (chip->sd_ctl & SUPPORT_MMC_DDR_MODE)) { | |
2839 | card_type_mask = 0x07; | |
2840 | } else { | |
2841 | card_type_mask = 0x03; | |
2842 | } | |
2843 | #else | |
2844 | if (chip->sd_ctl & SUPPORT_MMC_DDR_MODE) { | |
2845 | card_type_mask = 0x07; | |
2846 | } else { | |
2847 | card_type_mask = 0x03; | |
2848 | } | |
2849 | #endif | |
2850 | } else { | |
2851 | card_type_mask = 0x03; | |
2852 | } | |
2853 | card_type = ptr[1] & card_type_mask; | |
2854 | if (card_type) { | |
2855 | u8 rsp[5]; | |
2856 | ||
2857 | if (card_type & 0x04) { | |
2858 | if (switch_ddr) { | |
2859 | SET_MMC_DDR52(sd_card); | |
2860 | } else { | |
2861 | SET_MMC_52M(sd_card); | |
2862 | } | |
2863 | } else if (card_type & 0x02) { | |
2864 | SET_MMC_52M(sd_card); | |
2865 | } else { | |
2866 | SET_MMC_26M(sd_card); | |
2867 | } | |
2868 | ||
2869 | retval = sd_send_cmd_get_rsp(chip, SWITCH, | |
2870 | 0x03B90100, SD_RSP_TYPE_R1b, rsp, 5); | |
2871 | if ((retval != STATUS_SUCCESS) || (rsp[4] & MMC_SWITCH_ERR)) { | |
2872 | CLR_MMC_HS(sd_card); | |
2873 | } | |
2874 | } | |
2875 | ||
2876 | sd_choose_proper_clock(chip); | |
2877 | retval = switch_clock(chip, sd_card->sd_clock); | |
2878 | if (retval != STATUS_SUCCESS) { | |
2879 | TRACE_RET(chip, STATUS_FAIL); | |
2880 | } | |
2881 | ||
2882 | if (mmc_test_switch_bus(chip, MMC_8BIT_BUS) == STATUS_SUCCESS) { | |
2883 | SET_MMC_8BIT(sd_card); | |
2884 | chip->card_bus_width[chip->card2lun[SD_CARD]] = 8; | |
2885 | #ifdef SUPPORT_SD_LOCK | |
2886 | sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE; | |
2887 | #endif | |
2888 | } else if (mmc_test_switch_bus(chip, MMC_4BIT_BUS) == STATUS_SUCCESS) { | |
2889 | SET_MMC_4BIT(sd_card); | |
2890 | chip->card_bus_width[chip->card2lun[SD_CARD]] = 4; | |
2891 | #ifdef SUPPORT_SD_LOCK | |
2892 | sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE; | |
2893 | #endif | |
2894 | } else { | |
2895 | CLR_MMC_8BIT(sd_card); | |
2896 | CLR_MMC_4BIT(sd_card); | |
2897 | } | |
2898 | ||
2899 | return STATUS_SUCCESS; | |
2900 | } | |
2901 | ||
2902 | ||
2903 | static int reset_mmc(struct rtsx_chip *chip) | |
2904 | { | |
2905 | struct sd_info *sd_card = &(chip->sd_card); | |
2906 | int retval, i = 0, j = 0, k = 0; | |
2907 | int switch_ddr = 1; | |
2908 | u8 rsp[16]; | |
2909 | u8 spec_ver = 0; | |
2910 | u32 temp; | |
2911 | ||
2912 | #ifdef SUPPORT_SD_LOCK | |
2913 | if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON) | |
2914 | goto MMC_UNLOCK_ENTRY; | |
2915 | #endif | |
2916 | ||
2917 | DDR_TUNING_FAIL: | |
2918 | ||
2919 | retval = sd_prepare_reset(chip); | |
2920 | if (retval != STATUS_SUCCESS) { | |
2921 | TRACE_RET(chip, retval); | |
2922 | } | |
2923 | ||
2924 | SET_MMC(sd_card); | |
2925 | ||
2926 | RTY_MMC_RST: | |
2927 | retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, SD_RSP_TYPE_R0, NULL, 0); | |
2928 | if (retval != STATUS_SUCCESS) { | |
2929 | TRACE_RET(chip, STATUS_FAIL); | |
2930 | } | |
2931 | ||
2932 | do { | |
2933 | if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) { | |
2934 | sd_set_err_code(chip, SD_NO_CARD); | |
2935 | TRACE_RET(chip, STATUS_FAIL); | |
2936 | } | |
2937 | ||
2938 | retval = sd_send_cmd_get_rsp(chip, SEND_OP_COND, | |
2939 | (SUPPORT_VOLTAGE|0x40000000), SD_RSP_TYPE_R3, rsp, 5); | |
2940 | if (retval != STATUS_SUCCESS) { | |
2941 | if (sd_check_err_code(chip, SD_BUSY) || sd_check_err_code(chip, SD_TO_ERR)) { | |
2942 | k++; | |
2943 | if (k < 20) { | |
2944 | sd_clr_err_code(chip); | |
2945 | goto RTY_MMC_RST; | |
2946 | } else { | |
2947 | TRACE_RET(chip, STATUS_FAIL); | |
2948 | } | |
2949 | } else { | |
2950 | j++; | |
2951 | if (j < 100) { | |
2952 | sd_clr_err_code(chip); | |
2953 | goto RTY_MMC_RST; | |
2954 | } else { | |
2955 | TRACE_RET(chip, STATUS_FAIL); | |
2956 | } | |
2957 | } | |
2958 | } | |
2959 | ||
2960 | wait_timeout(20); | |
2961 | i++; | |
2962 | } while (!(rsp[1] & 0x80) && (i < 255)); | |
2963 | ||
2964 | if (i == 255) { | |
2965 | TRACE_RET(chip, STATUS_FAIL); | |
2966 | } | |
2967 | ||
2968 | if ((rsp[1] & 0x60) == 0x40) { | |
2969 | SET_MMC_SECTOR_MODE(sd_card); | |
2970 | } else { | |
2971 | CLR_MMC_SECTOR_MODE(sd_card); | |
2972 | } | |
2973 | ||
2974 | retval = sd_send_cmd_get_rsp(chip, ALL_SEND_CID, 0, SD_RSP_TYPE_R2, NULL, 0); | |
2975 | if (retval != STATUS_SUCCESS) { | |
2976 | TRACE_RET(chip, STATUS_FAIL); | |
2977 | } | |
2978 | ||
2979 | sd_card->sd_addr = 0x00100000; | |
2980 | retval = sd_send_cmd_get_rsp(chip, SET_RELATIVE_ADDR, sd_card->sd_addr, SD_RSP_TYPE_R6, rsp, 5); | |
2981 | if (retval != STATUS_SUCCESS) { | |
2982 | TRACE_RET(chip, STATUS_FAIL); | |
2983 | } | |
2984 | ||
2985 | retval = sd_check_csd(chip, 1); | |
2986 | if (retval != STATUS_SUCCESS) { | |
2987 | TRACE_RET(chip, STATUS_FAIL); | |
2988 | } | |
2989 | ||
2990 | spec_ver = (sd_card->raw_csd[0] & 0x3C) >> 2; | |
2991 | ||
2992 | retval = sd_select_card(chip, 1); | |
2993 | if (retval != STATUS_SUCCESS) { | |
2994 | TRACE_RET(chip, STATUS_FAIL); | |
2995 | } | |
2996 | ||
2997 | retval = sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200, SD_RSP_TYPE_R1, NULL, 0); | |
2998 | if (retval != STATUS_SUCCESS) { | |
2999 | TRACE_RET(chip, STATUS_FAIL); | |
3000 | } | |
3001 | ||
3002 | #ifdef SUPPORT_SD_LOCK | |
3003 | MMC_UNLOCK_ENTRY: | |
3004 | retval = sd_update_lock_status(chip); | |
3005 | if (retval != STATUS_SUCCESS) { | |
3006 | TRACE_RET(chip, STATUS_FAIL); | |
3007 | } | |
3008 | #endif | |
3009 | ||
3010 | retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0); | |
3011 | if (retval != STATUS_SUCCESS) { | |
3012 | TRACE_RET(chip, STATUS_FAIL); | |
3013 | } | |
3014 | ||
3015 | chip->card_bus_width[chip->card2lun[SD_CARD]] = 1; | |
3016 | ||
3017 | if (!sd_card->mmc_dont_switch_bus) { | |
3018 | if (spec_ver == 4) { | |
3019 | (void)mmc_switch_timing_bus(chip, switch_ddr); | |
3020 | } | |
3021 | ||
3022 | if (CHK_MMC_SECTOR_MODE(sd_card) && (sd_card->capacity == 0)) { | |
3023 | TRACE_RET(chip, STATUS_FAIL); | |
3024 | } | |
3025 | ||
3026 | if (switch_ddr && CHK_MMC_DDR52(sd_card)) { | |
3027 | retval = sd_set_init_para(chip); | |
3028 | if (retval != STATUS_SUCCESS) { | |
3029 | TRACE_RET(chip, STATUS_FAIL); | |
3030 | } | |
3031 | ||
3032 | retval = mmc_ddr_tuning(chip); | |
3033 | if (retval != STATUS_SUCCESS) { | |
3034 | retval = sd_init_power(chip); | |
3035 | if (retval != STATUS_SUCCESS) { | |
3036 | TRACE_RET(chip, STATUS_FAIL); | |
3037 | } | |
3038 | switch_ddr = 0; | |
3039 | goto DDR_TUNING_FAIL; | |
3040 | } | |
3041 | ||
3042 | retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000); | |
3043 | if (retval == STATUS_SUCCESS) { | |
3044 | retval = sd_read_lba0(chip); | |
3045 | if (retval != STATUS_SUCCESS) { | |
3046 | retval = sd_init_power(chip); | |
3047 | if (retval != STATUS_SUCCESS) { | |
3048 | TRACE_RET(chip, STATUS_FAIL); | |
3049 | } | |
3050 | switch_ddr = 0; | |
3051 | goto DDR_TUNING_FAIL; | |
3052 | } | |
3053 | } | |
3054 | } | |
3055 | } | |
3056 | ||
3057 | #ifdef SUPPORT_SD_LOCK | |
3058 | if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON) { | |
3059 | RTSX_WRITE_REG(chip, REG_SD_BLOCK_CNT_H, 0xFF, 0x02); | |
3060 | RTSX_WRITE_REG(chip, REG_SD_BLOCK_CNT_L, 0xFF, 0x00); | |
3061 | } | |
3062 | #endif | |
3063 | ||
3064 | temp = rtsx_readl(chip, RTSX_BIPR); | |
3065 | if (temp & SD_WRITE_PROTECT) { | |
3066 | chip->card_wp |= SD_CARD; | |
3067 | } | |
3068 | ||
3069 | return STATUS_SUCCESS; | |
3070 | } | |
3071 | ||
77d89b08 | 3072 | int reset_sd_card(struct rtsx_chip *chip) |
3073 | { | |
3074 | struct sd_info *sd_card = &(chip->sd_card); | |
3075 | int retval; | |
3076 | ||
3077 | sd_init_reg_addr(chip); | |
3078 | ||
2d2322b2 | 3079 | memset(sd_card, 0, sizeof(struct sd_info)); |
3080 | chip->capacity[chip->card2lun[SD_CARD]] = 0; | |
77d89b08 | 3081 | |
3082 | retval = enable_card_clock(chip, SD_CARD); | |
3083 | if (retval != STATUS_SUCCESS) { | |
3084 | TRACE_RET(chip, STATUS_FAIL); | |
3085 | } | |
3086 | ||
3087 | if (chip->ignore_sd && CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) { | |
3088 | if (chip->asic_code) { | |
3089 | retval = sd_pull_ctl_enable(chip); | |
3090 | if (retval != STATUS_SUCCESS) { | |
3091 | TRACE_RET(chip, STATUS_FAIL); | |
3092 | } | |
3093 | } else { | |
3094 | retval = rtsx_write_register(chip, FPGA_PULL_CTL, | |
3095 | FPGA_SD_PULL_CTL_BIT | 0x20, 0); | |
3096 | if (retval != STATUS_SUCCESS) { | |
3097 | TRACE_RET(chip, STATUS_FAIL); | |
3098 | } | |
3099 | } | |
3100 | retval = card_share_mode(chip, SD_CARD); | |
3101 | if (retval != STATUS_SUCCESS) { | |
3102 | TRACE_RET(chip, STATUS_FAIL); | |
3103 | } | |
3104 | ||
3105 | chip->sd_io = 1; | |
3106 | TRACE_RET(chip, STATUS_FAIL); | |
3107 | } | |
3108 | ||
3109 | retval = sd_init_power(chip); | |
3110 | if (retval != STATUS_SUCCESS) { | |
3111 | TRACE_RET(chip, STATUS_FAIL); | |
3112 | } | |
3113 | ||
3114 | if (chip->sd_ctl & RESET_MMC_FIRST) { | |
3115 | retval = reset_mmc(chip); | |
3116 | if ((retval != STATUS_SUCCESS) && !sd_check_err_code(chip, SD_NO_CARD)) { | |
3117 | retval = reset_sd(chip); | |
3118 | if (retval != STATUS_SUCCESS) { | |
3119 | if (CHECK_PID(chip, 0x5209)) { | |
3120 | retval = sd_change_bank_voltage(chip, SD_IO_3V3); | |
3121 | if (retval != STATUS_SUCCESS) { | |
3122 | TRACE_RET(chip, STATUS_FAIL); | |
3123 | } | |
3124 | } | |
3125 | } | |
3126 | } | |
3127 | } else { | |
3128 | retval = reset_sd(chip); | |
3129 | if (retval != STATUS_SUCCESS) { | |
3130 | if (sd_check_err_code(chip, SD_NO_CARD)) { | |
3131 | TRACE_RET(chip, STATUS_FAIL); | |
3132 | } | |
3133 | ||
3134 | if (CHECK_PID(chip, 0x5209)) { | |
3135 | retval = sd_change_bank_voltage(chip, SD_IO_3V3); | |
3136 | if (retval != STATUS_SUCCESS) { | |
3137 | TRACE_RET(chip, STATUS_FAIL); | |
3138 | } | |
3139 | } | |
3140 | ||
3141 | if (!chip->sd_io) { | |
3142 | retval = reset_mmc(chip); | |
3143 | } | |
3144 | } | |
3145 | } | |
3146 | ||
3147 | if (retval != STATUS_SUCCESS) { | |
3148 | TRACE_RET(chip, STATUS_FAIL); | |
3149 | } | |
3150 | ||
3151 | retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0); | |
3152 | if (retval != STATUS_SUCCESS) { | |
3153 | TRACE_RET(chip, STATUS_FAIL); | |
3154 | } | |
3155 | RTSX_WRITE_REG(chip, REG_SD_BYTE_CNT_L, 0xFF, 0); | |
3156 | RTSX_WRITE_REG(chip, REG_SD_BYTE_CNT_H, 0xFF, 2); | |
3157 | ||
3158 | chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity; | |
3159 | ||
3160 | retval = sd_set_init_para(chip); | |
3161 | if (retval != STATUS_SUCCESS) { | |
3162 | TRACE_RET(chip, STATUS_FAIL); | |
3163 | } | |
3164 | ||
3165 | RTSX_DEBUGP("sd_card->sd_type = 0x%x\n", sd_card->sd_type); | |
3166 | ||
3167 | return STATUS_SUCCESS; | |
3168 | } | |
3169 | ||
3170 | static int reset_mmc_only(struct rtsx_chip *chip) | |
3171 | { | |
3172 | struct sd_info *sd_card = &(chip->sd_card); | |
3173 | int retval; | |
3174 | ||
3175 | sd_card->sd_type = 0; | |
3176 | sd_card->seq_mode = 0; | |
3177 | sd_card->sd_data_buf_ready = 0; | |
3178 | sd_card->capacity = 0; | |
3179 | sd_card->sd_switch_fail = 0; | |
3180 | ||
3181 | #ifdef SUPPORT_SD_LOCK | |
3182 | sd_card->sd_lock_status = 0; | |
3183 | sd_card->sd_erase_status = 0; | |
3184 | #endif | |
3185 | ||
3186 | chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity = 0; | |
3187 | ||
3188 | retval = enable_card_clock(chip, SD_CARD); | |
3189 | if (retval != STATUS_SUCCESS) { | |
3190 | TRACE_RET(chip, STATUS_FAIL); | |
3191 | } | |
3192 | ||
3193 | retval = sd_init_power(chip); | |
3194 | if (retval != STATUS_SUCCESS) { | |
3195 | TRACE_RET(chip, STATUS_FAIL); | |
3196 | } | |
3197 | ||
3198 | retval = reset_mmc(chip); | |
3199 | if (retval != STATUS_SUCCESS) { | |
3200 | TRACE_RET(chip, STATUS_FAIL); | |
3201 | } | |
3202 | ||
3203 | retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0); | |
3204 | if (retval != STATUS_SUCCESS) { | |
3205 | TRACE_RET(chip, STATUS_FAIL); | |
3206 | } | |
3207 | RTSX_WRITE_REG(chip, REG_SD_BYTE_CNT_L, 0xFF, 0); | |
3208 | RTSX_WRITE_REG(chip, REG_SD_BYTE_CNT_H, 0xFF, 2); | |
3209 | ||
3210 | chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity; | |
3211 | ||
3212 | retval = sd_set_init_para(chip); | |
3213 | if (retval != STATUS_SUCCESS) { | |
3214 | TRACE_RET(chip, STATUS_FAIL); | |
3215 | } | |
3216 | ||
3217 | RTSX_DEBUGP("In reset_mmc_only, sd_card->sd_type = 0x%x\n", sd_card->sd_type); | |
3218 | ||
3219 | return STATUS_SUCCESS; | |
3220 | } | |
3221 | ||
3222 | #define WAIT_DATA_READY_RTY_CNT 255 | |
3223 | ||
3224 | static int wait_data_buf_ready(struct rtsx_chip *chip) | |
3225 | { | |
3226 | struct sd_info *sd_card = &(chip->sd_card); | |
3227 | int i, retval; | |
3228 | ||
3229 | for (i = 0; i < WAIT_DATA_READY_RTY_CNT; i++) { | |
3230 | if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) { | |
3231 | sd_set_err_code(chip, SD_NO_CARD); | |
3232 | TRACE_RET(chip, STATUS_FAIL); | |
3233 | } | |
3234 | ||
3235 | sd_card->sd_data_buf_ready = 0; | |
3236 | ||
3237 | retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, | |
3238 | sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0); | |
3239 | if (retval != STATUS_SUCCESS) { | |
3240 | TRACE_RET(chip, STATUS_FAIL); | |
3241 | } | |
3242 | ||
3243 | if (sd_card->sd_data_buf_ready) { | |
3244 | return sd_send_cmd_get_rsp(chip, SEND_STATUS, | |
3245 | sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0); | |
3246 | } | |
3247 | } | |
3248 | ||
3249 | sd_set_err_code(chip, SD_TO_ERR); | |
3250 | ||
3251 | TRACE_RET(chip, STATUS_FAIL); | |
3252 | } | |
3253 | ||
3254 | void sd_stop_seq_mode(struct rtsx_chip *chip) | |
3255 | { | |
3256 | struct sd_info *sd_card = &(chip->sd_card); | |
3257 | int retval; | |
3258 | ||
3259 | if (sd_card->seq_mode) { | |
3260 | retval = sd_switch_clock(chip); | |
3261 | if (retval != STATUS_SUCCESS) { | |
3262 | return; | |
3263 | } | |
3264 | ||
3265 | retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0, | |
3266 | SD_RSP_TYPE_R1b, NULL, 0); | |
3267 | if (retval != STATUS_SUCCESS) { | |
3268 | sd_set_err_code(chip, SD_STS_ERR); | |
3269 | } | |
3270 | retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000); | |
3271 | if (retval != STATUS_SUCCESS) { | |
3272 | sd_set_err_code(chip, SD_STS_ERR); | |
3273 | } | |
3274 | sd_card->seq_mode = 0; | |
3275 | ||
3276 | rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH); | |
3277 | } | |
3278 | } | |
3279 | ||
3280 | static inline int sd_auto_tune_clock(struct rtsx_chip *chip) | |
3281 | { | |
3282 | struct sd_info *sd_card = &(chip->sd_card); | |
3283 | int retval; | |
3284 | ||
3285 | if (chip->asic_code) { | |
3286 | if (sd_card->sd_clock > 30) { | |
3287 | sd_card->sd_clock -= 20; | |
3288 | } | |
3289 | } else { | |
3290 | switch (sd_card->sd_clock) { | |
3291 | case CLK_200: | |
3292 | sd_card->sd_clock = CLK_150; | |
3293 | break; | |
3294 | ||
3295 | case CLK_150: | |
3296 | sd_card->sd_clock = CLK_120; | |
3297 | break; | |
3298 | ||
3299 | case CLK_120: | |
3300 | sd_card->sd_clock = CLK_100; | |
3301 | break; | |
3302 | ||
3303 | case CLK_100: | |
3304 | sd_card->sd_clock = CLK_80; | |
3305 | break; | |
3306 | ||
3307 | case CLK_80: | |
3308 | sd_card->sd_clock = CLK_60; | |
3309 | break; | |
3310 | ||
3311 | case CLK_60: | |
3312 | sd_card->sd_clock = CLK_50; | |
3313 | break; | |
3314 | ||
3315 | default: | |
3316 | break; | |
3317 | } | |
3318 | } | |
3319 | ||
3320 | retval = sd_switch_clock(chip); | |
3321 | if (retval != STATUS_SUCCESS) { | |
3322 | TRACE_RET(chip, STATUS_FAIL); | |
3323 | } | |
3324 | ||
3325 | return STATUS_SUCCESS; | |
3326 | } | |
3327 | ||
3328 | int sd_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, u32 start_sector, u16 sector_cnt) | |
3329 | { | |
3330 | struct sd_info *sd_card = &(chip->sd_card); | |
3331 | u32 data_addr; | |
3332 | u8 cfg2; | |
3333 | int retval; | |
3334 | ||
3335 | if (srb->sc_data_direction == DMA_FROM_DEVICE) { | |
3336 | RTSX_DEBUGP("sd_rw: Read %d %s from 0x%x\n", sector_cnt, | |
3337 | (sector_cnt > 1) ? "sectors" : "sector", start_sector); | |
3338 | } else { | |
3339 | RTSX_DEBUGP("sd_rw: Write %d %s to 0x%x\n", sector_cnt, | |
3340 | (sector_cnt > 1) ? "sectors" : "sector", start_sector); | |
3341 | } | |
3342 | ||
3343 | sd_card->cleanup_counter = 0; | |
3344 | ||
3345 | if (!(chip->card_ready & SD_CARD)) { | |
3346 | sd_card->seq_mode = 0; | |
3347 | ||
3348 | retval = reset_sd_card(chip); | |
3349 | if (retval == STATUS_SUCCESS) { | |
3350 | chip->card_ready |= SD_CARD; | |
3351 | chip->card_fail &= ~SD_CARD; | |
3352 | } else { | |
3353 | chip->card_ready &= ~SD_CARD; | |
3354 | chip->card_fail |= SD_CARD; | |
3355 | chip->capacity[chip->card2lun[SD_CARD]] = 0; | |
3356 | chip->rw_need_retry = 1; | |
3357 | TRACE_RET(chip, STATUS_FAIL); | |
3358 | } | |
3359 | } | |
3360 | ||
3361 | if (!CHK_SD_HCXC(sd_card) && !CHK_MMC_SECTOR_MODE(sd_card)) { | |
3362 | data_addr = start_sector << 9; | |
3363 | } else { | |
3364 | data_addr = start_sector; | |
3365 | } | |
3366 | ||
3367 | sd_clr_err_code(chip); | |
3368 | ||
3369 | retval = sd_switch_clock(chip); | |
3370 | if (retval != STATUS_SUCCESS) { | |
3371 | sd_set_err_code(chip, SD_IO_ERR); | |
3372 | TRACE_GOTO(chip, RW_FAIL); | |
3373 | } | |
3374 | ||
3375 | if (sd_card->seq_mode && ((sd_card->pre_dir != srb->sc_data_direction) | |
3376 | || ((sd_card->pre_sec_addr + sd_card->pre_sec_cnt) != start_sector))) { | |
3377 | if ((sd_card->pre_sec_cnt < 0x80) | |
3378 | && (sd_card->pre_dir == DMA_FROM_DEVICE) | |
3379 | && !CHK_SD30_SPEED(sd_card) | |
3380 | && !CHK_SD_HS(sd_card) | |
3381 | && !CHK_MMC_HS(sd_card)) { | |
3382 | sd_send_cmd_get_rsp(chip, SEND_STATUS, | |
3383 | sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0); | |
3384 | } | |
3385 | ||
3386 | retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, | |
3387 | 0, SD_RSP_TYPE_R1b, NULL, 0); | |
3388 | if (retval != STATUS_SUCCESS) { | |
3389 | chip->rw_need_retry = 1; | |
3390 | sd_set_err_code(chip, SD_STS_ERR); | |
3391 | TRACE_GOTO(chip, RW_FAIL); | |
3392 | } | |
3393 | ||
3394 | sd_card->seq_mode = 0; | |
3395 | ||
3396 | retval = rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH); | |
3397 | if (retval != STATUS_SUCCESS) { | |
3398 | sd_set_err_code(chip, SD_IO_ERR); | |
3399 | TRACE_GOTO(chip, RW_FAIL); | |
3400 | } | |
3401 | ||
3402 | if ((sd_card->pre_sec_cnt < 0x80) | |
3403 | && !CHK_SD30_SPEED(sd_card) | |
3404 | && !CHK_SD_HS(sd_card) | |
3405 | && !CHK_MMC_HS(sd_card)) { | |
3406 | sd_send_cmd_get_rsp(chip, SEND_STATUS, | |
3407 | sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0); | |
3408 | } | |
3409 | } | |
3410 | ||
3411 | rtsx_init_cmd(chip); | |
3412 | ||
3413 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0x00); | |
3414 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 0x02); | |
3415 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, (u8)sector_cnt); | |
3416 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, (u8)(sector_cnt >> 8)); | |
3417 | ||
3418 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER); | |
3419 | ||
3420 | if (CHK_MMC_8BIT(sd_card)) { | |
3421 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_8); | |
3422 | } else if (CHK_MMC_4BIT(sd_card) || CHK_SD(sd_card)) { | |
3423 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4); | |
3424 | } else { | |
3425 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_1); | |
3426 | } | |
3427 | ||
3428 | if (sd_card->seq_mode) { | |
3429 | cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END | | |
3430 | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0; | |
3431 | if (CHECK_PID(chip, 0x5209)) { | |
3432 | if (!CHK_SD30_SPEED(sd_card)) { | |
3433 | cfg2 |= SD_NO_CHECK_WAIT_CRC_TO; | |
3434 | } | |
3435 | } | |
3436 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, cfg2); | |
3437 | ||
3438 | trans_dma_enable(srb->sc_data_direction, chip, sector_cnt * 512, DMA_512); | |
3439 | ||
3440 | if (srb->sc_data_direction == DMA_FROM_DEVICE) { | |
3441 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, | |
3442 | SD_TM_AUTO_READ_3 | SD_TRANSFER_START); | |
3443 | } else { | |
3444 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, | |
3445 | SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START); | |
3446 | } | |
3447 | ||
3448 | rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END); | |
3449 | ||
3450 | rtsx_send_cmd_no_wait(chip); | |
3451 | } else { | |
3452 | if (srb->sc_data_direction == DMA_FROM_DEVICE) { | |
3453 | RTSX_DEBUGP("SD/MMC CMD %d\n", READ_MULTIPLE_BLOCK); | |
3454 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, | |
3455 | 0x40 | READ_MULTIPLE_BLOCK); | |
3456 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, (u8)(data_addr >> 24)); | |
3457 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, (u8)(data_addr >> 16)); | |
3458 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, (u8)(data_addr >> 8)); | |
3459 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, (u8)data_addr); | |
3460 | ||
3461 | cfg2 = SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END | | |
3462 | SD_CHECK_CRC7 | SD_RSP_LEN_6; | |
3463 | if (CHECK_PID(chip, 0x5209)) { | |
3464 | if (!CHK_SD30_SPEED(sd_card)) { | |
3465 | cfg2 |= SD_NO_CHECK_WAIT_CRC_TO; | |
3466 | } | |
3467 | } | |
3468 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, cfg2); | |
3469 | ||
3470 | trans_dma_enable(srb->sc_data_direction, chip, sector_cnt * 512, DMA_512); | |
3471 | ||
3472 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, | |
3473 | SD_TM_AUTO_READ_2 | SD_TRANSFER_START); | |
3474 | rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, | |
3475 | SD_TRANSFER_END, SD_TRANSFER_END); | |
3476 | ||
3477 | rtsx_send_cmd_no_wait(chip); | |
3478 | } else { | |
3479 | retval = rtsx_send_cmd(chip, SD_CARD, 50); | |
3480 | if (retval < 0) { | |
3481 | rtsx_clear_sd_error(chip); | |
3482 | ||
3483 | chip->rw_need_retry = 1; | |
3484 | sd_set_err_code(chip, SD_TO_ERR); | |
3485 | TRACE_GOTO(chip, RW_FAIL); | |
3486 | } | |
3487 | ||
3488 | retval = wait_data_buf_ready(chip); | |
3489 | if (retval != STATUS_SUCCESS) { | |
3490 | chip->rw_need_retry = 1; | |
3491 | sd_set_err_code(chip, SD_TO_ERR); | |
3492 | TRACE_GOTO(chip, RW_FAIL); | |
3493 | } | |
3494 | ||
3495 | retval = sd_send_cmd_get_rsp(chip, WRITE_MULTIPLE_BLOCK, | |
3496 | data_addr, SD_RSP_TYPE_R1, NULL, 0); | |
3497 | if (retval != STATUS_SUCCESS) { | |
3498 | chip->rw_need_retry = 1; | |
3499 | TRACE_GOTO(chip, RW_FAIL); | |
3500 | } | |
3501 | ||
3502 | rtsx_init_cmd(chip); | |
3503 | ||
3504 | cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END | | |
3505 | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0; | |
3506 | if (CHECK_PID(chip, 0x5209)) { | |
3507 | if (!CHK_SD30_SPEED(sd_card)) { | |
3508 | cfg2 |= SD_NO_CHECK_WAIT_CRC_TO; | |
3509 | } | |
3510 | } | |
3511 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, cfg2); | |
3512 | ||
3513 | trans_dma_enable(srb->sc_data_direction, chip, sector_cnt * 512, DMA_512); | |
3514 | ||
3515 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, | |
3516 | SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START); | |
3517 | rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, | |
3518 | SD_TRANSFER_END, SD_TRANSFER_END); | |
3519 | ||
3520 | rtsx_send_cmd_no_wait(chip); | |
3521 | } | |
3522 | ||
3523 | sd_card->seq_mode = 1; | |
3524 | } | |
3525 | ||
3526 | retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb), scsi_bufflen(srb), | |
3527 | scsi_sg_count(srb), srb->sc_data_direction, chip->sd_timeout); | |
3528 | if (retval < 0) { | |
3529 | u8 stat = 0; | |
3530 | int err; | |
3531 | ||
3532 | sd_card->seq_mode = 0; | |
3533 | ||
3534 | if (retval == -ETIMEDOUT) { | |
3535 | err = STATUS_TIMEDOUT; | |
3536 | } else { | |
3537 | err = STATUS_FAIL; | |
3538 | } | |
3539 | ||
3540 | rtsx_read_register(chip, REG_SD_STAT1, &stat); | |
3541 | rtsx_clear_sd_error(chip); | |
3542 | if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) { | |
3543 | chip->rw_need_retry = 0; | |
3544 | RTSX_DEBUGP("No card exist, exit sd_rw\n"); | |
3545 | TRACE_RET(chip, STATUS_FAIL); | |
3546 | } | |
3547 | ||
3548 | chip->rw_need_retry = 1; | |
3549 | ||
3550 | retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0, SD_RSP_TYPE_R1b, NULL, 0); | |
3551 | if (retval != STATUS_SUCCESS) { | |
3552 | sd_set_err_code(chip, SD_STS_ERR); | |
3553 | TRACE_GOTO(chip, RW_FAIL); | |
3554 | } | |
3555 | ||
3556 | if (stat & (SD_CRC7_ERR | SD_CRC16_ERR | SD_CRC_WRITE_ERR)) { | |
3557 | RTSX_DEBUGP("SD CRC error, tune clock!\n"); | |
3558 | sd_set_err_code(chip, SD_CRC_ERR); | |
3559 | TRACE_GOTO(chip, RW_FAIL); | |
3560 | } | |
3561 | ||
3562 | if (err == STATUS_TIMEDOUT) { | |
3563 | sd_set_err_code(chip, SD_TO_ERR); | |
3564 | TRACE_GOTO(chip, RW_FAIL); | |
3565 | } | |
3566 | ||
3567 | TRACE_RET(chip, err); | |
3568 | } | |
3569 | ||
3570 | sd_card->pre_sec_addr = start_sector; | |
3571 | sd_card->pre_sec_cnt = sector_cnt; | |
3572 | sd_card->pre_dir = srb->sc_data_direction; | |
3573 | ||
3574 | return STATUS_SUCCESS; | |
3575 | ||
3576 | RW_FAIL: | |
3577 | sd_card->seq_mode = 0; | |
3578 | ||
3579 | if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) { | |
3580 | chip->rw_need_retry = 0; | |
3581 | RTSX_DEBUGP("No card exist, exit sd_rw\n"); | |
3582 | TRACE_RET(chip, STATUS_FAIL); | |
3583 | } | |
3584 | ||
3585 | if (sd_check_err_code(chip, SD_CRC_ERR)) { | |
3586 | if (CHK_MMC_4BIT(sd_card) || CHK_MMC_8BIT(sd_card)) { | |
3587 | sd_card->mmc_dont_switch_bus = 1; | |
3588 | reset_mmc_only(chip); | |
3589 | sd_card->mmc_dont_switch_bus = 0; | |
3590 | } else { | |
3591 | sd_card->need_retune = 1; | |
3592 | sd_auto_tune_clock(chip); | |
3593 | } | |
3594 | } else if (sd_check_err_code(chip, SD_TO_ERR | SD_STS_ERR)) { | |
3595 | retval = reset_sd_card(chip); | |
3596 | if (retval != STATUS_SUCCESS) { | |
3597 | chip->card_ready &= ~SD_CARD; | |
3598 | chip->card_fail |= SD_CARD; | |
3599 | chip->capacity[chip->card2lun[SD_CARD]] = 0; | |
3600 | } | |
3601 | } | |
3602 | ||
3603 | TRACE_RET(chip, STATUS_FAIL); | |
3604 | } | |
3605 | ||
3606 | #ifdef SUPPORT_CPRM | |
3607 | int soft_reset_sd_card(struct rtsx_chip *chip) | |
3608 | { | |
3609 | return reset_sd(chip); | |
3610 | } | |
3611 | ||
3612 | int ext_sd_send_cmd_get_rsp(struct rtsx_chip *chip, u8 cmd_idx, | |
3613 | u32 arg, u8 rsp_type, u8 *rsp, int rsp_len, int special_check) | |
3614 | { | |
3615 | int retval; | |
3616 | int timeout = 100; | |
3617 | u16 reg_addr; | |
3618 | u8 *ptr; | |
3619 | int stat_idx = 0; | |
3620 | int rty_cnt = 0; | |
3621 | ||
3622 | RTSX_DEBUGP("EXT SD/MMC CMD %d\n", cmd_idx); | |
3623 | ||
3624 | if (rsp_type == SD_RSP_TYPE_R1b) { | |
3625 | timeout = 3000; | |
3626 | } | |
3627 | ||
3628 | RTY_SEND_CMD: | |
3629 | ||
3630 | rtsx_init_cmd(chip); | |
3631 | ||
3632 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | cmd_idx); | |
3633 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, (u8)(arg >> 24)); | |
3634 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, (u8)(arg >> 16)); | |
3635 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, (u8)(arg >> 8)); | |
3636 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, (u8)arg); | |
3637 | ||
3638 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type); | |
3639 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, | |
3640 | 0x01, PINGPONG_BUFFER); | |
3641 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, | |
3642 | 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START); | |
3643 | rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END); | |
3644 | ||
3645 | if (rsp_type == SD_RSP_TYPE_R2) { | |
3646 | for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16; reg_addr++) { | |
3647 | rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0); | |
3648 | } | |
3649 | stat_idx = 17; | |
3650 | } else if (rsp_type != SD_RSP_TYPE_R0) { | |
3651 | for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4; reg_addr++) { | |
3652 | rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0); | |
3653 | } | |
3654 | stat_idx = 6; | |
3655 | } | |
3656 | rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_CMD5, 0, 0); | |
3657 | ||
3658 | rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_STAT1, 0, 0); | |
3659 | ||
3660 | retval = rtsx_send_cmd(chip, SD_CARD, timeout); | |
3661 | if (retval < 0) { | |
3662 | if (retval == -ETIMEDOUT) { | |
3663 | rtsx_clear_sd_error(chip); | |
3664 | ||
3665 | if (rsp_type & SD_WAIT_BUSY_END) { | |
3666 | retval = sd_check_data0_status(chip); | |
3667 | if (retval != STATUS_SUCCESS) { | |
3668 | TRACE_RET(chip, retval); | |
3669 | } | |
3670 | } else { | |
3671 | sd_set_err_code(chip, SD_TO_ERR); | |
3672 | } | |
3673 | } | |
3674 | TRACE_RET(chip, STATUS_FAIL); | |
3675 | } | |
3676 | ||
3677 | if (rsp_type == SD_RSP_TYPE_R0) { | |
3678 | return STATUS_SUCCESS; | |
3679 | } | |
3680 | ||
3681 | ptr = rtsx_get_cmd_data(chip) + 1; | |
3682 | ||
3683 | if ((ptr[0] & 0xC0) != 0) { | |
3684 | sd_set_err_code(chip, SD_STS_ERR); | |
3685 | TRACE_RET(chip, STATUS_FAIL); | |
3686 | } | |
3687 | ||
3688 | if (!(rsp_type & SD_NO_CHECK_CRC7)) { | |
3689 | if (ptr[stat_idx] & SD_CRC7_ERR) { | |
3690 | if (cmd_idx == WRITE_MULTIPLE_BLOCK) { | |
3691 | sd_set_err_code(chip, SD_CRC_ERR); | |
3692 | TRACE_RET(chip, STATUS_FAIL); | |
3693 | } | |
3694 | if (rty_cnt < SD_MAX_RETRY_COUNT) { | |
3695 | wait_timeout(20); | |
3696 | rty_cnt++; | |
3697 | goto RTY_SEND_CMD; | |
3698 | } else { | |
3699 | sd_set_err_code(chip, SD_CRC_ERR); | |
3700 | TRACE_RET(chip, STATUS_FAIL); | |
3701 | } | |
3702 | } | |
3703 | } | |
3704 | ||
3705 | if ((cmd_idx == SELECT_CARD) || (cmd_idx == APP_CMD) || | |
3706 | (cmd_idx == SEND_STATUS) || (cmd_idx == STOP_TRANSMISSION)) { | |
3707 | if ((cmd_idx != STOP_TRANSMISSION) && (special_check == 0)) { | |
3708 | if (ptr[1] & 0x80) { | |
3709 | TRACE_RET(chip, STATUS_FAIL); | |
3710 | } | |
3711 | } | |
3712 | #ifdef SUPPORT_SD_LOCK | |
3713 | if (ptr[1] & 0x7D) | |
3714 | #else | |
3715 | if (ptr[1] & 0x7F) | |
3716 | #endif | |
3717 | { | |
3718 | TRACE_RET(chip, STATUS_FAIL); | |
3719 | } | |
3720 | if (ptr[2] & 0xF8) { | |
3721 | TRACE_RET(chip, STATUS_FAIL); | |
3722 | } | |
3723 | ||
3724 | if (cmd_idx == SELECT_CARD) { | |
3725 | if (rsp_type == SD_RSP_TYPE_R2) { | |
3726 | if ((ptr[3] & 0x1E) != 0x04) { | |
3727 | TRACE_RET(chip, STATUS_FAIL); | |
3728 | } | |
3729 | } else if (rsp_type == SD_RSP_TYPE_R2) { | |
3730 | if ((ptr[3] & 0x1E) != 0x03) { | |
3731 | TRACE_RET(chip, STATUS_FAIL); | |
3732 | } | |
3733 | } | |
3734 | } | |
3735 | } | |
3736 | ||
3737 | if (rsp && rsp_len) { | |
3738 | memcpy(rsp, ptr, rsp_len); | |
3739 | } | |
3740 | ||
3741 | return STATUS_SUCCESS; | |
3742 | } | |
3743 | ||
3744 | int ext_sd_get_rsp(struct rtsx_chip *chip, int len, u8 *rsp, u8 rsp_type) | |
3745 | { | |
3746 | int retval, rsp_len; | |
3747 | u16 reg_addr; | |
3748 | ||
3749 | if (rsp_type == SD_RSP_TYPE_R0) { | |
3750 | return STATUS_SUCCESS; | |
3751 | } | |
3752 | ||
3753 | rtsx_init_cmd(chip); | |
3754 | ||
3755 | if (rsp_type == SD_RSP_TYPE_R2) { | |
3756 | for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16; reg_addr++) { | |
3757 | rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0xFF, 0); | |
3758 | } | |
3759 | rsp_len = 17; | |
3760 | } else if (rsp_type != SD_RSP_TYPE_R0) { | |
3761 | for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4; reg_addr++) { | |
3762 | rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0xFF, 0); | |
3763 | } | |
3764 | rsp_len = 6; | |
3765 | } | |
3766 | rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_CMD5, 0xFF, 0); | |
3767 | ||
3768 | retval = rtsx_send_cmd(chip, SD_CARD, 100); | |
3769 | if (retval != STATUS_SUCCESS) { | |
3770 | TRACE_RET(chip, STATUS_FAIL); | |
3771 | } | |
3772 | ||
3773 | if (rsp) { | |
3774 | int min_len = (rsp_len < len) ? rsp_len : len; | |
3775 | ||
3776 | memcpy(rsp, rtsx_get_cmd_data(chip), min_len); | |
3777 | ||
3778 | RTSX_DEBUGP("min_len = %d\n", min_len); | |
3779 | RTSX_DEBUGP("Response in cmd buf: 0x%x 0x%x 0x%x 0x%x\n", | |
3780 | rsp[0], rsp[1], rsp[2], rsp[3]); | |
3781 | } | |
3782 | ||
3783 | return STATUS_SUCCESS; | |
3784 | } | |
3785 | ||
3786 | int sd_pass_thru_mode(struct scsi_cmnd *srb, struct rtsx_chip *chip) | |
3787 | { | |
3788 | struct sd_info *sd_card = &(chip->sd_card); | |
3789 | unsigned int lun = SCSI_LUN(srb); | |
3790 | int len; | |
3791 | u8 buf[18] = { | |
3792 | 0x00, | |
3793 | 0x00, | |
3794 | 0x00, | |
3795 | 0x0E, | |
3796 | 0x00, | |
3797 | 0x00, | |
3798 | 0x00, | |
3799 | 0x00, | |
3800 | 0x53, | |
3801 | 0x44, | |
3802 | 0x20, | |
3803 | 0x43, | |
3804 | 0x61, | |
3805 | 0x72, | |
3806 | 0x64, | |
3807 | 0x00, | |
3808 | 0x00, | |
3809 | 0x00, | |
3810 | }; | |
3811 | ||
3812 | sd_card->pre_cmd_err = 0; | |
3813 | ||
3814 | if (!(CHK_BIT(chip->lun_mc, lun))) { | |
3815 | SET_BIT(chip->lun_mc, lun); | |
3816 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE); | |
3817 | TRACE_RET(chip, TRANSPORT_FAILED); | |
3818 | } | |
3819 | ||
3820 | if ((0x53 != srb->cmnd[2]) || (0x44 != srb->cmnd[3]) || (0x20 != srb->cmnd[4]) || | |
3821 | (0x43 != srb->cmnd[5]) || (0x61 != srb->cmnd[6]) || | |
3822 | (0x72 != srb->cmnd[7]) || (0x64 != srb->cmnd[8])) { | |
3823 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); | |
3824 | TRACE_RET(chip, TRANSPORT_FAILED); | |
3825 | } | |
3826 | ||
3827 | switch (srb->cmnd[1] & 0x0F) { | |
3828 | case 0: | |
3829 | sd_card->sd_pass_thru_en = 0; | |
3830 | break; | |
3831 | ||
3832 | case 1: | |
3833 | sd_card->sd_pass_thru_en = 1; | |
3834 | break; | |
3835 | ||
3836 | default: | |
3837 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); | |
3838 | TRACE_RET(chip, TRANSPORT_FAILED); | |
3839 | } | |
3840 | ||
3841 | buf[5] = (1 == CHK_SD(sd_card)) ? 0x01 : 0x02; | |
3842 | if (chip->card_wp & SD_CARD) { | |
3843 | buf[5] |= 0x80; | |
3844 | } | |
3845 | ||
3846 | buf[6] = (u8)(sd_card->sd_addr >> 16); | |
3847 | buf[7] = (u8)(sd_card->sd_addr >> 24); | |
3848 | ||
3849 | buf[15] = chip->max_lun; | |
3850 | ||
3851 | len = min(18, (int)scsi_bufflen(srb)); | |
3852 | rtsx_stor_set_xfer_buf(buf, len, srb); | |
3853 | ||
3854 | return TRANSPORT_GOOD; | |
3855 | } | |
3856 | ||
3857 | static inline int get_rsp_type(struct scsi_cmnd *srb, u8 *rsp_type, int *rsp_len) | |
3858 | { | |
3859 | if (!rsp_type || !rsp_len) { | |
3860 | return STATUS_FAIL; | |
3861 | } | |
3862 | ||
3863 | switch (srb->cmnd[10]) { | |
3864 | case 0x03: | |
3865 | *rsp_type = SD_RSP_TYPE_R0; | |
3866 | *rsp_len = 0; | |
3867 | break; | |
3868 | ||
3869 | case 0x04: | |
3870 | *rsp_type = SD_RSP_TYPE_R1; | |
3871 | *rsp_len = 6; | |
3872 | break; | |
3873 | ||
3874 | case 0x05: | |
3875 | *rsp_type = SD_RSP_TYPE_R1b; | |
3876 | *rsp_len = 6; | |
3877 | break; | |
3878 | ||
3879 | case 0x06: | |
3880 | *rsp_type = SD_RSP_TYPE_R2; | |
3881 | *rsp_len = 17; | |
3882 | break; | |
3883 | ||
3884 | case 0x07: | |
3885 | *rsp_type = SD_RSP_TYPE_R3; | |
3886 | *rsp_len = 6; | |
3887 | break; | |
3888 | ||
3889 | default: | |
3890 | return STATUS_FAIL; | |
3891 | } | |
3892 | ||
3893 | return STATUS_SUCCESS; | |
3894 | } | |
3895 | ||
3896 | int sd_execute_no_data(struct scsi_cmnd *srb, struct rtsx_chip *chip) | |
3897 | { | |
3898 | struct sd_info *sd_card = &(chip->sd_card); | |
3899 | unsigned int lun = SCSI_LUN(srb); | |
3900 | int retval, rsp_len; | |
3901 | u8 cmd_idx, rsp_type; | |
3902 | u8 standby = 0, acmd = 0; | |
3903 | u32 arg; | |
3904 | ||
3905 | if (!sd_card->sd_pass_thru_en) { | |
3906 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); | |
3907 | TRACE_RET(chip, TRANSPORT_FAILED); | |
3908 | } | |
3909 | ||
3910 | retval = sd_switch_clock(chip); | |
3911 | if (retval != STATUS_SUCCESS) { | |
3912 | TRACE_RET(chip, TRANSPORT_FAILED); | |
3913 | } | |
3914 | ||
3915 | if (sd_card->pre_cmd_err) { | |
3916 | sd_card->pre_cmd_err = 0; | |
3917 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE); | |
3918 | TRACE_RET(chip, TRANSPORT_FAILED); | |
3919 | } | |
3920 | ||
3921 | cmd_idx = srb->cmnd[2] & 0x3F; | |
3922 | if (srb->cmnd[1] & 0x02) { | |
3923 | standby = 1; | |
3924 | } | |
3925 | if (srb->cmnd[1] & 0x01) { | |
3926 | acmd = 1; | |
3927 | } | |
3928 | ||
3929 | arg = ((u32)srb->cmnd[3] << 24) | ((u32)srb->cmnd[4] << 16) | | |
3930 | ((u32)srb->cmnd[5] << 8) | srb->cmnd[6]; | |
3931 | ||
3932 | retval = get_rsp_type(srb, &rsp_type, &rsp_len); | |
3933 | if (retval != STATUS_SUCCESS) { | |
3934 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); | |
3935 | TRACE_RET(chip, TRANSPORT_FAILED); | |
3936 | } | |
3937 | sd_card->last_rsp_type = rsp_type; | |
3938 | ||
3939 | retval = sd_switch_clock(chip); | |
3940 | if (retval != STATUS_SUCCESS) { | |
3941 | TRACE_RET(chip, TRANSPORT_FAILED); | |
3942 | } | |
3943 | ||
3944 | #ifdef SUPPORT_SD_LOCK | |
3945 | if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) { | |
3946 | if (CHK_MMC_8BIT(sd_card)) { | |
3947 | retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_8); | |
3948 | if (retval != STATUS_SUCCESS) { | |
3949 | TRACE_RET(chip, TRANSPORT_FAILED); | |
3950 | } | |
3951 | } else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card)) { | |
3952 | retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4); | |
3953 | if (retval != STATUS_SUCCESS) { | |
3954 | TRACE_RET(chip, TRANSPORT_FAILED); | |
3955 | } | |
3956 | } | |
3957 | } | |
3958 | #else | |
3959 | retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4); | |
3960 | if (retval != STATUS_SUCCESS) { | |
3961 | TRACE_RET(chip, TRANSPORT_FAILED); | |
3962 | } | |
3963 | #endif | |
3964 | ||
3965 | if (standby) { | |
3966 | retval = sd_select_card(chip, 0); | |
3967 | if (retval != STATUS_SUCCESS) { | |
3968 | TRACE_GOTO(chip, SD_Execute_Cmd_Failed); | |
3969 | } | |
3970 | } | |
3971 | ||
3972 | if (acmd) { | |
3973 | retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, | |
3974 | SD_RSP_TYPE_R1, NULL, 0, 0); | |
3975 | if (retval != STATUS_SUCCESS) { | |
3976 | TRACE_GOTO(chip, SD_Execute_Cmd_Failed); | |
3977 | } | |
3978 | } | |
3979 | ||
3980 | retval = ext_sd_send_cmd_get_rsp(chip, cmd_idx, arg, rsp_type, | |
3981 | sd_card->rsp, rsp_len, 0); | |
3982 | if (retval != STATUS_SUCCESS) { | |
3983 | TRACE_GOTO(chip, SD_Execute_Cmd_Failed); | |
3984 | } | |
3985 | ||
3986 | if (standby) { | |
3987 | retval = sd_select_card(chip, 1); | |
3988 | if (retval != STATUS_SUCCESS) { | |
3989 | TRACE_GOTO(chip, SD_Execute_Cmd_Failed); | |
3990 | } | |
3991 | } | |
3992 | ||
3993 | #ifdef SUPPORT_SD_LOCK | |
3994 | retval = sd_update_lock_status(chip); | |
3995 | if (retval != STATUS_SUCCESS) { | |
3996 | TRACE_GOTO(chip, SD_Execute_Cmd_Failed); | |
3997 | } | |
3998 | #endif | |
3999 | ||
4000 | scsi_set_resid(srb, 0); | |
4001 | return TRANSPORT_GOOD; | |
4002 | ||
4003 | SD_Execute_Cmd_Failed: | |
4004 | sd_card->pre_cmd_err = 1; | |
4005 | set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE); | |
4006 | release_sd_card(chip); | |
4007 | do_reset_sd_card(chip); | |
4008 | if (!(chip->card_ready & SD_CARD)) { | |
4009 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); | |
4010 | } | |
4011 | ||
4012 | TRACE_RET(chip, TRANSPORT_FAILED); | |
4013 | } | |
4014 | ||
4015 | int sd_execute_read_data(struct scsi_cmnd *srb, struct rtsx_chip *chip) | |
4016 | { | |
4017 | struct sd_info *sd_card = &(chip->sd_card); | |
4018 | unsigned int lun = SCSI_LUN(srb); | |
4019 | int retval, rsp_len, i; | |
4020 | int cmd13_checkbit = 0, read_err = 0; | |
4021 | u8 cmd_idx, rsp_type, bus_width; | |
4022 | u8 send_cmd12 = 0, standby = 0, acmd = 0; | |
4023 | u32 data_len; | |
4024 | ||
4025 | if (!sd_card->sd_pass_thru_en) { | |
4026 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); | |
4027 | TRACE_RET(chip, TRANSPORT_FAILED); | |
4028 | } | |
4029 | ||
4030 | if (sd_card->pre_cmd_err) { | |
4031 | sd_card->pre_cmd_err = 0; | |
4032 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE); | |
4033 | TRACE_RET(chip, TRANSPORT_FAILED); | |
4034 | } | |
4035 | ||
4036 | retval = sd_switch_clock(chip); | |
4037 | if (retval != STATUS_SUCCESS) { | |
4038 | TRACE_RET(chip, TRANSPORT_FAILED); | |
4039 | } | |
4040 | ||
4041 | cmd_idx = srb->cmnd[2] & 0x3F; | |
4042 | if (srb->cmnd[1] & 0x04) { | |
4043 | send_cmd12 = 1; | |
4044 | } | |
4045 | if (srb->cmnd[1] & 0x02) { | |
4046 | standby = 1; | |
4047 | } | |
4048 | if (srb->cmnd[1] & 0x01) { | |
4049 | acmd = 1; | |
4050 | } | |
4051 | ||
4052 | data_len = ((u32)srb->cmnd[7] << 16) | ((u32)srb->cmnd[8] << 8) | srb->cmnd[9]; | |
4053 | ||
4054 | retval = get_rsp_type(srb, &rsp_type, &rsp_len); | |
4055 | if (retval != STATUS_SUCCESS) { | |
4056 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); | |
4057 | TRACE_RET(chip, TRANSPORT_FAILED); | |
4058 | } | |
4059 | sd_card->last_rsp_type = rsp_type; | |
4060 | ||
4061 | retval = sd_switch_clock(chip); | |
4062 | if (retval != STATUS_SUCCESS) { | |
4063 | TRACE_RET(chip, TRANSPORT_FAILED); | |
4064 | } | |
4065 | ||
4066 | #ifdef SUPPORT_SD_LOCK | |
4067 | if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) { | |
4068 | if (CHK_MMC_8BIT(sd_card)) { | |
4069 | bus_width = SD_BUS_WIDTH_8; | |
4070 | } else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card)) { | |
4071 | bus_width = SD_BUS_WIDTH_4; | |
4072 | } else { | |
4073 | bus_width = SD_BUS_WIDTH_1; | |
4074 | } | |
4075 | } else { | |
4076 | bus_width = SD_BUS_WIDTH_4; | |
4077 | } | |
4078 | RTSX_DEBUGP("bus_width = %d\n", bus_width); | |
4079 | #else | |
4080 | bus_width = SD_BUS_WIDTH_4; | |
4081 | #endif | |
4082 | ||
4083 | if (data_len < 512) { | |
4084 | retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, data_len, | |
4085 | SD_RSP_TYPE_R1, NULL, 0, 0); | |
4086 | if (retval != STATUS_SUCCESS) { | |
4087 | TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed); | |
4088 | } | |
4089 | } | |
4090 | ||
4091 | if (standby) { | |
4092 | retval = sd_select_card(chip, 0); | |
4093 | if (retval != STATUS_SUCCESS) { | |
4094 | TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed); | |
4095 | } | |
4096 | } | |
4097 | ||
4098 | if (acmd) { | |
4099 | retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, | |
4100 | SD_RSP_TYPE_R1, NULL, 0, 0); | |
4101 | if (retval != STATUS_SUCCESS) { | |
4102 | TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed); | |
4103 | } | |
4104 | } | |
4105 | ||
4106 | if (data_len <= 512) { | |
4107 | int min_len; | |
4108 | u8 *buf; | |
4109 | u16 byte_cnt, blk_cnt; | |
4110 | u8 cmd[5]; | |
4111 | ||
4112 | byte_cnt = ((u16)(srb->cmnd[8] & 0x03) << 8) | srb->cmnd[9]; | |
4113 | blk_cnt = 1; | |
4114 | ||
4115 | cmd[0] = 0x40 | cmd_idx; | |
4116 | cmd[1] = srb->cmnd[3]; | |
4117 | cmd[2] = srb->cmnd[4]; | |
4118 | cmd[3] = srb->cmnd[5]; | |
4119 | cmd[4] = srb->cmnd[6]; | |
4120 | ||
4121 | buf = (u8 *)kmalloc(data_len, GFP_KERNEL); | |
4122 | if (buf == NULL) { | |
4123 | TRACE_RET(chip, TRANSPORT_ERROR); | |
4124 | } | |
4125 | ||
4126 | retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, byte_cnt, | |
4127 | blk_cnt, bus_width, buf, data_len, 2000); | |
4128 | if (retval != STATUS_SUCCESS) { | |
4129 | read_err = 1; | |
4130 | kfree(buf); | |
4131 | rtsx_clear_sd_error(chip); | |
4132 | TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed); | |
4133 | } | |
4134 | ||
4135 | min_len = min(data_len, scsi_bufflen(srb)); | |
4136 | rtsx_stor_set_xfer_buf(buf, min_len, srb); | |
4137 | ||
4138 | kfree(buf); | |
4139 | } else if (!(data_len & 0x1FF)) { | |
4140 | rtsx_init_cmd(chip); | |
4141 | ||
4142 | trans_dma_enable(DMA_FROM_DEVICE, chip, data_len, DMA_512); | |
4143 | ||
4144 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 0x02); | |
4145 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0x00); | |
4146 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, | |
4147 | 0xFF, (srb->cmnd[7] & 0xFE) >> 1); | |
4148 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, | |
4149 | 0xFF, (u8)((data_len & 0x0001FE00) >> 9)); | |
4150 | ||
4151 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | cmd_idx); | |
4152 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, srb->cmnd[3]); | |
4153 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, srb->cmnd[4]); | |
4154 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, srb->cmnd[5]); | |
4155 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, srb->cmnd[6]); | |
4156 | ||
4157 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width); | |
4158 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type); | |
4159 | ||
4160 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, | |
4161 | 0xFF, SD_TM_AUTO_READ_2 | SD_TRANSFER_START); | |
4162 | rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END); | |
4163 | ||
4164 | rtsx_send_cmd_no_wait(chip); | |
4165 | ||
4166 | retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb), scsi_bufflen(srb), | |
4167 | scsi_sg_count(srb), DMA_FROM_DEVICE, 10000); | |
4168 | if (retval < 0) { | |
4169 | read_err = 1; | |
4170 | rtsx_clear_sd_error(chip); | |
4171 | TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed); | |
4172 | } | |
4173 | ||
4174 | } else { | |
4175 | TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed); | |
4176 | } | |
4177 | ||
4178 | retval = ext_sd_get_rsp(chip, rsp_len, sd_card->rsp, rsp_type); | |
4179 | if (retval != STATUS_SUCCESS) { | |
4180 | TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed); | |
4181 | } | |
4182 | ||
4183 | if (standby) { | |
4184 | retval = sd_select_card(chip, 1); | |
4185 | if (retval != STATUS_SUCCESS) { | |
4186 | TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed); | |
4187 | } | |
4188 | } | |
4189 | ||
4190 | if (send_cmd12) { | |
4191 | retval = ext_sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, | |
4192 | 0, SD_RSP_TYPE_R1b, NULL, 0, 0); | |
4193 | if (retval != STATUS_SUCCESS) { | |
4194 | TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed); | |
4195 | } | |
4196 | } | |
4197 | ||
4198 | if (data_len < 512) { | |
4199 | retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200, | |
4200 | SD_RSP_TYPE_R1, NULL, 0, 0); | |
4201 | if (retval != STATUS_SUCCESS) { | |
4202 | TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed); | |
4203 | } | |
4204 | ||
4205 | retval = rtsx_write_register(chip, SD_BYTE_CNT_H, 0xFF, 0x02); | |
4206 | if (retval != STATUS_SUCCESS) { | |
4207 | TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed); | |
4208 | } | |
4209 | retval = rtsx_write_register(chip, SD_BYTE_CNT_L, 0xFF, 0x00); | |
4210 | if (retval != STATUS_SUCCESS) { | |
4211 | TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed); | |
4212 | } | |
4213 | } | |
4214 | ||
4215 | if ((srb->cmnd[1] & 0x02) || (srb->cmnd[1] & 0x04)) { | |
4216 | cmd13_checkbit = 1; | |
4217 | } | |
4218 | ||
4219 | for (i = 0; i < 3; i++) { | |
4220 | retval = ext_sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, | |
4221 | SD_RSP_TYPE_R1, NULL, 0, cmd13_checkbit); | |
4222 | if (retval == STATUS_SUCCESS) { | |
4223 | break; | |
4224 | } | |
4225 | } | |
4226 | if (retval != STATUS_SUCCESS) { | |
4227 | TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed); | |
4228 | } | |
4229 | ||
4230 | scsi_set_resid(srb, 0); | |
4231 | return TRANSPORT_GOOD; | |
4232 | ||
4233 | SD_Execute_Read_Cmd_Failed: | |
4234 | sd_card->pre_cmd_err = 1; | |
4235 | set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE); | |
4236 | if (read_err) { | |
4237 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); | |
4238 | } | |
4239 | release_sd_card(chip); | |
4240 | do_reset_sd_card(chip); | |
4241 | if (!(chip->card_ready & SD_CARD)) { | |
4242 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); | |
4243 | } | |
4244 | ||
4245 | TRACE_RET(chip, TRANSPORT_FAILED); | |
4246 | } | |
4247 | ||
4248 | int sd_execute_write_data(struct scsi_cmnd *srb, struct rtsx_chip *chip) | |
4249 | { | |
4250 | struct sd_info *sd_card = &(chip->sd_card); | |
4251 | unsigned int lun = SCSI_LUN(srb); | |
4252 | int retval, rsp_len, i; | |
4253 | int cmd13_checkbit = 0, write_err = 0; | |
4254 | u8 cmd_idx, rsp_type; | |
4255 | u8 send_cmd12 = 0, standby = 0, acmd = 0; | |
4256 | u32 data_len, arg; | |
4257 | #ifdef SUPPORT_SD_LOCK | |
4258 | int lock_cmd_fail = 0; | |
4259 | u8 sd_lock_state = 0; | |
4260 | u8 lock_cmd_type = 0; | |
4261 | #endif | |
4262 | ||
4263 | if (!sd_card->sd_pass_thru_en) { | |
4264 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); | |
4265 | TRACE_RET(chip, TRANSPORT_FAILED); | |
4266 | } | |
4267 | ||
4268 | if (sd_card->pre_cmd_err) { | |
4269 | sd_card->pre_cmd_err = 0; | |
4270 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE); | |
4271 | TRACE_RET(chip, TRANSPORT_FAILED); | |
4272 | } | |
4273 | ||
4274 | retval = sd_switch_clock(chip); | |
4275 | if (retval != STATUS_SUCCESS) { | |
4276 | TRACE_RET(chip, TRANSPORT_FAILED); | |
4277 | } | |
4278 | ||
4279 | cmd_idx = srb->cmnd[2] & 0x3F; | |
4280 | if (srb->cmnd[1] & 0x04) { | |
4281 | send_cmd12 = 1; | |
4282 | } | |
4283 | if (srb->cmnd[1] & 0x02) { | |
4284 | standby = 1; | |
4285 | } | |
4286 | if (srb->cmnd[1] & 0x01) { | |
4287 | acmd = 1; | |
4288 | } | |
4289 | ||
4290 | data_len = ((u32)srb->cmnd[7] << 16) | ((u32)srb->cmnd[8] << 8) | srb->cmnd[9]; | |
4291 | arg = ((u32)srb->cmnd[3] << 24) | ((u32)srb->cmnd[4] << 16) | | |
4292 | ((u32)srb->cmnd[5] << 8) | srb->cmnd[6]; | |
4293 | ||
4294 | #ifdef SUPPORT_SD_LOCK | |
4295 | if (cmd_idx == LOCK_UNLOCK) { | |
4296 | sd_lock_state = sd_card->sd_lock_status; | |
4297 | sd_lock_state &= SD_LOCKED; | |
4298 | } | |
4299 | #endif | |
4300 | ||
4301 | retval = get_rsp_type(srb, &rsp_type, &rsp_len); | |
4302 | if (retval != STATUS_SUCCESS) { | |
4303 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); | |
4304 | TRACE_RET(chip, TRANSPORT_FAILED); | |
4305 | } | |
4306 | sd_card->last_rsp_type = rsp_type; | |
4307 | ||
4308 | retval = sd_switch_clock(chip); | |
4309 | if (retval != STATUS_SUCCESS) { | |
4310 | TRACE_RET(chip, TRANSPORT_FAILED); | |
4311 | } | |
4312 | ||
4313 | #ifdef SUPPORT_SD_LOCK | |
4314 | if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) { | |
4315 | if (CHK_MMC_8BIT(sd_card)) { | |
4316 | retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_8); | |
4317 | if (retval != STATUS_SUCCESS) { | |
4318 | TRACE_RET(chip, TRANSPORT_FAILED); | |
4319 | } | |
4320 | } else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card)) { | |
4321 | retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4); | |
4322 | if (retval != STATUS_SUCCESS) { | |
4323 | TRACE_RET(chip, TRANSPORT_FAILED); | |
4324 | } | |
4325 | } | |
4326 | } | |
4327 | #else | |
4328 | retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4); | |
4329 | if (retval != STATUS_SUCCESS) { | |
4330 | TRACE_RET(chip, TRANSPORT_FAILED); | |
4331 | } | |
4332 | #endif | |
4333 | ||
4334 | if (data_len < 512) { | |
4335 | retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, data_len, | |
4336 | SD_RSP_TYPE_R1, NULL, 0, 0); | |
4337 | if (retval != STATUS_SUCCESS) { | |
4338 | TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed); | |
4339 | } | |
4340 | } | |
4341 | ||
4342 | if (standby) { | |
4343 | retval = sd_select_card(chip, 0); | |
4344 | if (retval != STATUS_SUCCESS) { | |
4345 | TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed); | |
4346 | } | |
4347 | } | |
4348 | ||
4349 | if (acmd) { | |
4350 | retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, | |
4351 | SD_RSP_TYPE_R1, NULL, 0, 0); | |
4352 | if (retval != STATUS_SUCCESS) { | |
4353 | TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed); | |
4354 | } | |
4355 | } | |
4356 | ||
4357 | retval = ext_sd_send_cmd_get_rsp(chip, cmd_idx, arg, rsp_type, | |
4358 | sd_card->rsp, rsp_len, 0); | |
4359 | if (retval != STATUS_SUCCESS) { | |
4360 | TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed); | |
4361 | } | |
4362 | ||
4363 | if (data_len <= 512) { | |
4364 | u16 i; | |
4365 | u8 *buf; | |
4366 | ||
4367 | buf = (u8 *)kmalloc(data_len, GFP_KERNEL); | |
4368 | if (buf == NULL) { | |
4369 | TRACE_RET(chip, TRANSPORT_ERROR); | |
4370 | } | |
4371 | ||
4372 | rtsx_stor_get_xfer_buf(buf, data_len, srb); | |
4373 | ||
4374 | #ifdef SUPPORT_SD_LOCK | |
4375 | if (cmd_idx == LOCK_UNLOCK) { | |
4376 | lock_cmd_type = buf[0] & 0x0F; | |
4377 | } | |
4378 | #endif | |
4379 | ||
4380 | if (data_len > 256) { | |
4381 | rtsx_init_cmd(chip); | |
4382 | for (i = 0; i < 256; i++) { | |
4383 | rtsx_add_cmd(chip, WRITE_REG_CMD, | |
4384 | PPBUF_BASE2 + i, 0xFF, buf[i]); | |
4385 | } | |
4386 | retval = rtsx_send_cmd(chip, 0, 250); | |
4387 | if (retval != STATUS_SUCCESS) { | |
4388 | kfree(buf); | |
4389 | TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed); | |
4390 | } | |
4391 | ||
4392 | rtsx_init_cmd(chip); | |
4393 | for (i = 256; i < data_len; i++) { | |
4394 | rtsx_add_cmd(chip, WRITE_REG_CMD, | |
4395 | PPBUF_BASE2 + i, 0xFF, buf[i]); | |
4396 | } | |
4397 | retval = rtsx_send_cmd(chip, 0, 250); | |
4398 | if (retval != STATUS_SUCCESS) { | |
4399 | kfree(buf); | |
4400 | TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed); | |
4401 | } | |
4402 | } else { | |
4403 | rtsx_init_cmd(chip); | |
4404 | for (i = 0; i < data_len; i++) { | |
4405 | rtsx_add_cmd(chip, WRITE_REG_CMD, | |
4406 | PPBUF_BASE2 + i, 0xFF, buf[i]); | |
4407 | } | |
4408 | retval = rtsx_send_cmd(chip, 0, 250); | |
4409 | if (retval != STATUS_SUCCESS) { | |
4410 | kfree(buf); | |
4411 | TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed); | |
4412 | } | |
4413 | } | |
4414 | ||
4415 | kfree(buf); | |
4416 | ||
4417 | rtsx_init_cmd(chip); | |
4418 | ||
4419 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, srb->cmnd[8] & 0x03); | |
4420 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, srb->cmnd[9]); | |
4421 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, 0x00); | |
4422 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, 0x01); | |
4423 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER); | |
4424 | ||
4425 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, | |
4426 | SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START); | |
4427 | rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END); | |
4428 | ||
4429 | retval = rtsx_send_cmd(chip, SD_CARD, 250); | |
4430 | } else if (!(data_len & 0x1FF)) { | |
4431 | rtsx_init_cmd(chip); | |
4432 | ||
4433 | trans_dma_enable(DMA_TO_DEVICE, chip, data_len, DMA_512); | |
4434 | ||
4435 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 0x02); | |
4436 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0x00); | |
4437 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, | |
4438 | 0xFF, (srb->cmnd[7] & 0xFE) >> 1); | |
4439 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, | |
4440 | 0xFF, (u8)((data_len & 0x0001FE00) >> 9)); | |
4441 | ||
4442 | rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START); | |
4443 | rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END); | |
4444 | ||
4445 | rtsx_send_cmd_no_wait(chip); | |
4446 | ||
4447 | retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb), scsi_bufflen(srb), | |
4448 | scsi_sg_count(srb), DMA_TO_DEVICE, 10000); | |
4449 | ||
4450 | } else { | |
4451 | TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed); | |
4452 | } | |
4453 | ||
4454 | if (retval < 0) { | |
4455 | write_err = 1; | |
4456 | rtsx_clear_sd_error(chip); | |
4457 | TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed); | |
4458 | } | |
4459 | ||
4460 | #ifdef SUPPORT_SD_LOCK | |
4461 | if (cmd_idx == LOCK_UNLOCK) { | |
4462 | if (lock_cmd_type == SD_ERASE) { | |
4463 | sd_card->sd_erase_status = SD_UNDER_ERASING; | |
4464 | scsi_set_resid(srb, 0); | |
4465 | return TRANSPORT_GOOD; | |
4466 | } | |
4467 | ||
4468 | rtsx_init_cmd(chip); | |
4469 | if (CHECK_PID(chip, 0x5209)) { | |
4470 | rtsx_add_cmd(chip, CHECK_REG_CMD, SD_BUS_STAT, SD_DAT0_STATUS, SD_DAT0_STATUS); | |
4471 | } else { | |
4472 | rtsx_add_cmd(chip, CHECK_REG_CMD, 0xFD30, 0x02, 0x02); | |
4473 | } | |
4474 | rtsx_send_cmd(chip, SD_CARD, 250); | |
4475 | ||
4476 | retval = sd_update_lock_status(chip); | |
4477 | if (retval != STATUS_SUCCESS) { | |
4478 | RTSX_DEBUGP("Lock command fail!\n"); | |
4479 | lock_cmd_fail = 1; | |
4480 | } | |
4481 | } | |
4482 | #endif /* SUPPORT_SD_LOCK */ | |
4483 | ||
4484 | if (standby) { | |
4485 | retval = sd_select_card(chip, 1); | |
4486 | if (retval != STATUS_SUCCESS) { | |
4487 | TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed); | |
4488 | } | |
4489 | } | |
4490 | ||
4491 | if (send_cmd12) { | |
4492 | retval = ext_sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, | |
4493 | 0, SD_RSP_TYPE_R1b, NULL, 0, 0); | |
4494 | if (retval != STATUS_SUCCESS) { | |
4495 | TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed); | |
4496 | } | |
4497 | } | |
4498 | ||
4499 | if (data_len < 512) { | |
4500 | retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200, | |
4501 | SD_RSP_TYPE_R1, NULL, 0, 0); | |
4502 | if (retval != STATUS_SUCCESS) { | |
4503 | TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed); | |
4504 | } | |
4505 | ||
4506 | retval = rtsx_write_register(chip, SD_BYTE_CNT_H, 0xFF, 0x02); | |
4507 | if (retval != STATUS_SUCCESS) { | |
4508 | TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed); | |
4509 | } | |
4510 | rtsx_write_register(chip, SD_BYTE_CNT_L, 0xFF, 0x00); | |
4511 | if (retval != STATUS_SUCCESS) { | |
4512 | TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed); | |
4513 | } | |
4514 | } | |
4515 | ||
4516 | if ((srb->cmnd[1] & 0x02) || (srb->cmnd[1] & 0x04)) { | |
4517 | cmd13_checkbit = 1; | |
4518 | } | |
4519 | ||
4520 | for (i = 0; i < 3; i++) { | |
4521 | retval = ext_sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, | |
4522 | SD_RSP_TYPE_R1, NULL, 0, cmd13_checkbit); | |
4523 | if (retval == STATUS_SUCCESS) { | |
4524 | break; | |
4525 | } | |
4526 | } | |
4527 | if (retval != STATUS_SUCCESS) { | |
4528 | TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed); | |
4529 | } | |
4530 | ||
4531 | #ifdef SUPPORT_SD_LOCK | |
4532 | if (cmd_idx == LOCK_UNLOCK) { | |
4533 | if (!lock_cmd_fail) { | |
4534 | RTSX_DEBUGP("lock_cmd_type = 0x%x\n", lock_cmd_type); | |
4535 | if (lock_cmd_type & SD_CLR_PWD) { | |
4536 | sd_card->sd_lock_status &= ~SD_PWD_EXIST; | |
4537 | } | |
4538 | if (lock_cmd_type & SD_SET_PWD) { | |
4539 | sd_card->sd_lock_status |= SD_PWD_EXIST; | |
4540 | } | |
4541 | } | |
4542 | ||
4543 | RTSX_DEBUGP("sd_lock_state = 0x%x, sd_card->sd_lock_status = 0x%x\n", | |
4544 | sd_lock_state, sd_card->sd_lock_status); | |
4545 | if (sd_lock_state ^ (sd_card->sd_lock_status & SD_LOCKED)) { | |
4546 | sd_card->sd_lock_notify = 1; | |
4547 | if (sd_lock_state) { | |
4548 | if (sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) { | |
4549 | sd_card->sd_lock_status |= (SD_UNLOCK_POW_ON | SD_SDR_RST); | |
4550 | if (CHK_SD(sd_card)) { | |
4551 | retval = reset_sd(chip); | |
4552 | if (retval != STATUS_SUCCESS) { | |
4553 | sd_card->sd_lock_status &= ~(SD_UNLOCK_POW_ON | SD_SDR_RST); | |
4554 | TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed); | |
4555 | } | |
4556 | } | |
4557 | ||
4558 | sd_card->sd_lock_status &= ~(SD_UNLOCK_POW_ON | SD_SDR_RST); | |
4559 | } | |
4560 | } | |
4561 | } | |
4562 | } | |
4563 | ||
4564 | if (lock_cmd_fail) { | |
4565 | scsi_set_resid(srb, 0); | |
4566 | set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE); | |
4567 | TRACE_RET(chip, TRANSPORT_FAILED); | |
4568 | } | |
4569 | #endif /* SUPPORT_SD_LOCK */ | |
4570 | ||
4571 | scsi_set_resid(srb, 0); | |
4572 | return TRANSPORT_GOOD; | |
4573 | ||
4574 | SD_Execute_Write_Cmd_Failed: | |
4575 | sd_card->pre_cmd_err = 1; | |
4576 | set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE); | |
4577 | if (write_err) { | |
4578 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR); | |
4579 | } | |
4580 | release_sd_card(chip); | |
4581 | do_reset_sd_card(chip); | |
4582 | if (!(chip->card_ready & SD_CARD)) { | |
4583 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); | |
4584 | } | |
4585 | ||
4586 | TRACE_RET(chip, TRANSPORT_FAILED); | |
4587 | } | |
4588 | ||
4589 | int sd_get_cmd_rsp(struct scsi_cmnd *srb, struct rtsx_chip *chip) | |
4590 | { | |
4591 | struct sd_info *sd_card = &(chip->sd_card); | |
4592 | unsigned int lun = SCSI_LUN(srb); | |
4593 | int count; | |
4594 | u16 data_len; | |
4595 | ||
4596 | if (!sd_card->sd_pass_thru_en) { | |
4597 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); | |
4598 | TRACE_RET(chip, TRANSPORT_FAILED); | |
4599 | } | |
4600 | ||
4601 | if (sd_card->pre_cmd_err) { | |
4602 | sd_card->pre_cmd_err = 0; | |
4603 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE); | |
4604 | TRACE_RET(chip, TRANSPORT_FAILED); | |
4605 | } | |
4606 | ||
4607 | data_len = ((u16)srb->cmnd[7] << 8) | srb->cmnd[8]; | |
4608 | ||
4609 | if (sd_card->last_rsp_type == SD_RSP_TYPE_R0) { | |
4610 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); | |
4611 | TRACE_RET(chip, TRANSPORT_FAILED); | |
4612 | } else if (sd_card->last_rsp_type == SD_RSP_TYPE_R2) { | |
4613 | count = (data_len < 17) ? data_len : 17; | |
4614 | } else { | |
4615 | count = (data_len < 6) ? data_len : 6; | |
4616 | } | |
4617 | rtsx_stor_set_xfer_buf(sd_card->rsp, count, srb); | |
4618 | ||
4619 | RTSX_DEBUGP("Response length: %d\n", data_len); | |
4620 | RTSX_DEBUGP("Response: 0x%x 0x%x 0x%x 0x%x\n", | |
4621 | sd_card->rsp[0], sd_card->rsp[1], sd_card->rsp[2], sd_card->rsp[3]); | |
4622 | ||
4623 | scsi_set_resid(srb, 0); | |
4624 | return TRANSPORT_GOOD; | |
4625 | } | |
4626 | ||
4627 | int sd_hw_rst(struct scsi_cmnd *srb, struct rtsx_chip *chip) | |
4628 | { | |
4629 | struct sd_info *sd_card = &(chip->sd_card); | |
4630 | unsigned int lun = SCSI_LUN(srb); | |
4631 | int retval; | |
4632 | ||
4633 | if (!sd_card->sd_pass_thru_en) { | |
4634 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); | |
4635 | TRACE_RET(chip, TRANSPORT_FAILED); | |
4636 | } | |
4637 | ||
4638 | if (sd_card->pre_cmd_err) { | |
4639 | sd_card->pre_cmd_err = 0; | |
4640 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE); | |
4641 | TRACE_RET(chip, TRANSPORT_FAILED); | |
4642 | } | |
4643 | ||
4644 | if ((0x53 != srb->cmnd[2]) || (0x44 != srb->cmnd[3]) || (0x20 != srb->cmnd[4]) || | |
4645 | (0x43 != srb->cmnd[5]) || (0x61 != srb->cmnd[6]) || | |
4646 | (0x72 != srb->cmnd[7]) || (0x64 != srb->cmnd[8])) { | |
4647 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); | |
4648 | TRACE_RET(chip, TRANSPORT_FAILED); | |
4649 | } | |
4650 | ||
4651 | switch (srb->cmnd[1] & 0x0F) { | |
4652 | case 0: | |
4653 | #ifdef SUPPORT_SD_LOCK | |
4654 | if (0x64 == srb->cmnd[9]) { | |
4655 | sd_card->sd_lock_status |= SD_SDR_RST; | |
4656 | } | |
4657 | #endif | |
4658 | retval = reset_sd_card(chip); | |
4659 | if (retval != STATUS_SUCCESS) { | |
4660 | #ifdef SUPPORT_SD_LOCK | |
4661 | sd_card->sd_lock_status &= ~SD_SDR_RST; | |
4662 | #endif | |
4663 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); | |
4664 | sd_card->pre_cmd_err = 1; | |
4665 | TRACE_RET(chip, TRANSPORT_FAILED); | |
4666 | } | |
4667 | #ifdef SUPPORT_SD_LOCK | |
4668 | sd_card->sd_lock_status &= ~SD_SDR_RST; | |
4669 | #endif | |
4670 | break; | |
4671 | ||
4672 | case 1: | |
4673 | retval = soft_reset_sd_card(chip); | |
4674 | if (retval != STATUS_SUCCESS) { | |
4675 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); | |
4676 | sd_card->pre_cmd_err = 1; | |
4677 | TRACE_RET(chip, TRANSPORT_FAILED); | |
4678 | } | |
4679 | break; | |
4680 | ||
4681 | default: | |
4682 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); | |
4683 | TRACE_RET(chip, TRANSPORT_FAILED); | |
4684 | } | |
4685 | ||
4686 | scsi_set_resid(srb, 0); | |
4687 | return TRANSPORT_GOOD; | |
4688 | } | |
4689 | #endif | |
4690 | ||
4691 | void sd_cleanup_work(struct rtsx_chip *chip) | |
4692 | { | |
4693 | struct sd_info *sd_card = &(chip->sd_card); | |
4694 | ||
4695 | if (sd_card->seq_mode) { | |
4696 | RTSX_DEBUGP("SD: stop transmission\n"); | |
4697 | sd_stop_seq_mode(chip); | |
4698 | sd_card->cleanup_counter = 0; | |
4699 | } | |
4700 | } | |
4701 | ||
4702 | int sd_power_off_card3v3(struct rtsx_chip *chip) | |
4703 | { | |
4704 | int retval; | |
4705 | ||
4706 | retval = disable_card_clock(chip, SD_CARD); | |
4707 | if (retval != STATUS_SUCCESS) { | |
4708 | TRACE_RET(chip, STATUS_FAIL); | |
4709 | } | |
4710 | ||
4711 | RTSX_WRITE_REG(chip, CARD_OE, SD_OUTPUT_EN, 0); | |
4712 | ||
4713 | if (!chip->ft2_fast_mode) { | |
4714 | retval = card_power_off(chip, SD_CARD); | |
4715 | if (retval != STATUS_SUCCESS) { | |
4716 | TRACE_RET(chip, STATUS_FAIL); | |
4717 | } | |
4718 | ||
4719 | wait_timeout(50); | |
4720 | } | |
4721 | ||
4722 | if (chip->asic_code) { | |
4723 | retval = sd_pull_ctl_disable(chip); | |
4724 | if (retval != STATUS_SUCCESS) { | |
4725 | TRACE_RET(chip, STATUS_FAIL); | |
4726 | } | |
4727 | } else { | |
4728 | RTSX_WRITE_REG(chip, FPGA_PULL_CTL, | |
4729 | FPGA_SD_PULL_CTL_BIT | 0x20, FPGA_SD_PULL_CTL_BIT); | |
4730 | } | |
4731 | ||
4732 | return STATUS_SUCCESS; | |
4733 | } | |
4734 | ||
4735 | int release_sd_card(struct rtsx_chip *chip) | |
4736 | { | |
4737 | struct sd_info *sd_card = &(chip->sd_card); | |
4738 | int retval; | |
4739 | ||
4740 | RTSX_DEBUGP("release_sd_card\n"); | |
4741 | ||
4742 | chip->card_ready &= ~SD_CARD; | |
4743 | chip->card_fail &= ~SD_CARD; | |
4744 | chip->card_wp &= ~SD_CARD; | |
4745 | ||
4746 | chip->sd_io = 0; | |
4747 | chip->sd_int = 0; | |
4748 | ||
4749 | #ifdef SUPPORT_SD_LOCK | |
4750 | sd_card->sd_lock_status = 0; | |
4751 | sd_card->sd_erase_status = 0; | |
4752 | #endif | |
4753 | ||
4754 | memset(sd_card->raw_csd, 0, 16); | |
4755 | memset(sd_card->raw_scr, 0, 8); | |
4756 | ||
4757 | retval = sd_power_off_card3v3(chip); | |
4758 | if (retval != STATUS_SUCCESS) { | |
4759 | TRACE_RET(chip, STATUS_FAIL); | |
4760 | } | |
4761 | ||
4762 | if (CHECK_PID(chip, 0x5209)) { | |
4763 | retval = sd_change_bank_voltage(chip, SD_IO_3V3); | |
4764 | if (retval != STATUS_SUCCESS) { | |
4765 | TRACE_RET(chip, STATUS_FAIL); | |
4766 | } | |
4767 | ||
4768 | if (CHK_SD30_SPEED(sd_card)) { | |
4769 | RTSX_WRITE_REG(chip, SD30_DRIVE_SEL, 0x07, chip->sd30_drive_sel_3v3); | |
4770 | } | |
4771 | ||
4772 | RTSX_WRITE_REG(chip, OCPPARA2, SD_OCP_THD_MASK, chip->sd_400mA_ocp_thd); | |
4773 | } | |
4774 | ||
4775 | return STATUS_SUCCESS; | |
4776 | } |