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3f85ce27 WD |
1 | /* |
2 | * Copyright (c) 2004 Picture Elements, Inc. | |
3 | * Stephen Williams (XXXXXXXXXXXXXXXX) | |
4 | * | |
5 | * This source code is free software; you can redistribute it | |
6 | * and/or modify it in source code form under the terms of the GNU | |
7 | * General Public License as published by the Free Software | |
8 | * Foundation; either version 2 of the License, or (at your option) | |
9 | * any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA | |
19 | */ | |
3f85ce27 WD |
20 | |
21 | /* | |
22 | * The Xilinx SystemACE chip support is activated by defining | |
23 | * CONFIG_SYSTEMACE to turn on support, and CFG_SYSTEMACE_BASE | |
24 | * to set the base address of the device. This code currently | |
25 | * assumes that the chip is connected via a byte-wide bus. | |
26 | * | |
27 | * The CONFIG_SYSTEMACE also adds to fat support the device class | |
28 | * "ace" that allows the user to execute "fatls ace 0" and the | |
29 | * like. This works by making the systemace_get_dev function | |
30 | * available to cmd_fat.c:get_dev and filling in a block device | |
31 | * description that has all the bits needed for FAT support to | |
32 | * read sectors. | |
8f79e4c2 | 33 | * |
fe599e17 WD |
34 | * According to Xilinx technical support, before accessing the |
35 | * SystemACE CF you need to set the following control bits: | |
984618f3 GL |
36 | * FORCECFGMODE : 1 |
37 | * CFGMODE : 0 | |
38 | * CFGSTART : 0 | |
3f85ce27 WD |
39 | */ |
40 | ||
984618f3 GL |
41 | #include <common.h> |
42 | #include <command.h> | |
43 | #include <systemace.h> | |
44 | #include <part.h> | |
45 | #include <asm/io.h> | |
3f85ce27 WD |
46 | |
47 | #ifdef CONFIG_SYSTEMACE | |
48 | ||
49 | /* | |
50 | * The ace_readw and writew functions read/write 16bit words, but the | |
51 | * offset value is the BYTE offset as most used in the Xilinx | |
52 | * datasheet for the SystemACE chip. The CFG_SYSTEMACE_BASE is defined | |
53 | * to be the base address for the chip, usually in the local | |
54 | * peripheral bus. | |
55 | */ | |
a5bbcc3c WD |
56 | #if (CFG_SYSTEMACE_WIDTH == 8) |
57 | #if !defined(__BIG_ENDIAN) | |
f4852ebe GL |
58 | #define ace_readw(off) ((readb(CFG_SYSTEMACE_BASE+off)<<8) | \ |
59 | (readb(CFG_SYSTEMACE_BASE+off+1))) | |
60 | #define ace_write(val, off) {writeb(val>>8, CFG_SYSTEMACE_BASE+off); \ | |
61 | writeb(val, CFG_SYSTEMACE_BASE+off+1);} | |
a5bbcc3c | 62 | #else |
f4852ebe GL |
63 | #define ace_readw(off) ((readb(CFG_SYSTEMACE_BASE+off)) | \ |
64 | (readb(CFG_SYSTEMACE_BASE+off+1)<<8)) | |
65 | #define ace_write(val, off) {writeb(val, CFG_SYSTEMACE_BASE+off); \ | |
66 | writeb(val>>8, CFG_SYSTEMACE_BASE+off+1);} | |
a5bbcc3c WD |
67 | #endif |
68 | #else | |
f4852ebe GL |
69 | #define ace_readw(off) (readw(CFG_SYSTEMACE_BASE+off)) |
70 | #define ace_writew(val, off) (writew(val, CFG_SYSTEMACE_BASE+off)) | |
a5bbcc3c | 71 | #endif |
3f85ce27 WD |
72 | |
73 | /* */ | |
74 | ||
984618f3 | 75 | static unsigned long systemace_read(int dev, unsigned long start, |
eb867a76 | 76 | unsigned long blkcnt, void *buffer); |
3f85ce27 | 77 | |
984618f3 | 78 | static block_dev_desc_t systemace_dev = { 0 }; |
3f85ce27 WD |
79 | |
80 | static int get_cf_lock(void) | |
81 | { | |
984618f3 | 82 | int retry = 10; |
3f85ce27 WD |
83 | |
84 | /* CONTROLREG = LOCKREG */ | |
984618f3 GL |
85 | unsigned val = ace_readw(0x18); |
86 | val |= 0x0002; | |
87 | ace_writew((val & 0xffff), 0x18); | |
3f85ce27 WD |
88 | |
89 | /* Wait for MPULOCK in STATUSREG[15:0] */ | |
984618f3 | 90 | while (!(ace_readw(0x04) & 0x0002)) { |
3f85ce27 | 91 | |
984618f3 GL |
92 | if (retry < 0) |
93 | return -1; | |
3f85ce27 | 94 | |
984618f3 GL |
95 | udelay(100000); |
96 | retry -= 1; | |
97 | } | |
3f85ce27 | 98 | |
984618f3 | 99 | return 0; |
3f85ce27 WD |
100 | } |
101 | ||
102 | static void release_cf_lock(void) | |
103 | { | |
984618f3 GL |
104 | unsigned val = ace_readw(0x18); |
105 | val &= ~(0x0002); | |
106 | ace_writew((val & 0xffff), 0x18); | |
3f85ce27 WD |
107 | } |
108 | ||
984618f3 | 109 | block_dev_desc_t *systemace_get_dev(int dev) |
3f85ce27 WD |
110 | { |
111 | /* The first time through this, the systemace_dev object is | |
112 | not yet initialized. In that case, fill it in. */ | |
984618f3 GL |
113 | if (systemace_dev.blksz == 0) { |
114 | systemace_dev.if_type = IF_TYPE_UNKNOWN; | |
115 | systemace_dev.dev = 0; | |
116 | systemace_dev.part_type = PART_TYPE_UNKNOWN; | |
117 | systemace_dev.type = DEV_TYPE_HARDDISK; | |
118 | systemace_dev.blksz = 512; | |
119 | systemace_dev.removable = 1; | |
120 | systemace_dev.block_read = systemace_read; | |
fe599e17 | 121 | |
984618f3 | 122 | init_part(&systemace_dev); |
fe599e17 | 123 | |
984618f3 | 124 | } |
3f85ce27 | 125 | |
984618f3 | 126 | return &systemace_dev; |
3f85ce27 WD |
127 | } |
128 | ||
129 | /* | |
130 | * This function is called (by dereferencing the block_read pointer in | |
131 | * the dev_desc) to read blocks of data. The return value is the | |
132 | * number of blocks read. A zero return indicates an error. | |
133 | */ | |
984618f3 | 134 | static unsigned long systemace_read(int dev, unsigned long start, |
eb867a76 | 135 | unsigned long blkcnt, void *buffer) |
3f85ce27 | 136 | { |
984618f3 GL |
137 | int retry; |
138 | unsigned blk_countdown; | |
eb867a76 | 139 | unsigned char *dp = buffer; |
984618f3 GL |
140 | unsigned val; |
141 | ||
142 | if (get_cf_lock() < 0) { | |
143 | unsigned status = ace_readw(0x04); | |
144 | ||
145 | /* If CFDETECT is false, card is missing. */ | |
146 | if (!(status & 0x0010)) { | |
147 | printf("** CompactFlash card not present. **\n"); | |
148 | return 0; | |
149 | } | |
150 | ||
151 | printf("**** ACE locked away from me (STATUSREG=%04x)\n", | |
152 | status); | |
153 | return 0; | |
154 | } | |
e7c85689 | 155 | #ifdef DEBUG_SYSTEMACE |
984618f3 | 156 | printf("... systemace read %lu sectors at %lu\n", blkcnt, start); |
e7c85689 WD |
157 | #endif |
158 | ||
984618f3 GL |
159 | retry = 2000; |
160 | for (;;) { | |
161 | val = ace_readw(0x04); | |
3f85ce27 | 162 | |
984618f3 GL |
163 | /* If CFDETECT is false, card is missing. */ |
164 | if (!(val & 0x0010)) { | |
165 | printf("**** ACE CompactFlash not found.\n"); | |
166 | release_cf_lock(); | |
167 | return 0; | |
168 | } | |
3f85ce27 | 169 | |
984618f3 GL |
170 | /* If RDYFORCMD, then we are ready to go. */ |
171 | if (val & 0x0100) | |
172 | break; | |
3f85ce27 | 173 | |
984618f3 GL |
174 | if (retry < 0) { |
175 | printf("**** SystemACE not ready.\n"); | |
176 | release_cf_lock(); | |
177 | return 0; | |
178 | } | |
3f85ce27 | 179 | |
984618f3 GL |
180 | udelay(1000); |
181 | retry -= 1; | |
182 | } | |
3f85ce27 | 183 | |
e7c85689 WD |
184 | /* The SystemACE can only transfer 256 sectors at a time, so |
185 | limit the current chunk of sectors. The blk_countdown | |
186 | variable is the number of sectors left to transfer. */ | |
3f85ce27 | 187 | |
984618f3 GL |
188 | blk_countdown = blkcnt; |
189 | while (blk_countdown > 0) { | |
190 | unsigned trans = blk_countdown; | |
3f85ce27 | 191 | |
984618f3 GL |
192 | if (trans > 256) |
193 | trans = 256; | |
3f85ce27 | 194 | |
e7c85689 | 195 | #ifdef DEBUG_SYSTEMACE |
984618f3 | 196 | printf("... transfer %lu sector in a chunk\n", trans); |
e7c85689 | 197 | #endif |
984618f3 GL |
198 | /* Write LBA block address */ |
199 | ace_writew((start >> 0) & 0xffff, 0x10); | |
200 | ace_writew((start >> 16) & 0x00ff, 0x12); | |
201 | ||
202 | /* NOTE: in the Write Sector count below, a count of 0 | |
203 | causes a transfer of 256, so &0xff gives the right | |
204 | value for whatever transfer count we want. */ | |
205 | ||
206 | /* Write sector count | ReadMemCardData. */ | |
207 | ace_writew((trans & 0xff) | 0x0300, 0x14); | |
208 | ||
209 | /* Reset the configruation controller */ | |
210 | val = ace_readw(0x18); | |
211 | val |= 0x0080; | |
212 | ace_writew(val, 0x18); | |
213 | ||
214 | retry = trans * 16; | |
215 | while (retry > 0) { | |
216 | int idx; | |
217 | ||
218 | /* Wait for buffer to become ready. */ | |
219 | while (!(ace_readw(0x04) & 0x0020)) { | |
220 | udelay(100); | |
221 | } | |
222 | ||
223 | /* Read 16 words of 2bytes from the sector buffer. */ | |
224 | for (idx = 0; idx < 16; idx += 1) { | |
225 | unsigned short val = ace_readw(0x40); | |
226 | *dp++ = val & 0xff; | |
227 | *dp++ = (val >> 8) & 0xff; | |
228 | } | |
229 | ||
230 | retry -= 1; | |
231 | } | |
232 | ||
233 | /* Clear the configruation controller reset */ | |
234 | val = ace_readw(0x18); | |
235 | val &= ~0x0080; | |
236 | ace_writew(val, 0x18); | |
237 | ||
238 | /* Count the blocks we transfer this time. */ | |
239 | start += trans; | |
240 | blk_countdown -= trans; | |
241 | } | |
242 | ||
243 | release_cf_lock(); | |
244 | ||
245 | return blkcnt; | |
3f85ce27 | 246 | } |
984618f3 | 247 | #endif /* CONFIG_SYSTEMACE */ |