[people/ms/u-boot.git] / drivers / timer / altera_timer.c

/*
 * (C) Copyright 2000-2002
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
 * Scott McNutt <smcnutt@psyent.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <dm.h>
#include <errno.h>
#include <timer.h>
#include <asm/io.h>

DECLARE_GLOBAL_DATA_PTR;

/* control register */
#define ALTERA_TIMER_CONT	BIT(1)	/* Continuous mode */
#define ALTERA_TIMER_START	BIT(2)	/* Start timer */
#define ALTERA_TIMER_STOP	BIT(3)	/* Stop timer */

struct altera_timer_regs {
	u32	status;		/* Timer status reg */
	u32	control;	/* Timer control reg */
	u32	periodl;	/* Timeout period low */
	u32	periodh;	/* Timeout period high */
	u32	snapl;		/* Snapshot low */
	u32	snaph;		/* Snapshot high */
};

struct altera_timer_platdata {
	struct altera_timer_regs *regs;
	unsigned long clock_rate;
};

static int altera_timer_get_count(struct udevice *dev, unsigned long *count)
{
	struct altera_timer_platdata *plat = dev->platdata;
	struct altera_timer_regs *const regs = plat->regs;
	u32 val;

	/* Trigger update */
	writel(0x0, &regs->snapl);

	/* Read timer value */
	val = readl(&regs->snapl) & 0xffff;
	val |= (readl(&regs->snaph) & 0xffff) << 16;
	*count = ~val;

	return 0;
}

static int altera_timer_probe(struct udevice *dev)
{
	struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
	struct altera_timer_platdata *plat = dev->platdata;
	struct altera_timer_regs *const regs = plat->regs;

	uc_priv->clock_rate = plat->clock_rate;

	writel(0, &regs->status);
	writel(0, &regs->control);
	writel(ALTERA_TIMER_STOP, &regs->control);

	writel(0xffff, &regs->periodl);
	writel(0xffff, &regs->periodh);
	writel(ALTERA_TIMER_CONT | ALTERA_TIMER_START, &regs->control);

	return 0;
}

static int altera_timer_ofdata_to_platdata(struct udevice *dev)
{
	struct altera_timer_platdata *plat = dev_get_platdata(dev);

	plat->regs = ioremap(dev_get_addr(dev),
		sizeof(struct altera_timer_regs));
	plat->clock_rate = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
		"clock-frequency", 0);

	return 0;
}

static const struct timer_ops altera_timer_ops = {
	.get_count = altera_timer_get_count,
};

static const struct udevice_id altera_timer_ids[] = {
	{ .compatible = "altr,timer-1.0" },
	{}
};

U_BOOT_DRIVER(altera_timer) = {
	.name	= "altera_timer",
	.id	= UCLASS_TIMER,
	.of_match = altera_timer_ids,
	.ofdata_to_platdata = altera_timer_ofdata_to_platdata,
	.platdata_auto_alloc_size = sizeof(struct altera_timer_platdata),
	.probe = altera_timer_probe,
	.ops	= &altera_timer_ops,
	.flags = DM_FLAG_PRE_RELOC,
};
Commit	Line	Data
a54915d8 TC	1	/*
	2	* (C) Copyright 2000-2002
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
	6	* Scott McNutt <smcnutt@psyent.com>
	7	*
	8	* SPDX-License-Identifier: GPL-2.0+
	9	*/
	10
	11	#include <common.h>
	12	#include <dm.h>
	13	#include <errno.h>
	14	#include <timer.h>
	15	#include <asm/io.h>
	16
	17	DECLARE_GLOBAL_DATA_PTR;
	18
1235e5a5 TC	19	/* control register */
	20	#define ALTERA_TIMER_CONT BIT(1) /* Continuous mode */
	21	#define ALTERA_TIMER_START BIT(2) /* Start timer */
	22	#define ALTERA_TIMER_STOP BIT(3) /* Stop timer */
	23
a54915d8 TC	24	struct altera_timer_regs {
	25	u32 status; /* Timer status reg */
	26	u32 control; /* Timer control reg */
	27	u32 periodl; /* Timeout period low */
	28	u32 periodh; /* Timeout period high */
	29	u32 snapl; /* Snapshot low */
	30	u32 snaph; /* Snapshot high */
	31	};
	32
	33	struct altera_timer_platdata {
	34	struct altera_timer_regs *regs;
	35	unsigned long clock_rate;
	36	};
	37
a54915d8 TC	38	static int altera_timer_get_count(struct udevice dev, unsigned long count)
	39	{
	40	struct altera_timer_platdata *plat = dev->platdata;
	41	struct altera_timer_regs *const regs = plat->regs;
	42	u32 val;
	43
	44	/* Trigger update */
	45	writel(0x0, &regs->snapl);
	46
	47	/* Read timer value */
	48	val = readl(&regs->snapl) & 0xffff;
	49	val \|= (readl(&regs->snaph) & 0xffff) << 16;
	50	*count = ~val;
	51
	52	return 0;
	53	}
	54
	55	static int altera_timer_probe(struct udevice *dev)
	56	{
	57	struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
	58	struct altera_timer_platdata *plat = dev->platdata;
	59	struct altera_timer_regs *const regs = plat->regs;
	60
	61	uc_priv->clock_rate = plat->clock_rate;
	62
	63	writel(0, &regs->status);
	64	writel(0, &regs->control);
	65	writel(ALTERA_TIMER_STOP, &regs->control);
	66
	67	writel(0xffff, &regs->periodl);
	68	writel(0xffff, &regs->periodh);
	69	writel(ALTERA_TIMER_CONT \| ALTERA_TIMER_START, &regs->control);
	70
	71	return 0;
	72	}
	73
	74	static int altera_timer_ofdata_to_platdata(struct udevice *dev)
	75	{
	76	struct altera_timer_platdata *plat = dev_get_platdata(dev);
	77
	78	plat->regs = ioremap(dev_get_addr(dev),
	79	sizeof(struct altera_timer_regs));
	80	plat->clock_rate = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
	81	"clock-frequency", 0);
	82
	83	return 0;
	84	}
	85
	86	static const struct timer_ops altera_timer_ops = {
	87	.get_count = altera_timer_get_count,
	88	};
	89
	90	static const struct udevice_id altera_timer_ids[] = {
1235e5a5 TC	91	{ .compatible = "altr,timer-1.0" },
1235e5a5 TC	92	{}
a54915d8 TC	93	};
	94
	95	U_BOOT_DRIVER(altera_timer) = {
	96	.name = "altera_timer",
	97	.id = UCLASS_TIMER,
	98	.of_match = altera_timer_ids,
	99	.ofdata_to_platdata = altera_timer_ofdata_to_platdata,
	100	.platdata_auto_alloc_size = sizeof(struct altera_timer_platdata),
	101	.probe = altera_timer_probe,
	102	.ops = &altera_timer_ops,
	103	.flags = DM_FLAG_PRE_RELOC,
	104	};