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Commit | Line | Data |
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42d1f039 | 1 | /* |
97d80fc3 | 2 | * Freescale Three Speed Ethernet Controller driver |
42d1f039 WD |
3 | * |
4 | * This software may be used and distributed according to the | |
5 | * terms of the GNU Public License, Version 2, incorporated | |
6 | * herein by reference. | |
7 | * | |
81f481ca | 8 | * Copyright 2004, 2007 Freescale Semiconductor, Inc. |
42d1f039 | 9 | * (C) Copyright 2003, Motorola, Inc. |
42d1f039 WD |
10 | * author Andy Fleming |
11 | * | |
12 | */ | |
13 | ||
14 | #include <config.h> | |
42d1f039 WD |
15 | #include <common.h> |
16 | #include <malloc.h> | |
17 | #include <net.h> | |
18 | #include <command.h> | |
19 | ||
20 | #if defined(CONFIG_TSEC_ENET) | |
21 | #include "tsec.h" | |
63ff004c | 22 | #include "miiphy.h" |
42d1f039 | 23 | |
d87080b7 WD |
24 | DECLARE_GLOBAL_DATA_PTR; |
25 | ||
63ff004c | 26 | #define TX_BUF_CNT 2 |
42d1f039 | 27 | |
89875e96 JL |
28 | static uint rxIdx; /* index of the current RX buffer */ |
29 | static uint txIdx; /* index of the current TX buffer */ | |
42d1f039 WD |
30 | |
31 | typedef volatile struct rtxbd { | |
32 | txbd8_t txbd[TX_BUF_CNT]; | |
33 | rxbd8_t rxbd[PKTBUFSRX]; | |
89875e96 | 34 | } RTXBD; |
42d1f039 | 35 | |
97d80fc3 WD |
36 | struct tsec_info_struct { |
37 | unsigned int phyaddr; | |
d9b94f28 | 38 | u32 flags; |
97d80fc3 WD |
39 | unsigned int phyregidx; |
40 | }; | |
41 | ||
97d80fc3 WD |
42 | /* The tsec_info structure contains 3 values which the |
43 | * driver uses to determine how to operate a given ethernet | |
09f3e09e | 44 | * device. The information needed is: |
97d80fc3 | 45 | * phyaddr - The address of the PHY which is attached to |
9d46ea4a | 46 | * the given device. |
97d80fc3 | 47 | * |
d9b94f28 JL |
48 | * flags - This variable indicates whether the device |
49 | * supports gigabit speed ethernet, and whether it should be | |
50 | * in reduced mode. | |
97d80fc3 WD |
51 | * |
52 | * phyregidx - This variable specifies which ethernet device | |
9d46ea4a | 53 | * controls the MII Management registers which are connected |
09f3e09e | 54 | * to the PHY. For now, only TSEC1 (index 0) has |
9d46ea4a | 55 | * access to the PHYs, so all of the entries have "0". |
97d80fc3 WD |
56 | * |
57 | * The values specified in the table are taken from the board's | |
58 | * config file in include/configs/. When implementing a new | |
59 | * board with ethernet capability, it is necessary to define: | |
09f3e09e AF |
60 | * TSECn_PHY_ADDR |
61 | * TSECn_PHYIDX | |
97d80fc3 | 62 | * |
09f3e09e | 63 | * for n = 1,2,3, etc. And for FEC: |
97d80fc3 WD |
64 | * FEC_PHY_ADDR |
65 | * FEC_PHYIDX | |
66 | */ | |
67 | static struct tsec_info_struct tsec_info[] = { | |
255a3577 KP |
68 | #if defined(CONFIG_TSEC1) |
69 | #if defined(CONFIG_MPC8544DS) || defined(CONFIG_MPC8641HPCN) | |
2f15278c | 70 | {TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX}, |
81f481ca | 71 | #else |
d9b94f28 | 72 | {TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX}, |
81f481ca | 73 | #endif |
89875e96 | 74 | {0, 0, 0}, |
97d80fc3 | 75 | #endif |
255a3577 KP |
76 | #if defined(CONFIG_TSEC2) |
77 | #if defined(CONFIG_MPC8641HPCN) | |
89875e96 | 78 | {TSEC2_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC2_PHYIDX}, |
9d46ea4a | 79 | #else |
255a3577 KP |
80 | {TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX}, |
81 | #endif | |
89875e96 | 82 | {0, 0, 0}, |
97d80fc3 WD |
83 | #endif |
84 | #ifdef CONFIG_MPC85XX_FEC | |
85 | {FEC_PHY_ADDR, 0, FEC_PHYIDX}, | |
9d46ea4a | 86 | #else |
255a3577 | 87 | #if defined(CONFIG_TSEC3) |
d9b94f28 | 88 | {TSEC3_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC3_PHYIDX}, |
debb7354 | 89 | #else |
89875e96 | 90 | {0, 0, 0}, |
debb7354 | 91 | #endif |
255a3577 | 92 | #if defined(CONFIG_TSEC4) |
09f3e09e | 93 | {TSEC4_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC4_PHYIDX}, |
debb7354 | 94 | #else |
89875e96 | 95 | {0, 0, 0}, |
debb7354 | 96 | #endif |
97d80fc3 WD |
97 | #endif |
98 | }; | |
99 | ||
d9b94f28 | 100 | #define MAXCONTROLLERS (4) |
97d80fc3 WD |
101 | |
102 | static int relocated = 0; | |
103 | ||
104 | static struct tsec_private *privlist[MAXCONTROLLERS]; | |
105 | ||
42d1f039 WD |
106 | #ifdef __GNUC__ |
107 | static RTXBD rtx __attribute__ ((aligned(8))); | |
108 | #else | |
109 | #error "rtx must be 64-bit aligned" | |
110 | #endif | |
111 | ||
89875e96 JL |
112 | static int tsec_send(struct eth_device *dev, |
113 | volatile void *packet, int length); | |
114 | static int tsec_recv(struct eth_device *dev); | |
115 | static int tsec_init(struct eth_device *dev, bd_t * bd); | |
116 | static void tsec_halt(struct eth_device *dev); | |
117 | static void init_registers(volatile tsec_t * regs); | |
97d80fc3 WD |
118 | static void startup_tsec(struct eth_device *dev); |
119 | static int init_phy(struct eth_device *dev); | |
120 | void write_phy_reg(struct tsec_private *priv, uint regnum, uint value); | |
121 | uint read_phy_reg(struct tsec_private *priv, uint regnum); | |
89875e96 | 122 | struct phy_info *get_phy_info(struct eth_device *dev); |
97d80fc3 WD |
123 | void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd); |
124 | static void adjust_link(struct eth_device *dev); | |
125 | static void relocate_cmds(void); | |
63ff004c | 126 | static int tsec_miiphy_write(char *devname, unsigned char addr, |
89875e96 | 127 | unsigned char reg, unsigned short value); |
63ff004c | 128 | static int tsec_miiphy_read(char *devname, unsigned char addr, |
89875e96 | 129 | unsigned char reg, unsigned short *value); |
97d80fc3 WD |
130 | |
131 | /* Initialize device structure. Returns success if PHY | |
132 | * initialization succeeded (i.e. if it recognizes the PHY) | |
133 | */ | |
89875e96 | 134 | int tsec_initialize(bd_t * bis, int index, char *devname) |
42d1f039 | 135 | { |
89875e96 | 136 | struct eth_device *dev; |
42d1f039 | 137 | int i; |
97d80fc3 | 138 | struct tsec_private *priv; |
42d1f039 | 139 | |
89875e96 | 140 | dev = (struct eth_device *)malloc(sizeof *dev); |
42d1f039 | 141 | |
89875e96 | 142 | if (NULL == dev) |
42d1f039 WD |
143 | return 0; |
144 | ||
145 | memset(dev, 0, sizeof *dev); | |
146 | ||
89875e96 | 147 | priv = (struct tsec_private *)malloc(sizeof(*priv)); |
97d80fc3 | 148 | |
89875e96 | 149 | if (NULL == priv) |
97d80fc3 WD |
150 | return 0; |
151 | ||
152 | privlist[index] = priv; | |
89875e96 | 153 | priv->regs = (volatile tsec_t *)(TSEC_BASE_ADDR + index * TSEC_SIZE); |
97d80fc3 | 154 | priv->phyregs = (volatile tsec_t *)(TSEC_BASE_ADDR + |
89875e96 JL |
155 | tsec_info[index].phyregidx * |
156 | TSEC_SIZE); | |
97d80fc3 WD |
157 | |
158 | priv->phyaddr = tsec_info[index].phyaddr; | |
d9b94f28 | 159 | priv->flags = tsec_info[index].flags; |
97d80fc3 | 160 | |
d9b94f28 | 161 | sprintf(dev->name, devname); |
42d1f039 | 162 | dev->iobase = 0; |
89875e96 JL |
163 | dev->priv = priv; |
164 | dev->init = tsec_init; | |
165 | dev->halt = tsec_halt; | |
166 | dev->send = tsec_send; | |
167 | dev->recv = tsec_recv; | |
42d1f039 WD |
168 | |
169 | /* Tell u-boot to get the addr from the env */ | |
89875e96 | 170 | for (i = 0; i < 6; i++) |
42d1f039 WD |
171 | dev->enetaddr[i] = 0; |
172 | ||
173 | eth_register(dev); | |
174 | ||
97d80fc3 WD |
175 | /* Reset the MAC */ |
176 | priv->regs->maccfg1 |= MACCFG1_SOFT_RESET; | |
177 | priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET); | |
7abf0c58 | 178 | |
63ff004c MB |
179 | #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) \ |
180 | && !defined(BITBANGMII) | |
181 | miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write); | |
182 | #endif | |
183 | ||
97d80fc3 WD |
184 | /* Try to initialize PHY here, and return */ |
185 | return init_phy(dev); | |
42d1f039 WD |
186 | } |
187 | ||
42d1f039 | 188 | /* Initializes data structures and registers for the controller, |
9d46ea4a | 189 | * and brings the interface up. Returns the link status, meaning |
97d80fc3 | 190 | * that it returns success if the link is up, failure otherwise. |
89875e96 JL |
191 | * This allows u-boot to find the first active controller. |
192 | */ | |
193 | int tsec_init(struct eth_device *dev, bd_t * bd) | |
42d1f039 | 194 | { |
42d1f039 WD |
195 | uint tempval; |
196 | char tmpbuf[MAC_ADDR_LEN]; | |
197 | int i; | |
97d80fc3 WD |
198 | struct tsec_private *priv = (struct tsec_private *)dev->priv; |
199 | volatile tsec_t *regs = priv->regs; | |
42d1f039 WD |
200 | |
201 | /* Make sure the controller is stopped */ | |
202 | tsec_halt(dev); | |
203 | ||
97d80fc3 | 204 | /* Init MACCFG2. Defaults to GMII */ |
42d1f039 WD |
205 | regs->maccfg2 = MACCFG2_INIT_SETTINGS; |
206 | ||
207 | /* Init ECNTRL */ | |
208 | regs->ecntrl = ECNTRL_INIT_SETTINGS; | |
209 | ||
210 | /* Copy the station address into the address registers. | |
211 | * Backwards, because little endian MACS are dumb */ | |
89875e96 | 212 | for (i = 0; i < MAC_ADDR_LEN; i++) { |
97d80fc3 | 213 | tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i]; |
42d1f039 | 214 | } |
89875e96 | 215 | regs->macstnaddr1 = *((uint *) (tmpbuf)); |
42d1f039 | 216 | |
89875e96 | 217 | tempval = *((uint *) (tmpbuf + 4)); |
42d1f039 | 218 | |
77ddac94 | 219 | regs->macstnaddr2 = tempval; |
42d1f039 | 220 | |
42d1f039 WD |
221 | /* reset the indices to zero */ |
222 | rxIdx = 0; | |
223 | txIdx = 0; | |
224 | ||
225 | /* Clear out (for the most part) the other registers */ | |
226 | init_registers(regs); | |
227 | ||
228 | /* Ready the device for tx/rx */ | |
97d80fc3 | 229 | startup_tsec(dev); |
42d1f039 | 230 | |
97d80fc3 WD |
231 | /* If there's no link, fail */ |
232 | return priv->link; | |
42d1f039 WD |
233 | |
234 | } | |
235 | ||
97d80fc3 WD |
236 | /* Write value to the device's PHY through the registers |
237 | * specified in priv, modifying the register specified in regnum. | |
238 | * It will wait for the write to be done (or for a timeout to | |
239 | * expire) before exiting | |
240 | */ | |
241 | void write_phy_reg(struct tsec_private *priv, uint regnum, uint value) | |
242 | { | |
243 | volatile tsec_t *regbase = priv->phyregs; | |
244 | uint phyid = priv->phyaddr; | |
89875e96 | 245 | int timeout = 1000000; |
97d80fc3 WD |
246 | |
247 | regbase->miimadd = (phyid << 8) | regnum; | |
248 | regbase->miimcon = value; | |
f046ccd1 | 249 | asm("sync"); |
97d80fc3 | 250 | |
89875e96 JL |
251 | timeout = 1000000; |
252 | while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ; | |
97d80fc3 WD |
253 | } |
254 | ||
97d80fc3 | 255 | /* Reads register regnum on the device's PHY through the |
9d46ea4a | 256 | * registers specified in priv. It lowers and raises the read |
97d80fc3 WD |
257 | * command, and waits for the data to become valid (miimind |
258 | * notvalid bit cleared), and the bus to cease activity (miimind | |
259 | * busy bit cleared), and then returns the value | |
260 | */ | |
261 | uint read_phy_reg(struct tsec_private *priv, uint regnum) | |
42d1f039 WD |
262 | { |
263 | uint value; | |
97d80fc3 WD |
264 | volatile tsec_t *regbase = priv->phyregs; |
265 | uint phyid = priv->phyaddr; | |
42d1f039 | 266 | |
97d80fc3 WD |
267 | /* Put the address of the phy, and the register |
268 | * number into MIIMADD */ | |
269 | regbase->miimadd = (phyid << 8) | regnum; | |
42d1f039 WD |
270 | |
271 | /* Clear the command register, and wait */ | |
272 | regbase->miimcom = 0; | |
f046ccd1 | 273 | asm("sync"); |
42d1f039 WD |
274 | |
275 | /* Initiate a read command, and wait */ | |
276 | regbase->miimcom = MIIM_READ_COMMAND; | |
f046ccd1 | 277 | asm("sync"); |
42d1f039 WD |
278 | |
279 | /* Wait for the the indication that the read is done */ | |
89875e96 | 280 | while ((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ; |
42d1f039 WD |
281 | |
282 | /* Grab the value read from the PHY */ | |
283 | value = regbase->miimstat; | |
284 | ||
285 | return value; | |
286 | } | |
287 | ||
97d80fc3 WD |
288 | /* Discover which PHY is attached to the device, and configure it |
289 | * properly. If the PHY is not recognized, then return 0 | |
290 | * (failure). Otherwise, return 1 | |
291 | */ | |
292 | static int init_phy(struct eth_device *dev) | |
42d1f039 | 293 | { |
97d80fc3 WD |
294 | struct tsec_private *priv = (struct tsec_private *)dev->priv; |
295 | struct phy_info *curphy; | |
89875e96 | 296 | volatile tsec_t *regs = (volatile tsec_t *)(TSEC_BASE_ADDR); |
42d1f039 WD |
297 | |
298 | /* Assign a Physical address to the TBI */ | |
89875e96 JL |
299 | regs->tbipa = TBIPA_VALUE; |
300 | regs = (volatile tsec_t *)(TSEC_BASE_ADDR + TSEC_SIZE); | |
301 | regs->tbipa = TBIPA_VALUE; | |
302 | asm("sync"); | |
3dd7f0f0 WD |
303 | |
304 | /* Reset MII (due to new addresses) */ | |
305 | priv->phyregs->miimcfg = MIIMCFG_RESET; | |
f046ccd1 | 306 | asm("sync"); |
3dd7f0f0 | 307 | priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE; |
f046ccd1 | 308 | asm("sync"); |
89875e96 | 309 | while (priv->phyregs->miimind & MIIMIND_BUSY) ; |
42d1f039 | 310 | |
89875e96 | 311 | if (0 == relocated) |
97d80fc3 | 312 | relocate_cmds(); |
42d1f039 | 313 | |
97d80fc3 WD |
314 | /* Get the cmd structure corresponding to the attached |
315 | * PHY */ | |
316 | curphy = get_phy_info(dev); | |
42d1f039 | 317 | |
4653f91c BW |
318 | if (curphy == NULL) { |
319 | priv->phyinfo = NULL; | |
97d80fc3 | 320 | printf("%s: No PHY found\n", dev->name); |
42d1f039 | 321 | |
97d80fc3 WD |
322 | return 0; |
323 | } | |
42d1f039 | 324 | |
97d80fc3 | 325 | priv->phyinfo = curphy; |
42d1f039 | 326 | |
97d80fc3 | 327 | phy_run_commands(priv, priv->phyinfo->config); |
42d1f039 | 328 | |
97d80fc3 WD |
329 | return 1; |
330 | } | |
42d1f039 | 331 | |
89875e96 JL |
332 | /* |
333 | * Returns which value to write to the control register. | |
334 | * For 10/100, the value is slightly different | |
335 | */ | |
336 | uint mii_cr_init(uint mii_reg, struct tsec_private * priv) | |
97d80fc3 | 337 | { |
89875e96 | 338 | if (priv->flags & TSEC_GIGABIT) |
97d80fc3 | 339 | return MIIM_CONTROL_INIT; |
42d1f039 | 340 | else |
97d80fc3 WD |
341 | return MIIM_CR_INIT; |
342 | } | |
42d1f039 | 343 | |
97d80fc3 | 344 | /* Parse the status register for link, and then do |
89875e96 JL |
345 | * auto-negotiation |
346 | */ | |
347 | uint mii_parse_sr(uint mii_reg, struct tsec_private * priv) | |
97d80fc3 | 348 | { |
5810dc3a | 349 | /* |
89875e96 JL |
350 | * Wait if PHY is capable of autonegotiation and autonegotiation |
351 | * is not complete. | |
5810dc3a SR |
352 | */ |
353 | mii_reg = read_phy_reg(priv, MIIM_STATUS); | |
89875e96 JL |
354 | if ((mii_reg & PHY_BMSR_AUTN_ABLE) |
355 | && !(mii_reg & PHY_BMSR_AUTN_COMP)) { | |
5810dc3a SR |
356 | int i = 0; |
357 | ||
89875e96 JL |
358 | puts("Waiting for PHY auto negotiation to complete"); |
359 | while (!((mii_reg & PHY_BMSR_AUTN_COMP) | |
360 | && (mii_reg & MIIM_STATUS_LINK))) { | |
5810dc3a SR |
361 | /* |
362 | * Timeout reached ? | |
363 | */ | |
364 | if (i > PHY_AUTONEGOTIATE_TIMEOUT) { | |
89875e96 | 365 | puts(" TIMEOUT !\n"); |
5810dc3a | 366 | priv->link = 0; |
fcfb9a57 | 367 | return 0; |
5810dc3a | 368 | } |
42d1f039 | 369 | |
5810dc3a | 370 | if ((i++ % 1000) == 0) { |
89875e96 | 371 | putc('.'); |
5810dc3a | 372 | } |
89875e96 | 373 | udelay(1000); /* 1 ms */ |
97d80fc3 | 374 | mii_reg = read_phy_reg(priv, MIIM_STATUS); |
5810dc3a | 375 | } |
89875e96 | 376 | puts(" done\n"); |
5810dc3a | 377 | priv->link = 1; |
89875e96 | 378 | udelay(500000); /* another 500 ms (results in faster booting) */ |
5810dc3a SR |
379 | } else { |
380 | priv->link = 1; | |
42d1f039 WD |
381 | } |
382 | ||
97d80fc3 WD |
383 | return 0; |
384 | } | |
42d1f039 | 385 | |
af1c2b84 DU |
386 | /* Generic function which updates the speed and duplex. If |
387 | * autonegotiation is enabled, it uses the AND of the link | |
388 | * partner's advertised capabilities and our advertised | |
389 | * capabilities. If autonegotiation is disabled, we use the | |
390 | * appropriate bits in the control register. | |
391 | * | |
392 | * Stolen from Linux's mii.c and phy_device.c | |
393 | */ | |
394 | uint mii_parse_link(uint mii_reg, struct tsec_private *priv) | |
395 | { | |
396 | /* We're using autonegotiation */ | |
397 | if (mii_reg & PHY_BMSR_AUTN_ABLE) { | |
398 | uint lpa = 0; | |
399 | uint gblpa = 0; | |
400 | ||
401 | /* Check for gigabit capability */ | |
402 | if (mii_reg & PHY_BMSR_EXT) { | |
403 | /* We want a list of states supported by | |
404 | * both PHYs in the link | |
405 | */ | |
406 | gblpa = read_phy_reg(priv, PHY_1000BTSR); | |
407 | gblpa &= read_phy_reg(priv, PHY_1000BTCR) << 2; | |
408 | } | |
409 | ||
410 | /* Set the baseline so we only have to set them | |
411 | * if they're different | |
412 | */ | |
413 | priv->speed = 10; | |
414 | priv->duplexity = 0; | |
415 | ||
416 | /* Check the gigabit fields */ | |
417 | if (gblpa & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) { | |
418 | priv->speed = 1000; | |
419 | ||
420 | if (gblpa & PHY_1000BTSR_1000FD) | |
421 | priv->duplexity = 1; | |
422 | ||
423 | /* We're done! */ | |
424 | return 0; | |
425 | } | |
426 | ||
427 | lpa = read_phy_reg(priv, PHY_ANAR); | |
428 | lpa &= read_phy_reg(priv, PHY_ANLPAR); | |
429 | ||
430 | if (lpa & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) { | |
431 | priv->speed = 100; | |
432 | ||
433 | if (lpa & PHY_ANLPAR_TXFD) | |
434 | priv->duplexity = 1; | |
435 | ||
436 | } else if (lpa & PHY_ANLPAR_10FD) | |
437 | priv->duplexity = 1; | |
438 | } else { | |
439 | uint bmcr = read_phy_reg(priv, PHY_BMCR); | |
440 | ||
441 | priv->speed = 10; | |
442 | priv->duplexity = 0; | |
443 | ||
444 | if (bmcr & PHY_BMCR_DPLX) | |
445 | priv->duplexity = 1; | |
446 | ||
447 | if (bmcr & PHY_BMCR_1000_MBPS) | |
448 | priv->speed = 1000; | |
449 | else if (bmcr & PHY_BMCR_100_MBPS) | |
450 | priv->speed = 100; | |
451 | } | |
452 | ||
453 | return 0; | |
454 | } | |
455 | ||
91e25769 PG |
456 | /* |
457 | * Parse the BCM54xx status register for speed and duplex information. | |
458 | * The linux sungem_phy has this information, but in a table format. | |
459 | */ | |
460 | uint mii_parse_BCM54xx_sr(uint mii_reg, struct tsec_private *priv) | |
461 | { | |
462 | ||
463 | switch((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >> MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT){ | |
464 | ||
465 | case 1: | |
466 | printf("Enet starting in 10BT/HD\n"); | |
467 | priv->duplexity = 0; | |
468 | priv->speed = 10; | |
469 | break; | |
470 | ||
471 | case 2: | |
472 | printf("Enet starting in 10BT/FD\n"); | |
473 | priv->duplexity = 1; | |
474 | priv->speed = 10; | |
475 | break; | |
476 | ||
477 | case 3: | |
478 | printf("Enet starting in 100BT/HD\n"); | |
479 | priv->duplexity = 0; | |
480 | priv->speed = 100; | |
481 | break; | |
482 | ||
483 | case 5: | |
484 | printf("Enet starting in 100BT/FD\n"); | |
485 | priv->duplexity = 1; | |
486 | priv->speed = 100; | |
487 | break; | |
488 | ||
489 | case 6: | |
490 | printf("Enet starting in 1000BT/HD\n"); | |
491 | priv->duplexity = 0; | |
492 | priv->speed = 1000; | |
493 | break; | |
494 | ||
495 | case 7: | |
496 | printf("Enet starting in 1000BT/FD\n"); | |
497 | priv->duplexity = 1; | |
498 | priv->speed = 1000; | |
499 | break; | |
500 | ||
501 | default: | |
502 | printf("Auto-neg error, defaulting to 10BT/HD\n"); | |
503 | priv->duplexity = 0; | |
504 | priv->speed = 10; | |
505 | break; | |
506 | } | |
507 | ||
508 | return 0; | |
509 | ||
510 | } | |
97d80fc3 | 511 | /* Parse the 88E1011's status register for speed and duplex |
89875e96 JL |
512 | * information |
513 | */ | |
514 | uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv) | |
97d80fc3 WD |
515 | { |
516 | uint speed; | |
517 | ||
5810dc3a SR |
518 | mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS); |
519 | ||
520 | if (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) && | |
521 | (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) { | |
522 | int i = 0; | |
523 | ||
89875e96 | 524 | puts("Waiting for PHY realtime link"); |
5810dc3a SR |
525 | while (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) && |
526 | (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) { | |
527 | /* | |
528 | * Timeout reached ? | |
529 | */ | |
530 | if (i > PHY_AUTONEGOTIATE_TIMEOUT) { | |
89875e96 | 531 | puts(" TIMEOUT !\n"); |
5810dc3a SR |
532 | priv->link = 0; |
533 | break; | |
534 | } | |
535 | ||
536 | if ((i++ % 1000) == 0) { | |
89875e96 | 537 | putc('.'); |
5810dc3a | 538 | } |
89875e96 | 539 | udelay(1000); /* 1 ms */ |
5810dc3a SR |
540 | mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS); |
541 | } | |
89875e96 JL |
542 | puts(" done\n"); |
543 | udelay(500000); /* another 500 ms (results in faster booting) */ | |
5810dc3a SR |
544 | } |
545 | ||
89875e96 | 546 | if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX) |
97d80fc3 WD |
547 | priv->duplexity = 1; |
548 | else | |
549 | priv->duplexity = 0; | |
550 | ||
89875e96 | 551 | speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED); |
97d80fc3 | 552 | |
89875e96 JL |
553 | switch (speed) { |
554 | case MIIM_88E1011_PHYSTAT_GBIT: | |
555 | priv->speed = 1000; | |
556 | break; | |
557 | case MIIM_88E1011_PHYSTAT_100: | |
558 | priv->speed = 100; | |
559 | break; | |
560 | default: | |
561 | priv->speed = 10; | |
42d1f039 WD |
562 | } |
563 | ||
97d80fc3 WD |
564 | return 0; |
565 | } | |
42d1f039 | 566 | |
97d80fc3 | 567 | /* Parse the cis8201's status register for speed and duplex |
89875e96 JL |
568 | * information |
569 | */ | |
570 | uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv) | |
97d80fc3 WD |
571 | { |
572 | uint speed; | |
573 | ||
89875e96 | 574 | if (mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX) |
97d80fc3 WD |
575 | priv->duplexity = 1; |
576 | else | |
577 | priv->duplexity = 0; | |
578 | ||
579 | speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED; | |
89875e96 JL |
580 | switch (speed) { |
581 | case MIIM_CIS8201_AUXCONSTAT_GBIT: | |
582 | priv->speed = 1000; | |
583 | break; | |
584 | case MIIM_CIS8201_AUXCONSTAT_100: | |
585 | priv->speed = 100; | |
586 | break; | |
587 | default: | |
588 | priv->speed = 10; | |
589 | break; | |
42d1f039 WD |
590 | } |
591 | ||
97d80fc3 WD |
592 | return 0; |
593 | } | |
89875e96 | 594 | |
debb7354 | 595 | /* Parse the vsc8244's status register for speed and duplex |
89875e96 JL |
596 | * information |
597 | */ | |
598 | uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv) | |
debb7354 | 599 | { |
89875e96 | 600 | uint speed; |
42d1f039 | 601 | |
89875e96 JL |
602 | if (mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX) |
603 | priv->duplexity = 1; | |
604 | else | |
605 | priv->duplexity = 0; | |
606 | ||
607 | speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED; | |
608 | switch (speed) { | |
609 | case MIIM_VSC8244_AUXCONSTAT_GBIT: | |
610 | priv->speed = 1000; | |
611 | break; | |
612 | case MIIM_VSC8244_AUXCONSTAT_100: | |
613 | priv->speed = 100; | |
614 | break; | |
615 | default: | |
616 | priv->speed = 10; | |
617 | break; | |
618 | } | |
619 | ||
620 | return 0; | |
621 | } | |
97d80fc3 WD |
622 | |
623 | /* Parse the DM9161's status register for speed and duplex | |
89875e96 JL |
624 | * information |
625 | */ | |
626 | uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv) | |
97d80fc3 | 627 | { |
89875e96 | 628 | if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H)) |
97d80fc3 WD |
629 | priv->speed = 100; |
630 | else | |
631 | priv->speed = 10; | |
632 | ||
89875e96 | 633 | if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F)) |
97d80fc3 WD |
634 | priv->duplexity = 1; |
635 | else | |
636 | priv->duplexity = 0; | |
637 | ||
638 | return 0; | |
639 | } | |
640 | ||
89875e96 JL |
641 | /* |
642 | * Hack to write all 4 PHYs with the LED values | |
643 | */ | |
644 | uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv) | |
97d80fc3 WD |
645 | { |
646 | uint phyid; | |
647 | volatile tsec_t *regbase = priv->phyregs; | |
89875e96 | 648 | int timeout = 1000000; |
97d80fc3 | 649 | |
89875e96 | 650 | for (phyid = 0; phyid < 4; phyid++) { |
97d80fc3 WD |
651 | regbase->miimadd = (phyid << 8) | mii_reg; |
652 | regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT; | |
f046ccd1 | 653 | asm("sync"); |
97d80fc3 | 654 | |
89875e96 JL |
655 | timeout = 1000000; |
656 | while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ; | |
42d1f039 | 657 | } |
42d1f039 | 658 | |
97d80fc3 | 659 | return MIIM_CIS8204_SLEDCON_INIT; |
42d1f039 WD |
660 | } |
661 | ||
89875e96 | 662 | uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv) |
d9b94f28 JL |
663 | { |
664 | if (priv->flags & TSEC_REDUCED) | |
665 | return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII; | |
666 | else | |
667 | return MIIM_CIS8204_EPHYCON_INIT; | |
668 | } | |
42d1f039 | 669 | |
97d80fc3 WD |
670 | /* Initialized required registers to appropriate values, zeroing |
671 | * those we don't care about (unless zero is bad, in which case, | |
89875e96 JL |
672 | * choose a more appropriate value) |
673 | */ | |
674 | static void init_registers(volatile tsec_t * regs) | |
42d1f039 WD |
675 | { |
676 | /* Clear IEVENT */ | |
677 | regs->ievent = IEVENT_INIT_CLEAR; | |
678 | ||
679 | regs->imask = IMASK_INIT_CLEAR; | |
680 | ||
681 | regs->hash.iaddr0 = 0; | |
682 | regs->hash.iaddr1 = 0; | |
683 | regs->hash.iaddr2 = 0; | |
684 | regs->hash.iaddr3 = 0; | |
685 | regs->hash.iaddr4 = 0; | |
686 | regs->hash.iaddr5 = 0; | |
687 | regs->hash.iaddr6 = 0; | |
688 | regs->hash.iaddr7 = 0; | |
689 | ||
690 | regs->hash.gaddr0 = 0; | |
691 | regs->hash.gaddr1 = 0; | |
692 | regs->hash.gaddr2 = 0; | |
693 | regs->hash.gaddr3 = 0; | |
694 | regs->hash.gaddr4 = 0; | |
695 | regs->hash.gaddr5 = 0; | |
696 | regs->hash.gaddr6 = 0; | |
697 | regs->hash.gaddr7 = 0; | |
698 | ||
699 | regs->rctrl = 0x00000000; | |
700 | ||
701 | /* Init RMON mib registers */ | |
702 | memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t)); | |
703 | ||
704 | regs->rmon.cam1 = 0xffffffff; | |
705 | regs->rmon.cam2 = 0xffffffff; | |
706 | ||
707 | regs->mrblr = MRBLR_INIT_SETTINGS; | |
708 | ||
709 | regs->minflr = MINFLR_INIT_SETTINGS; | |
710 | ||
711 | regs->attr = ATTR_INIT_SETTINGS; | |
712 | regs->attreli = ATTRELI_INIT_SETTINGS; | |
713 | ||
714 | } | |
715 | ||
97d80fc3 | 716 | /* Configure maccfg2 based on negotiated speed and duplex |
89875e96 JL |
717 | * reported by PHY handling code |
718 | */ | |
97d80fc3 WD |
719 | static void adjust_link(struct eth_device *dev) |
720 | { | |
721 | struct tsec_private *priv = (struct tsec_private *)dev->priv; | |
722 | volatile tsec_t *regs = priv->regs; | |
723 | ||
89875e96 JL |
724 | if (priv->link) { |
725 | if (priv->duplexity != 0) | |
97d80fc3 WD |
726 | regs->maccfg2 |= MACCFG2_FULL_DUPLEX; |
727 | else | |
728 | regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX); | |
729 | ||
89875e96 JL |
730 | switch (priv->speed) { |
731 | case 1000: | |
732 | regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF)) | |
733 | | MACCFG2_GMII); | |
734 | break; | |
735 | case 100: | |
736 | case 10: | |
737 | regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF)) | |
738 | | MACCFG2_MII); | |
739 | ||
f484dc79 NS |
740 | /* Set R100 bit in all modes although |
741 | * it is only used in RGMII mode | |
89875e96 | 742 | */ |
f484dc79 | 743 | if (priv->speed == 100) |
89875e96 JL |
744 | regs->ecntrl |= ECNTRL_R100; |
745 | else | |
746 | regs->ecntrl &= ~(ECNTRL_R100); | |
747 | break; | |
748 | default: | |
749 | printf("%s: Speed was bad\n", dev->name); | |
750 | break; | |
97d80fc3 WD |
751 | } |
752 | ||
753 | printf("Speed: %d, %s duplex\n", priv->speed, | |
89875e96 | 754 | (priv->duplexity) ? "full" : "half"); |
97d80fc3 WD |
755 | |
756 | } else { | |
757 | printf("%s: No link.\n", dev->name); | |
758 | } | |
759 | } | |
760 | ||
97d80fc3 | 761 | /* Set up the buffers and their descriptors, and bring up the |
89875e96 JL |
762 | * interface |
763 | */ | |
97d80fc3 | 764 | static void startup_tsec(struct eth_device *dev) |
42d1f039 WD |
765 | { |
766 | int i; | |
97d80fc3 WD |
767 | struct tsec_private *priv = (struct tsec_private *)dev->priv; |
768 | volatile tsec_t *regs = priv->regs; | |
42d1f039 WD |
769 | |
770 | /* Point to the buffer descriptors */ | |
771 | regs->tbase = (unsigned int)(&rtx.txbd[txIdx]); | |
772 | regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]); | |
773 | ||
774 | /* Initialize the Rx Buffer descriptors */ | |
775 | for (i = 0; i < PKTBUFSRX; i++) { | |
776 | rtx.rxbd[i].status = RXBD_EMPTY; | |
777 | rtx.rxbd[i].length = 0; | |
89875e96 | 778 | rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i]; |
42d1f039 | 779 | } |
89875e96 | 780 | rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP; |
42d1f039 WD |
781 | |
782 | /* Initialize the TX Buffer Descriptors */ | |
89875e96 | 783 | for (i = 0; i < TX_BUF_CNT; i++) { |
42d1f039 WD |
784 | rtx.txbd[i].status = 0; |
785 | rtx.txbd[i].length = 0; | |
786 | rtx.txbd[i].bufPtr = 0; | |
787 | } | |
89875e96 | 788 | rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP; |
42d1f039 | 789 | |
97d80fc3 | 790 | /* Start up the PHY */ |
4653f91c BW |
791 | if(priv->phyinfo) |
792 | phy_run_commands(priv, priv->phyinfo->startup); | |
af1c2b84 | 793 | |
97d80fc3 WD |
794 | adjust_link(dev); |
795 | ||
42d1f039 WD |
796 | /* Enable Transmit and Receive */ |
797 | regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN); | |
798 | ||
799 | /* Tell the DMA it is clear to go */ | |
800 | regs->dmactrl |= DMACTRL_INIT_SETTINGS; | |
801 | regs->tstat = TSTAT_CLEAR_THALT; | |
802 | regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); | |
803 | } | |
804 | ||
9d46ea4a | 805 | /* This returns the status bits of the device. The return value |
42d1f039 | 806 | * is never checked, and this is what the 8260 driver did, so we |
9d46ea4a | 807 | * do the same. Presumably, this would be zero if there were no |
89875e96 JL |
808 | * errors |
809 | */ | |
810 | static int tsec_send(struct eth_device *dev, volatile void *packet, int length) | |
42d1f039 WD |
811 | { |
812 | int i; | |
813 | int result = 0; | |
97d80fc3 WD |
814 | struct tsec_private *priv = (struct tsec_private *)dev->priv; |
815 | volatile tsec_t *regs = priv->regs; | |
42d1f039 WD |
816 | |
817 | /* Find an empty buffer descriptor */ | |
89875e96 | 818 | for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) { |
42d1f039 | 819 | if (i >= TOUT_LOOP) { |
89875e96 | 820 | debug("%s: tsec: tx buffers full\n", dev->name); |
42d1f039 WD |
821 | return result; |
822 | } | |
823 | } | |
824 | ||
89875e96 | 825 | rtx.txbd[txIdx].bufPtr = (uint) packet; |
42d1f039 | 826 | rtx.txbd[txIdx].length = length; |
89875e96 JL |
827 | rtx.txbd[txIdx].status |= |
828 | (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT); | |
42d1f039 WD |
829 | |
830 | /* Tell the DMA to go */ | |
831 | regs->tstat = TSTAT_CLEAR_THALT; | |
832 | ||
833 | /* Wait for buffer to be transmitted */ | |
89875e96 | 834 | for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) { |
42d1f039 | 835 | if (i >= TOUT_LOOP) { |
89875e96 | 836 | debug("%s: tsec: tx error\n", dev->name); |
42d1f039 WD |
837 | return result; |
838 | } | |
839 | } | |
840 | ||
841 | txIdx = (txIdx + 1) % TX_BUF_CNT; | |
842 | result = rtx.txbd[txIdx].status & TXBD_STATS; | |
843 | ||
844 | return result; | |
845 | } | |
846 | ||
89875e96 | 847 | static int tsec_recv(struct eth_device *dev) |
42d1f039 WD |
848 | { |
849 | int length; | |
97d80fc3 WD |
850 | struct tsec_private *priv = (struct tsec_private *)dev->priv; |
851 | volatile tsec_t *regs = priv->regs; | |
42d1f039 | 852 | |
89875e96 | 853 | while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) { |
42d1f039 WD |
854 | |
855 | length = rtx.rxbd[rxIdx].length; | |
856 | ||
857 | /* Send the packet up if there were no errors */ | |
858 | if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) { | |
859 | NetReceive(NetRxPackets[rxIdx], length - 4); | |
97d80fc3 WD |
860 | } else { |
861 | printf("Got error %x\n", | |
89875e96 | 862 | (rtx.rxbd[rxIdx].status & RXBD_STATS)); |
42d1f039 WD |
863 | } |
864 | ||
865 | rtx.rxbd[rxIdx].length = 0; | |
866 | ||
867 | /* Set the wrap bit if this is the last element in the list */ | |
89875e96 JL |
868 | rtx.rxbd[rxIdx].status = |
869 | RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0); | |
42d1f039 WD |
870 | |
871 | rxIdx = (rxIdx + 1) % PKTBUFSRX; | |
872 | } | |
873 | ||
89875e96 | 874 | if (regs->ievent & IEVENT_BSY) { |
42d1f039 WD |
875 | regs->ievent = IEVENT_BSY; |
876 | regs->rstat = RSTAT_CLEAR_RHALT; | |
877 | } | |
878 | ||
879 | return -1; | |
880 | ||
881 | } | |
882 | ||
97d80fc3 | 883 | /* Stop the interface */ |
89875e96 | 884 | static void tsec_halt(struct eth_device *dev) |
42d1f039 | 885 | { |
97d80fc3 WD |
886 | struct tsec_private *priv = (struct tsec_private *)dev->priv; |
887 | volatile tsec_t *regs = priv->regs; | |
42d1f039 WD |
888 | |
889 | regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); | |
890 | regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS); | |
891 | ||
89875e96 | 892 | while (!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))) ; |
42d1f039 WD |
893 | |
894 | regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN); | |
895 | ||
97d80fc3 | 896 | /* Shut down the PHY, as needed */ |
4653f91c BW |
897 | if(priv->phyinfo) |
898 | phy_run_commands(priv, priv->phyinfo->shutdown); | |
97d80fc3 WD |
899 | } |
900 | ||
91e25769 PG |
901 | /* The 5411 id is 0x206070, the 5421 is 0x2060e0 */ |
902 | struct phy_info phy_info_BCM5461S = { | |
903 | 0x02060c1, /* 5461 ID */ | |
904 | "Broadcom BCM5461S", | |
905 | 0, /* not clear to me what minor revisions we can shift away */ | |
906 | (struct phy_cmd[]) { /* config */ | |
907 | /* Reset and configure the PHY */ | |
908 | {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, | |
909 | {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, | |
910 | {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, | |
911 | {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, | |
912 | {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, | |
913 | {miim_end,} | |
914 | }, | |
915 | (struct phy_cmd[]) { /* startup */ | |
916 | /* Status is read once to clear old link state */ | |
917 | {MIIM_STATUS, miim_read, NULL}, | |
918 | /* Auto-negotiate */ | |
919 | {MIIM_STATUS, miim_read, &mii_parse_sr}, | |
920 | /* Read the status */ | |
921 | {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr}, | |
922 | {miim_end,} | |
923 | }, | |
924 | (struct phy_cmd[]) { /* shutdown */ | |
925 | {miim_end,} | |
926 | }, | |
927 | }; | |
928 | ||
c3243cf7 JH |
929 | struct phy_info phy_info_BCM5464S = { |
930 | 0x02060b1, /* 5464 ID */ | |
931 | "Broadcom BCM5464S", | |
932 | 0, /* not clear to me what minor revisions we can shift away */ | |
933 | (struct phy_cmd[]) { /* config */ | |
934 | /* Reset and configure the PHY */ | |
935 | {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, | |
936 | {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, | |
937 | {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, | |
938 | {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, | |
939 | {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, | |
940 | {miim_end,} | |
941 | }, | |
942 | (struct phy_cmd[]) { /* startup */ | |
943 | /* Status is read once to clear old link state */ | |
944 | {MIIM_STATUS, miim_read, NULL}, | |
945 | /* Auto-negotiate */ | |
946 | {MIIM_STATUS, miim_read, &mii_parse_sr}, | |
947 | /* Read the status */ | |
948 | {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr}, | |
949 | {miim_end,} | |
950 | }, | |
951 | (struct phy_cmd[]) { /* shutdown */ | |
952 | {miim_end,} | |
953 | }, | |
954 | }; | |
955 | ||
97d80fc3 WD |
956 | struct phy_info phy_info_M88E1011S = { |
957 | 0x01410c6, | |
958 | "Marvell 88E1011S", | |
959 | 4, | |
89875e96 JL |
960 | (struct phy_cmd[]){ /* config */ |
961 | /* Reset and configure the PHY */ | |
962 | {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, | |
963 | {0x1d, 0x1f, NULL}, | |
964 | {0x1e, 0x200c, NULL}, | |
965 | {0x1d, 0x5, NULL}, | |
966 | {0x1e, 0x0, NULL}, | |
967 | {0x1e, 0x100, NULL}, | |
968 | {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, | |
969 | {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, | |
970 | {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, | |
971 | {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, | |
972 | {miim_end,} | |
973 | }, | |
974 | (struct phy_cmd[]){ /* startup */ | |
975 | /* Status is read once to clear old link state */ | |
976 | {MIIM_STATUS, miim_read, NULL}, | |
977 | /* Auto-negotiate */ | |
978 | {MIIM_STATUS, miim_read, &mii_parse_sr}, | |
979 | /* Read the status */ | |
980 | {MIIM_88E1011_PHY_STATUS, miim_read, | |
981 | &mii_parse_88E1011_psr}, | |
982 | {miim_end,} | |
983 | }, | |
984 | (struct phy_cmd[]){ /* shutdown */ | |
985 | {miim_end,} | |
986 | }, | |
97d80fc3 WD |
987 | }; |
988 | ||
9d46ea4a WD |
989 | struct phy_info phy_info_M88E1111S = { |
990 | 0x01410cc, | |
991 | "Marvell 88E1111S", | |
992 | 4, | |
89875e96 JL |
993 | (struct phy_cmd[]){ /* config */ |
994 | /* Reset and configure the PHY */ | |
995 | {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, | |
996 | {0x1d, 0x1f, NULL}, | |
997 | {0x1e, 0x200c, NULL}, | |
998 | {0x1d, 0x5, NULL}, | |
999 | {0x1e, 0x0, NULL}, | |
1000 | {0x1e, 0x100, NULL}, | |
f484dc79 | 1001 | {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */ |
89875e96 JL |
1002 | {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, |
1003 | {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, | |
1004 | {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, | |
1005 | {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, | |
1006 | {miim_end,} | |
1007 | }, | |
1008 | (struct phy_cmd[]){ /* startup */ | |
1009 | /* Status is read once to clear old link state */ | |
1010 | {MIIM_STATUS, miim_read, NULL}, | |
1011 | /* Auto-negotiate */ | |
1012 | {MIIM_STATUS, miim_read, &mii_parse_sr}, | |
1013 | /* Read the status */ | |
1014 | {MIIM_88E1011_PHY_STATUS, miim_read, | |
1015 | &mii_parse_88E1011_psr}, | |
1016 | {miim_end,} | |
1017 | }, | |
1018 | (struct phy_cmd[]){ /* shutdown */ | |
1019 | {miim_end,} | |
1020 | }, | |
9d46ea4a WD |
1021 | }; |
1022 | ||
09f3e09e AF |
1023 | static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv) |
1024 | { | |
09f3e09e AF |
1025 | uint mii_data = read_phy_reg(priv, mii_reg); |
1026 | ||
09f3e09e AF |
1027 | /* Setting MIIM_88E1145_PHY_EXT_CR */ |
1028 | if (priv->flags & TSEC_REDUCED) | |
1029 | return mii_data | | |
89875e96 | 1030 | MIIM_M88E1145_RGMII_RX_DELAY | MIIM_M88E1145_RGMII_TX_DELAY; |
09f3e09e AF |
1031 | else |
1032 | return mii_data; | |
1033 | } | |
1034 | ||
1035 | static struct phy_info phy_info_M88E1145 = { | |
1036 | 0x01410cd, | |
1037 | "Marvell 88E1145", | |
1038 | 4, | |
89875e96 JL |
1039 | (struct phy_cmd[]){ /* config */ |
1040 | /* Errata E0, E1 */ | |
1041 | {29, 0x001b, NULL}, | |
1042 | {30, 0x418f, NULL}, | |
1043 | {29, 0x0016, NULL}, | |
1044 | {30, 0xa2da, NULL}, | |
1045 | ||
1046 | /* Reset and configure the PHY */ | |
1047 | {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, | |
1048 | {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, | |
1049 | {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, | |
1050 | {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO, | |
1051 | NULL}, | |
1052 | {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode}, | |
1053 | {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, | |
1054 | {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL}, | |
1055 | {miim_end,} | |
1056 | }, | |
1057 | (struct phy_cmd[]){ /* startup */ | |
1058 | /* Status is read once to clear old link state */ | |
1059 | {MIIM_STATUS, miim_read, NULL}, | |
1060 | /* Auto-negotiate */ | |
1061 | {MIIM_STATUS, miim_read, &mii_parse_sr}, | |
1062 | {MIIM_88E1111_PHY_LED_CONTROL, | |
1063 | MIIM_88E1111_PHY_LED_DIRECT, NULL}, | |
1064 | /* Read the Status */ | |
1065 | {MIIM_88E1011_PHY_STATUS, miim_read, | |
1066 | &mii_parse_88E1011_psr}, | |
1067 | {miim_end,} | |
1068 | }, | |
1069 | (struct phy_cmd[]){ /* shutdown */ | |
1070 | {miim_end,} | |
1071 | }, | |
09f3e09e AF |
1072 | }; |
1073 | ||
97d80fc3 WD |
1074 | struct phy_info phy_info_cis8204 = { |
1075 | 0x3f11, | |
1076 | "Cicada Cis8204", | |
1077 | 6, | |
89875e96 JL |
1078 | (struct phy_cmd[]){ /* config */ |
1079 | /* Override PHY config settings */ | |
1080 | {MIIM_CIS8201_AUX_CONSTAT, | |
1081 | MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, | |
1082 | /* Configure some basic stuff */ | |
1083 | {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, | |
1084 | {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT, | |
1085 | &mii_cis8204_fixled}, | |
1086 | {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT, | |
1087 | &mii_cis8204_setmode}, | |
1088 | {miim_end,} | |
1089 | }, | |
1090 | (struct phy_cmd[]){ /* startup */ | |
1091 | /* Read the Status (2x to make sure link is right) */ | |
1092 | {MIIM_STATUS, miim_read, NULL}, | |
1093 | /* Auto-negotiate */ | |
1094 | {MIIM_STATUS, miim_read, &mii_parse_sr}, | |
1095 | /* Read the status */ | |
1096 | {MIIM_CIS8201_AUX_CONSTAT, miim_read, | |
1097 | &mii_parse_cis8201}, | |
1098 | {miim_end,} | |
1099 | }, | |
1100 | (struct phy_cmd[]){ /* shutdown */ | |
1101 | {miim_end,} | |
1102 | }, | |
97d80fc3 WD |
1103 | }; |
1104 | ||
1105 | /* Cicada 8201 */ | |
1106 | struct phy_info phy_info_cis8201 = { | |
1107 | 0xfc41, | |
1108 | "CIS8201", | |
1109 | 4, | |
89875e96 JL |
1110 | (struct phy_cmd[]){ /* config */ |
1111 | /* Override PHY config settings */ | |
1112 | {MIIM_CIS8201_AUX_CONSTAT, | |
1113 | MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, | |
1114 | /* Set up the interface mode */ | |
1115 | {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, | |
1116 | NULL}, | |
1117 | /* Configure some basic stuff */ | |
1118 | {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, | |
1119 | {miim_end,} | |
1120 | }, | |
1121 | (struct phy_cmd[]){ /* startup */ | |
1122 | /* Read the Status (2x to make sure link is right) */ | |
1123 | {MIIM_STATUS, miim_read, NULL}, | |
1124 | /* Auto-negotiate */ | |
1125 | {MIIM_STATUS, miim_read, &mii_parse_sr}, | |
1126 | /* Read the status */ | |
1127 | {MIIM_CIS8201_AUX_CONSTAT, miim_read, | |
1128 | &mii_parse_cis8201}, | |
1129 | {miim_end,} | |
1130 | }, | |
1131 | (struct phy_cmd[]){ /* shutdown */ | |
1132 | {miim_end,} | |
1133 | }, | |
97d80fc3 | 1134 | }; |
debb7354 | 1135 | struct phy_info phy_info_VSC8244 = { |
89875e96 JL |
1136 | 0x3f1b, |
1137 | "Vitesse VSC8244", | |
1138 | 6, | |
1139 | (struct phy_cmd[]){ /* config */ | |
1140 | /* Override PHY config settings */ | |
1141 | /* Configure some basic stuff */ | |
1142 | {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, | |
1143 | {miim_end,} | |
1144 | }, | |
1145 | (struct phy_cmd[]){ /* startup */ | |
1146 | /* Read the Status (2x to make sure link is right) */ | |
1147 | {MIIM_STATUS, miim_read, NULL}, | |
1148 | /* Auto-negotiate */ | |
1149 | {MIIM_STATUS, miim_read, &mii_parse_sr}, | |
1150 | /* Read the status */ | |
1151 | {MIIM_VSC8244_AUX_CONSTAT, miim_read, | |
1152 | &mii_parse_vsc8244}, | |
1153 | {miim_end,} | |
1154 | }, | |
1155 | (struct phy_cmd[]){ /* shutdown */ | |
1156 | {miim_end,} | |
1157 | }, | |
debb7354 | 1158 | }; |
97d80fc3 | 1159 | |
97d80fc3 WD |
1160 | struct phy_info phy_info_dm9161 = { |
1161 | 0x0181b88, | |
1162 | "Davicom DM9161E", | |
1163 | 4, | |
89875e96 JL |
1164 | (struct phy_cmd[]){ /* config */ |
1165 | {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL}, | |
1166 | /* Do not bypass the scrambler/descrambler */ | |
1167 | {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL}, | |
1168 | /* Clear 10BTCSR to default */ | |
1169 | {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT, | |
1170 | NULL}, | |
1171 | /* Configure some basic stuff */ | |
1172 | {MIIM_CONTROL, MIIM_CR_INIT, NULL}, | |
1173 | /* Restart Auto Negotiation */ | |
1174 | {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL}, | |
1175 | {miim_end,} | |
1176 | }, | |
1177 | (struct phy_cmd[]){ /* startup */ | |
1178 | /* Status is read once to clear old link state */ | |
1179 | {MIIM_STATUS, miim_read, NULL}, | |
1180 | /* Auto-negotiate */ | |
1181 | {MIIM_STATUS, miim_read, &mii_parse_sr}, | |
1182 | /* Read the status */ | |
1183 | {MIIM_DM9161_SCSR, miim_read, | |
1184 | &mii_parse_dm9161_scsr}, | |
1185 | {miim_end,} | |
1186 | }, | |
1187 | (struct phy_cmd[]){ /* shutdown */ | |
1188 | {miim_end,} | |
1189 | }, | |
97d80fc3 | 1190 | }; |
af1c2b84 DU |
1191 | /* a generic flavor. */ |
1192 | struct phy_info phy_info_generic = { | |
1193 | 0, | |
1194 | "Unknown/Generic PHY", | |
1195 | 32, | |
1196 | (struct phy_cmd[]) { /* config */ | |
1197 | {PHY_BMCR, PHY_BMCR_RESET, NULL}, | |
1198 | {PHY_BMCR, PHY_BMCR_AUTON|PHY_BMCR_RST_NEG, NULL}, | |
1199 | {miim_end,} | |
1200 | }, | |
1201 | (struct phy_cmd[]) { /* startup */ | |
1202 | {PHY_BMSR, miim_read, NULL}, | |
1203 | {PHY_BMSR, miim_read, &mii_parse_sr}, | |
1204 | {PHY_BMSR, miim_read, &mii_parse_link}, | |
1205 | {miim_end,} | |
1206 | }, | |
1207 | (struct phy_cmd[]) { /* shutdown */ | |
1208 | {miim_end,} | |
1209 | } | |
1210 | }; | |
1211 | ||
97d80fc3 | 1212 | |
3dd7f0f0 WD |
1213 | uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv) |
1214 | { | |
3c2b3d45 WD |
1215 | unsigned int speed; |
1216 | if (priv->link) { | |
1217 | speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK; | |
1218 | ||
1219 | switch (speed) { | |
1220 | case MIIM_LXT971_SR2_10HDX: | |
1221 | priv->speed = 10; | |
1222 | priv->duplexity = 0; | |
1223 | break; | |
1224 | case MIIM_LXT971_SR2_10FDX: | |
1225 | priv->speed = 10; | |
1226 | priv->duplexity = 1; | |
1227 | break; | |
1228 | case MIIM_LXT971_SR2_100HDX: | |
1229 | priv->speed = 100; | |
1230 | priv->duplexity = 0; | |
1231 | default: | |
1232 | priv->speed = 100; | |
1233 | priv->duplexity = 1; | |
1234 | break; | |
1235 | } | |
1236 | } else { | |
1237 | priv->speed = 0; | |
1238 | priv->duplexity = 0; | |
1239 | } | |
1240 | ||
1241 | return 0; | |
3dd7f0f0 WD |
1242 | } |
1243 | ||
9d46ea4a WD |
1244 | static struct phy_info phy_info_lxt971 = { |
1245 | 0x0001378e, | |
1246 | "LXT971", | |
1247 | 4, | |
89875e96 JL |
1248 | (struct phy_cmd[]){ /* config */ |
1249 | {MIIM_CR, MIIM_CR_INIT, mii_cr_init}, /* autonegotiate */ | |
1250 | {miim_end,} | |
1251 | }, | |
1252 | (struct phy_cmd[]){ /* startup - enable interrupts */ | |
1253 | /* { 0x12, 0x00f2, NULL }, */ | |
1254 | {MIIM_STATUS, miim_read, NULL}, | |
1255 | {MIIM_STATUS, miim_read, &mii_parse_sr}, | |
1256 | {MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2}, | |
1257 | {miim_end,} | |
1258 | }, | |
1259 | (struct phy_cmd[]){ /* shutdown - disable interrupts */ | |
1260 | {miim_end,} | |
1261 | }, | |
9d46ea4a WD |
1262 | }; |
1263 | ||
be5048f1 | 1264 | /* Parse the DP83865's link and auto-neg status register for speed and duplex |
89875e96 JL |
1265 | * information |
1266 | */ | |
be5048f1 WD |
1267 | uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv) |
1268 | { | |
1269 | switch (mii_reg & MIIM_DP83865_SPD_MASK) { | |
1270 | ||
1271 | case MIIM_DP83865_SPD_1000: | |
1272 | priv->speed = 1000; | |
1273 | break; | |
1274 | ||
1275 | case MIIM_DP83865_SPD_100: | |
1276 | priv->speed = 100; | |
1277 | break; | |
1278 | ||
1279 | default: | |
1280 | priv->speed = 10; | |
1281 | break; | |
1282 | ||
1283 | } | |
1284 | ||
1285 | if (mii_reg & MIIM_DP83865_DPX_FULL) | |
1286 | priv->duplexity = 1; | |
1287 | else | |
1288 | priv->duplexity = 0; | |
1289 | ||
1290 | return 0; | |
1291 | } | |
1292 | ||
1293 | struct phy_info phy_info_dp83865 = { | |
1294 | 0x20005c7, | |
1295 | "NatSemi DP83865", | |
1296 | 4, | |
89875e96 JL |
1297 | (struct phy_cmd[]){ /* config */ |
1298 | {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL}, | |
1299 | {miim_end,} | |
1300 | }, | |
1301 | (struct phy_cmd[]){ /* startup */ | |
1302 | /* Status is read once to clear old link state */ | |
1303 | {MIIM_STATUS, miim_read, NULL}, | |
1304 | /* Auto-negotiate */ | |
1305 | {MIIM_STATUS, miim_read, &mii_parse_sr}, | |
1306 | /* Read the link and auto-neg status */ | |
1307 | {MIIM_DP83865_LANR, miim_read, | |
1308 | &mii_parse_dp83865_lanr}, | |
1309 | {miim_end,} | |
1310 | }, | |
1311 | (struct phy_cmd[]){ /* shutdown */ | |
1312 | {miim_end,} | |
1313 | }, | |
be5048f1 WD |
1314 | }; |
1315 | ||
97d80fc3 | 1316 | struct phy_info *phy_info[] = { |
97d80fc3 | 1317 | &phy_info_cis8204, |
2ad6b513 | 1318 | &phy_info_cis8201, |
91e25769 | 1319 | &phy_info_BCM5461S, |
c3243cf7 | 1320 | &phy_info_BCM5464S, |
97d80fc3 | 1321 | &phy_info_M88E1011S, |
9d46ea4a | 1322 | &phy_info_M88E1111S, |
09f3e09e | 1323 | &phy_info_M88E1145, |
97d80fc3 | 1324 | &phy_info_dm9161, |
9d46ea4a | 1325 | &phy_info_lxt971, |
debb7354 | 1326 | &phy_info_VSC8244, |
be5048f1 | 1327 | &phy_info_dp83865, |
af1c2b84 | 1328 | &phy_info_generic, |
97d80fc3 WD |
1329 | NULL |
1330 | }; | |
1331 | ||
97d80fc3 | 1332 | /* Grab the identifier of the device's PHY, and search through |
9d46ea4a | 1333 | * all of the known PHYs to see if one matches. If so, return |
89875e96 JL |
1334 | * it, if not, return NULL |
1335 | */ | |
1336 | struct phy_info *get_phy_info(struct eth_device *dev) | |
97d80fc3 WD |
1337 | { |
1338 | struct tsec_private *priv = (struct tsec_private *)dev->priv; | |
1339 | uint phy_reg, phy_ID; | |
1340 | int i; | |
1341 | struct phy_info *theInfo = NULL; | |
1342 | ||
1343 | /* Grab the bits from PHYIR1, and put them in the upper half */ | |
1344 | phy_reg = read_phy_reg(priv, MIIM_PHYIR1); | |
1345 | phy_ID = (phy_reg & 0xffff) << 16; | |
1346 | ||
1347 | /* Grab the bits from PHYIR2, and put them in the lower half */ | |
1348 | phy_reg = read_phy_reg(priv, MIIM_PHYIR2); | |
1349 | phy_ID |= (phy_reg & 0xffff); | |
1350 | ||
1351 | /* loop through all the known PHY types, and find one that */ | |
1352 | /* matches the ID we read from the PHY. */ | |
89875e96 JL |
1353 | for (i = 0; phy_info[i]; i++) { |
1354 | if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) | |
97d80fc3 WD |
1355 | theInfo = phy_info[i]; |
1356 | } | |
1357 | ||
89875e96 | 1358 | if (theInfo == NULL) { |
97d80fc3 WD |
1359 | printf("%s: PHY id %x is not supported!\n", dev->name, phy_ID); |
1360 | return NULL; | |
1361 | } else { | |
5810dc3a | 1362 | debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID); |
97d80fc3 WD |
1363 | } |
1364 | ||
1365 | return theInfo; | |
42d1f039 | 1366 | } |
7abf0c58 | 1367 | |
97d80fc3 | 1368 | /* Execute the given series of commands on the given device's |
89875e96 JL |
1369 | * PHY, running functions as necessary |
1370 | */ | |
97d80fc3 WD |
1371 | void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd) |
1372 | { | |
1373 | int i; | |
1374 | uint result; | |
1375 | volatile tsec_t *phyregs = priv->phyregs; | |
1376 | ||
1377 | phyregs->miimcfg = MIIMCFG_RESET; | |
1378 | ||
1379 | phyregs->miimcfg = MIIMCFG_INIT_VALUE; | |
1380 | ||
89875e96 | 1381 | while (phyregs->miimind & MIIMIND_BUSY) ; |
97d80fc3 | 1382 | |
89875e96 JL |
1383 | for (i = 0; cmd->mii_reg != miim_end; i++) { |
1384 | if (cmd->mii_data == miim_read) { | |
97d80fc3 WD |
1385 | result = read_phy_reg(priv, cmd->mii_reg); |
1386 | ||
89875e96 JL |
1387 | if (cmd->funct != NULL) |
1388 | (*(cmd->funct)) (result, priv); | |
97d80fc3 WD |
1389 | |
1390 | } else { | |
89875e96 JL |
1391 | if (cmd->funct != NULL) |
1392 | result = (*(cmd->funct)) (cmd->mii_reg, priv); | |
97d80fc3 WD |
1393 | else |
1394 | result = cmd->mii_data; | |
1395 | ||
1396 | write_phy_reg(priv, cmd->mii_reg, result); | |
1397 | ||
1398 | } | |
1399 | cmd++; | |
1400 | } | |
1401 | } | |
1402 | ||
97d80fc3 WD |
1403 | /* Relocate the function pointers in the phy cmd lists */ |
1404 | static void relocate_cmds(void) | |
1405 | { | |
1406 | struct phy_cmd **cmdlistptr; | |
1407 | struct phy_cmd *cmd; | |
89875e96 | 1408 | int i, j, k; |
97d80fc3 | 1409 | |
89875e96 | 1410 | for (i = 0; phy_info[i]; i++) { |
97d80fc3 WD |
1411 | /* First thing's first: relocate the pointers to the |
1412 | * PHY command structures (the structs were done) */ | |
89875e96 JL |
1413 | phy_info[i] = (struct phy_info *)((uint) phy_info[i] |
1414 | + gd->reloc_off); | |
97d80fc3 WD |
1415 | phy_info[i]->name += gd->reloc_off; |
1416 | phy_info[i]->config = | |
89875e96 JL |
1417 | (struct phy_cmd *)((uint) phy_info[i]->config |
1418 | + gd->reloc_off); | |
97d80fc3 | 1419 | phy_info[i]->startup = |
89875e96 JL |
1420 | (struct phy_cmd *)((uint) phy_info[i]->startup |
1421 | + gd->reloc_off); | |
97d80fc3 | 1422 | phy_info[i]->shutdown = |
89875e96 JL |
1423 | (struct phy_cmd *)((uint) phy_info[i]->shutdown |
1424 | + gd->reloc_off); | |
97d80fc3 WD |
1425 | |
1426 | cmdlistptr = &phy_info[i]->config; | |
89875e96 JL |
1427 | j = 0; |
1428 | for (; cmdlistptr <= &phy_info[i]->shutdown; cmdlistptr++) { | |
1429 | k = 0; | |
1430 | for (cmd = *cmdlistptr; | |
1431 | cmd->mii_reg != miim_end; | |
1432 | cmd++) { | |
97d80fc3 | 1433 | /* Only relocate non-NULL pointers */ |
89875e96 | 1434 | if (cmd->funct) |
97d80fc3 WD |
1435 | cmd->funct += gd->reloc_off; |
1436 | ||
1437 | k++; | |
1438 | } | |
1439 | j++; | |
1440 | } | |
1441 | } | |
1442 | ||
1443 | relocated = 1; | |
1444 | } | |
1445 | ||
63ff004c MB |
1446 | #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) \ |
1447 | && !defined(BITBANGMII) | |
97d80fc3 | 1448 | |
89875e96 | 1449 | struct tsec_private *get_priv_for_phy(unsigned char phyaddr) |
97d80fc3 WD |
1450 | { |
1451 | int i; | |
1452 | ||
89875e96 JL |
1453 | for (i = 0; i < MAXCONTROLLERS; i++) { |
1454 | if (privlist[i]->phyaddr == phyaddr) | |
97d80fc3 WD |
1455 | return privlist[i]; |
1456 | } | |
1457 | ||
1458 | return NULL; | |
1459 | } | |
1460 | ||
7abf0c58 WD |
1461 | /* |
1462 | * Read a MII PHY register. | |
1463 | * | |
1464 | * Returns: | |
97d80fc3 | 1465 | * 0 on success |
7abf0c58 | 1466 | */ |
63ff004c | 1467 | static int tsec_miiphy_read(char *devname, unsigned char addr, |
89875e96 | 1468 | unsigned char reg, unsigned short *value) |
7abf0c58 | 1469 | { |
97d80fc3 WD |
1470 | unsigned short ret; |
1471 | struct tsec_private *priv = get_priv_for_phy(addr); | |
1472 | ||
89875e96 | 1473 | if (NULL == priv) { |
97d80fc3 WD |
1474 | printf("Can't read PHY at address %d\n", addr); |
1475 | return -1; | |
1476 | } | |
7abf0c58 | 1477 | |
97d80fc3 WD |
1478 | ret = (unsigned short)read_phy_reg(priv, reg); |
1479 | *value = ret; | |
7abf0c58 WD |
1480 | |
1481 | return 0; | |
1482 | } | |
1483 | ||
1484 | /* | |
1485 | * Write a MII PHY register. | |
1486 | * | |
1487 | * Returns: | |
97d80fc3 | 1488 | * 0 on success |
7abf0c58 | 1489 | */ |
63ff004c | 1490 | static int tsec_miiphy_write(char *devname, unsigned char addr, |
89875e96 | 1491 | unsigned char reg, unsigned short value) |
7abf0c58 | 1492 | { |
97d80fc3 WD |
1493 | struct tsec_private *priv = get_priv_for_phy(addr); |
1494 | ||
89875e96 | 1495 | if (NULL == priv) { |
97d80fc3 WD |
1496 | printf("Can't write PHY at address %d\n", addr); |
1497 | return -1; | |
1498 | } | |
7abf0c58 | 1499 | |
97d80fc3 | 1500 | write_phy_reg(priv, reg, value); |
7abf0c58 WD |
1501 | |
1502 | return 0; | |
1503 | } | |
97d80fc3 | 1504 | |
63ff004c MB |
1505 | #endif /* defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) |
1506 | && !defined(BITBANGMII) */ | |
97d80fc3 | 1507 | |
42d1f039 | 1508 | #endif /* CONFIG_TSEC_ENET */ |