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1/*
2 * tsec.h
3 *
4 * Driver for the Motorola Triple Speed Ethernet Controller
5 *
6 * This software may be used and distributed according to the
7 * terms of the GNU Public License, Version 2, incorporated
8 * herein by reference.
9 *
81f481ca 10 * Copyright 2004, 2007 Freescale Semiconductor, Inc.
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11 * (C) Copyright 2003, Motorola, Inc.
12 * maintained by Xianghua Xiao (x.xiao@motorola.com)
13 * author Andy Fleming
14 *
15 */
16
17#ifndef __TSEC_H
18#define __TSEC_H
19
20#include <net.h>
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21#include <config.h>
22
23#ifndef CFG_TSEC1_OFFSET
24 #define CFG_TSEC1_OFFSET (0x24000)
25#endif
42d1f039 26
97d80fc3 27#define TSEC_SIZE 0x01000
42d1f039 28
f046ccd1 29/* FIXME: Should these be pushed back to 83xx and 85xx config files? */
debb7354 30#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
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31 #define TSEC_BASE_ADDR (CFG_IMMR + CFG_TSEC1_OFFSET)
32#elif defined(CONFIG_MPC83XX)
d239d74b 33 #define TSEC_BASE_ADDR (CFG_IMMR + CFG_TSEC1_OFFSET)
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34#endif
35
36
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37#define MAC_ADDR_LEN 6
38
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39/* #define TSEC_TIMEOUT 1000000 */
40#define TSEC_TIMEOUT 1000
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41#define TOUT_LOOP 1000000
42
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43#define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* in ms */
44
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45/* MAC register bits */
46#define MACCFG1_SOFT_RESET 0x80000000
47#define MACCFG1_RESET_RX_MC 0x00080000
48#define MACCFG1_RESET_TX_MC 0x00040000
49#define MACCFG1_RESET_RX_FUN 0x00020000
50#define MACCFG1_RESET_TX_FUN 0x00010000
51#define MACCFG1_LOOPBACK 0x00000100
52#define MACCFG1_RX_FLOW 0x00000020
53#define MACCFG1_TX_FLOW 0x00000010
54#define MACCFG1_SYNCD_RX_EN 0x00000008
55#define MACCFG1_RX_EN 0x00000004
56#define MACCFG1_SYNCD_TX_EN 0x00000002
57#define MACCFG1_TX_EN 0x00000001
58
59#define MACCFG2_INIT_SETTINGS 0x00007205
60#define MACCFG2_FULL_DUPLEX 0x00000001
61#define MACCFG2_IF 0x00000300
97d80fc3 62#define MACCFG2_GMII 0x00000200
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63#define MACCFG2_MII 0x00000100
64
65#define ECNTRL_INIT_SETTINGS 0x00001000
66#define ECNTRL_TBI_MODE 0x00000020
d9b94f28 67#define ECNTRL_R100 0x00000008
81f481ca 68#define ECNTRL_SGMII_MODE 0x00000002
42d1f039 69
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70#define miim_end -2
71#define miim_read -1
72
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73#define TBIPA_VALUE 0x1f
74#define MIIMCFG_INIT_VALUE 0x00000003
75#define MIIMCFG_RESET 0x80000000
76
77#define MIIMIND_BUSY 0x00000001
78#define MIIMIND_NOTVALID 0x00000004
79
42d1f039 80#define MIIM_CONTROL 0x00
97d80fc3 81#define MIIM_CONTROL_RESET 0x00009140
42d1f039 82#define MIIM_CONTROL_INIT 0x00001140
5810dc3a 83#define MIIM_CONTROL_RESTART 0x00001340
42d1f039 84#define MIIM_ANEN 0x00001000
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85
86#define MIIM_CR 0x00
87#define MIIM_CR_RST 0x00008000
88#define MIIM_CR_INIT 0x00001000
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89
90#define MIIM_STATUS 0x1
91#define MIIM_STATUS_AN_DONE 0x00000020
97d80fc3 92#define MIIM_STATUS_LINK 0x0004
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93#define PHY_BMSR_AUTN_ABLE 0x0008
94#define PHY_BMSR_AUTN_COMP 0x0020
42d1f039 95
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96#define MIIM_PHYIR1 0x2
97#define MIIM_PHYIR2 0x3
42d1f039 98
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99#define MIIM_ANAR 0x4
100#define MIIM_ANAR_INIT 0x1e1
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101
102#define MIIM_TBI_ANLPBPA 0x5
103#define MIIM_TBI_ANLPBPA_HALF 0x00000040
104#define MIIM_TBI_ANLPBPA_FULL 0x00000020
105
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106#define MIIM_TBI_ANEX 0x6
107#define MIIM_TBI_ANEX_NP 0x00000004
108#define MIIM_TBI_ANEX_PRX 0x00000002
109
110#define MIIM_GBIT_CONTROL 0x9
111#define MIIM_GBIT_CONTROL_INIT 0xe00
112
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113/* Broadcom BCM54xx -- taken from linux sungem_phy */
114#define MIIM_BCM54xx_AUXSTATUS 0x19
115#define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK 0x0700
116#define MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT 8
117
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118/* Cicada Auxiliary Control/Status Register */
119#define MIIM_CIS8201_AUX_CONSTAT 0x1c
120#define MIIM_CIS8201_AUXCONSTAT_INIT 0x0004
121#define MIIM_CIS8201_AUXCONSTAT_DUPLEX 0x0020
122#define MIIM_CIS8201_AUXCONSTAT_SPEED 0x0018
123#define MIIM_CIS8201_AUXCONSTAT_GBIT 0x0010
124#define MIIM_CIS8201_AUXCONSTAT_100 0x0008
42d1f039 125
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126/* Cicada Extended Control Register 1 */
127#define MIIM_CIS8201_EXT_CON1 0x17
128#define MIIM_CIS8201_EXTCON1_INIT 0x0000
42d1f039 129
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130/* Cicada 8204 Extended PHY Control Register 1 */
131#define MIIM_CIS8204_EPHY_CON 0x17
132#define MIIM_CIS8204_EPHYCON_INIT 0x0006
03469832 133#define MIIM_CIS8204_EPHYCON_RGMII 0x1100
42d1f039 134
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135/* Cicada 8204 Serial LED Control Register */
136#define MIIM_CIS8204_SLED_CON 0x1b
137#define MIIM_CIS8204_SLEDCON_INIT 0x1115
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138
139#define MIIM_GBIT_CON 0x09
7abf0c58 140#define MIIM_GBIT_CON_ADVERT 0x0e00
42d1f039 141
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142/* Entry for Vitesse VSC8244 regs starts here */
143/* Vitesse VSC8244 Auxiliary Control/Status Register */
144#define MIIM_VSC8244_AUX_CONSTAT 0x1c
145#define MIIM_VSC8244_AUXCONSTAT_INIT 0x0000
146#define MIIM_VSC8244_AUXCONSTAT_DUPLEX 0x0020
147#define MIIM_VSC8244_AUXCONSTAT_SPEED 0x0018
148#define MIIM_VSC8244_AUXCONSTAT_GBIT 0x0010
149#define MIIM_VSC8244_AUXCONSTAT_100 0x0008
150#define MIIM_CONTROL_INIT_LOOPBACK 0x4000
151
152/* Vitesse VSC8244 Extended PHY Control Register 1 */
153#define MIIM_VSC8244_EPHY_CON 0x17
154#define MIIM_VSC8244_EPHYCON_INIT 0x0006
155
156/* Vitesse VSC8244 Serial LED Control Register */
157#define MIIM_VSC8244_LED_CON 0x1b
158#define MIIM_VSC8244_LEDCON_INIT 0xF011
159
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160/* 88E1011 PHY Status Register */
161#define MIIM_88E1011_PHY_STATUS 0x11
162#define MIIM_88E1011_PHYSTAT_SPEED 0xc000
163#define MIIM_88E1011_PHYSTAT_GBIT 0x8000
164#define MIIM_88E1011_PHYSTAT_100 0x4000
165#define MIIM_88E1011_PHYSTAT_DUPLEX 0x2000
166#define MIIM_88E1011_PHYSTAT_SPDDONE 0x0800
167#define MIIM_88E1011_PHYSTAT_LINK 0x0400
168
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169#define MIIM_88E1011_PHY_SCR 0x10
170#define MIIM_88E1011_PHY_MDI_X_AUTO 0x0060
171
172/* 88E1111 PHY LED Control Register */
173#define MIIM_88E1111_PHY_LED_CONTROL 24
174#define MIIM_88E1111_PHY_LED_DIRECT 0x4100
175#define MIIM_88E1111_PHY_LED_COMBINE 0x411C
176
177/* 88E1145 Extended PHY Specific Control Register */
178#define MIIM_88E1145_PHY_EXT_CR 20
179#define MIIM_M88E1145_RGMII_RX_DELAY 0x0080
180#define MIIM_M88E1145_RGMII_TX_DELAY 0x0002
181
182#define MIIM_88E1145_PHY_PAGE 29
183#define MIIM_88E1145_PHY_CAL_OV 30
184
185
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186/* DM9161 Control register values */
187#define MIIM_DM9161_CR_STOP 0x0400
188#define MIIM_DM9161_CR_RSTAN 0x1200
189
190#define MIIM_DM9161_SCR 0x10
191#define MIIM_DM9161_SCR_INIT 0x0610
192
193/* DM9161 Specified Configuration and Status Register */
194#define MIIM_DM9161_SCSR 0x11
195#define MIIM_DM9161_SCSR_100F 0x8000
196#define MIIM_DM9161_SCSR_100H 0x4000
197#define MIIM_DM9161_SCSR_10F 0x2000
198#define MIIM_DM9161_SCSR_10H 0x1000
199
200/* DM9161 10BT Configuration/Status */
201#define MIIM_DM9161_10BTCSR 0x12
202#define MIIM_DM9161_10BTCSR_INIT 0x7800
42d1f039 203
3dd7f0f0 204/* LXT971 Status 2 registers */
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205#define MIIM_LXT971_SR2 0x11 /* Status Register 2 */
206#define MIIM_LXT971_SR2_SPEED_MASK 0x4200
207#define MIIM_LXT971_SR2_10HDX 0x0000 /* 10 Mbit half duplex selected */
208#define MIIM_LXT971_SR2_10FDX 0x0200 /* 10 Mbit full duplex selected */
209#define MIIM_LXT971_SR2_100HDX 0x4000 /* 100 Mbit half duplex selected */
210#define MIIM_LXT971_SR2_100FDX 0x4200 /* 100 Mbit full duplex selected */
3dd7f0f0 211
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212/* DP83865 Control register values */
213#define MIIM_DP83865_CR_INIT 0x9200
214
215/* DP83865 Link and Auto-Neg Status Register */
216#define MIIM_DP83865_LANR 0x11
217#define MIIM_DP83865_SPD_MASK 0x0018
218#define MIIM_DP83865_SPD_1000 0x0010
219#define MIIM_DP83865_SPD_100 0x0008
220#define MIIM_DP83865_DPX_FULL 0x0002
221
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222#define MIIM_READ_COMMAND 0x00000001
223
224#define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN
225
226#define MINFLR_INIT_SETTINGS 0x00000040
227
228#define DMACTRL_INIT_SETTINGS 0x000000c3
229#define DMACTRL_GRS 0x00000010
230#define DMACTRL_GTS 0x00000008
231
232#define TSTAT_CLEAR_THALT 0x80000000
233#define RSTAT_CLEAR_RHALT 0x00800000
234
7abf0c58 235
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236#define IEVENT_INIT_CLEAR 0xffffffff
237#define IEVENT_BABR 0x80000000
238#define IEVENT_RXC 0x40000000
239#define IEVENT_BSY 0x20000000
240#define IEVENT_EBERR 0x10000000
241#define IEVENT_MSRO 0x04000000
242#define IEVENT_GTSC 0x02000000
243#define IEVENT_BABT 0x01000000
244#define IEVENT_TXC 0x00800000
245#define IEVENT_TXE 0x00400000
246#define IEVENT_TXB 0x00200000
247#define IEVENT_TXF 0x00100000
248#define IEVENT_IE 0x00080000
249#define IEVENT_LC 0x00040000
250#define IEVENT_CRL 0x00020000
251#define IEVENT_XFUN 0x00010000
252#define IEVENT_RXB0 0x00008000
253#define IEVENT_GRSC 0x00000100
254#define IEVENT_RXF0 0x00000080
255
256#define IMASK_INIT_CLEAR 0x00000000
257#define IMASK_TXEEN 0x00400000
258#define IMASK_TXBEN 0x00200000
259#define IMASK_TXFEN 0x00100000
260#define IMASK_RXFEN0 0x00000080
261
262
263/* Default Attribute fields */
264#define ATTR_INIT_SETTINGS 0x000000c0
265#define ATTRELI_INIT_SETTINGS 0x00000000
266
267
268/* TxBD status field bits */
269#define TXBD_READY 0x8000
270#define TXBD_PADCRC 0x4000
271#define TXBD_WRAP 0x2000
272#define TXBD_INTERRUPT 0x1000
273#define TXBD_LAST 0x0800
274#define TXBD_CRC 0x0400
275#define TXBD_DEF 0x0200
276#define TXBD_HUGEFRAME 0x0080
277#define TXBD_LATECOLLISION 0x0080
278#define TXBD_RETRYLIMIT 0x0040
279#define TXBD_RETRYCOUNTMASK 0x003c
280#define TXBD_UNDERRUN 0x0002
281#define TXBD_STATS 0x03ff
282
283/* RxBD status field bits */
284#define RXBD_EMPTY 0x8000
285#define RXBD_RO1 0x4000
286#define RXBD_WRAP 0x2000
287#define RXBD_INTERRUPT 0x1000
288#define RXBD_LAST 0x0800
289#define RXBD_FIRST 0x0400
290#define RXBD_MISS 0x0100
291#define RXBD_BROADCAST 0x0080
292#define RXBD_MULTICAST 0x0040
293#define RXBD_LARGE 0x0020
294#define RXBD_NONOCTET 0x0010
295#define RXBD_SHORT 0x0008
296#define RXBD_CRCERR 0x0004
297#define RXBD_OVERRUN 0x0002
298#define RXBD_TRUNCATED 0x0001
299#define RXBD_STATS 0x003f
300
301typedef struct txbd8
302{
303 ushort status; /* Status Fields */
304 ushort length; /* Buffer length */
305 uint bufPtr; /* Buffer Pointer */
306} txbd8_t;
307
308typedef struct rxbd8
309{
310 ushort status; /* Status Fields */
311 ushort length; /* Buffer Length */
312 uint bufPtr; /* Buffer Pointer */
313} rxbd8_t;
314
315typedef struct rmon_mib
316{
317 /* Transmit and Receive Counters */
318 uint tr64; /* Transmit and Receive 64-byte Frame Counter */
319 uint tr127; /* Transmit and Receive 65-127 byte Frame Counter */
320 uint tr255; /* Transmit and Receive 128-255 byte Frame Counter */
321 uint tr511; /* Transmit and Receive 256-511 byte Frame Counter */
322 uint tr1k; /* Transmit and Receive 512-1023 byte Frame Counter */
323 uint trmax; /* Transmit and Receive 1024-1518 byte Frame Counter */
324 uint trmgv; /* Transmit and Receive 1519-1522 byte Good VLAN Frame */
325 /* Receive Counters */
326 uint rbyt; /* Receive Byte Counter */
327 uint rpkt; /* Receive Packet Counter */
328 uint rfcs; /* Receive FCS Error Counter */
329 uint rmca; /* Receive Multicast Packet (Counter) */
330 uint rbca; /* Receive Broadcast Packet */
331 uint rxcf; /* Receive Control Frame Packet */
332 uint rxpf; /* Receive Pause Frame Packet */
333 uint rxuo; /* Receive Unknown OP Code */
334 uint raln; /* Receive Alignment Error */
335 uint rflr; /* Receive Frame Length Error */
336 uint rcde; /* Receive Code Error */
337 uint rcse; /* Receive Carrier Sense Error */
338 uint rund; /* Receive Undersize Packet */
339 uint rovr; /* Receive Oversize Packet */
340 uint rfrg; /* Receive Fragments */
341 uint rjbr; /* Receive Jabber */
342 uint rdrp; /* Receive Drop */
343 /* Transmit Counters */
344 uint tbyt; /* Transmit Byte Counter */
345 uint tpkt; /* Transmit Packet */
346 uint tmca; /* Transmit Multicast Packet */
347 uint tbca; /* Transmit Broadcast Packet */
348 uint txpf; /* Transmit Pause Control Frame */
349 uint tdfr; /* Transmit Deferral Packet */
350 uint tedf; /* Transmit Excessive Deferral Packet */
351 uint tscl; /* Transmit Single Collision Packet */
352 /* (0x2_n700) */
353 uint tmcl; /* Transmit Multiple Collision Packet */
354 uint tlcl; /* Transmit Late Collision Packet */
355 uint txcl; /* Transmit Excessive Collision Packet */
356 uint tncl; /* Transmit Total Collision */
357
358 uint res2;
359
360 uint tdrp; /* Transmit Drop Frame */
361 uint tjbr; /* Transmit Jabber Frame */
362 uint tfcs; /* Transmit FCS Error */
363 uint txcf; /* Transmit Control Frame */
364 uint tovr; /* Transmit Oversize Frame */
365 uint tund; /* Transmit Undersize Frame */
366 uint tfrg; /* Transmit Fragments Frame */
367 /* General Registers */
368 uint car1; /* Carry Register One */
369 uint car2; /* Carry Register Two */
370 uint cam1; /* Carry Register One Mask */
371 uint cam2; /* Carry Register Two Mask */
372} rmon_mib_t;
373
374typedef struct tsec_hash_regs
375{
376 uint iaddr0; /* Individual Address Register 0 */
377 uint iaddr1; /* Individual Address Register 1 */
378 uint iaddr2; /* Individual Address Register 2 */
379 uint iaddr3; /* Individual Address Register 3 */
380 uint iaddr4; /* Individual Address Register 4 */
381 uint iaddr5; /* Individual Address Register 5 */
382 uint iaddr6; /* Individual Address Register 6 */
383 uint iaddr7; /* Individual Address Register 7 */
384 uint res1[24];
385 uint gaddr0; /* Group Address Register 0 */
386 uint gaddr1; /* Group Address Register 1 */
387 uint gaddr2; /* Group Address Register 2 */
388 uint gaddr3; /* Group Address Register 3 */
389 uint gaddr4; /* Group Address Register 4 */
390 uint gaddr5; /* Group Address Register 5 */
391 uint gaddr6; /* Group Address Register 6 */
392 uint gaddr7; /* Group Address Register 7 */
393 uint res2[24];
394} tsec_hash_t;
395
396typedef struct tsec
397{
398 /* General Control and Status Registers (0x2_n000) */
399 uint res000[4];
400
401 uint ievent; /* Interrupt Event */
402 uint imask; /* Interrupt Mask */
403 uint edis; /* Error Disabled */
404 uint res01c;
405 uint ecntrl; /* Ethernet Control */
406 uint minflr; /* Minimum Frame Length */
407 uint ptv; /* Pause Time Value */
408 uint dmactrl; /* DMA Control */
409 uint tbipa; /* TBI PHY Address */
410
411 uint res034[3];
412 uint res040[48];
413
414 /* Transmit Control and Status Registers (0x2_n100) */
415 uint tctrl; /* Transmit Control */
416 uint tstat; /* Transmit Status */
417 uint res108;
418 uint tbdlen; /* Tx BD Data Length */
419 uint res110[5];
420 uint ctbptr; /* Current TxBD Pointer */
421 uint res128[23];
422 uint tbptr; /* TxBD Pointer */
423 uint res188[30];
424 /* (0x2_n200) */
425 uint res200;
426 uint tbase; /* TxBD Base Address */
427 uint res208[42];
428 uint ostbd; /* Out of Sequence TxBD */
429 uint ostbdp; /* Out of Sequence Tx Data Buffer Pointer */
430 uint res2b8[18];
431
432 /* Receive Control and Status Registers (0x2_n300) */
433 uint rctrl; /* Receive Control */
434 uint rstat; /* Receive Status */
435 uint res308;
436 uint rbdlen; /* RxBD Data Length */
437 uint res310[4];
438 uint res320;
439 uint crbptr; /* Current Receive Buffer Pointer */
440 uint res328[6];
441 uint mrblr; /* Maximum Receive Buffer Length */
442 uint res344[16];
443 uint rbptr; /* RxBD Pointer */
444 uint res388[30];
445 /* (0x2_n400) */
446 uint res400;
447 uint rbase; /* RxBD Base Address */
448 uint res408[62];
449
450 /* MAC Registers (0x2_n500) */
451 uint maccfg1; /* MAC Configuration #1 */
452 uint maccfg2; /* MAC Configuration #2 */
453 uint ipgifg; /* Inter Packet Gap/Inter Frame Gap */
454 uint hafdup; /* Half-duplex */
455 uint maxfrm; /* Maximum Frame */
456 uint res514;
457 uint res518;
458
459 uint res51c;
460
461 uint miimcfg; /* MII Management: Configuration */
462 uint miimcom; /* MII Management: Command */
463 uint miimadd; /* MII Management: Address */
464 uint miimcon; /* MII Management: Control */
465 uint miimstat; /* MII Management: Status */
466 uint miimind; /* MII Management: Indicators */
467
468 uint res538;
469
470 uint ifstat; /* Interface Status */
471 uint macstnaddr1; /* Station Address, part 1 */
472 uint macstnaddr2; /* Station Address, part 2 */
473 uint res548[46];
474
475 /* (0x2_n600) */
476 uint res600[32];
477
478 /* RMON MIB Registers (0x2_n680-0x2_n73c) */
479 rmon_mib_t rmon;
480 uint res740[48];
481
482 /* Hash Function Registers (0x2_n800) */
483 tsec_hash_t hash;
484
485 uint res900[128];
486
487 /* Pattern Registers (0x2_nb00) */
488 uint resb00[62];
489 uint attr; /* Default Attribute Register */
490 uint attreli; /* Default Attribute Extract Length and Index */
491
492 /* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */
493 uint resc00[256];
494} tsec_t;
495
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496#define TSEC_GIGABIT (1)
497
498/* This flag currently only has
499 * meaning if we're using the eTSEC */
500#define TSEC_REDUCED (1 << 1)
501
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502struct tsec_private {
503 volatile tsec_t *regs;
504 volatile tsec_t *phyregs;
505 struct phy_info *phyinfo;
506 uint phyaddr;
d9b94f28 507 u32 flags;
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508 uint link;
509 uint duplexity;
510 uint speed;
511};
512
513
514/*
515 * struct phy_cmd: A command for reading or writing a PHY register
516 *
517 * mii_reg: The register to read or write
518 *
519 * mii_data: For writes, the value to put in the register.
520 * A value of -1 indicates this is a read.
521 *
522 * funct: A function pointer which is invoked for each command.
523 * For reads, this function will be passed the value read
524 * from the PHY, and process it.
525 * For writes, the result of this function will be written
526 * to the PHY register
527 */
528struct phy_cmd {
529 uint mii_reg;
530 uint mii_data;
531 uint (*funct) (uint mii_reg, struct tsec_private* priv);
532};
533
534/* struct phy_info: a structure which defines attributes for a PHY
535 *
536 * id will contain a number which represents the PHY. During
537 * startup, the driver will poll the PHY to find out what its
538 * UID--as defined by registers 2 and 3--is. The 32-bit result
539 * gotten from the PHY will be shifted right by "shift" bits to
540 * discard any bits which may change based on revision numbers
541 * unimportant to functionality
542 *
543 * The struct phy_cmd entries represent pointers to an arrays of
544 * commands which tell the driver what to do to the PHY.
545 */
546struct phy_info {
547 uint id;
548 char *name;
549 uint shift;
550 /* Called to configure the PHY, and modify the controller
551 * based on the results */
552 struct phy_cmd *config;
553
554 /* Called when starting up the controller */
555 struct phy_cmd *startup;
556
557 /* Called when bringing down the controller */
558 struct phy_cmd *shutdown;
559};
560
42d1f039 561#endif /* __TSEC_H */