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d1927cee 1/***********************************************************************
2 *
3 * Copyright (c) 2005 Freescale Semiconductor, Inc.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 * Description:
24 * Ethernet interface for Tundra TSI108 bridge chip
25 *
26 ***********************************************************************/
27
28#include <config.h>
29
30#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) \
31 && defined(CONFIG_TSI108_ETH)
32
33#if !defined(CONFIG_TSI108_ETH_NUM_PORTS) || (CONFIG_TSI108_ETH_NUM_PORTS > 2)
34#error "CONFIG_TSI108_ETH_NUM_PORTS must be defined as 1 or 2"
35#endif
36
37#include <common.h>
38#include <malloc.h>
39#include <net.h>
40#include <asm/cache.h>
41
42#ifdef DEBUG
43#define TSI108_ETH_DEBUG 7
44#else
45#define TSI108_ETH_DEBUG 0
46#endif
47
48#if TSI108_ETH_DEBUG > 0
ee311214 49#define debug_lev(lev, fmt, args...) \
50if (lev <= TSI108_ETH_DEBUG) \
51printf ("%s %d: " fmt, __FUNCTION__, __LINE__, ##args)
d1927cee 52#else
53#define debug_lev(lev, fmt, args...) do{}while(0)
54#endif
55
56#define RX_PRINT_ERRORS
57#define TX_PRINT_ERRORS
58
ee311214 59#define ETH_BASE (CFG_TSI108_CSR_BASE + 0x6000)
d1927cee 60
ee311214 61#define ETH_PORT_OFFSET 0x400
d1927cee 62
63#define __REG32(base, offset) (*((volatile u32 *)((char *)(base) + (offset))))
64
ee311214 65#define reg_MAC_CONFIG_1(base) __REG32(base, 0x00000000)
66#define MAC_CONFIG_1_TX_ENABLE (0x00000001)
67#define MAC_CONFIG_1_SYNC_TX_ENABLE (0x00000002)
68#define MAC_CONFIG_1_RX_ENABLE (0x00000004)
69#define MAC_CONFIG_1_SYNC_RX_ENABLE (0x00000008)
70#define MAC_CONFIG_1_TX_FLOW_CONTROL (0x00000010)
71#define MAC_CONFIG_1_RX_FLOW_CONTROL (0x00000020)
72#define MAC_CONFIG_1_LOOP_BACK (0x00000100)
73#define MAC_CONFIG_1_RESET_TX_FUNCTION (0x00010000)
74#define MAC_CONFIG_1_RESET_RX_FUNCTION (0x00020000)
75#define MAC_CONFIG_1_RESET_TX_MAC (0x00040000)
76#define MAC_CONFIG_1_RESET_RX_MAC (0x00080000)
77#define MAC_CONFIG_1_SIM_RESET (0x40000000)
78#define MAC_CONFIG_1_SOFT_RESET (0x80000000)
79
80#define reg_MAC_CONFIG_2(base) __REG32(base, 0x00000004)
81#define MAC_CONFIG_2_FULL_DUPLEX (0x00000001)
82#define MAC_CONFIG_2_CRC_ENABLE (0x00000002)
83#define MAC_CONFIG_2_PAD_CRC (0x00000004)
84#define MAC_CONFIG_2_LENGTH_CHECK (0x00000010)
85#define MAC_CONFIG_2_HUGE_FRAME (0x00000020)
86#define MAC_CONFIG_2_INTERFACE_MODE(val) (((val) & 0x3) << 8)
87#define MAC_CONFIG_2_PREAMBLE_LENGTH(val) (((val) & 0xf) << 12)
88#define INTERFACE_MODE_NIBBLE 1 /* 10/100 Mb/s MII) */
89#define INTERFACE_MODE_BYTE 2 /* 1000 Mb/s GMII/TBI */
90
91#define reg_MAXIMUM_FRAME_LENGTH(base) __REG32(base, 0x00000010)
92
93#define reg_MII_MGMT_CONFIG(base) __REG32(base, 0x00000020)
94#define MII_MGMT_CONFIG_MGMT_CLOCK_SELECT(val) ((val) & 0x7)
95#define MII_MGMT_CONFIG_NO_PREAMBLE (0x00000010)
96#define MII_MGMT_CONFIG_SCAN_INCREMENT (0x00000020)
97#define MII_MGMT_CONFIG_RESET_MGMT (0x80000000)
98
99#define reg_MII_MGMT_COMMAND(base) __REG32(base, 0x00000024)
100#define MII_MGMT_COMMAND_READ_CYCLE (0x00000001)
101#define MII_MGMT_COMMAND_SCAN_CYCLE (0x00000002)
102
103#define reg_MII_MGMT_ADDRESS(base) __REG32(base, 0x00000028)
104#define reg_MII_MGMT_CONTROL(base) __REG32(base, 0x0000002c)
105#define reg_MII_MGMT_STATUS(base) __REG32(base, 0x00000030)
106
107#define reg_MII_MGMT_INDICATORS(base) __REG32(base, 0x00000034)
108#define MII_MGMT_INDICATORS_BUSY (0x00000001)
109#define MII_MGMT_INDICATORS_SCAN (0x00000002)
110#define MII_MGMT_INDICATORS_NOT_VALID (0x00000004)
111
112#define reg_INTERFACE_STATUS(base) __REG32(base, 0x0000003c)
113#define INTERFACE_STATUS_LINK_FAIL (0x00000008)
114#define INTERFACE_STATUS_EXCESS_DEFER (0x00000200)
115
116#define reg_STATION_ADDRESS_1(base) __REG32(base, 0x00000040)
117#define reg_STATION_ADDRESS_2(base) __REG32(base, 0x00000044)
118
119#define reg_PORT_CONTROL(base) __REG32(base, 0x00000200)
120#define PORT_CONTROL_PRI (0x00000001)
121#define PORT_CONTROL_BPT (0x00010000)
122#define PORT_CONTROL_SPD (0x00040000)
123#define PORT_CONTROL_RBC (0x00080000)
124#define PORT_CONTROL_PRB (0x00200000)
125#define PORT_CONTROL_DIS (0x00400000)
126#define PORT_CONTROL_TBI (0x00800000)
127#define PORT_CONTROL_STE (0x10000000)
128#define PORT_CONTROL_ZOR (0x20000000)
129#define PORT_CONTROL_CLR (0x40000000)
130#define PORT_CONTROL_SRT (0x80000000)
131
132#define reg_TX_CONFIG(base) __REG32(base, 0x00000220)
133#define TX_CONFIG_START_Q (0x00000003)
134#define TX_CONFIG_EHP (0x00400000)
135#define TX_CONFIG_CHP (0x00800000)
136#define TX_CONFIG_RST (0x80000000)
137
138#define reg_TX_CONTROL(base) __REG32(base, 0x00000224)
139#define TX_CONTROL_GO (0x00008000)
140#define TX_CONTROL_MP (0x01000000)
141#define TX_CONTROL_EAI (0x20000000)
142#define TX_CONTROL_ABT (0x40000000)
143#define TX_CONTROL_EII (0x80000000)
144
145#define reg_TX_STATUS(base) __REG32(base, 0x00000228)
146#define TX_STATUS_QUEUE_USABLE (0x0000000f)
147#define TX_STATUS_CURR_Q (0x00000300)
148#define TX_STATUS_ACT (0x00008000)
149#define TX_STATUS_QUEUE_IDLE (0x000f0000)
150#define TX_STATUS_EOQ_PENDING (0x0f000000)
151
152#define reg_TX_EXTENDED_STATUS(base) __REG32(base, 0x0000022c)
153#define TX_EXTENDED_STATUS_END_OF_QUEUE_CONDITION (0x0000000f)
154#define TX_EXTENDED_STATUS_END_OF_FRAME_CONDITION (0x00000f00)
155#define TX_EXTENDED_STATUS_DESCRIPTOR_INTERRUPT_CONDITION (0x000f0000)
156#define TX_EXTENDED_STATUS_ERROR_FLAG (0x0f000000)
157
158#define reg_TX_THRESHOLDS(base) __REG32(base, 0x00000230)
d1927cee 159
160#define reg_TX_DIAGNOSTIC_ADDR(base) __REG32(base, 0x00000270)
ee311214 161#define TX_DIAGNOSTIC_ADDR_INDEX (0x0000007f)
162#define TX_DIAGNOSTIC_ADDR_DFR (0x40000000)
163#define TX_DIAGNOSTIC_ADDR_AI (0x80000000)
164
165#define reg_TX_DIAGNOSTIC_DATA(base) __REG32(base, 0x00000274)
166
167#define reg_TX_ERROR_STATUS(base) __REG32(base, 0x00000278)
168#define TX_ERROR_STATUS (0x00000278)
169#define TX_ERROR_STATUS_QUEUE_0_ERROR_RESPONSE (0x0000000f)
170#define TX_ERROR_STATUS_TEA_ON_QUEUE_0 (0x00000010)
171#define TX_ERROR_STATUS_RER_ON_QUEUE_0 (0x00000020)
172#define TX_ERROR_STATUS_TER_ON_QUEUE_0 (0x00000040)
173#define TX_ERROR_STATUS_DER_ON_QUEUE_0 (0x00000080)
174#define TX_ERROR_STATUS_QUEUE_1_ERROR_RESPONSE (0x00000f00)
175#define TX_ERROR_STATUS_TEA_ON_QUEUE_1 (0x00001000)
176#define TX_ERROR_STATUS_RER_ON_QUEUE_1 (0x00002000)
177#define TX_ERROR_STATUS_TER_ON_QUEUE_1 (0x00004000)
178#define TX_ERROR_STATUS_DER_ON_QUEUE_1 (0x00008000)
179#define TX_ERROR_STATUS_QUEUE_2_ERROR_RESPONSE (0x000f0000)
180#define TX_ERROR_STATUS_TEA_ON_QUEUE_2 (0x00100000)
181#define TX_ERROR_STATUS_RER_ON_QUEUE_2 (0x00200000)
182#define TX_ERROR_STATUS_TER_ON_QUEUE_2 (0x00400000)
183#define TX_ERROR_STATUS_DER_ON_QUEUE_2 (0x00800000)
184#define TX_ERROR_STATUS_QUEUE_3_ERROR_RESPONSE (0x0f000000)
185#define TX_ERROR_STATUS_TEA_ON_QUEUE_3 (0x10000000)
186#define TX_ERROR_STATUS_RER_ON_QUEUE_3 (0x20000000)
187#define TX_ERROR_STATUS_TER_ON_QUEUE_3 (0x40000000)
188#define TX_ERROR_STATUS_DER_ON_QUEUE_3 (0x80000000)
189
190#define reg_TX_QUEUE_0_CONFIG(base) __REG32(base, 0x00000280)
191#define TX_QUEUE_0_CONFIG_OCN_PORT (0x0000003f)
192#define TX_QUEUE_0_CONFIG_BSWP (0x00000400)
193#define TX_QUEUE_0_CONFIG_WSWP (0x00000800)
194#define TX_QUEUE_0_CONFIG_AM (0x00004000)
195#define TX_QUEUE_0_CONFIG_GVI (0x00008000)
196#define TX_QUEUE_0_CONFIG_EEI (0x00010000)
197#define TX_QUEUE_0_CONFIG_ELI (0x00020000)
198#define TX_QUEUE_0_CONFIG_ENI (0x00040000)
199#define TX_QUEUE_0_CONFIG_ESI (0x00080000)
200#define TX_QUEUE_0_CONFIG_EDI (0x00100000)
201
202#define reg_TX_QUEUE_0_BUF_CONFIG(base) __REG32(base, 0x00000284)
203#define TX_QUEUE_0_BUF_CONFIG_OCN_PORT (0x0000003f)
204#define TX_QUEUE_0_BUF_CONFIG_BURST (0x00000300)
205#define TX_QUEUE_0_BUF_CONFIG_BSWP (0x00000400)
206#define TX_QUEUE_0_BUF_CONFIG_WSWP (0x00000800)
207
208#define OCN_PORT_HLP 0 /* HLP Interface */
209#define OCN_PORT_PCI_X 1 /* PCI-X Interface */
d1927cee 210#define OCN_PORT_PROCESSOR_MASTER 2 /* Processor Interface (master) */
ee311214 211#define OCN_PORT_PROCESSOR_SLAVE 3 /* Processor Interface (slave) */
212#define OCN_PORT_MEMORY 4 /* Memory Controller */
213#define OCN_PORT_DMA 5 /* DMA Controller */
214#define OCN_PORT_ETHERNET 6 /* Ethernet Controller */
215#define OCN_PORT_PRINT 7 /* Print Engine Interface */
216
217#define reg_TX_QUEUE_0_PTR_LOW(base) __REG32(base, 0x00000288)
218
219#define reg_TX_QUEUE_0_PTR_HIGH(base) __REG32(base, 0x0000028c)
220#define TX_QUEUE_0_PTR_HIGH_VALID (0x80000000)
221
222#define reg_RX_CONFIG(base) __REG32(base, 0x00000320)
223#define RX_CONFIG_DEF_Q (0x00000003)
224#define RX_CONFIG_EMF (0x00000100)
225#define RX_CONFIG_EUF (0x00000200)
226#define RX_CONFIG_BFE (0x00000400)
227#define RX_CONFIG_MFE (0x00000800)
228#define RX_CONFIG_UFE (0x00001000)
229#define RX_CONFIG_SE (0x00002000)
230#define RX_CONFIG_ABF (0x00200000)
231#define RX_CONFIG_APE (0x00400000)
232#define RX_CONFIG_CHP (0x00800000)
233#define RX_CONFIG_RST (0x80000000)
234
235#define reg_RX_CONTROL(base) __REG32(base, 0x00000324)
236#define GE_E0_RX_CONTROL_QUEUE_ENABLES (0x0000000f)
237#define GE_E0_RX_CONTROL_GO (0x00008000)
238#define GE_E0_RX_CONTROL_EAI (0x20000000)
239#define GE_E0_RX_CONTROL_ABT (0x40000000)
240#define GE_E0_RX_CONTROL_EII (0x80000000)
241
242#define reg_RX_EXTENDED_STATUS(base) __REG32(base, 0x0000032c)
243#define RX_EXTENDED_STATUS (0x0000032c)
244#define RX_EXTENDED_STATUS_EOQ (0x0000000f)
245#define RX_EXTENDED_STATUS_EOQ_0 (0x00000001)
246#define RX_EXTENDED_STATUS_EOF (0x00000f00)
247#define RX_EXTENDED_STATUS_DESCRIPTOR_INTERRUPT_CONDITION (0x000f0000)
248#define RX_EXTENDED_STATUS_ERROR_FLAG (0x0f000000)
249
250#define reg_RX_THRESHOLDS(base) __REG32(base, 0x00000330)
251
252#define reg_RX_DIAGNOSTIC_ADDR(base) __REG32(base, 0x00000370)
253#define RX_DIAGNOSTIC_ADDR_INDEX (0x0000007f)
254#define RX_DIAGNOSTIC_ADDR_DFR (0x40000000)
255#define RX_DIAGNOSTIC_ADDR_AI (0x80000000)
256
257#define reg_RX_DIAGNOSTIC_DATA(base) __REG32(base, 0x00000374)
258
259#define reg_RX_QUEUE_0_CONFIG(base) __REG32(base, 0x00000380)
260#define RX_QUEUE_0_CONFIG_OCN_PORT (0x0000003f)
261#define RX_QUEUE_0_CONFIG_BSWP (0x00000400)
262#define RX_QUEUE_0_CONFIG_WSWP (0x00000800)
263#define RX_QUEUE_0_CONFIG_AM (0x00004000)
264#define RX_QUEUE_0_CONFIG_EEI (0x00010000)
265#define RX_QUEUE_0_CONFIG_ELI (0x00020000)
266#define RX_QUEUE_0_CONFIG_ENI (0x00040000)
267#define RX_QUEUE_0_CONFIG_ESI (0x00080000)
268#define RX_QUEUE_0_CONFIG_EDI (0x00100000)
269
270#define reg_RX_QUEUE_0_BUF_CONFIG(base) __REG32(base, 0x00000384)
271#define RX_QUEUE_0_BUF_CONFIG_OCN_PORT (0x0000003f)
272#define RX_QUEUE_0_BUF_CONFIG_BURST (0x00000300)
273#define RX_QUEUE_0_BUF_CONFIG_BSWP (0x00000400)
274#define RX_QUEUE_0_BUF_CONFIG_WSWP (0x00000800)
275
276#define reg_RX_QUEUE_0_PTR_LOW(base) __REG32(base, 0x00000388)
277
278#define reg_RX_QUEUE_0_PTR_HIGH(base) __REG32(base, 0x0000038c)
279#define RX_QUEUE_0_PTR_HIGH_VALID (0x80000000)
d1927cee 280
281/*
282 * PHY register definitions
283 */
284/* the first 15 PHY registers are standard. */
ee311214 285#define PHY_CTRL_REG 0 /* Control Register */
286#define PHY_STATUS_REG 1 /* Status Regiser */
287#define PHY_ID1_REG 2 /* Phy Id Reg (word 1) */
288#define PHY_ID2_REG 3 /* Phy Id Reg (word 2) */
289#define PHY_AN_ADV_REG 4 /* Autoneg Advertisement */
290#define PHY_LP_ABILITY_REG 5 /* Link Partner Ability (Base Page) */
291#define PHY_AUTONEG_EXP_REG 6 /* Autoneg Expansion Reg */
292#define PHY_NEXT_PAGE_TX_REG 7 /* Next Page TX */
293#define PHY_LP_NEXT_PAGE_REG 8 /* Link Partner Next Page */
294#define PHY_1000T_CTRL_REG 9 /* 1000Base-T Control Reg */
295#define PHY_1000T_STATUS_REG 10 /* 1000Base-T Status Reg */
296#define PHY_EXT_STATUS_REG 11 /* Extended Status Reg */
d1927cee 297
298/*
299 * PHY Register bit masks.
300 */
ee311214 301#define PHY_CTRL_RESET (1 << 15)
302#define PHY_CTRL_LOOPBACK (1 << 14)
303#define PHY_CTRL_SPEED0 (1 << 13)
304#define PHY_CTRL_AN_EN (1 << 12)
305#define PHY_CTRL_PWR_DN (1 << 11)
306#define PHY_CTRL_ISOLATE (1 << 10)
307#define PHY_CTRL_RESTART_AN (1 << 9)
308#define PHY_CTRL_FULL_DUPLEX (1 << 8)
309#define PHY_CTRL_CT_EN (1 << 7)
310#define PHY_CTRL_SPEED1 (1 << 6)
311
312#define PHY_STAT_100BASE_T4 (1 << 15)
313#define PHY_STAT_100BASE_X_FD (1 << 14)
314#define PHY_STAT_100BASE_X_HD (1 << 13)
315#define PHY_STAT_10BASE_T_FD (1 << 12)
316#define PHY_STAT_10BASE_T_HD (1 << 11)
317#define PHY_STAT_100BASE_T2_FD (1 << 10)
318#define PHY_STAT_100BASE_T2_HD (1 << 9)
319#define PHY_STAT_EXT_STAT (1 << 8)
320#define PHY_STAT_RESERVED (1 << 7)
321#define PHY_STAT_MFPS (1 << 6) /* Management Frames Preamble Suppression */
322#define PHY_STAT_AN_COMPLETE (1 << 5)
323#define PHY_STAT_REM_FAULT (1 << 4)
324#define PHY_STAT_AN_CAP (1 << 3)
325#define PHY_STAT_LINK_UP (1 << 2)
326#define PHY_STAT_JABBER (1 << 1)
327#define PHY_STAT_EXT_CAP (1 << 0)
328
329#define TBI_CONTROL_2 0x11
330#define TBI_CONTROL_2_ENABLE_COMMA_DETECT 0x0001
331#define TBI_CONTROL_2_ENABLE_WRAP 0x0002
332#define TBI_CONTROL_2_G_MII_MODE 0x0010
333#define TBI_CONTROL_2_RECEIVE_CLOCK_SELECT 0x0020
334#define TBI_CONTROL_2_AUTO_NEGOTIATION_SENSE 0x0100
335#define TBI_CONTROL_2_DISABLE_TRANSMIT_RUNNING_DISPARITY 0x1000
336#define TBI_CONTROL_2_DISABLE_RECEIVE_RUNNING_DISPARITY 0x2000
337#define TBI_CONTROL_2_SHORTCUT_LINK_TIMER 0x4000
338#define TBI_CONTROL_2_SOFT_RESET 0x8000
d1927cee 339
340/* marvel specific */
ee311214 341#define MV1111_EXT_CTRL1_REG 16 /* PHY Specific Control Reg */
342#define MV1111_SPEC_STAT_REG 17 /* PHY Specific Status Reg */
343#define MV1111_EXT_CTRL2_REG 20 /* Extended PHY Specific Control Reg */
d1927cee 344
345/*
346 * MARVELL 88E1111 PHY register bit masks
347 */
348/* PHY Specific Status Register (MV1111_EXT_CTRL1_REG) */
349
ee311214 350#define SPEC_STAT_SPEED_MASK (3 << 14)
351#define SPEC_STAT_FULL_DUP (1 << 13)
352#define SPEC_STAT_PAGE_RCVD (1 << 12)
353#define SPEC_STAT_RESOLVED (1 << 11) /* Speed and Duplex Resolved */
354#define SPEC_STAT_LINK_UP (1 << 10)
355#define SPEC_STAT_CABLE_LEN_MASK (7 << 7)/* Cable Length (100/1000 modes only) */
356#define SPEC_STAT_MDIX (1 << 6)
357#define SPEC_STAT_POLARITY (1 << 1)
358#define SPEC_STAT_JABBER (1 << 0)
d1927cee 359
ee311214 360#define SPEED_1000 (2 << 14)
361#define SPEED_100 (1 << 14)
362#define SPEED_10 (0 << 14)
d1927cee 363
ee311214 364#define TBI_ADDR 0x1E /* Ten Bit Interface address */
d1927cee 365
366/* negotiated link parameters */
ee311214 367#define LINK_SPEED_UNKNOWN 0
368#define LINK_SPEED_10 1
369#define LINK_SPEED_100 2
370#define LINK_SPEED_1000 3
d1927cee 371
ee311214 372#define LINK_DUPLEX_UNKNOWN 0
373#define LINK_DUPLEX_HALF 1
374#define LINK_DUPLEX_FULL 2
d1927cee 375
376static unsigned int phy_address[] = { 8, 9 };
377
378#define vuint32 volatile u32
379
380/* TX/RX buffer descriptors. MUST be cache line aligned in memory. (32 byte)
381 * This structure is accessed by the ethernet DMA engine which means it
382 * MUST be in LITTLE ENDIAN format */
383struct dma_descriptor {
384 vuint32 start_addr0; /* buffer address, least significant bytes. */
385 vuint32 start_addr1; /* buffer address, most significant bytes. */
386 vuint32 next_descr_addr0;/* next descriptor address, least significant bytes. Must be 64-bit aligned. */
387 vuint32 next_descr_addr1;/* next descriptor address, most significant bytes. */
388 vuint32 vlan_byte_count;/* VLAN tag(top 2 bytes) and byte countt (bottom 2 bytes). */
389 vuint32 config_status; /* Configuration/Status. */
390 vuint32 reserved1; /* reserved to make the descriptor cache line aligned. */
391 vuint32 reserved2; /* reserved to make the descriptor cache line aligned. */
392};
393
394/* last next descriptor address flag */
ee311214 395#define DMA_DESCR_LAST (1 << 31)
d1927cee 396
397/* TX DMA descriptor config status bits */
ee311214 398#define DMA_DESCR_TX_EOF (1 << 0) /* end of frame */
399#define DMA_DESCR_TX_SOF (1 << 1) /* start of frame */
400#define DMA_DESCR_TX_PFVLAN (1 << 2)
401#define DMA_DESCR_TX_HUGE (1 << 3)
402#define DMA_DESCR_TX_PAD (1 << 4)
403#define DMA_DESCR_TX_CRC (1 << 5)
404#define DMA_DESCR_TX_DESCR_INT (1 << 14)
405#define DMA_DESCR_TX_RETRY_COUNT 0x000F0000
406#define DMA_DESCR_TX_ONE_COLLISION (1 << 20)
407#define DMA_DESCR_TX_LATE_COLLISION (1 << 24)
408#define DMA_DESCR_TX_UNDERRUN (1 << 25)
409#define DMA_DESCR_TX_RETRY_LIMIT (1 << 26)
410#define DMA_DESCR_TX_OK (1 << 30)
411#define DMA_DESCR_TX_OWNER (1 << 31)
d1927cee 412
413/* RX DMA descriptor status bits */
ee311214 414#define DMA_DESCR_RX_EOF (1 << 0)
415#define DMA_DESCR_RX_SOF (1 << 1)
416#define DMA_DESCR_RX_VTF (1 << 2)
417#define DMA_DESCR_RX_FRAME_IS_TYPE (1 << 3)
418#define DMA_DESCR_RX_SHORT_FRAME (1 << 4)
419#define DMA_DESCR_RX_HASH_MATCH (1 << 7)
420#define DMA_DESCR_RX_BAD_FRAME (1 << 8)
421#define DMA_DESCR_RX_OVERRUN (1 << 9)
422#define DMA_DESCR_RX_MAX_FRAME_LEN (1 << 11)
423#define DMA_DESCR_RX_CRC_ERROR (1 << 12)
424#define DMA_DESCR_RX_DESCR_INT (1 << 13)
425#define DMA_DESCR_RX_OWNER (1 << 15)
426
427#define RX_BUFFER_SIZE PKTSIZE
428#define NUM_RX_DESC PKTBUFSRX
d1927cee 429
430static struct dma_descriptor tx_descriptor __attribute__ ((aligned(32)));
431
432static struct dma_descriptor rx_descr_array[NUM_RX_DESC]
ee311214 433 __attribute__ ((aligned(32)));
d1927cee 434
435static struct dma_descriptor *rx_descr_current;
436
ee311214 437static int tsi108_eth_probe (struct eth_device *dev, bd_t * bis);
438static int tsi108_eth_send (struct eth_device *dev,
d1927cee 439 volatile void *packet, int length);
ee311214 440static int tsi108_eth_recv (struct eth_device *dev);
441static void tsi108_eth_halt (struct eth_device *dev);
442static unsigned int read_phy (unsigned int base,
d1927cee 443 unsigned int phy_addr, unsigned int phy_reg);
ee311214 444static void write_phy (unsigned int base,
d1927cee 445 unsigned int phy_addr,
446 unsigned int phy_reg, unsigned int phy_data);
447
448#if TSI108_ETH_DEBUG > 100
449/*
450 * print phy debug infomation
451 */
ee311214 452static void dump_phy_regs (unsigned int phy_addr)
d1927cee 453{
454 int i;
455
ee311214 456 printf ("PHY %d registers\n", phy_addr);
d1927cee 457 for (i = 0; i <= 30; i++) {
ee311214 458 printf ("%2d 0x%04x\n", i, read_phy (ETH_BASE, phy_addr, i));
d1927cee 459 }
ee311214 460 printf ("\n");
d1927cee 461
462}
463#else
464#define dump_phy_regs(base) do{}while(0)
465#endif
466
467#if TSI108_ETH_DEBUG > 100
468/*
469 * print debug infomation
470 */
ee311214 471static void tx_diag_regs (unsigned int base)
d1927cee 472{
473 int i;
474 unsigned long dummy;
475
ee311214 476 printf ("TX diagnostics registers\n");
d1927cee 477 reg_TX_DIAGNOSTIC_ADDR(base) = 0x00 | TX_DIAGNOSTIC_ADDR_AI;
ee311214 478 udelay (1000);
d1927cee 479 dummy = reg_TX_DIAGNOSTIC_DATA(base);
480 for (i = 0x00; i <= 0x05; i++) {
ee311214 481 udelay (1000);
482 printf ("0x%02x 0x%08x\n", i, reg_TX_DIAGNOSTIC_DATA(base));
d1927cee 483 }
484 reg_TX_DIAGNOSTIC_ADDR(base) = 0x40 | TX_DIAGNOSTIC_ADDR_AI;
ee311214 485 udelay (1000);
d1927cee 486 dummy = reg_TX_DIAGNOSTIC_DATA(base);
487 for (i = 0x40; i <= 0x47; i++) {
ee311214 488 udelay (1000);
489 printf ("0x%02x 0x%08x\n", i, reg_TX_DIAGNOSTIC_DATA(base));
d1927cee 490 }
ee311214 491 printf ("\n");
d1927cee 492
493}
494#else
495#define tx_diag_regs(base) do{}while(0)
496#endif
497
498#if TSI108_ETH_DEBUG > 100
499/*
500 * print debug infomation
501 */
ee311214 502static void rx_diag_regs (unsigned int base)
d1927cee 503{
504 int i;
505 unsigned long dummy;
506
ee311214 507 printf ("RX diagnostics registers\n");
d1927cee 508 reg_RX_DIAGNOSTIC_ADDR(base) = 0x00 | RX_DIAGNOSTIC_ADDR_AI;
ee311214 509 udelay (1000);
d1927cee 510 dummy = reg_RX_DIAGNOSTIC_DATA(base);
511 for (i = 0x00; i <= 0x05; i++) {
ee311214 512 udelay (1000);
513 printf ("0x%02x 0x%08x\n", i, reg_RX_DIAGNOSTIC_DATA(base));
d1927cee 514 }
515 reg_RX_DIAGNOSTIC_ADDR(base) = 0x40 | RX_DIAGNOSTIC_ADDR_AI;
ee311214 516 udelay (1000);
d1927cee 517 dummy = reg_RX_DIAGNOSTIC_DATA(base);
518 for (i = 0x08; i <= 0x0a; i++) {
ee311214 519 udelay (1000);
520 printf ("0x%02x 0x%08x\n", i, reg_RX_DIAGNOSTIC_DATA(base));
d1927cee 521 }
ee311214 522 printf ("\n");
d1927cee 523
524}
525#else
526#define rx_diag_regs(base) do{}while(0)
527#endif
528
529#if TSI108_ETH_DEBUG > 100
530/*
531 * print debug infomation
532 */
ee311214 533static void debug_mii_regs (unsigned int base)
d1927cee 534{
ee311214 535 printf ("MII_MGMT_CONFIG 0x%08x\n", reg_MII_MGMT_CONFIG(base));
536 printf ("MII_MGMT_COMMAND 0x%08x\n", reg_MII_MGMT_COMMAND(base));
537 printf ("MII_MGMT_ADDRESS 0x%08x\n", reg_MII_MGMT_ADDRESS(base));
538 printf ("MII_MGMT_CONTROL 0x%08x\n", reg_MII_MGMT_CONTROL(base));
539 printf ("MII_MGMT_STATUS 0x%08x\n", reg_MII_MGMT_STATUS(base));
540 printf ("MII_MGMT_INDICATORS 0x%08x\n", reg_MII_MGMT_INDICATORS(base));
541 printf ("\n");
d1927cee 542
543}
544#else
545#define debug_mii_regs(base) do{}while(0)
546#endif
547
548/*
549 * Wait until the phy bus is non-busy
550 */
ee311214 551static void phy_wait (unsigned int base, unsigned int condition)
d1927cee 552{
553 int timeout;
554
555 timeout = 0;
556 while (reg_MII_MGMT_INDICATORS(base) & condition) {
ee311214 557 udelay (10);
d1927cee 558 if (++timeout > 10000) {
ee311214 559 printf ("ERROR: timeout waiting for phy bus (%d)\n",
d1927cee 560 condition);
561 break;
562 }
563 }
564}
565
566/*
567 * read phy register
568 */
ee311214 569static unsigned int read_phy (unsigned int base,
d1927cee 570 unsigned int phy_addr, unsigned int phy_reg)
571{
572 unsigned int value;
573
ee311214 574 phy_wait (base, MII_MGMT_INDICATORS_BUSY);
d1927cee 575
576 reg_MII_MGMT_ADDRESS(base) = (phy_addr << 8) | phy_reg;
577
578 /* Ensure that the Read Cycle bit is cleared prior to next read cycle */
579 reg_MII_MGMT_COMMAND(base) = 0;
580
581 /* start the read */
582 reg_MII_MGMT_COMMAND(base) = MII_MGMT_COMMAND_READ_CYCLE;
583
584 /* wait for the read to complete */
ee311214 585 phy_wait (base,
d1927cee 586 MII_MGMT_INDICATORS_NOT_VALID | MII_MGMT_INDICATORS_BUSY);
587
588 value = reg_MII_MGMT_STATUS(base);
589
590 reg_MII_MGMT_COMMAND(base) = 0;
591
592 return value;
593}
594
595/*
596 * write phy register
597 */
ee311214 598static void write_phy (unsigned int base,
d1927cee 599 unsigned int phy_addr,
600 unsigned int phy_reg, unsigned int phy_data)
601{
ee311214 602 phy_wait (base, MII_MGMT_INDICATORS_BUSY);
d1927cee 603
604 reg_MII_MGMT_ADDRESS(base) = (phy_addr << 8) | phy_reg;
605
606 /* Ensure that the Read Cycle bit is cleared prior to next cycle */
607 reg_MII_MGMT_COMMAND(base) = 0;
608
609 /* start the write */
610 reg_MII_MGMT_CONTROL(base) = phy_data;
611}
612
613/*
614 * configure the marvell 88e1111 phy
615 */
ee311214 616static int marvell_88e_phy_config (struct eth_device *dev, int *speed,
d1927cee 617 int *duplex)
618{
619 unsigned long base;
620 unsigned long phy_addr;
621 unsigned int phy_status;
622 unsigned int phy_spec_status;
623 int timeout;
624 int phy_speed;
625 int phy_duplex;
626 unsigned int value;
627
628 phy_speed = LINK_SPEED_UNKNOWN;
629 phy_duplex = LINK_DUPLEX_UNKNOWN;
630
631 base = dev->iobase;
632 phy_addr = (unsigned long)dev->priv;
633
634 /* Take the PHY out of reset. */
ee311214 635 write_phy (ETH_BASE, phy_addr, PHY_CTRL_REG, PHY_CTRL_RESET);
d1927cee 636
637 /* Wait for the reset process to complete. */
ee311214 638 udelay (10);
d1927cee 639 timeout = 0;
640 while ((phy_status =
ee311214 641 read_phy (ETH_BASE, phy_addr, PHY_CTRL_REG)) & PHY_CTRL_RESET) {
642 udelay (10);
d1927cee 643 if (++timeout > 10000) {
ee311214 644 printf ("ERROR: timeout waiting for phy reset\n");
d1927cee 645 break;
646 }
647 }
648
649 /* TBI Configuration. */
ee311214 650 write_phy (base, TBI_ADDR, TBI_CONTROL_2, TBI_CONTROL_2_G_MII_MODE |
d1927cee 651 TBI_CONTROL_2_RECEIVE_CLOCK_SELECT);
652 /* Wait for the link to be established. */
653 timeout = 0;
654 do {
ee311214 655 udelay (20000);
656 phy_status = read_phy (ETH_BASE, phy_addr, PHY_STATUS_REG);
d1927cee 657 if (++timeout > 100) {
658 debug_lev(1, "ERROR: unable to establish link!!!\n");
659 break;
660 }
661 } while ((phy_status & PHY_STAT_LINK_UP) == 0);
662
ee311214 663 if ((phy_status & PHY_STAT_LINK_UP) == 0)
d1927cee 664 return 0;
d1927cee 665
666 value = 0;
ee311214 667 phy_spec_status = read_phy (ETH_BASE, phy_addr, MV1111_SPEC_STAT_REG);
d1927cee 668 if (phy_spec_status & SPEC_STAT_RESOLVED) {
669 switch (phy_spec_status & SPEC_STAT_SPEED_MASK) {
670 case SPEED_1000:
671 phy_speed = LINK_SPEED_1000;
672 value |= PHY_CTRL_SPEED1;
673 break;
674 case SPEED_100:
675 phy_speed = LINK_SPEED_100;
676 value |= PHY_CTRL_SPEED0;
677 break;
678 case SPEED_10:
679 phy_speed = LINK_SPEED_10;
680 break;
681 }
682 if (phy_spec_status & SPEC_STAT_FULL_DUP) {
683 phy_duplex = LINK_DUPLEX_FULL;
684 value |= PHY_CTRL_FULL_DUPLEX;
ee311214 685 } else
d1927cee 686 phy_duplex = LINK_DUPLEX_HALF;
d1927cee 687 }
688 /* set TBI speed */
ee311214 689 write_phy (base, TBI_ADDR, PHY_CTRL_REG, value);
690 write_phy (base, TBI_ADDR, PHY_AN_ADV_REG, 0x0060);
d1927cee 691
692#if TSI108_ETH_DEBUG > 0
ee311214 693 printf ("%s link is up", dev->name);
694 phy_spec_status = read_phy (ETH_BASE, phy_addr, MV1111_SPEC_STAT_REG);
d1927cee 695 if (phy_spec_status & SPEC_STAT_RESOLVED) {
696 switch (phy_speed) {
697 case LINK_SPEED_1000:
ee311214 698 printf (", 1000 Mbps");
d1927cee 699 break;
700 case LINK_SPEED_100:
ee311214 701 printf (", 100 Mbps");
d1927cee 702 break;
703 case LINK_SPEED_10:
ee311214 704 printf (", 10 Mbps");
d1927cee 705 break;
706 }
ee311214 707 if (phy_duplex == LINK_DUPLEX_FULL)
708 printf (", Full duplex");
709 else
710 printf (", Half duplex");
d1927cee 711 }
ee311214 712 printf ("\n");
d1927cee 713#endif
714
ee311214 715 dump_phy_regs (TBI_ADDR);
716 if (speed)
d1927cee 717 *speed = phy_speed;
ee311214 718 if (duplex)
d1927cee 719 *duplex = phy_duplex;
d1927cee 720
721 return 1;
722}
723
724/*
725 * External interface
726 *
727 * register the tsi108 ethernet controllers with the multi-ethernet system
728 */
ee311214 729int tsi108_eth_initialize (bd_t * bis)
d1927cee 730{
731 struct eth_device *dev;
732 int index;
733
734 for (index = 0; index < CONFIG_TSI108_ETH_NUM_PORTS; index++) {
735 dev = (struct eth_device *)malloc(sizeof(struct eth_device));
736
ee311214 737 sprintf (dev->name, "TSI108_eth%d", index);
d1927cee 738
739 dev->iobase = ETH_BASE + (index * ETH_PORT_OFFSET);
740 dev->priv = (void *)(phy_address[index]);
741 dev->init = tsi108_eth_probe;
742 dev->halt = tsi108_eth_halt;
743 dev->send = tsi108_eth_send;
744 dev->recv = tsi108_eth_recv;
745
746 eth_register(dev);
747 }
748 return index;
749}
750
751/*
752 * probe for and initialize a single ethernet interface
753 */
ee311214 754static int tsi108_eth_probe (struct eth_device *dev, bd_t * bis)
d1927cee 755{
756 unsigned long base;
757 unsigned long value;
758 int index;
759 struct dma_descriptor *tx_descr;
760 struct dma_descriptor *rx_descr;
761 int speed;
762 int duplex;
763
764 base = dev->iobase;
765
766 reg_PORT_CONTROL(base) = PORT_CONTROL_STE | PORT_CONTROL_BPT;
767
768 /* Bring DMA/FIFO out of reset. */
769 reg_TX_CONFIG(base) = 0x00000000;
770 reg_RX_CONFIG(base) = 0x00000000;
771
772 reg_TX_THRESHOLDS(base) = (192 << 16) | 192;
773 reg_RX_THRESHOLDS(base) = (192 << 16) | 112;
774
775 /* Bring MAC out of reset. */
776 reg_MAC_CONFIG_1(base) = 0x00000000;
777
778 /* DMA MAC configuration. */
779 reg_MAC_CONFIG_1(base) =
780 MAC_CONFIG_1_RX_ENABLE | MAC_CONFIG_1_TX_ENABLE;
781
782 reg_MII_MGMT_CONFIG(base) = MII_MGMT_CONFIG_NO_PREAMBLE;
783 reg_MAXIMUM_FRAME_LENGTH(base) = RX_BUFFER_SIZE;
784
785 /* Note: Early tsi108 manual did not have correct byte order
786 * for the station address.*/
787 reg_STATION_ADDRESS_1(base) = (dev->enetaddr[5] << 24) |
788 (dev->enetaddr[4] << 16) |
789 (dev->enetaddr[3] << 8) | (dev->enetaddr[2] << 0);
790
791 reg_STATION_ADDRESS_2(base) = (dev->enetaddr[1] << 24) |
792 (dev->enetaddr[0] << 16);
793
ee311214 794 if (marvell_88e_phy_config(dev, &speed, &duplex) == 0)
d1927cee 795 return 0;
d1927cee 796
797 value =
798 MAC_CONFIG_2_PREAMBLE_LENGTH(7) | MAC_CONFIG_2_PAD_CRC |
799 MAC_CONFIG_2_CRC_ENABLE;
ee311214 800 if (speed == LINK_SPEED_1000)
d1927cee 801 value |= MAC_CONFIG_2_INTERFACE_MODE(INTERFACE_MODE_BYTE);
ee311214 802 else {
d1927cee 803 value |= MAC_CONFIG_2_INTERFACE_MODE(INTERFACE_MODE_NIBBLE);
804 reg_PORT_CONTROL(base) |= PORT_CONTROL_SPD;
805 }
806 if (duplex == LINK_DUPLEX_FULL) {
807 value |= MAC_CONFIG_2_FULL_DUPLEX;
808 reg_PORT_CONTROL(base) &= ~PORT_CONTROL_BPT;
ee311214 809 } else
d1927cee 810 reg_PORT_CONTROL(base) |= PORT_CONTROL_BPT;
d1927cee 811 reg_MAC_CONFIG_2(base) = value;
812
813 reg_RX_CONFIG(base) = RX_CONFIG_SE;
814 reg_RX_QUEUE_0_CONFIG(base) = OCN_PORT_MEMORY;
815 reg_RX_QUEUE_0_BUF_CONFIG(base) = OCN_PORT_MEMORY;
816
817 /* initialize the RX DMA descriptors */
818 rx_descr = &rx_descr_array[0];
819 rx_descr_current = rx_descr;
820 for (index = 0; index < NUM_RX_DESC; index++) {
821 /* make sure the receive buffers are not in cache */
822 invalidate_dcache_range((unsigned long)NetRxPackets[index],
823 (unsigned long)NetRxPackets[index] +
824 RX_BUFFER_SIZE);
825 rx_descr->start_addr0 =
826 cpu_to_le32((vuint32) NetRxPackets[index]);
827 rx_descr->start_addr1 = 0;
828 rx_descr->next_descr_addr0 =
829 cpu_to_le32((vuint32) (rx_descr + 1));
830 rx_descr->next_descr_addr1 = 0;
831 rx_descr->vlan_byte_count = 0;
832 rx_descr->config_status = cpu_to_le32((RX_BUFFER_SIZE << 16) |
833 DMA_DESCR_RX_OWNER);
834 rx_descr++;
835 }
836 rx_descr--;
837 rx_descr->next_descr_addr0 = 0;
838 rx_descr->next_descr_addr1 = cpu_to_le32(DMA_DESCR_LAST);
839 /* Push the descriptors to RAM so the ethernet DMA can see them */
840 invalidate_dcache_range((unsigned long)rx_descr_array,
841 (unsigned long)rx_descr_array +
842 sizeof(rx_descr_array));
843
844 /* enable RX queue */
845 reg_RX_CONTROL(base) = TX_CONTROL_GO | 0x01;
846 reg_RX_QUEUE_0_PTR_LOW(base) = (u32) rx_descr_current;
847 /* enable receive DMA */
848 reg_RX_QUEUE_0_PTR_HIGH(base) = RX_QUEUE_0_PTR_HIGH_VALID;
849
850 reg_TX_QUEUE_0_CONFIG(base) = OCN_PORT_MEMORY;
851 reg_TX_QUEUE_0_BUF_CONFIG(base) = OCN_PORT_MEMORY;
852
853 /* initialize the TX DMA descriptor */
854 tx_descr = &tx_descriptor;
855
856 tx_descr->start_addr0 = 0;
857 tx_descr->start_addr1 = 0;
858 tx_descr->next_descr_addr0 = 0;
859 tx_descr->next_descr_addr1 = cpu_to_le32(DMA_DESCR_LAST);
860 tx_descr->vlan_byte_count = 0;
861 tx_descr->config_status = cpu_to_le32(DMA_DESCR_TX_OK |
862 DMA_DESCR_TX_SOF |
863 DMA_DESCR_TX_EOF);
864 /* enable TX queue */
865 reg_TX_CONTROL(base) = TX_CONTROL_GO | 0x01;
866
867 return 1;
868}
869
870/*
871 * send a packet
872 */
ee311214 873static int tsi108_eth_send (struct eth_device *dev,
d1927cee 874 volatile void *packet, int length)
875{
876 unsigned long base;
877 int timeout;
878 struct dma_descriptor *tx_descr;
879 unsigned long status;
880
881 base = dev->iobase;
882 tx_descr = &tx_descriptor;
883
884 /* Wait until the last packet has been transmitted. */
885 timeout = 0;
886 do {
887 /* make sure we see the changes made by the DMA engine */
888 invalidate_dcache_range((unsigned long)tx_descr,
889 (unsigned long)tx_descr +
890 sizeof(struct dma_descriptor));
891
ee311214 892 if (timeout != 0)
893 udelay (15);
d1927cee 894 if (++timeout > 10000) {
895 tx_diag_regs(base);
896 debug_lev(1,
897 "ERROR: timeout waiting for last transmit packet to be sent\n");
898 return 0;
899 }
900 } while (tx_descr->config_status & cpu_to_le32(DMA_DESCR_TX_OWNER));
901
902 status = le32_to_cpu(tx_descr->config_status);
903 if ((status & DMA_DESCR_TX_OK) == 0) {
904#ifdef TX_PRINT_ERRORS
ee311214 905 printf ("TX packet error: 0x%08x\n %s%s%s%s\n", status,
d1927cee 906 status & DMA_DESCR_TX_OK ? "tx error, " : "",
907 status & DMA_DESCR_TX_RETRY_LIMIT ?
908 "retry limit reached, " : "",
909 status & DMA_DESCR_TX_UNDERRUN ? "underrun, " : "",
910 status & DMA_DESCR_TX_LATE_COLLISION ? "late collision, "
911 : "");
912#endif
913 }
914
ee311214 915 debug_lev (9, "sending packet %d\n", length);
d1927cee 916 tx_descr->start_addr0 = cpu_to_le32((vuint32) packet);
917 tx_descr->start_addr1 = 0;
918 tx_descr->next_descr_addr0 = 0;
919 tx_descr->next_descr_addr1 = cpu_to_le32(DMA_DESCR_LAST);
920 tx_descr->vlan_byte_count = cpu_to_le32(length);
921 tx_descr->config_status = cpu_to_le32(DMA_DESCR_TX_OWNER |
922 DMA_DESCR_TX_CRC |
923 DMA_DESCR_TX_PAD |
924 DMA_DESCR_TX_SOF |
925 DMA_DESCR_TX_EOF);
926
927 invalidate_dcache_range((unsigned long)tx_descr,
928 (unsigned long)tx_descr +
929 sizeof(struct dma_descriptor));
930
931 invalidate_dcache_range((unsigned long)packet,
932 (unsigned long)packet + length);
933
934 reg_TX_QUEUE_0_PTR_LOW(base) = (u32) tx_descr;
935 reg_TX_QUEUE_0_PTR_HIGH(base) = TX_QUEUE_0_PTR_HIGH_VALID;
936
937 return length;
938}
939
940/*
941 * Check for received packets and send them up the protocal stack
942 */
ee311214 943static int tsi108_eth_recv (struct eth_device *dev)
d1927cee 944{
945 struct dma_descriptor *rx_descr;
946 unsigned long base;
947 int length = 0;
948 unsigned long status;
949 volatile uchar *buffer;
950
951 base = dev->iobase;
952
953 /* make sure we see the changes made by the DMA engine */
ee311214 954 invalidate_dcache_range ((unsigned long)rx_descr_array,
d1927cee 955 (unsigned long)rx_descr_array +
956 sizeof(rx_descr_array));
957
958 /* process all of the received packets */
959 rx_descr = rx_descr_current;
960 while ((rx_descr->config_status & cpu_to_le32(DMA_DESCR_RX_OWNER)) == 0) {
961 /* check for error */
962 status = le32_to_cpu(rx_descr->config_status);
963 if (status & DMA_DESCR_RX_BAD_FRAME) {
964#ifdef RX_PRINT_ERRORS
ee311214 965 printf ("RX packet error: 0x%08x\n %s%s%s%s%s%s\n",
d1927cee 966 status,
967 status & DMA_DESCR_RX_FRAME_IS_TYPE ? "too big, "
968 : "",
969 status & DMA_DESCR_RX_SHORT_FRAME ? "too short, "
970 : "",
971 status & DMA_DESCR_RX_BAD_FRAME ? "bad frame, " :
972 "",
973 status & DMA_DESCR_RX_OVERRUN ? "overrun, " : "",
974 status & DMA_DESCR_RX_MAX_FRAME_LEN ?
975 "max length, " : "",
976 status & DMA_DESCR_RX_CRC_ERROR ? "CRC error, " :
977 "");
978#endif
979 } else {
980 length =
981 le32_to_cpu(rx_descr->vlan_byte_count) & 0xFFFF;
982
983 /*** process packet ***/
984 buffer =
985 (volatile uchar
ee311214 986 *)(le32_to_cpu (rx_descr->start_addr0));
987 NetReceive (buffer, length);
d1927cee 988
ee311214 989 invalidate_dcache_range ((unsigned long)buffer,
d1927cee 990 (unsigned long)buffer +
991 RX_BUFFER_SIZE);
992 }
993 /* Give this buffer back to the DMA engine */
994 rx_descr->vlan_byte_count = 0;
ee311214 995 rx_descr->config_status = cpu_to_le32 ((RX_BUFFER_SIZE << 16) |
d1927cee 996 DMA_DESCR_RX_OWNER);
997 /* move descriptor pointer forward */
998 rx_descr =
999 (struct dma_descriptor
ee311214 1000 *)(le32_to_cpu (rx_descr->next_descr_addr0));
1001 if (rx_descr == 0)
d1927cee 1002 rx_descr = &rx_descr_array[0];
d1927cee 1003 }
1004 /* remember where we are for next time */
1005 rx_descr_current = rx_descr;
1006
1007 /* If the DMA engine has reached the end of the queue
1008 * start over at the begining */
1009 if (reg_RX_EXTENDED_STATUS(base) & RX_EXTENDED_STATUS_EOQ_0) {
1010
1011 reg_RX_EXTENDED_STATUS(base) = RX_EXTENDED_STATUS_EOQ_0;
1012 reg_RX_QUEUE_0_PTR_LOW(base) = (u32) & rx_descr_array[0];
1013 reg_RX_QUEUE_0_PTR_HIGH(base) = RX_QUEUE_0_PTR_HIGH_VALID;
1014 }
1015
1016 return length;
1017}
1018
1019/*
1020 * disable an ethernet interface
1021 */
ee311214 1022static void tsi108_eth_halt (struct eth_device *dev)
d1927cee 1023{
1024 unsigned long base;
1025
1026 base = dev->iobase;
1027
1028 /* Put DMA/FIFO into reset state. */
1029 reg_TX_CONFIG(base) = TX_CONFIG_RST;
1030 reg_RX_CONFIG(base) = RX_CONFIG_RST;
1031
1032 /* Put MAC into reset state. */
1033 reg_MAC_CONFIG_1(base) = MAC_CONFIG_1_SOFT_RESET;
1034}
1035
1036#endif