]> git.ipfire.org Git - thirdparty/linux.git/blame - drivers/tty/rocket.c
projects / thirdparty / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'riscv-for-linus-5.7-rc4' of git://git.kernel.org/pub/scm/linux/kernel...
[thirdparty/linux.git] / drivers / tty / rocket.c
CommitLineData
e3b3d0f5 1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
1da177e4
LT		 2/*
3 * RocketPort device driver for Linux
4 *
5 * Written by Theodore Ts'o, 1995, 1996, 1997, 1998, 1999, 2000.
6 *
7 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003 by Comtrol, Inc.
1da177e4
LT		 8 */
9
10/*
11 * Kernel Synchronization:
12 *
13 * This driver has 2 kernel control paths - exception handlers (calls into the driver
14 * from user mode) and the timer bottom half (tasklet). This is a polled driver, interrupts
15 * are not used.
16 *
17 * Critical data:
18 * - rp_table[], accessed through passed "info" pointers, is a global (static) array of
19 * serial port state information and the xmit_buf circular buffer. Protected by
20 * a per port spinlock.
21 * - xmit_flags[], an array of ints indexed by line (port) number, indicating that there
22 * is data to be transmitted. Protected by atomic bit operations.
23 * - rp_num_ports, int indicating number of open ports, protected by atomic operations.
24 *
25 * rp_write() and rp_write_char() functions use a per port semaphore to protect against
26 * simultaneous access to the same port by more than one process.
27 */
28
29/****** Defines ******/
1da177e4
LT		 30#define ROCKET_PARANOIA_CHECK
31#define ROCKET_DISABLE_SIMUSAGE
32
33#undef ROCKET_SOFT_FLOW
34#undef ROCKET_DEBUG_OPEN
35#undef ROCKET_DEBUG_INTR
36#undef ROCKET_DEBUG_WRITE
37#undef ROCKET_DEBUG_FLOW
38#undef ROCKET_DEBUG_THROTTLE
39#undef ROCKET_DEBUG_WAIT_UNTIL_SENT
40#undef ROCKET_DEBUG_RECEIVE
41#undef ROCKET_DEBUG_HANGUP
42#undef REV_PCI_ORDER
43#undef ROCKET_DEBUG_IO
44
37c44b52 45#define POLL_PERIOD (HZ/100) /* Polling period .01 seconds (10ms) */
1da177e4
LT		 46
47/****** Kernel includes ******/
48
1da177e4
LT		 49#include <linux/module.h>
50#include <linux/errno.h>
51#include <linux/major.h>
52#include <linux/kernel.h>
53#include <linux/signal.h>
54#include <linux/slab.h>
55#include <linux/mm.h>
56#include <linux/sched.h>
57#include <linux/timer.h>
58#include <linux/interrupt.h>
59#include <linux/tty.h>
60#include <linux/tty_driver.h>
61#include <linux/tty_flip.h>
44b7d1b3 62#include <linux/serial.h>
1da177e4
LT		 63#include <linux/string.h>
64#include <linux/fcntl.h>
65#include <linux/ptrace.h>
69f545ea 66#include <linux/mutex.h>
1da177e4
LT		 67#include <linux/ioport.h>
68#include <linux/delay.h>
8cf5a8c5 69#include <linux/completion.h>
1da177e4
LT		 70#include <linux/wait.h>
71#include <linux/pci.h>
44b7d1b3 72#include <linux/uaccess.h>
60063497 73#include <linux/atomic.h>
457fb605 74#include <asm/unaligned.h>
1da177e4
LT		 75#include <linux/bitops.h>
76#include <linux/spinlock.h>
1da177e4
LT		 77#include <linux/init.h>
78
79/****** RocketPort includes ******/
80
81#include "rocket_int.h"
82#include "rocket.h"
83
84#define ROCKET_VERSION "2.09"
85#define ROCKET_DATE "12-June-2003"
86
87/****** RocketPort Local Variables ******/
88
24ed960a 89static void rp_do_poll(struct timer_list *unused);
40565f19 90
1da177e4
LT		 91static struct tty_driver *rocket_driver;
92
93static struct rocket_version driver_version = {
94 ROCKET_VERSION, ROCKET_DATE
95};
96
97static struct r_port *rp_table[MAX_RP_PORTS]; /* The main repository of serial port state information. */
98static unsigned int xmit_flags[NUM_BOARDS]; /* Bit significant, indicates port had data to transmit. */
99 /* eg. Bit 0 indicates port 0 has xmit data, ... */
100static atomic_t rp_num_ports_open; /* Number of serial ports open */
1d27e3e2 101static DEFINE_TIMER(rocket_timer, rp_do_poll);
1da177e4
LT		 102
103static unsigned long board1; /* ISA addresses, retrieved from rocketport.conf */
104static unsigned long board2;
105static unsigned long board3;
106static unsigned long board4;
107static unsigned long controller;
90ab5ee9 108static bool support_low_speed;
1da177e4
LT		 109static unsigned long modem1;
110static unsigned long modem2;
111static unsigned long modem3;
112static unsigned long modem4;
113static unsigned long pc104_1[8];
114static unsigned long pc104_2[8];
115static unsigned long pc104_3[8];
116static unsigned long pc104_4[8];
117static unsigned long *pc104[4] = { pc104_1, pc104_2, pc104_3, pc104_4 };
118
119static int rp_baud_base[NUM_BOARDS]; /* Board config info (Someday make a per-board structure) */
120static unsigned long rcktpt_io_addr[NUM_BOARDS];
121static int rcktpt_type[NUM_BOARDS];
122static int is_PCI[NUM_BOARDS];
123static rocketModel_t rocketModel[NUM_BOARDS];
124static int max_board;
31f35939 125static const struct tty_port_operations rocket_port_ops;
1da177e4
LT		 126
127/*
128 * The following arrays define the interrupt bits corresponding to each AIOP.
129 * These bits are different between the ISA and regular PCI boards and the
130 * Universal PCI boards.
131 */
132
133static Word_t aiop_intr_bits[AIOP_CTL_SIZE] = {
134 AIOP_INTR_BIT_0,
135 AIOP_INTR_BIT_1,
136 AIOP_INTR_BIT_2,
137 AIOP_INTR_BIT_3
138};
139
416187ca 140#ifdef CONFIG_PCI
1da177e4
LT		 141static Word_t upci_aiop_intr_bits[AIOP_CTL_SIZE] = {
142 UPCI_AIOP_INTR_BIT_0,
143 UPCI_AIOP_INTR_BIT_1,
144 UPCI_AIOP_INTR_BIT_2,
145 UPCI_AIOP_INTR_BIT_3
146};
416187ca 147#endif
1da177e4 148
f15313bf
AB		 149static Byte_t RData[RDATASIZE] = {
150 0x00, 0x09, 0xf6, 0x82,
151 0x02, 0x09, 0x86, 0xfb,
152 0x04, 0x09, 0x00, 0x0a,
153 0x06, 0x09, 0x01, 0x0a,
154 0x08, 0x09, 0x8a, 0x13,
155 0x0a, 0x09, 0xc5, 0x11,
156 0x0c, 0x09, 0x86, 0x85,
157 0x0e, 0x09, 0x20, 0x0a,
158 0x10, 0x09, 0x21, 0x0a,
159 0x12, 0x09, 0x41, 0xff,
160 0x14, 0x09, 0x82, 0x00,
161 0x16, 0x09, 0x82, 0x7b,
162 0x18, 0x09, 0x8a, 0x7d,
163 0x1a, 0x09, 0x88, 0x81,
164 0x1c, 0x09, 0x86, 0x7a,
165 0x1e, 0x09, 0x84, 0x81,
166 0x20, 0x09, 0x82, 0x7c,
167 0x22, 0x09, 0x0a, 0x0a
168};
169
170static Byte_t RRegData[RREGDATASIZE] = {
171 0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */
172 0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */
173 0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */
174 0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */
175 0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */
176 0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */
177 0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */
178 0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
179 0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
180 0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
181 0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
182 0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
183 0x22, 0x09, 0x0a, 0x0a /* 30: Rx FIFO Enable */
184};
185
186static CONTROLLER_T sController[CTL_SIZE] = {
187 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
188 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
189 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
190 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
191 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
192 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
193 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
194 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}
195};
196
197static Byte_t sBitMapClrTbl[8] = {
198 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f
199};
200
201static Byte_t sBitMapSetTbl[8] = {
202 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
203};
204
205static int sClockPrescale = 0x14;
206
1da177e4
LT		 207/*
208 * Line number is the ttySIx number (x), the Minor number. We
209 * assign them sequentially, starting at zero. The following
210 * array keeps track of the line number assigned to a given board/aiop/channel.
211 */
212static unsigned char lineNumbers[MAX_RP_PORTS];
213static unsigned long nextLineNumber;
214
215/***** RocketPort Static Prototypes *********/
216static int __init init_ISA(int i);
217static void rp_wait_until_sent(struct tty_struct *tty, int timeout);
218static void rp_flush_buffer(struct tty_struct *tty);
1da177e4
LT		 219static unsigned char GetLineNumber(int ctrl, int aiop, int ch);
220static unsigned char SetLineNumber(int ctrl, int aiop, int ch);
221static void rp_start(struct tty_struct *tty);
f15313bf
AB		 222static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
223 int ChanNum);
224static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);
225static void sFlushRxFIFO(CHANNEL_T * ChP);
226static void sFlushTxFIFO(CHANNEL_T * ChP);
227static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags);
228static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags);
229static void sModemReset(CONTROLLER_T * CtlP, int chan, int on);
230static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on);
231static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
f15313bf
AB		 232static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
233 ByteIO_t * AiopIOList, int AiopIOListSize,
234 int IRQNum, Byte_t Frequency, int PeriodicOnly);
235static int sReadAiopID(ByteIO_t io);
236static int sReadAiopNumChan(WordIO_t io);
1da177e4 237
1da177e4
LT		 238MODULE_AUTHOR("Theodore Ts'o");
239MODULE_DESCRIPTION("Comtrol RocketPort driver");
3b60daf8 240module_param_hw(board1, ulong, ioport, 0);
1da177e4 241MODULE_PARM_DESC(board1, "I/O port for (ISA) board #1");
3b60daf8 242module_param_hw(board2, ulong, ioport, 0);
1da177e4 243MODULE_PARM_DESC(board2, "I/O port for (ISA) board #2");
3b60daf8 244module_param_hw(board3, ulong, ioport, 0);
1da177e4 245MODULE_PARM_DESC(board3, "I/O port for (ISA) board #3");
3b60daf8 246module_param_hw(board4, ulong, ioport, 0);
1da177e4 247MODULE_PARM_DESC(board4, "I/O port for (ISA) board #4");
3b60daf8 248module_param_hw(controller, ulong, ioport, 0);
1da177e4
LT		 249MODULE_PARM_DESC(controller, "I/O port for (ISA) rocketport controller");
250module_param(support_low_speed, bool, 0);
251MODULE_PARM_DESC(support_low_speed, "1 means support 50 baud, 0 means support 460400 baud");
252module_param(modem1, ulong, 0);
253MODULE_PARM_DESC(modem1, "1 means (ISA) board #1 is a RocketModem");
254module_param(modem2, ulong, 0);
255MODULE_PARM_DESC(modem2, "1 means (ISA) board #2 is a RocketModem");
256module_param(modem3, ulong, 0);
257MODULE_PARM_DESC(modem3, "1 means (ISA) board #3 is a RocketModem");
258module_param(modem4, ulong, 0);
259MODULE_PARM_DESC(modem4, "1 means (ISA) board #4 is a RocketModem");
260module_param_array(pc104_1, ulong, NULL, 0);
261MODULE_PARM_DESC(pc104_1, "set interface types for ISA(PC104) board #1 (e.g. pc104_1=232,232,485,485,...");
262module_param_array(pc104_2, ulong, NULL, 0);
263MODULE_PARM_DESC(pc104_2, "set interface types for ISA(PC104) board #2 (e.g. pc104_2=232,232,485,485,...");
264module_param_array(pc104_3, ulong, NULL, 0);
265MODULE_PARM_DESC(pc104_3, "set interface types for ISA(PC104) board #3 (e.g. pc104_3=232,232,485,485,...");
266module_param_array(pc104_4, ulong, NULL, 0);
267MODULE_PARM_DESC(pc104_4, "set interface types for ISA(PC104) board #4 (e.g. pc104_4=232,232,485,485,...");
268
423ea325 269static int __init rp_init(void);
1da177e4
LT		 270static void rp_cleanup_module(void);
271
272module_init(rp_init);
273module_exit(rp_cleanup_module);
274
1da177e4 275
1da177e4 276MODULE_LICENSE("Dual BSD/GPL");
1da177e4
LT		 277
278/*************************************************************************/
279/* Module code starts here */
280
281static inline int rocket_paranoia_check(struct r_port *info,
282 const char *routine)
283{
284#ifdef ROCKET_PARANOIA_CHECK
285 if (!info)
286 return 1;
287 if (info->magic != RPORT_MAGIC) {
68562b79
JS		 288 printk(KERN_WARNING "Warning: bad magic number for rocketport "
289 "struct in %s\n", routine);
1da177e4
LT		 290 return 1;
291 }
292#endif
293 return 0;
294}
295
296
297/* Serial port receive data function. Called (from timer poll) when an AIOPIC signals
298 * that receive data is present on a serial port. Pulls data from FIFO, moves it into the
299 * tty layer.
300 */
2e124b4a
JS		 301static void rp_do_receive(struct r_port *info, CHANNEL_t *cp,
302 unsigned int ChanStatus)
1da177e4
LT		 303{
304 unsigned int CharNStat;
cc44a817
PF		 305 int ToRecv, wRecv, space;
306 unsigned char *cbuf;
1da177e4
LT		 307
308 ToRecv = sGetRxCnt(cp);
1da177e4 309#ifdef ROCKET_DEBUG_INTR
68562b79 310 printk(KERN_INFO "rp_do_receive(%d)...\n", ToRecv);
1da177e4 311#endif
cc44a817
PF		 312 if (ToRecv == 0)
313 return;
33f0f88f 314
1da177e4
LT		 315 /*
316 * if status indicates there are errored characters in the
317 * FIFO, then enter status mode (a word in FIFO holds
318 * character and status).
319 */
320 if (ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
321 if (!(ChanStatus & STATMODE)) {
322#ifdef ROCKET_DEBUG_RECEIVE
68562b79 323 printk(KERN_INFO "Entering STATMODE...\n");
1da177e4
LT		 324#endif
325 ChanStatus |= STATMODE;
326 sEnRxStatusMode(cp);
327 }
328 }
329
330 /*
331 * if we previously entered status mode, then read down the
332 * FIFO one word at a time, pulling apart the character and
333 * the status. Update error counters depending on status
334 */
335 if (ChanStatus & STATMODE) {
336#ifdef ROCKET_DEBUG_RECEIVE
68562b79
JS		 337 printk(KERN_INFO "Ignore %x, read %x...\n",
338 info->ignore_status_mask, info->read_status_mask);
1da177e4
LT		 339#endif
340 while (ToRecv) {
cc44a817
PF		 341 char flag;
342
1da177e4
LT		 343 CharNStat = sInW(sGetTxRxDataIO(cp));
344#ifdef ROCKET_DEBUG_RECEIVE
68562b79 345 printk(KERN_INFO "%x...\n", CharNStat);
1da177e4
LT		 346#endif
347 if (CharNStat & STMBREAKH)
348 CharNStat &= ~(STMFRAMEH | STMPARITYH);
349 if (CharNStat & info->ignore_status_mask) {
350 ToRecv--;
351 continue;
352 }
353 CharNStat &= info->read_status_mask;
354 if (CharNStat & STMBREAKH)
cc44a817 355 flag = TTY_BREAK;
1da177e4 356 else if (CharNStat & STMPARITYH)
cc44a817 357 flag = TTY_PARITY;
1da177e4 358 else if (CharNStat & STMFRAMEH)
cc44a817 359 flag = TTY_FRAME;
1da177e4 360 else if (CharNStat & STMRCVROVRH)
cc44a817 361 flag = TTY_OVERRUN;
1da177e4 362 else
cc44a817 363 flag = TTY_NORMAL;
92a19f9c
JS		 364 tty_insert_flip_char(&info->port, CharNStat & 0xff,
365 flag);
1da177e4
LT		 366 ToRecv--;
367 }
368
369 /*
370 * after we've emptied the FIFO in status mode, turn
371 * status mode back off
372 */
373 if (sGetRxCnt(cp) == 0) {
374#ifdef ROCKET_DEBUG_RECEIVE
375 printk(KERN_INFO "Status mode off.\n");
376#endif
377 sDisRxStatusMode(cp);
378 }
379 } else {
380 /*
381 * we aren't in status mode, so read down the FIFO two
382 * characters at time by doing repeated word IO
383 * transfer.
384 */
2f693357 385 space = tty_prepare_flip_string(&info->port, &cbuf, ToRecv);
cc44a817
PF		 386 if (space < ToRecv) {
387#ifdef ROCKET_DEBUG_RECEIVE
388 printk(KERN_INFO "rp_do_receive:insufficient space ToRecv=%d space=%d\n", ToRecv, space);
389#endif
390 if (space <= 0)
391 return;
392 ToRecv = space;
393 }
1da177e4
LT		 394 wRecv = ToRecv >> 1;
395 if (wRecv)
396 sInStrW(sGetTxRxDataIO(cp), (unsigned short *) cbuf, wRecv);
397 if (ToRecv & 1)
398 cbuf[ToRecv - 1] = sInB(sGetTxRxDataIO(cp));
1da177e4
LT		 399 }
400 /* Push the data up to the tty layer */
2e124b4a 401 tty_flip_buffer_push(&info->port);
1da177e4
LT		 402}
403
404/*
405 * Serial port transmit data function. Called from the timer polling loop as a
406 * result of a bit set in xmit_flags[], indicating data (from the tty layer) is ready
407 * to be sent out the serial port. Data is buffered in rp_table[line].xmit_buf, it is
408 * moved to the port's xmit FIFO. *info is critical data, protected by spinlocks.
409 */
410static void rp_do_transmit(struct r_port *info)
411{
412 int c;
413 CHANNEL_t *cp = &info->channel;
414 struct tty_struct *tty;
415 unsigned long flags;
416
417#ifdef ROCKET_DEBUG_INTR
68562b79 418 printk(KERN_DEBUG "%s\n", __func__);
1da177e4
LT		 419#endif
420 if (!info)
421 return;
47b01b3a
AC		 422 tty = tty_port_tty_get(&info->port);
423
424 if (tty == NULL) {
425 printk(KERN_WARNING "rp: WARNING %s called with tty==NULL\n", __func__);
1da177e4
LT		 426 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
427 return;
428 }
429
430 spin_lock_irqsave(&info->slock, flags);
1da177e4
LT		 431 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
432
433 /* Loop sending data to FIFO until done or FIFO full */
434 while (1) {
ee797069 435 if (tty->stopped)
1da177e4 436 break;
709107fc
HH		 437 c = min(info->xmit_fifo_room, info->xmit_cnt);
438 c = min(c, XMIT_BUF_SIZE - info->xmit_tail);
1da177e4
LT		 439 if (c <= 0 || info->xmit_fifo_room <= 0)
440 break;
441 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) (info->xmit_buf + info->xmit_tail), c / 2);
442 if (c & 1)
443 sOutB(sGetTxRxDataIO(cp), info->xmit_buf[info->xmit_tail + c - 1]);
444 info->xmit_tail += c;
445 info->xmit_tail &= XMIT_BUF_SIZE - 1;
446 info->xmit_cnt -= c;
447 info->xmit_fifo_room -= c;
448#ifdef ROCKET_DEBUG_INTR
68562b79 449 printk(KERN_INFO "tx %d chars...\n", c);
1da177e4
LT		 450#endif
451 }
452
453 if (info->xmit_cnt == 0)
454 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
455
456 if (info->xmit_cnt < WAKEUP_CHARS) {
457 tty_wakeup(tty);
1da177e4
LT		 458#ifdef ROCKETPORT_HAVE_POLL_WAIT
459 wake_up_interruptible(&tty->poll_wait);
460#endif
461 }
462
463 spin_unlock_irqrestore(&info->slock, flags);
47b01b3a 464 tty_kref_put(tty);
1da177e4
LT		 465
466#ifdef ROCKET_DEBUG_INTR
68562b79 467 printk(KERN_DEBUG "(%d,%d,%d,%d)...\n", info->xmit_cnt, info->xmit_head,
1da177e4
LT		 468 info->xmit_tail, info->xmit_fifo_room);
469#endif
470}
471
472/*
473 * Called when a serial port signals it has read data in it's RX FIFO.
474 * It checks what interrupts are pending and services them, including
475 * receiving serial data.
476 */
477static void rp_handle_port(struct r_port *info)
478{
479 CHANNEL_t *cp;
1da177e4
LT		 480 unsigned int IntMask, ChanStatus;
481
482 if (!info)
483 return;
484
d41861ca 485 if (!tty_port_initialized(&info->port)) {
68562b79
JS		 486 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
487 "info->flags & NOT_INIT\n");
1da177e4
LT		 488 return;
489 }
2e124b4a 490
1da177e4 491 cp = &info->channel;
1da177e4
LT		 492
493 IntMask = sGetChanIntID(cp) & info->intmask;
494#ifdef ROCKET_DEBUG_INTR
68562b79 495 printk(KERN_INFO "rp_interrupt %02x...\n", IntMask);
1da177e4
LT		 496#endif
497 ChanStatus = sGetChanStatus(cp);
498 if (IntMask & RXF_TRIG) { /* Rx FIFO trigger level */
2e124b4a 499 rp_do_receive(info, cp, ChanStatus);
1da177e4
LT		 500 }
501 if (IntMask & DELTA_CD) { /* CD change */
502#if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_INTR) || defined(ROCKET_DEBUG_HANGUP))
68562b79 503 printk(KERN_INFO "ttyR%d CD now %s...\n", info->line,
1da177e4
LT		 504 (ChanStatus & CD_ACT) ? "on" : "off");
505#endif
506 if (!(ChanStatus & CD_ACT) && info->cd_status) {
507#ifdef ROCKET_DEBUG_HANGUP
508 printk(KERN_INFO "CD drop, calling hangup.\n");
509#endif
aa27a094 510 tty_port_tty_hangup(&info->port, false);
1da177e4
LT		 511 }
512 info->cd_status = (ChanStatus & CD_ACT) ? 1 : 0;
e60a1084 513 wake_up_interruptible(&info->port.open_wait);
1da177e4
LT		 514 }
515#ifdef ROCKET_DEBUG_INTR
516 if (IntMask & DELTA_CTS) { /* CTS change */
517 printk(KERN_INFO "CTS change...\n");
518 }
519 if (IntMask & DELTA_DSR) { /* DSR change */
520 printk(KERN_INFO "DSR change...\n");
521 }
522#endif
523}
524
525/*
526 * The top level polling routine. Repeats every 1/100 HZ (10ms).
527 */
24ed960a 528static void rp_do_poll(struct timer_list *unused)
1da177e4
LT		 529{
530 CONTROLLER_t *ctlp;
6c0286b1
JS		 531 int ctrl, aiop, ch, line;
532 unsigned int xmitmask, i;
1da177e4
LT		 533 unsigned int CtlMask;
534 unsigned char AiopMask;
535 Word_t bit;
536
537 /* Walk through all the boards (ctrl's) */
538 for (ctrl = 0; ctrl < max_board; ctrl++) {
539 if (rcktpt_io_addr[ctrl] <= 0)
540 continue;
541
542 /* Get a ptr to the board's control struct */
543 ctlp = sCtlNumToCtlPtr(ctrl);
544
3a4fa0a2 545 /* Get the interrupt status from the board */
1da177e4
LT		 546#ifdef CONFIG_PCI
547 if (ctlp->BusType == isPCI)
548 CtlMask = sPCIGetControllerIntStatus(ctlp);
549 else
550#endif
551 CtlMask = sGetControllerIntStatus(ctlp);
552
553 /* Check if any AIOP read bits are set */
554 for (aiop = 0; CtlMask; aiop++) {
555 bit = ctlp->AiopIntrBits[aiop];
556 if (CtlMask & bit) {
557 CtlMask &= ~bit;
558 AiopMask = sGetAiopIntStatus(ctlp, aiop);
559
560 /* Check if any port read bits are set */
561 for (ch = 0; AiopMask; AiopMask >>= 1, ch++) {
562 if (AiopMask & 1) {
563
564 /* Get the line number (/dev/ttyRx number). */
565 /* Read the data from the port. */
566 line = GetLineNumber(ctrl, aiop, ch);
567 rp_handle_port(rp_table[line]);
568 }
569 }
570 }
571 }
572
573 xmitmask = xmit_flags[ctrl];
574
575 /*
576 * xmit_flags contains bit-significant flags, indicating there is data
577 * to xmit on the port. Bit 0 is port 0 on this board, bit 1 is port
578 * 1, ... (32 total possible). The variable i has the aiop and ch
579 * numbers encoded in it (port 0-7 are aiop0, 8-15 are aiop1, etc).
580 */
581 if (xmitmask) {
582 for (i = 0; i < rocketModel[ctrl].numPorts; i++) {
583 if (xmitmask & (1 << i)) {
584 aiop = (i & 0x18) >> 3;
585 ch = i & 0x07;
586 line = GetLineNumber(ctrl, aiop, ch);
587 rp_do_transmit(rp_table[line]);
588 }
589 }
590 }
591 }
592
593 /*
594 * Reset the timer so we get called at the next clock tick (10ms).
595 */
596 if (atomic_read(&rp_num_ports_open))
597 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
598}
599
600/*
601 * Initializes the r_port structure for a port, as well as enabling the port on
602 * the board.
603 * Inputs: board, aiop, chan numbers
604 */
06ed48b7
JL		 605static void __init
606init_r_port(int board, int aiop, int chan, struct pci_dev *pci_dev)
1da177e4
LT		 607{
608 unsigned rocketMode;
609 struct r_port *info;
610 int line;
611 CONTROLLER_T *ctlp;
612
613 /* Get the next available line number */
614 line = SetLineNumber(board, aiop, chan);
615
616 ctlp = sCtlNumToCtlPtr(board);
617
618 /* Get a r_port struct for the port, fill it in and save it globally, indexed by line number */
dd00cc48 619 info = kzalloc(sizeof (struct r_port), GFP_KERNEL);
1da177e4 620 if (!info) {
68562b79
JS		 621 printk(KERN_ERR "Couldn't allocate info struct for line #%d\n",
622 line);
1da177e4
LT		 623 return;
624 }
1da177e4
LT		 625
626 info->magic = RPORT_MAGIC;
627 info->line = line;
628 info->ctlp = ctlp;
629 info->board = board;
630 info->aiop = aiop;
631 info->chan = chan;
31f35939
AC		 632 tty_port_init(&info->port);
633 info->port.ops = &rocket_port_ops;
1da177e4 634 info->flags &= ~ROCKET_MODE_MASK;
7127d243
JS		 635 if (board < ARRAY_SIZE(pc104) && line < ARRAY_SIZE(pc104_1))
636 switch (pc104[board][line]) {
637 case 422:
638 info->flags |= ROCKET_MODE_RS422;
639 break;
640 case 485:
641 info->flags |= ROCKET_MODE_RS485;
642 break;
643 case 232:
644 default:
645 info->flags |= ROCKET_MODE_RS232;
646 break;
647 }
648 else
1da177e4 649 info->flags |= ROCKET_MODE_RS232;
1da177e4
LT		 650
651 info->intmask = RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR;
652 if (sInitChan(ctlp, &info->channel, aiop, chan) == 0) {
68562b79
JS		 653 printk(KERN_ERR "RocketPort sInitChan(%d, %d, %d) failed!\n",
654 board, aiop, chan);
191c5f10 655 tty_port_destroy(&info->port);
1da177e4
LT		 656 kfree(info);
657 return;
658 }
659
660 rocketMode = info->flags & ROCKET_MODE_MASK;
661
662 if ((info->flags & ROCKET_RTS_TOGGLE) || (rocketMode == ROCKET_MODE_RS485))
663 sEnRTSToggle(&info->channel);
664 else
665 sDisRTSToggle(&info->channel);
666
667 if (ctlp->boardType == ROCKET_TYPE_PC104) {
668 switch (rocketMode) {
669 case ROCKET_MODE_RS485:
670 sSetInterfaceMode(&info->channel, InterfaceModeRS485);
671 break;
672 case ROCKET_MODE_RS422:
673 sSetInterfaceMode(&info->channel, InterfaceModeRS422);
674 break;
675 case ROCKET_MODE_RS232:
676 default:
677 if (info->flags & ROCKET_RTS_TOGGLE)
678 sSetInterfaceMode(&info->channel, InterfaceModeRS232T);
679 else
680 sSetInterfaceMode(&info->channel, InterfaceModeRS232);
681 break;
682 }
683 }
684 spin_lock_init(&info->slock);
69f545ea 685 mutex_init(&info->write_mtx);
1da177e4 686 rp_table[line] = info;
734cc178
JS		 687 tty_port_register_device(&info->port, rocket_driver, line,
688 pci_dev ? &pci_dev->dev : NULL);
1da177e4
LT		 689}
690
691/*
692 * Configures a rocketport port according to its termio settings. Called from
693 * user mode into the driver (exception handler). *info CD manipulation is spinlock protected.
694 */
47b01b3a 695static void configure_r_port(struct tty_struct *tty, struct r_port *info,
606d099c 696 struct ktermios *old_termios)
1da177e4
LT		 697{
698 unsigned cflag;
699 unsigned long flags;
700 unsigned rocketMode;
701 int bits, baud, divisor;
702 CHANNEL_t *cp;
adc8d746 703 struct ktermios *t = &tty->termios;
1da177e4 704
1da177e4 705 cp = &info->channel;
6df3526b 706 cflag = t->c_cflag;
1da177e4
LT		 707
708 /* Byte size and parity */
709 if ((cflag & CSIZE) == CS8) {
710 sSetData8(cp);
711 bits = 10;
712 } else {
713 sSetData7(cp);
714 bits = 9;
715 }
716 if (cflag & CSTOPB) {
717 sSetStop2(cp);
718 bits++;
719 } else {
720 sSetStop1(cp);
721 }
722
723 if (cflag & PARENB) {
724 sEnParity(cp);
725 bits++;
726 if (cflag & PARODD) {
727 sSetOddParity(cp);
728 } else {
729 sSetEvenParity(cp);
730 }
731 } else {
732 sDisParity(cp);
733 }
734
735 /* baud rate */
47b01b3a 736 baud = tty_get_baud_rate(tty);
1da177e4
LT		 737 if (!baud)
738 baud = 9600;
739 divisor = ((rp_baud_base[info->board] + (baud >> 1)) / baud) - 1;
740 if ((divisor >= 8192 || divisor < 0) && old_termios) {
6df3526b 741 baud = tty_termios_baud_rate(old_termios);
1da177e4
LT		 742 if (!baud)
743 baud = 9600;
744 divisor = (rp_baud_base[info->board] / baud) - 1;
745 }
746 if (divisor >= 8192 || divisor < 0) {
747 baud = 9600;
748 divisor = (rp_baud_base[info->board] / baud) - 1;
749 }
750 info->cps = baud / bits;
751 sSetBaud(cp, divisor);
752
6df3526b 753 /* FIXME: Should really back compute a baud rate from the divisor */
47b01b3a 754 tty_encode_baud_rate(tty, baud, baud);
6df3526b 755
1da177e4
LT		 756 if (cflag & CRTSCTS) {
757 info->intmask |= DELTA_CTS;
758 sEnCTSFlowCtl(cp);
759 } else {
760 info->intmask &= ~DELTA_CTS;
761 sDisCTSFlowCtl(cp);
762 }
763 if (cflag & CLOCAL) {
764 info->intmask &= ~DELTA_CD;
765 } else {
766 spin_lock_irqsave(&info->slock, flags);
767 if (sGetChanStatus(cp) & CD_ACT)
768 info->cd_status = 1;
769 else
770 info->cd_status = 0;
771 info->intmask |= DELTA_CD;
772 spin_unlock_irqrestore(&info->slock, flags);
773 }
774
775 /*
776 * Handle software flow control in the board
777 */
778#ifdef ROCKET_SOFT_FLOW
47b01b3a 779 if (I_IXON(tty)) {
1da177e4 780 sEnTxSoftFlowCtl(cp);
47b01b3a 781 if (I_IXANY(tty)) {
1da177e4
LT		 782 sEnIXANY(cp);
783 } else {
784 sDisIXANY(cp);
785 }
47b01b3a
AC		 786 sSetTxXONChar(cp, START_CHAR(tty));
787 sSetTxXOFFChar(cp, STOP_CHAR(tty));
1da177e4
LT		 788 } else {
789 sDisTxSoftFlowCtl(cp);
790 sDisIXANY(cp);
791 sClrTxXOFF(cp);
792 }
793#endif
794
795 /*
796 * Set up ignore/read mask words
797 */
798 info->read_status_mask = STMRCVROVRH | 0xFF;
47b01b3a 799 if (I_INPCK(tty))
1da177e4 800 info->read_status_mask |= STMFRAMEH | STMPARITYH;
47b01b3a 801 if (I_BRKINT(tty) || I_PARMRK(tty))
1da177e4
LT		 802 info->read_status_mask |= STMBREAKH;
803
804 /*
805 * Characters to ignore
806 */
807 info->ignore_status_mask = 0;
47b01b3a 808 if (I_IGNPAR(tty))
1da177e4 809 info->ignore_status_mask |= STMFRAMEH | STMPARITYH;
47b01b3a 810 if (I_IGNBRK(tty)) {
1da177e4
LT		 811 info->ignore_status_mask |= STMBREAKH;
812 /*
813 * If we're ignoring parity and break indicators,
814 * ignore overruns too. (For real raw support).
815 */
47b01b3a 816 if (I_IGNPAR(tty))
1da177e4
LT		 817 info->ignore_status_mask |= STMRCVROVRH;
818 }
819
820 rocketMode = info->flags & ROCKET_MODE_MASK;
821
822 if ((info->flags & ROCKET_RTS_TOGGLE)
823 || (rocketMode == ROCKET_MODE_RS485))
824 sEnRTSToggle(cp);
825 else
826 sDisRTSToggle(cp);
827
828 sSetRTS(&info->channel);
829
830 if (cp->CtlP->boardType == ROCKET_TYPE_PC104) {
831 switch (rocketMode) {
832 case ROCKET_MODE_RS485:
833 sSetInterfaceMode(cp, InterfaceModeRS485);
834 break;
835 case ROCKET_MODE_RS422:
836 sSetInterfaceMode(cp, InterfaceModeRS422);
837 break;
838 case ROCKET_MODE_RS232:
839 default:
840 if (info->flags & ROCKET_RTS_TOGGLE)
841 sSetInterfaceMode(cp, InterfaceModeRS232T);
842 else
843 sSetInterfaceMode(cp, InterfaceModeRS232);
844 break;
845 }
846 }
847}
848
31f35939
AC		 849static int carrier_raised(struct tty_port *port)
850{
851 struct r_port *info = container_of(port, struct r_port, port);
852 return (sGetChanStatusLo(&info->channel) & CD_ACT) ? 1 : 0;
853}
854
fcc8ac18 855static void dtr_rts(struct tty_port *port, int on)
5d951fb4
AC		 856{
857 struct r_port *info = container_of(port, struct r_port, port);
fcc8ac18
AC		 858 if (on) {
859 sSetDTR(&info->channel);
860 sSetRTS(&info->channel);
861 } else {
862 sClrDTR(&info->channel);
863 sClrRTS(&info->channel);
864 }
5d951fb4
AC		 865}
866
1da177e4
LT		 867/*
868 * Exception handler that opens a serial port. Creates xmit_buf storage, fills in
869 * port's r_port struct. Initializes the port hardware.
870 */
871static int rp_open(struct tty_struct *tty, struct file *filp)
872{
873 struct r_port *info;
fba85e01 874 struct tty_port *port;
410235fd 875 int retval;
1da177e4
LT		 876 CHANNEL_t *cp;
877 unsigned long page;
878
410235fd
JS		 879 info = rp_table[tty->index];
880 if (info == NULL)
1da177e4 881 return -ENXIO;
fba85e01
AC		 882 port = &info->port;
883
1da177e4
LT		 884 page = __get_free_page(GFP_KERNEL);
885 if (!page)
886 return -ENOMEM;
887
1da177e4
LT		 888 /*
889 * We must not sleep from here until the port is marked fully in use.
890 */
891 if (info->xmit_buf)
892 free_page(page);
893 else
894 info->xmit_buf = (unsigned char *) page;
895
896 tty->driver_data = info;
fba85e01 897 tty_port_tty_set(port, tty);
1da177e4 898
fba85e01 899 if (port->count++ == 0) {
1da177e4
LT		 900 atomic_inc(&rp_num_ports_open);
901
902#ifdef ROCKET_DEBUG_OPEN
68562b79
JS		 903 printk(KERN_INFO "rocket mod++ = %d...\n",
904 atomic_read(&rp_num_ports_open));
1da177e4
LT		 905#endif
906 }
907#ifdef ROCKET_DEBUG_OPEN
e60a1084 908 printk(KERN_INFO "rp_open ttyR%d, count=%d\n", info->line, info->port.count);
1da177e4
LT		 909#endif
910
911 /*
912 * Info->count is now 1; so it's safe to sleep now.
913 */
d41861ca 914 if (!tty_port_initialized(port)) {
1da177e4
LT		 915 cp = &info->channel;
916 sSetRxTrigger(cp, TRIG_1);
917 if (sGetChanStatus(cp) & CD_ACT)
918 info->cd_status = 1;
919 else
920 info->cd_status = 0;
921 sDisRxStatusMode(cp);
922 sFlushRxFIFO(cp);
923 sFlushTxFIFO(cp);
924
925 sEnInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
926 sSetRxTrigger(cp, TRIG_1);
927
928 sGetChanStatus(cp);
929 sDisRxStatusMode(cp);
930 sClrTxXOFF(cp);
931
932 sDisCTSFlowCtl(cp);
933 sDisTxSoftFlowCtl(cp);
934
935 sEnRxFIFO(cp);
936 sEnTransmit(cp);
937
d41861ca 938 tty_port_set_initialized(&info->port, 1);
1da177e4 939
47b01b3a 940 configure_r_port(tty, info, NULL);
9db276f8 941 if (C_BAUD(tty)) {
1da177e4
LT		 942 sSetDTR(cp);
943 sSetRTS(cp);
944 }
945 }
946 /* Starts (or resets) the maint polling loop */
947 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
948
fba85e01 949 retval = tty_port_block_til_ready(port, tty, filp);
1da177e4
LT		 950 if (retval) {
951#ifdef ROCKET_DEBUG_OPEN
952 printk(KERN_INFO "rp_open returning after block_til_ready with %d\n", retval);
953#endif
954 return retval;
955 }
956 return 0;
957}
958
959/*
e60a1084 960 * Exception handler that closes a serial port. info->port.count is considered critical.
1da177e4
LT		 961 */
962static void rp_close(struct tty_struct *tty, struct file *filp)
963{
c9f19e96 964 struct r_port *info = tty->driver_data;
c1314a49 965 struct tty_port *port = &info->port;
1da177e4
LT		 966 int timeout;
967 CHANNEL_t *cp;
968
969 if (rocket_paranoia_check(info, "rp_close"))
970 return;
971
972#ifdef ROCKET_DEBUG_OPEN
e60a1084 973 printk(KERN_INFO "rp_close ttyR%d, count = %d\n", info->line, info->port.count);
1da177e4
LT		 974#endif
975
fba85e01 976 if (tty_port_close_start(port, tty, filp) == 0)
1da177e4 977 return;
1da177e4 978
417b6e0e 979 mutex_lock(&port->mutex);
1da177e4 980 cp = &info->channel;
1da177e4
LT		 981 /*
982 * Before we drop DTR, make sure the UART transmitter
983 * has completely drained; this is especially
984 * important if there is a transmit FIFO!
985 */
986 timeout = (sGetTxCnt(cp) + 1) * HZ / info->cps;
987 if (timeout == 0)
988 timeout = 1;
989 rp_wait_until_sent(tty, timeout);
990 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
991
992 sDisTransmit(cp);
993 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
994 sDisCTSFlowCtl(cp);
995 sDisTxSoftFlowCtl(cp);
996 sClrTxXOFF(cp);
997 sFlushRxFIFO(cp);
998 sFlushTxFIFO(cp);
999 sClrRTS(cp);
1000 if (C_HUPCL(tty))
1001 sClrDTR(cp);
1002
f6de0c98 1003 rp_flush_buffer(tty);
1da177e4
LT		 1004
1005 tty_ldisc_flush(tty);
1006
1007 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1008
fba85e01
AC		 1009 /* We can't yet use tty_port_close_end as the buffer handling in this
1010 driver is a bit different to the usual */
1011
c1314a49
AC		 1012 if (port->blocked_open) {
1013 if (port->close_delay) {
1014 msleep_interruptible(jiffies_to_msecs(port->close_delay));
1da177e4 1015 }
c1314a49 1016 wake_up_interruptible(&port->open_wait);
1da177e4
LT		 1017 } else {
1018 if (info->xmit_buf) {
1019 free_page((unsigned long) info->xmit_buf);
1020 info->xmit_buf = NULL;
1021 }
1022 }
417b6e0e 1023 spin_lock_irq(&port->lock);
1da177e4 1024 tty->closing = 0;
417b6e0e 1025 spin_unlock_irq(&port->lock);
d41861ca 1026 tty_port_set_initialized(port, 0);
807c8d81 1027 tty_port_set_active(port, 0);
417b6e0e 1028 mutex_unlock(&port->mutex);
fba85e01 1029 tty_port_tty_set(port, NULL);
417b6e0e 1030
1da177e4
LT		 1031 atomic_dec(&rp_num_ports_open);
1032
1033#ifdef ROCKET_DEBUG_OPEN
68562b79
JS		 1034 printk(KERN_INFO "rocket mod-- = %d...\n",
1035 atomic_read(&rp_num_ports_open));
1da177e4
LT		 1036 printk(KERN_INFO "rp_close ttyR%d complete shutdown\n", info->line);
1037#endif
1038
1039}
1040
1041static void rp_set_termios(struct tty_struct *tty,
606d099c 1042 struct ktermios *old_termios)
1da177e4 1043{
c9f19e96 1044 struct r_port *info = tty->driver_data;
1da177e4
LT		 1045 CHANNEL_t *cp;
1046 unsigned cflag;
1047
1048 if (rocket_paranoia_check(info, "rp_set_termios"))
1049 return;
1050
adc8d746 1051 cflag = tty->termios.c_cflag;
1da177e4 1052
1da177e4
LT		 1053 /*
1054 * This driver doesn't support CS5 or CS6
1055 */
1056 if (((cflag & CSIZE) == CS5) || ((cflag & CSIZE) == CS6))
adc8d746 1057 tty->termios.c_cflag =
1da177e4 1058 ((cflag & ~CSIZE) | (old_termios->c_cflag & CSIZE));
6df3526b 1059 /* Or CMSPAR */
adc8d746 1060 tty->termios.c_cflag &= ~CMSPAR;
1da177e4 1061
47b01b3a 1062 configure_r_port(tty, info, old_termios);
1da177e4
LT		 1063
1064 cp = &info->channel;
1065
1066 /* Handle transition to B0 status */
9db276f8 1067 if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
1da177e4
LT		 1068 sClrDTR(cp);
1069 sClrRTS(cp);
1070 }
1071
1072 /* Handle transition away from B0 status */
9db276f8 1073 if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
ee797069 1074 sSetRTS(cp);
1da177e4
LT		 1075 sSetDTR(cp);
1076 }
1077
9db276f8 1078 if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty))
1da177e4 1079 rp_start(tty);
1da177e4
LT		 1080}
1081
9e98966c 1082static int rp_break(struct tty_struct *tty, int break_state)
1da177e4 1083{
c9f19e96 1084 struct r_port *info = tty->driver_data;
1da177e4
LT		 1085 unsigned long flags;
1086
1087 if (rocket_paranoia_check(info, "rp_break"))
9e98966c 1088 return -EINVAL;
1da177e4
LT		 1089
1090 spin_lock_irqsave(&info->slock, flags);
1091 if (break_state == -1)
1092 sSendBreak(&info->channel);
1093 else
1094 sClrBreak(&info->channel);
1095 spin_unlock_irqrestore(&info->slock, flags);
9e98966c 1096 return 0;
1da177e4
LT		 1097}
1098
1099/*
1100 * sGetChanRI used to be a macro in rocket_int.h. When the functionality for
1101 * the UPCI boards was added, it was decided to make this a function because
1102 * the macro was getting too complicated. All cases except the first one
1103 * (UPCIRingInd) are taken directly from the original macro.
1104 */
1105static int sGetChanRI(CHANNEL_T * ChP)
1106{
1107 CONTROLLER_t *CtlP = ChP->CtlP;
1108 int ChanNum = ChP->ChanNum;
1109 int RingInd = 0;
1110
1111 if (CtlP->UPCIRingInd)
1112 RingInd = !(sInB(CtlP->UPCIRingInd) & sBitMapSetTbl[ChanNum]);
1113 else if (CtlP->AltChanRingIndicator)
1114 RingInd = sInB((ByteIO_t) (ChP->ChanStat + 8)) & DSR_ACT;
1115 else if (CtlP->boardType == ROCKET_TYPE_PC104)
1116 RingInd = !(sInB(CtlP->AiopIO[3]) & sBitMapSetTbl[ChanNum]);
1117
1118 return RingInd;
1119}
1120
1121/********************************************************************************************/
1122/* Here are the routines used by rp_ioctl. These are all called from exception handlers. */
1123
1124/*
1125 * Returns the state of the serial modem control lines. These next 2 functions
1126 * are the way kernel versions > 2.5 handle modem control lines rather than IOCTLs.
1127 */
60b33c13 1128static int rp_tiocmget(struct tty_struct *tty)
1da177e4 1129{
c9f19e96 1130 struct r_port *info = tty->driver_data;
1da177e4
LT		 1131 unsigned int control, result, ChanStatus;
1132
1133 ChanStatus = sGetChanStatusLo(&info->channel);
1134 control = info->channel.TxControl[3];
1135 result = ((control & SET_RTS) ? TIOCM_RTS : 0) |
1136 ((control & SET_DTR) ? TIOCM_DTR : 0) |
1137 ((ChanStatus & CD_ACT) ? TIOCM_CAR : 0) |
1138 (sGetChanRI(&info->channel) ? TIOCM_RNG : 0) |
1139 ((ChanStatus & DSR_ACT) ? TIOCM_DSR : 0) |
1140 ((ChanStatus & CTS_ACT) ? TIOCM_CTS : 0);
1141
1142 return result;
1143}
1144
1145/*
1146 * Sets the modem control lines
1147 */
20b9d177
AC		 1148static int rp_tiocmset(struct tty_struct *tty,
1149 unsigned int set, unsigned int clear)
1da177e4 1150{
c9f19e96 1151 struct r_port *info = tty->driver_data;
1da177e4
LT		 1152
1153 if (set & TIOCM_RTS)
1154 info->channel.TxControl[3] |= SET_RTS;
1155 if (set & TIOCM_DTR)
1156 info->channel.TxControl[3] |= SET_DTR;
1157 if (clear & TIOCM_RTS)
1158 info->channel.TxControl[3] &= ~SET_RTS;
1159 if (clear & TIOCM_DTR)
1160 info->channel.TxControl[3] &= ~SET_DTR;
1161
457fb605 1162 out32(info->channel.IndexAddr, info->channel.TxControl);
1da177e4
LT		 1163 return 0;
1164}
1165
1166static int get_config(struct r_port *info, struct rocket_config __user *retinfo)
1167{
1168 struct rocket_config tmp;
1169
1da177e4 1170 memset(&tmp, 0, sizeof (tmp));
417b6e0e 1171 mutex_lock(&info->port.mutex);
1da177e4
LT		 1172 tmp.line = info->line;
1173 tmp.flags = info->flags;
44b7d1b3
AC		 1174 tmp.close_delay = info->port.close_delay;
1175 tmp.closing_wait = info->port.closing_wait;
1da177e4 1176 tmp.port = rcktpt_io_addr[(info->line >> 5) & 3];
417b6e0e 1177 mutex_unlock(&info->port.mutex);
1da177e4
LT		 1178
1179 if (copy_to_user(retinfo, &tmp, sizeof (*retinfo)))
1180 return -EFAULT;
1181 return 0;
1182}
1183
47b01b3a
AC		 1184static int set_config(struct tty_struct *tty, struct r_port *info,
1185 struct rocket_config __user *new_info)
1da177e4
LT		 1186{
1187 struct rocket_config new_serial;
1188
1189 if (copy_from_user(&new_serial, new_info, sizeof (new_serial)))
1190 return -EFAULT;
1191
417b6e0e 1192 mutex_lock(&info->port.mutex);
1da177e4
LT		 1193 if (!capable(CAP_SYS_ADMIN))
1194 {
417b6e0e
AC		 1195 if ((new_serial.flags & ~ROCKET_USR_MASK) != (info->flags & ~ROCKET_USR_MASK)) {
1196 mutex_unlock(&info->port.mutex);
1da177e4 1197 return -EPERM;
417b6e0e 1198 }
1da177e4 1199 info->flags = ((info->flags & ~ROCKET_USR_MASK) | (new_serial.flags & ROCKET_USR_MASK));
49bf7eaf 1200 mutex_unlock(&info->port.mutex);
1da177e4
LT		 1201 return 0;
1202 }
1203
48a7bd11
JH		 1204 if ((new_serial.flags ^ info->flags) & ROCKET_SPD_MASK) {
1205 /* warn about deprecation, unless clearing */
1206 if (new_serial.flags & ROCKET_SPD_MASK)
1207 dev_warn_ratelimited(tty->dev, "use of SPD flags is deprecated\n");
1208 }
1209
1da177e4 1210 info->flags = ((info->flags & ~ROCKET_FLAGS) | (new_serial.flags & ROCKET_FLAGS));
44b7d1b3
AC		 1211 info->port.close_delay = new_serial.close_delay;
1212 info->port.closing_wait = new_serial.closing_wait;
1da177e4 1213
417b6e0e 1214 mutex_unlock(&info->port.mutex);
1da177e4 1215
47b01b3a 1216 configure_r_port(tty, info, NULL);
1da177e4
LT		 1217 return 0;
1218}
1219
1220/*
1221 * This function fills in a rocket_ports struct with information
1222 * about what boards/ports are in the system. This info is passed
1223 * to user space. See setrocket.c where the info is used to create
1224 * the /dev/ttyRx ports.
1225 */
1226static int get_ports(struct r_port *info, struct rocket_ports __user *retports)
1227{
4d2c82b1
SM		 1228 struct rocket_ports *tmp;
1229 int board, ret = 0;
1da177e4 1230
4d2c82b1
SM		 1231 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
1232 if (!tmp)
1233 return -ENOMEM;
1234
1235 tmp->tty_major = rocket_driver->major;
1da177e4
LT		 1236
1237 for (board = 0; board < 4; board++) {
4d2c82b1
SM		 1238 tmp->rocketModel[board].model = rocketModel[board].model;
1239 strcpy(tmp->rocketModel[board].modelString,
1240 rocketModel[board].modelString);
1241 tmp->rocketModel[board].numPorts = rocketModel[board].numPorts;
1242 tmp->rocketModel[board].loadrm2 = rocketModel[board].loadrm2;
1243 tmp->rocketModel[board].startingPortNumber =
1244 rocketModel[board].startingPortNumber;
1da177e4 1245 }
4d2c82b1
SM		 1246 if (copy_to_user(retports, tmp, sizeof(*retports)))
1247 ret = -EFAULT;
1248 kfree(tmp);
1249 return ret;
1da177e4
LT		 1250}
1251
1252static int reset_rm2(struct r_port *info, void __user *arg)
1253{
1254 int reset;
1255
4129a645
AC		 1256 if (!capable(CAP_SYS_ADMIN))
1257 return -EPERM;
1258
1da177e4
LT		 1259 if (copy_from_user(&reset, arg, sizeof (int)))
1260 return -EFAULT;
1261 if (reset)
1262 reset = 1;
1263
1264 if (rcktpt_type[info->board] != ROCKET_TYPE_MODEMII &&
1265 rcktpt_type[info->board] != ROCKET_TYPE_MODEMIII)
1266 return -EINVAL;
1267
1268 if (info->ctlp->BusType == isISA)
1269 sModemReset(info->ctlp, info->chan, reset);
1270 else
1271 sPCIModemReset(info->ctlp, info->chan, reset);
1272
1273 return 0;
1274}
1275
1276static int get_version(struct r_port *info, struct rocket_version __user *retvers)
1277{
1278 if (copy_to_user(retvers, &driver_version, sizeof (*retvers)))
1279 return -EFAULT;
1280 return 0;
1281}
1282
1283/* IOCTL call handler into the driver */
6caa76b7 1284static int rp_ioctl(struct tty_struct *tty,
1da177e4
LT		 1285 unsigned int cmd, unsigned long arg)
1286{
c9f19e96 1287 struct r_port *info = tty->driver_data;
1da177e4 1288 void __user *argp = (void __user *)arg;
bdf183aa 1289 int ret = 0;
1da177e4
LT		 1290
1291 if (cmd != RCKP_GET_PORTS && rocket_paranoia_check(info, "rp_ioctl"))
1292 return -ENXIO;
1293
1294 switch (cmd) {
1da177e4 1295 case RCKP_GET_CONFIG:
8ef79565
FH		 1296 dev_warn_ratelimited(tty->dev,
1297 "RCKP_GET_CONFIG option is deprecated\n");
bdf183aa
AC		 1298 ret = get_config(info, argp);
1299 break;
1da177e4 1300 case RCKP_SET_CONFIG:
8ef79565
FH		 1301 dev_warn_ratelimited(tty->dev,
1302 "RCKP_SET_CONFIG option is deprecated\n");
47b01b3a 1303 ret = set_config(tty, info, argp);
bdf183aa 1304 break;
1da177e4 1305 case RCKP_GET_PORTS:
8ef79565
FH		 1306 dev_warn_ratelimited(tty->dev,
1307 "RCKP_GET_PORTS option is deprecated\n");
bdf183aa
AC		 1308 ret = get_ports(info, argp);
1309 break;
1da177e4 1310 case RCKP_RESET_RM2:
8ef79565
FH		 1311 dev_warn_ratelimited(tty->dev,
1312 "RCKP_RESET_RM2 option is deprecated\n");
bdf183aa
AC		 1313 ret = reset_rm2(info, argp);
1314 break;
1da177e4 1315 case RCKP_GET_VERSION:
8ef79565
FH		 1316 dev_warn_ratelimited(tty->dev,
1317 "RCKP_GET_VERSION option is deprecated\n");
bdf183aa
AC		 1318 ret = get_version(info, argp);
1319 break;
1da177e4 1320 default:
bdf183aa 1321 ret = -ENOIOCTLCMD;
1da177e4 1322 }
bdf183aa 1323 return ret;
1da177e4
LT		 1324}
1325
1326static void rp_send_xchar(struct tty_struct *tty, char ch)
1327{
c9f19e96 1328 struct r_port *info = tty->driver_data;
1da177e4
LT		 1329 CHANNEL_t *cp;
1330
1331 if (rocket_paranoia_check(info, "rp_send_xchar"))
1332 return;
1333
1334 cp = &info->channel;
1335 if (sGetTxCnt(cp))
1336 sWriteTxPrioByte(cp, ch);
1337 else
1338 sWriteTxByte(sGetTxRxDataIO(cp), ch);
1339}
1340
1341static void rp_throttle(struct tty_struct *tty)
1342{
c9f19e96 1343 struct r_port *info = tty->driver_data;
1da177e4
LT		 1344
1345#ifdef ROCKET_DEBUG_THROTTLE
fdfb719e 1346 printk(KERN_INFO "throttle %s ....\n", tty->name);
1da177e4
LT		 1347#endif
1348
1349 if (rocket_paranoia_check(info, "rp_throttle"))
1350 return;
1351
1da177e4
LT		 1352 if (I_IXOFF(tty))
1353 rp_send_xchar(tty, STOP_CHAR(tty));
1354
1355 sClrRTS(&info->channel);
1356}
1357
1358static void rp_unthrottle(struct tty_struct *tty)
1359{
c9f19e96 1360 struct r_port *info = tty->driver_data;
1da177e4 1361#ifdef ROCKET_DEBUG_THROTTLE
fdfb719e 1362 printk(KERN_INFO "unthrottle %s ....\n", tty->name);
1da177e4
LT		 1363#endif
1364
e5f50fbe 1365 if (rocket_paranoia_check(info, "rp_unthrottle"))
1da177e4
LT		 1366 return;
1367
1da177e4
LT		 1368 if (I_IXOFF(tty))
1369 rp_send_xchar(tty, START_CHAR(tty));
1370
1371 sSetRTS(&info->channel);
1372}
1373
1374/*
1375 * ------------------------------------------------------------
1376 * rp_stop() and rp_start()
1377 *
1378 * This routines are called before setting or resetting tty->stopped.
1379 * They enable or disable transmitter interrupts, as necessary.
1380 * ------------------------------------------------------------
1381 */
1382static void rp_stop(struct tty_struct *tty)
1383{
c9f19e96 1384 struct r_port *info = tty->driver_data;
1da177e4
LT		 1385
1386#ifdef ROCKET_DEBUG_FLOW
1387 printk(KERN_INFO "stop %s: %d %d....\n", tty->name,
1388 info->xmit_cnt, info->xmit_fifo_room);
1389#endif
1390
1391 if (rocket_paranoia_check(info, "rp_stop"))
1392 return;
1393
1394 if (sGetTxCnt(&info->channel))
1395 sDisTransmit(&info->channel);
1396}
1397
1398static void rp_start(struct tty_struct *tty)
1399{
c9f19e96 1400 struct r_port *info = tty->driver_data;
1da177e4
LT		 1401
1402#ifdef ROCKET_DEBUG_FLOW
1403 printk(KERN_INFO "start %s: %d %d....\n", tty->name,
1404 info->xmit_cnt, info->xmit_fifo_room);
1405#endif
1406
1407 if (rocket_paranoia_check(info, "rp_stop"))
1408 return;
1409
1410 sEnTransmit(&info->channel);
1411 set_bit((info->aiop * 8) + info->chan,
1412 (void *) &xmit_flags[info->board]);
1413}
1414
1415/*
1416 * rp_wait_until_sent() --- wait until the transmitter is empty
1417 */
1418static void rp_wait_until_sent(struct tty_struct *tty, int timeout)
1419{
c9f19e96 1420 struct r_port *info = tty->driver_data;
1da177e4
LT		 1421 CHANNEL_t *cp;
1422 unsigned long orig_jiffies;
1423 int check_time, exit_time;
1424 int txcnt;
1425
1426 if (rocket_paranoia_check(info, "rp_wait_until_sent"))
1427 return;
1428
1429 cp = &info->channel;
1430
1431 orig_jiffies = jiffies;
1432#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
e5f50fbe 1433 printk(KERN_INFO "In %s(%d) (jiff=%lu)...\n", __func__, timeout,
1da177e4 1434 jiffies);
68562b79 1435 printk(KERN_INFO "cps=%d...\n", info->cps);
1da177e4
LT		 1436#endif
1437 while (1) {
1438 txcnt = sGetTxCnt(cp);
1439 if (!txcnt) {
1440 if (sGetChanStatusLo(cp) & TXSHRMT)
1441 break;
1442 check_time = (HZ / info->cps) / 5;
1443 } else {
1444 check_time = HZ * txcnt / info->cps;
1445 }
1446 if (timeout) {
1447 exit_time = orig_jiffies + timeout - jiffies;
1448 if (exit_time <= 0)
1449 break;
1450 if (exit_time < check_time)
1451 check_time = exit_time;
1452 }
1453 if (check_time == 0)
1454 check_time = 1;
1455#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
68562b79
JS		 1456 printk(KERN_INFO "txcnt = %d (jiff=%lu,check=%d)...\n", txcnt,
1457 jiffies, check_time);
1da177e4
LT		 1458#endif
1459 msleep_interruptible(jiffies_to_msecs(check_time));
1460 if (signal_pending(current))
1461 break;
1462 }
cc0a8fbb 1463 __set_current_state(TASK_RUNNING);
1da177e4
LT		 1464#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1465 printk(KERN_INFO "txcnt = %d (jiff=%lu)...done\n", txcnt, jiffies);
1466#endif
1467}
1468
1469/*
1470 * rp_hangup() --- called by tty_hangup() when a hangup is signaled.
1471 */
1472static void rp_hangup(struct tty_struct *tty)
1473{
1474 CHANNEL_t *cp;
c9f19e96 1475 struct r_port *info = tty->driver_data;
417b6e0e 1476 unsigned long flags;
1da177e4
LT		 1477
1478 if (rocket_paranoia_check(info, "rp_hangup"))
1479 return;
1480
1481#if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_HANGUP))
68562b79 1482 printk(KERN_INFO "rp_hangup of ttyR%d...\n", info->line);
1da177e4
LT		 1483#endif
1484 rp_flush_buffer(tty);
417b6e0e 1485 spin_lock_irqsave(&info->port.lock, flags);
e60a1084 1486 if (info->port.count)
1da177e4
LT		 1487 atomic_dec(&rp_num_ports_open);
1488 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
417b6e0e 1489 spin_unlock_irqrestore(&info->port.lock, flags);
1da177e4 1490
fba85e01 1491 tty_port_hangup(&info->port);
1da177e4
LT		 1492
1493 cp = &info->channel;
1494 sDisRxFIFO(cp);
1495 sDisTransmit(cp);
1496 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1497 sDisCTSFlowCtl(cp);
1498 sDisTxSoftFlowCtl(cp);
1499 sClrTxXOFF(cp);
d41861ca 1500 tty_port_set_initialized(&info->port, 0);
1da177e4 1501
e60a1084 1502 wake_up_interruptible(&info->port.open_wait);
1da177e4
LT		 1503}
1504
1505/*
1506 * Exception handler - write char routine. The RocketPort driver uses a
1507 * double-buffering strategy, with the twist that if the in-memory CPU
1508 * buffer is empty, and there's space in the transmit FIFO, the
1509 * writing routines will write directly to transmit FIFO.
1510 * Write buffer and counters protected by spinlocks
1511 */
bbbbb96f 1512static int rp_put_char(struct tty_struct *tty, unsigned char ch)
1da177e4 1513{
c9f19e96 1514 struct r_port *info = tty->driver_data;
1da177e4
LT		 1515 CHANNEL_t *cp;
1516 unsigned long flags;
1517
1518 if (rocket_paranoia_check(info, "rp_put_char"))
bbbbb96f 1519 return 0;
1da177e4 1520
69f545ea
MK		 1521 /*
1522 * Grab the port write mutex, locking out other processes that try to
1523 * write to this port
1524 */
1525 mutex_lock(&info->write_mtx);
1da177e4
LT		 1526
1527#ifdef ROCKET_DEBUG_WRITE
68562b79 1528 printk(KERN_INFO "rp_put_char %c...\n", ch);
1da177e4
LT		 1529#endif
1530
1531 spin_lock_irqsave(&info->slock, flags);
1532 cp = &info->channel;
1533
ee797069 1534 if (!tty->stopped && info->xmit_fifo_room == 0)
1da177e4
LT		 1535 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1536
ee797069 1537 if (tty->stopped || info->xmit_fifo_room == 0 || info->xmit_cnt != 0) {
1da177e4
LT		 1538 info->xmit_buf[info->xmit_head++] = ch;
1539 info->xmit_head &= XMIT_BUF_SIZE - 1;
1540 info->xmit_cnt++;
1541 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1542 } else {
1543 sOutB(sGetTxRxDataIO(cp), ch);
1544 info->xmit_fifo_room--;
1545 }
1546 spin_unlock_irqrestore(&info->slock, flags);
69f545ea 1547 mutex_unlock(&info->write_mtx);
bbbbb96f 1548 return 1;
1da177e4
LT		 1549}
1550
1551/*
1552 * Exception handler - write routine, called when user app writes to the device.
69f545ea 1553 * A per port write mutex is used to protect from another process writing to
1da177e4
LT		 1554 * this port at the same time. This other process could be running on the other CPU
1555 * or get control of the CPU if the copy_from_user() blocks due to a page fault (swapped out).
1556 * Spinlocks protect the info xmit members.
1557 */
1558static int rp_write(struct tty_struct *tty,
1559 const unsigned char *buf, int count)
1560{
c9f19e96 1561 struct r_port *info = tty->driver_data;
1da177e4
LT		 1562 CHANNEL_t *cp;
1563 const unsigned char *b;
1564 int c, retval = 0;
1565 unsigned long flags;
1566
1567 if (count <= 0 || rocket_paranoia_check(info, "rp_write"))
1568 return 0;
1569
1e3e8d91
SS		 1570 if (mutex_lock_interruptible(&info->write_mtx))
1571 return -ERESTARTSYS;
1da177e4
LT		 1572
1573#ifdef ROCKET_DEBUG_WRITE
68562b79 1574 printk(KERN_INFO "rp_write %d chars...\n", count);
1da177e4
LT		 1575#endif
1576 cp = &info->channel;
1577
ee797069 1578 if (!tty->stopped && info->xmit_fifo_room < count)
1da177e4
LT		 1579 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1580
1581 /*
1582 * If the write queue for the port is empty, and there is FIFO space, stuff bytes
1583 * into FIFO. Use the write queue for temp storage.
1584 */
ee797069 1585 if (!tty->stopped && info->xmit_cnt == 0 && info->xmit_fifo_room > 0) {
1da177e4
LT		 1586 c = min(count, info->xmit_fifo_room);
1587 b = buf;
1588
1589 /* Push data into FIFO, 2 bytes at a time */
1590 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) b, c / 2);
1591
1592 /* If there is a byte remaining, write it */
1593 if (c & 1)
1594 sOutB(sGetTxRxDataIO(cp), b[c - 1]);
1595
1596 retval += c;
1597 buf += c;
1598 count -= c;
1599
1600 spin_lock_irqsave(&info->slock, flags);
1601 info->xmit_fifo_room -= c;
1602 spin_unlock_irqrestore(&info->slock, flags);
1603 }
1604
1605 /* If count is zero, we wrote it all and are done */
1606 if (!count)
1607 goto end;
1608
1609 /* Write remaining data into the port's xmit_buf */
1610 while (1) {
47b01b3a 1611 /* Hung up ? */
807c8d81 1612 if (!tty_port_active(&info->port))
1da177e4 1613 goto end;
709107fc
HH		 1614 c = min(count, XMIT_BUF_SIZE - info->xmit_cnt - 1);
1615 c = min(c, XMIT_BUF_SIZE - info->xmit_head);
1da177e4
LT		 1616 if (c <= 0)
1617 break;
1618
1619 b = buf;
1620 memcpy(info->xmit_buf + info->xmit_head, b, c);
1621
1622 spin_lock_irqsave(&info->slock, flags);
1623 info->xmit_head =
1624 (info->xmit_head + c) & (XMIT_BUF_SIZE - 1);
1625 info->xmit_cnt += c;
1626 spin_unlock_irqrestore(&info->slock, flags);
1627
1628 buf += c;
1629 count -= c;
1630 retval += c;
1631 }
1632
ee797069 1633 if ((retval > 0) && !tty->stopped)
1da177e4
LT		 1634 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1635
1636end:
1637 if (info->xmit_cnt < WAKEUP_CHARS) {
1638 tty_wakeup(tty);
1da177e4
LT		 1639#ifdef ROCKETPORT_HAVE_POLL_WAIT
1640 wake_up_interruptible(&tty->poll_wait);
1641#endif
1642 }
69f545ea 1643 mutex_unlock(&info->write_mtx);
1da177e4
LT		 1644 return retval;
1645}
1646
1647/*
1648 * Return the number of characters that can be sent. We estimate
1649 * only using the in-memory transmit buffer only, and ignore the
1650 * potential space in the transmit FIFO.
1651 */
1652static int rp_write_room(struct tty_struct *tty)
1653{
c9f19e96 1654 struct r_port *info = tty->driver_data;
1da177e4
LT		 1655 int ret;
1656
1657 if (rocket_paranoia_check(info, "rp_write_room"))
1658 return 0;
1659
1660 ret = XMIT_BUF_SIZE - info->xmit_cnt - 1;
1661 if (ret < 0)
1662 ret = 0;
1663#ifdef ROCKET_DEBUG_WRITE
68562b79 1664 printk(KERN_INFO "rp_write_room returns %d...\n", ret);
1da177e4
LT		 1665#endif
1666 return ret;
1667}
1668
1669/*
1670 * Return the number of characters in the buffer. Again, this only
1671 * counts those characters in the in-memory transmit buffer.
1672 */
1673static int rp_chars_in_buffer(struct tty_struct *tty)
1674{
c9f19e96 1675 struct r_port *info = tty->driver_data;
1da177e4
LT		 1676
1677 if (rocket_paranoia_check(info, "rp_chars_in_buffer"))
1678 return 0;
1679
1da177e4 1680#ifdef ROCKET_DEBUG_WRITE
68562b79 1681 printk(KERN_INFO "rp_chars_in_buffer returns %d...\n", info->xmit_cnt);
1da177e4
LT		 1682#endif
1683 return info->xmit_cnt;
1684}
1685
1686/*
1687 * Flushes the TX fifo for a port, deletes data in the xmit_buf stored in the
1688 * r_port struct for the port. Note that spinlock are used to protect info members,
1689 * do not call this function if the spinlock is already held.
1690 */
1691static void rp_flush_buffer(struct tty_struct *tty)
1692{
c9f19e96 1693 struct r_port *info = tty->driver_data;
1da177e4
LT		 1694 CHANNEL_t *cp;
1695 unsigned long flags;
1696
1697 if (rocket_paranoia_check(info, "rp_flush_buffer"))
1698 return;
1699
1700 spin_lock_irqsave(&info->slock, flags);
1701 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1702 spin_unlock_irqrestore(&info->slock, flags);
1703
1da177e4
LT		 1704#ifdef ROCKETPORT_HAVE_POLL_WAIT
1705 wake_up_interruptible(&tty->poll_wait);
1706#endif
1707 tty_wakeup(tty);
1708
1709 cp = &info->channel;
1710 sFlushTxFIFO(cp);
1711}
1712
1713#ifdef CONFIG_PCI
1714
311df74a 1715static const struct pci_device_id rocket_pci_ids[] = {
b9d42395
KC		 1716 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4QUAD) },
1717 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8OCTA) },
1718 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP8OCTA) },
1719 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8INTF) },
1720 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP8INTF) },
1721 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8J) },
1722 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4J) },
1723 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8SNI) },
1724 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP16SNI) },
1725 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP16INTF) },
1726 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP16INTF) },
1727 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_CRP16INTF) },
1728 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP32INTF) },
1729 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP32INTF) },
1730 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RPP4) },
1731 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RPP8) },
1732 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP2_232) },
1733 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP2_422) },
1734 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP6M) },
1735 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4M) },
1736 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_UPCI_RM3_8PORT) },
1737 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_UPCI_RM3_4PORT) },
8d5916d3
JS		 1738 { }
1739};
1740MODULE_DEVICE_TABLE(pci, rocket_pci_ids);
1741
416187ca
JS		 1742/* Resets the speaker controller on RocketModem II and III devices */
1743static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model)
1744{
1745 ByteIO_t addr;
1746
1747 /* RocketModem II speaker control is at the 8th port location of offset 0x40 */
1748 if ((model == MODEL_RP4M) || (model == MODEL_RP6M)) {
1749 addr = CtlP->AiopIO[0] + 0x4F;
1750 sOutB(addr, 0);
1751 }
1752
1753 /* RocketModem III speaker control is at the 1st port location of offset 0x80 */
1754 if ((model == MODEL_UPCI_RM3_8PORT)
1755 || (model == MODEL_UPCI_RM3_4PORT)) {
1756 addr = CtlP->AiopIO[0] + 0x88;
1757 sOutB(addr, 0);
1758 }
1759}
1760
1761/***************************************************************************
1762Function: sPCIInitController
1763Purpose: Initialization of controller global registers and controller
1764 structure.
1765Call: sPCIInitController(CtlP,CtlNum,AiopIOList,AiopIOListSize,
1766 IRQNum,Frequency,PeriodicOnly)
1767 CONTROLLER_T *CtlP; Ptr to controller structure
1768 int CtlNum; Controller number
1769 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
1770 This list must be in the order the AIOPs will be found on the
1771 controller. Once an AIOP in the list is not found, it is
1772 assumed that there are no more AIOPs on the controller.
1773 int AiopIOListSize; Number of addresses in AiopIOList
1774 int IRQNum; Interrupt Request number. Can be any of the following:
1775 0: Disable global interrupts
1776 3: IRQ 3
1777 4: IRQ 4
1778 5: IRQ 5
1779 9: IRQ 9
1780 10: IRQ 10
1781 11: IRQ 11
1782 12: IRQ 12
1783 15: IRQ 15
1784 Byte_t Frequency: A flag identifying the frequency
1785 of the periodic interrupt, can be any one of the following:
1786 FREQ_DIS - periodic interrupt disabled
1787 FREQ_137HZ - 137 Hertz
1788 FREQ_69HZ - 69 Hertz
1789 FREQ_34HZ - 34 Hertz
1790 FREQ_17HZ - 17 Hertz
1791 FREQ_9HZ - 9 Hertz
1792 FREQ_4HZ - 4 Hertz
1793 If IRQNum is set to 0 the Frequency parameter is
1794 overidden, it is forced to a value of FREQ_DIS.
1795 int PeriodicOnly: 1 if all interrupts except the periodic
1796 interrupt are to be blocked.
1797 0 is both the periodic interrupt and
1798 other channel interrupts are allowed.
1799 If IRQNum is set to 0 the PeriodicOnly parameter is
1800 overidden, it is forced to a value of 0.
1801Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
1802 initialization failed.
1803
1804Comments:
1805 If periodic interrupts are to be disabled but AIOP interrupts
1806 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
1807
1808 If interrupts are to be completely disabled set IRQNum to 0.
1809
1810 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
1811 invalid combination.
1812
1813 This function performs initialization of global interrupt modes,
1814 but it does not actually enable global interrupts. To enable
1815 and disable global interrupts use functions sEnGlobalInt() and
1816 sDisGlobalInt(). Enabling of global interrupts is normally not
1817 done until all other initializations are complete.
1818
1819 Even if interrupts are globally enabled, they must also be
1820 individually enabled for each channel that is to generate
1821 interrupts.
1822
1823Warnings: No range checking on any of the parameters is done.
1824
1825 No context switches are allowed while executing this function.
1826
1827 After this function all AIOPs on the controller are disabled,
1828 they can be enabled with sEnAiop().
1829*/
1830static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
1831 ByteIO_t * AiopIOList, int AiopIOListSize,
1832 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
1833 int PeriodicOnly, int altChanRingIndicator,
1834 int UPCIRingInd)
1835{
1836 int i;
1837 ByteIO_t io;
1838
1839 CtlP->AltChanRingIndicator = altChanRingIndicator;
1840 CtlP->UPCIRingInd = UPCIRingInd;
1841 CtlP->CtlNum = CtlNum;
1842 CtlP->CtlID = CTLID_0001; /* controller release 1 */
1843 CtlP->BusType = isPCI; /* controller release 1 */
1844
1845 if (ConfigIO) {
1846 CtlP->isUPCI = 1;
1847 CtlP->PCIIO = ConfigIO + _PCI_9030_INT_CTRL;
1848 CtlP->PCIIO2 = ConfigIO + _PCI_9030_GPIO_CTRL;
1849 CtlP->AiopIntrBits = upci_aiop_intr_bits;
1850 } else {
1851 CtlP->isUPCI = 0;
1852 CtlP->PCIIO =
1853 (WordIO_t) ((ByteIO_t) AiopIOList[0] + _PCI_INT_FUNC);
1854 CtlP->AiopIntrBits = aiop_intr_bits;
1855 }
1856
1857 sPCIControllerEOI(CtlP); /* clear EOI if warm init */
1858 /* Init AIOPs */
1859 CtlP->NumAiop = 0;
1860 for (i = 0; i < AiopIOListSize; i++) {
1861 io = AiopIOList[i];
1862 CtlP->AiopIO[i] = (WordIO_t) io;
1863 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
1864
1865 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
1866 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
1867 break; /* done looking for AIOPs */
1868
1869 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
1870 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
1871 sOutB(io + _INDX_DATA, sClockPrescale);
1872 CtlP->NumAiop++; /* bump count of AIOPs */
1873 }
1874
1875 if (CtlP->NumAiop == 0)
1876 return (-1);
1877 else
1878 return (CtlP->NumAiop);
1879}
1880
1da177e4
LT		 1881/*
1882 * Called when a PCI card is found. Retrieves and stores model information,
1883 * init's aiopic and serial port hardware.
1884 * Inputs: i is the board number (0-n)
1885 */
f15313bf 1886static __init int register_PCI(int i, struct pci_dev *dev)
1da177e4
LT		 1887{
1888 int num_aiops, aiop, max_num_aiops, num_chan, chan;
1889 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
1da177e4
LT		 1890 CONTROLLER_t *ctlp;
1891
1892 int fast_clock = 0;
1893 int altChanRingIndicator = 0;
1894 int ports_per_aiop = 8;
1da177e4
LT		 1895 WordIO_t ConfigIO = 0;
1896 ByteIO_t UPCIRingInd = 0;
1897
b9d42395 1898 if (!dev || !pci_match_id(rocket_pci_ids, dev) ||
0419056e 1899 pci_enable_device(dev) || i >= NUM_BOARDS)
1da177e4
LT		 1900 return 0;
1901
1902 rcktpt_io_addr[i] = pci_resource_start(dev, 0);
1da177e4
LT		 1903
1904 rcktpt_type[i] = ROCKET_TYPE_NORMAL;
1905 rocketModel[i].loadrm2 = 0;
1906 rocketModel[i].startingPortNumber = nextLineNumber;
1907
1908 /* Depending on the model, set up some config variables */
1909 switch (dev->device) {
1910 case PCI_DEVICE_ID_RP4QUAD:
1da177e4
LT		 1911 max_num_aiops = 1;
1912 ports_per_aiop = 4;
1913 rocketModel[i].model = MODEL_RP4QUAD;
1914 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/quad cable");
1915 rocketModel[i].numPorts = 4;
1916 break;
1917 case PCI_DEVICE_ID_RP8OCTA:
1da177e4
LT		 1918 max_num_aiops = 1;
1919 rocketModel[i].model = MODEL_RP8OCTA;
1920 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/octa cable");
1921 rocketModel[i].numPorts = 8;
1922 break;
1923 case PCI_DEVICE_ID_URP8OCTA:
1da177e4
LT		 1924 max_num_aiops = 1;
1925 rocketModel[i].model = MODEL_UPCI_RP8OCTA;
1926 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/octa cable");
1927 rocketModel[i].numPorts = 8;
1928 break;
1929 case PCI_DEVICE_ID_RP8INTF:
1da177e4
LT		 1930 max_num_aiops = 1;
1931 rocketModel[i].model = MODEL_RP8INTF;
1932 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/external I/F");
1933 rocketModel[i].numPorts = 8;
1934 break;
1935 case PCI_DEVICE_ID_URP8INTF:
1da177e4
LT		 1936 max_num_aiops = 1;
1937 rocketModel[i].model = MODEL_UPCI_RP8INTF;
1938 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/external I/F");
1939 rocketModel[i].numPorts = 8;
1940 break;
1941 case PCI_DEVICE_ID_RP8J:
1da177e4
LT		 1942 max_num_aiops = 1;
1943 rocketModel[i].model = MODEL_RP8J;
1944 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/RJ11 connectors");
1945 rocketModel[i].numPorts = 8;
1946 break;
1947 case PCI_DEVICE_ID_RP4J:
1da177e4
LT		 1948 max_num_aiops = 1;
1949 ports_per_aiop = 4;
1950 rocketModel[i].model = MODEL_RP4J;
1951 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/RJ45 connectors");
1952 rocketModel[i].numPorts = 4;
1953 break;
1954 case PCI_DEVICE_ID_RP8SNI:
1da177e4
LT		 1955 max_num_aiops = 1;
1956 rocketModel[i].model = MODEL_RP8SNI;
1957 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/ custom DB78");
1958 rocketModel[i].numPorts = 8;
1959 break;
1960 case PCI_DEVICE_ID_RP16SNI:
1da177e4
LT		 1961 max_num_aiops = 2;
1962 rocketModel[i].model = MODEL_RP16SNI;
1963 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/ custom DB78");
1964 rocketModel[i].numPorts = 16;
1965 break;
1966 case PCI_DEVICE_ID_RP16INTF:
1da177e4
LT		 1967 max_num_aiops = 2;
1968 rocketModel[i].model = MODEL_RP16INTF;
1969 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/external I/F");
1970 rocketModel[i].numPorts = 16;
1971 break;
1972 case PCI_DEVICE_ID_URP16INTF:
1da177e4
LT		 1973 max_num_aiops = 2;
1974 rocketModel[i].model = MODEL_UPCI_RP16INTF;
1975 strcpy(rocketModel[i].modelString, "RocketPort UPCI 16 port w/external I/F");
1976 rocketModel[i].numPorts = 16;
1977 break;
1978 case PCI_DEVICE_ID_CRP16INTF:
1da177e4
LT		 1979 max_num_aiops = 2;
1980 rocketModel[i].model = MODEL_CPCI_RP16INTF;
1981 strcpy(rocketModel[i].modelString, "RocketPort Compact PCI 16 port w/external I/F");
1982 rocketModel[i].numPorts = 16;
1983 break;
1984 case PCI_DEVICE_ID_RP32INTF:
1da177e4
LT		 1985 max_num_aiops = 4;
1986 rocketModel[i].model = MODEL_RP32INTF;
1987 strcpy(rocketModel[i].modelString, "RocketPort 32 port w/external I/F");
1988 rocketModel[i].numPorts = 32;
1989 break;
1990 case PCI_DEVICE_ID_URP32INTF:
1da177e4
LT		 1991 max_num_aiops = 4;
1992 rocketModel[i].model = MODEL_UPCI_RP32INTF;
1993 strcpy(rocketModel[i].modelString, "RocketPort UPCI 32 port w/external I/F");
1994 rocketModel[i].numPorts = 32;
1995 break;
1996 case PCI_DEVICE_ID_RPP4:
1da177e4
LT		 1997 max_num_aiops = 1;
1998 ports_per_aiop = 4;
1999 altChanRingIndicator++;
2000 fast_clock++;
2001 rocketModel[i].model = MODEL_RPP4;
2002 strcpy(rocketModel[i].modelString, "RocketPort Plus 4 port");
2003 rocketModel[i].numPorts = 4;
2004 break;
2005 case PCI_DEVICE_ID_RPP8:
1da177e4
LT		 2006 max_num_aiops = 2;
2007 ports_per_aiop = 4;
2008 altChanRingIndicator++;
2009 fast_clock++;
2010 rocketModel[i].model = MODEL_RPP8;
2011 strcpy(rocketModel[i].modelString, "RocketPort Plus 8 port");
2012 rocketModel[i].numPorts = 8;
2013 break;
2014 case PCI_DEVICE_ID_RP2_232:
1da177e4
LT		 2015 max_num_aiops = 1;
2016 ports_per_aiop = 2;
2017 altChanRingIndicator++;
2018 fast_clock++;
2019 rocketModel[i].model = MODEL_RP2_232;
2020 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS232");
2021 rocketModel[i].numPorts = 2;
2022 break;
2023 case PCI_DEVICE_ID_RP2_422:
1da177e4
LT		 2024 max_num_aiops = 1;
2025 ports_per_aiop = 2;
2026 altChanRingIndicator++;
2027 fast_clock++;
2028 rocketModel[i].model = MODEL_RP2_422;
2029 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS422");
2030 rocketModel[i].numPorts = 2;
2031 break;
2032 case PCI_DEVICE_ID_RP6M:
2033
2034 max_num_aiops = 1;
2035 ports_per_aiop = 6;
1da177e4 2036
57fedc7a
JS		 2037 /* If revision is 1, the rocketmodem flash must be loaded.
2038 * If it is 2 it is a "socketed" version. */
2039 if (dev->revision == 1) {
1da177e4
LT		 2040 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2041 rocketModel[i].loadrm2 = 1;
2042 } else {
2043 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2044 }
2045
2046 rocketModel[i].model = MODEL_RP6M;
2047 strcpy(rocketModel[i].modelString, "RocketModem 6 port");
2048 rocketModel[i].numPorts = 6;
2049 break;
2050 case PCI_DEVICE_ID_RP4M:
2051 max_num_aiops = 1;
2052 ports_per_aiop = 4;
57fedc7a 2053 if (dev->revision == 1) {
1da177e4
LT		 2054 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2055 rocketModel[i].loadrm2 = 1;
2056 } else {
2057 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2058 }
2059
2060 rocketModel[i].model = MODEL_RP4M;
2061 strcpy(rocketModel[i].modelString, "RocketModem 4 port");
2062 rocketModel[i].numPorts = 4;
2063 break;
2064 default:
1da177e4
LT		 2065 max_num_aiops = 0;
2066 break;
2067 }
2068
2069 /*
2070 * Check for UPCI boards.
2071 */
2072
2073 switch (dev->device) {
2074 case PCI_DEVICE_ID_URP32INTF:
2075 case PCI_DEVICE_ID_URP8INTF:
2076 case PCI_DEVICE_ID_URP16INTF:
2077 case PCI_DEVICE_ID_CRP16INTF:
2078 case PCI_DEVICE_ID_URP8OCTA:
2079 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2080 ConfigIO = pci_resource_start(dev, 1);
2081 if (dev->device == PCI_DEVICE_ID_URP8OCTA) {
2082 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2083
2084 /*
2085 * Check for octa or quad cable.
2086 */
2087 if (!
2088 (sInW(ConfigIO + _PCI_9030_GPIO_CTRL) &
2089 PCI_GPIO_CTRL_8PORT)) {
1da177e4
LT		 2090 ports_per_aiop = 4;
2091 rocketModel[i].numPorts = 4;
2092 }
2093 }
2094 break;
2095 case PCI_DEVICE_ID_UPCI_RM3_8PORT:
1da177e4
LT		 2096 max_num_aiops = 1;
2097 rocketModel[i].model = MODEL_UPCI_RM3_8PORT;
2098 strcpy(rocketModel[i].modelString, "RocketModem III 8 port");
2099 rocketModel[i].numPorts = 8;
2100 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2101 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2102 ConfigIO = pci_resource_start(dev, 1);
2103 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2104 break;
2105 case PCI_DEVICE_ID_UPCI_RM3_4PORT:
1da177e4
LT		 2106 max_num_aiops = 1;
2107 rocketModel[i].model = MODEL_UPCI_RM3_4PORT;
2108 strcpy(rocketModel[i].modelString, "RocketModem III 4 port");
2109 rocketModel[i].numPorts = 4;
2110 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2111 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2112 ConfigIO = pci_resource_start(dev, 1);
2113 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2114 break;
2115 default:
2116 break;
2117 }
2118
1da177e4
LT		 2119 if (fast_clock) {
2120 sClockPrescale = 0x12; /* mod 2 (divide by 3) */
2121 rp_baud_base[i] = 921600;
2122 } else {
2123 /*
2124 * If support_low_speed is set, use the slow clock
2125 * prescale, which supports 50 bps
2126 */
2127 if (support_low_speed) {
2128 /* mod 9 (divide by 10) prescale */
2129 sClockPrescale = 0x19;
2130 rp_baud_base[i] = 230400;
2131 } else {
25985edc 2132 /* mod 4 (divide by 5) prescale */
1da177e4
LT		 2133 sClockPrescale = 0x14;
2134 rp_baud_base[i] = 460800;
2135 }
2136 }
2137
2138 for (aiop = 0; aiop < max_num_aiops; aiop++)
2139 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x40);
2140 ctlp = sCtlNumToCtlPtr(i);
2141 num_aiops = sPCIInitController(ctlp, i, aiopio, max_num_aiops, ConfigIO, 0, FREQ_DIS, 0, altChanRingIndicator, UPCIRingInd);
2142 for (aiop = 0; aiop < max_num_aiops; aiop++)
2143 ctlp->AiopNumChan[aiop] = ports_per_aiop;
2144
68562b79
JS		 2145 dev_info(&dev->dev, "comtrol PCI controller #%d found at "
2146 "address %04lx, %d AIOP(s) (%s), creating ttyR%d - %ld\n",
2147 i, rcktpt_io_addr[i], num_aiops, rocketModel[i].modelString,
2148 rocketModel[i].startingPortNumber,
2149 rocketModel[i].startingPortNumber + rocketModel[i].numPorts-1);
1da177e4
LT		 2150
2151 if (num_aiops <= 0) {
2152 rcktpt_io_addr[i] = 0;
2153 return (0);
2154 }
2155 is_PCI[i] = 1;
2156
2157 /* Reset the AIOPIC, init the serial ports */
2158 for (aiop = 0; aiop < num_aiops; aiop++) {
2159 sResetAiopByNum(ctlp, aiop);
2160 num_chan = ports_per_aiop;
2161 for (chan = 0; chan < num_chan; chan++)
2162 init_r_port(i, aiop, chan, dev);
2163 }
2164
2165 /* Rocket modems must be reset */
2166 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) ||
2167 (rcktpt_type[i] == ROCKET_TYPE_MODEMII) ||
2168 (rcktpt_type[i] == ROCKET_TYPE_MODEMIII)) {
2169 num_chan = ports_per_aiop;
2170 for (chan = 0; chan < num_chan; chan++)
2171 sPCIModemReset(ctlp, chan, 1);
48a67f5d 2172 msleep(500);
1da177e4
LT		 2173 for (chan = 0; chan < num_chan; chan++)
2174 sPCIModemReset(ctlp, chan, 0);
48a67f5d 2175 msleep(500);
1da177e4
LT		 2176 rmSpeakerReset(ctlp, rocketModel[i].model);
2177 }
2178 return (1);
2179}
2180
2181/*
2182 * Probes for PCI cards, inits them if found
2183 * Input: board_found = number of ISA boards already found, or the
2184 * starting board number
2185 * Returns: Number of PCI boards found
2186 */
2187static int __init init_PCI(int boards_found)
2188{
2189 struct pci_dev *dev = NULL;
2190 int count = 0;
2191
2192 /* Work through the PCI device list, pulling out ours */
606d099c 2193 while ((dev = pci_get_device(PCI_VENDOR_ID_RP, PCI_ANY_ID, dev))) {
1da177e4
LT		 2194 if (register_PCI(count + boards_found, dev))
2195 count++;
2196 }
2197 return (count);
2198}
2199
2200#endif /* CONFIG_PCI */
2201
2202/*
2203 * Probes for ISA cards
2204 * Input: i = the board number to look for
2205 * Returns: 1 if board found, 0 else
2206 */
2207static int __init init_ISA(int i)
2208{
2209 int num_aiops, num_chan = 0, total_num_chan = 0;
2210 int aiop, chan;
2211 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
2212 CONTROLLER_t *ctlp;
2213 char *type_string;
2214
2215 /* If io_addr is zero, no board configured */
2216 if (rcktpt_io_addr[i] == 0)
2217 return (0);
2218
2219 /* Reserve the IO region */
2220 if (!request_region(rcktpt_io_addr[i], 64, "Comtrol RocketPort")) {
68562b79
JS		 2221 printk(KERN_ERR "Unable to reserve IO region for configured "
2222 "ISA RocketPort at address 0x%lx, board not "
2223 "installed...\n", rcktpt_io_addr[i]);
1da177e4
LT		 2224 rcktpt_io_addr[i] = 0;
2225 return (0);
2226 }
2227
2228 ctlp = sCtlNumToCtlPtr(i);
2229
2230 ctlp->boardType = rcktpt_type[i];
2231
2232 switch (rcktpt_type[i]) {
2233 case ROCKET_TYPE_PC104:
2234 type_string = "(PC104)";
2235 break;
2236 case ROCKET_TYPE_MODEM:
2237 type_string = "(RocketModem)";
2238 break;
2239 case ROCKET_TYPE_MODEMII:
2240 type_string = "(RocketModem II)";
2241 break;
2242 default:
2243 type_string = "";
2244 break;
2245 }
2246
2247 /*
2248 * If support_low_speed is set, use the slow clock prescale,
2249 * which supports 50 bps
2250 */
2251 if (support_low_speed) {
2252 sClockPrescale = 0x19; /* mod 9 (divide by 10) prescale */
2253 rp_baud_base[i] = 230400;
2254 } else {
25985edc 2255 sClockPrescale = 0x14; /* mod 4 (divide by 5) prescale */
1da177e4
LT		 2256 rp_baud_base[i] = 460800;
2257 }
2258
2259 for (aiop = 0; aiop < MAX_AIOPS_PER_BOARD; aiop++)
2260 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x400);
2261
2262 num_aiops = sInitController(ctlp, i, controller + (i * 0x400), aiopio, MAX_AIOPS_PER_BOARD, 0, FREQ_DIS, 0);
2263
2264 if (ctlp->boardType == ROCKET_TYPE_PC104) {
2265 sEnAiop(ctlp, 2); /* only one AIOPIC, but these */
2266 sEnAiop(ctlp, 3); /* CSels used for other stuff */
2267 }
2268
2269 /* If something went wrong initing the AIOP's release the ISA IO memory */
2270 if (num_aiops <= 0) {
2271 release_region(rcktpt_io_addr[i], 64);
2272 rcktpt_io_addr[i] = 0;
2273 return (0);
2274 }
2275
2276 rocketModel[i].startingPortNumber = nextLineNumber;
2277
2278 for (aiop = 0; aiop < num_aiops; aiop++) {
2279 sResetAiopByNum(ctlp, aiop);
2280 sEnAiop(ctlp, aiop);
2281 num_chan = sGetAiopNumChan(ctlp, aiop);
2282 total_num_chan += num_chan;
2283 for (chan = 0; chan < num_chan; chan++)
2284 init_r_port(i, aiop, chan, NULL);
2285 }
2286 is_PCI[i] = 0;
2287 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || (rcktpt_type[i] == ROCKET_TYPE_MODEMII)) {
2288 num_chan = sGetAiopNumChan(ctlp, 0);
2289 total_num_chan = num_chan;
2290 for (chan = 0; chan < num_chan; chan++)
2291 sModemReset(ctlp, chan, 1);
48a67f5d 2292 msleep(500);
1da177e4
LT		 2293 for (chan = 0; chan < num_chan; chan++)
2294 sModemReset(ctlp, chan, 0);
48a67f5d 2295 msleep(500);
1da177e4
LT		 2296 strcpy(rocketModel[i].modelString, "RocketModem ISA");
2297 } else {
2298 strcpy(rocketModel[i].modelString, "RocketPort ISA");
2299 }
2300 rocketModel[i].numPorts = total_num_chan;
2301 rocketModel[i].model = MODEL_ISA;
2302
2303 printk(KERN_INFO "RocketPort ISA card #%d found at 0x%lx - %d AIOPs %s\n",
2304 i, rcktpt_io_addr[i], num_aiops, type_string);
2305
2306 printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
2307 rocketModel[i].modelString,
2308 rocketModel[i].startingPortNumber,
2309 rocketModel[i].startingPortNumber +
2310 rocketModel[i].numPorts - 1);
2311
2312 return (1);
2313}
2314
b68e31d0 2315static const struct tty_operations rocket_ops = {
1da177e4
LT		 2316 .open = rp_open,
2317 .close = rp_close,
2318 .write = rp_write,
2319 .put_char = rp_put_char,
2320 .write_room = rp_write_room,
2321 .chars_in_buffer = rp_chars_in_buffer,
2322 .flush_buffer = rp_flush_buffer,
2323 .ioctl = rp_ioctl,
2324 .throttle = rp_throttle,
2325 .unthrottle = rp_unthrottle,
2326 .set_termios = rp_set_termios,
2327 .stop = rp_stop,
2328 .start = rp_start,
2329 .hangup = rp_hangup,
2330 .break_ctl = rp_break,
2331 .send_xchar = rp_send_xchar,
2332 .wait_until_sent = rp_wait_until_sent,
2333 .tiocmget = rp_tiocmget,
2334 .tiocmset = rp_tiocmset,
2335};
2336
31f35939
AC		 2337static const struct tty_port_operations rocket_port_ops = {
2338 .carrier_raised = carrier_raised,
fcc8ac18 2339 .dtr_rts = dtr_rts,
31f35939
AC		 2340};
2341
1da177e4
LT		 2342/*
2343 * The module "startup" routine; it's run when the module is loaded.
2344 */
d269cdd0 2345static int __init rp_init(void)
1da177e4 2346{
4384a3fa 2347 int ret = -ENOMEM, pci_boards_found, isa_boards_found, i;
1da177e4
LT		 2348
2349 printk(KERN_INFO "RocketPort device driver module, version %s, %s\n",
2350 ROCKET_VERSION, ROCKET_DATE);
2351
2352 rocket_driver = alloc_tty_driver(MAX_RP_PORTS);
2353 if (!rocket_driver)
4384a3fa 2354 goto err;
1da177e4 2355
1da177e4
LT		 2356 /*
2357 * If board 1 is non-zero, there is at least one ISA configured. If controller is
2358 * zero, use the default controller IO address of board1 + 0x40.
2359 */
2360 if (board1) {
2361 if (controller == 0)
2362 controller = board1 + 0x40;
2363 } else {
2364 controller = 0; /* Used as a flag, meaning no ISA boards */
2365 }
2366
2367 /* If an ISA card is configured, reserve the 4 byte IO space for the Mudbac controller */
2368 if (controller && (!request_region(controller, 4, "Comtrol RocketPort"))) {
4384a3fa
JS		 2369 printk(KERN_ERR "Unable to reserve IO region for first "
2370 "configured ISA RocketPort controller 0x%lx. "
2371 "Driver exiting\n", controller);
2372 ret = -EBUSY;
2373 goto err_tty;
1da177e4
LT		 2374 }
2375
2376 /* Store ISA variable retrieved from command line or .conf file. */
2377 rcktpt_io_addr[0] = board1;
2378 rcktpt_io_addr[1] = board2;
2379 rcktpt_io_addr[2] = board3;
2380 rcktpt_io_addr[3] = board4;
2381
2382 rcktpt_type[0] = modem1 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2383 rcktpt_type[0] = pc104_1[0] ? ROCKET_TYPE_PC104 : rcktpt_type[0];
2384 rcktpt_type[1] = modem2 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2385 rcktpt_type[1] = pc104_2[0] ? ROCKET_TYPE_PC104 : rcktpt_type[1];
2386 rcktpt_type[2] = modem3 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2387 rcktpt_type[2] = pc104_3[0] ? ROCKET_TYPE_PC104 : rcktpt_type[2];
2388 rcktpt_type[3] = modem4 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2389 rcktpt_type[3] = pc104_4[0] ? ROCKET_TYPE_PC104 : rcktpt_type[3];
2390
2391 /*
2392 * Set up the tty driver structure and then register this
2393 * driver with the tty layer.
2394 */
2395
331b8319 2396 rocket_driver->flags = TTY_DRIVER_DYNAMIC_DEV;
1da177e4
LT		 2397 rocket_driver->name = "ttyR";
2398 rocket_driver->driver_name = "Comtrol RocketPort";
2399 rocket_driver->major = TTY_ROCKET_MAJOR;
2400 rocket_driver->minor_start = 0;
2401 rocket_driver->type = TTY_DRIVER_TYPE_SERIAL;
2402 rocket_driver->subtype = SERIAL_TYPE_NORMAL;
2403 rocket_driver->init_termios = tty_std_termios;
2404 rocket_driver->init_termios.c_cflag =
2405 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
606d099c
AC		 2406 rocket_driver->init_termios.c_ispeed = 9600;
2407 rocket_driver->init_termios.c_ospeed = 9600;
1da177e4 2408#ifdef ROCKET_SOFT_FLOW
ac6aec2f 2409 rocket_driver->flags |= TTY_DRIVER_REAL_RAW;
1da177e4
LT		 2410#endif
2411 tty_set_operations(rocket_driver, &rocket_ops);
2412
4384a3fa
JS		 2413 ret = tty_register_driver(rocket_driver);
2414 if (ret < 0) {
2415 printk(KERN_ERR "Couldn't install tty RocketPort driver\n");
713efa9a 2416 goto err_controller;
1da177e4
LT		 2417 }
2418
2419#ifdef ROCKET_DEBUG_OPEN
2420 printk(KERN_INFO "RocketPort driver is major %d\n", rocket_driver.major);
2421#endif
2422
2423 /*
2424 * OK, let's probe each of the controllers looking for boards. Any boards found
2425 * will be initialized here.
2426 */
2427 isa_boards_found = 0;
2428 pci_boards_found = 0;
2429
2430 for (i = 0; i < NUM_BOARDS; i++) {
2431 if (init_ISA(i))
2432 isa_boards_found++;
2433 }
2434
2435#ifdef CONFIG_PCI
2436 if (isa_boards_found < NUM_BOARDS)
2437 pci_boards_found = init_PCI(isa_boards_found);
2438#endif
2439
2440 max_board = pci_boards_found + isa_boards_found;
2441
2442 if (max_board == 0) {
4384a3fa
JS		 2443 printk(KERN_ERR "No rocketport ports found; unloading driver\n");
2444 ret = -ENXIO;
2445 goto err_ttyu;
1da177e4
LT		 2446 }
2447
2448 return 0;
4384a3fa
JS		 2449err_ttyu:
2450 tty_unregister_driver(rocket_driver);
713efa9a
DC		 2451err_controller:
2452 if (controller)
2453 release_region(controller, 4);
4384a3fa
JS		 2454err_tty:
2455 put_tty_driver(rocket_driver);
2456err:
2457 return ret;
1da177e4
LT		 2458}
2459
1da177e4
LT		 2460
2461static void rp_cleanup_module(void)
2462{
2463 int retval;
2464 int i;
2465
2466 del_timer_sync(&rocket_timer);
2467
2468 retval = tty_unregister_driver(rocket_driver);
2469 if (retval)
68562b79 2470 printk(KERN_ERR "Error %d while trying to unregister "
1da177e4 2471 "rocketport driver\n", -retval);
1da177e4 2472
735d5661 2473 for (i = 0; i < MAX_RP_PORTS; i++)
ac6aec2f
JS		 2474 if (rp_table[i]) {
2475 tty_unregister_device(rocket_driver, i);
191c5f10 2476 tty_port_destroy(&rp_table[i]->port);
ac6aec2f
JS		 2477 kfree(rp_table[i]);
2478 }
2479
2480 put_tty_driver(rocket_driver);
1da177e4
LT		 2481
2482 for (i = 0; i < NUM_BOARDS; i++) {
2483 if (rcktpt_io_addr[i] <= 0 || is_PCI[i])
2484 continue;
2485 release_region(rcktpt_io_addr[i], 64);
2486 }
2487 if (controller)
2488 release_region(controller, 4);
2489}
1da177e4 2490
1da177e4
LT		 2491/***************************************************************************
2492Function: sInitController
2493Purpose: Initialization of controller global registers and controller
2494 structure.
2495Call: sInitController(CtlP,CtlNum,MudbacIO,AiopIOList,AiopIOListSize,
2496 IRQNum,Frequency,PeriodicOnly)
2497 CONTROLLER_T *CtlP; Ptr to controller structure
2498 int CtlNum; Controller number
2499 ByteIO_t MudbacIO; Mudbac base I/O address.
2500 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2501 This list must be in the order the AIOPs will be found on the
2502 controller. Once an AIOP in the list is not found, it is
2503 assumed that there are no more AIOPs on the controller.
2504 int AiopIOListSize; Number of addresses in AiopIOList
2505 int IRQNum; Interrupt Request number. Can be any of the following:
2506 0: Disable global interrupts
2507 3: IRQ 3
2508 4: IRQ 4
2509 5: IRQ 5
2510 9: IRQ 9
2511 10: IRQ 10
2512 11: IRQ 11
2513 12: IRQ 12
2514 15: IRQ 15
2515 Byte_t Frequency: A flag identifying the frequency
2516 of the periodic interrupt, can be any one of the following:
2517 FREQ_DIS - periodic interrupt disabled
2518 FREQ_137HZ - 137 Hertz
2519 FREQ_69HZ - 69 Hertz
2520 FREQ_34HZ - 34 Hertz
2521 FREQ_17HZ - 17 Hertz
2522 FREQ_9HZ - 9 Hertz
2523 FREQ_4HZ - 4 Hertz
2524 If IRQNum is set to 0 the Frequency parameter is
2525 overidden, it is forced to a value of FREQ_DIS.
f15313bf 2526 int PeriodicOnly: 1 if all interrupts except the periodic
1da177e4 2527 interrupt are to be blocked.
f15313bf 2528 0 is both the periodic interrupt and
1da177e4
LT		 2529 other channel interrupts are allowed.
2530 If IRQNum is set to 0 the PeriodicOnly parameter is
f15313bf 2531 overidden, it is forced to a value of 0.
1da177e4
LT		 2532Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2533 initialization failed.
2534
2535Comments:
2536 If periodic interrupts are to be disabled but AIOP interrupts
f15313bf 2537 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
1da177e4
LT		 2538
2539 If interrupts are to be completely disabled set IRQNum to 0.
2540
f15313bf 2541 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
1da177e4
LT		 2542 invalid combination.
2543
2544 This function performs initialization of global interrupt modes,
2545 but it does not actually enable global interrupts. To enable
2546 and disable global interrupts use functions sEnGlobalInt() and
2547 sDisGlobalInt(). Enabling of global interrupts is normally not
2548 done until all other initializations are complete.
2549
2550 Even if interrupts are globally enabled, they must also be
2551 individually enabled for each channel that is to generate
2552 interrupts.
2553
2554Warnings: No range checking on any of the parameters is done.
2555
2556 No context switches are allowed while executing this function.
2557
2558 After this function all AIOPs on the controller are disabled,
2559 they can be enabled with sEnAiop().
2560*/
f15313bf
AB		 2561static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
2562 ByteIO_t * AiopIOList, int AiopIOListSize,
2563 int IRQNum, Byte_t Frequency, int PeriodicOnly)
1da177e4
LT		 2564{
2565 int i;
2566 ByteIO_t io;
2567 int done;
2568
2569 CtlP->AiopIntrBits = aiop_intr_bits;
2570 CtlP->AltChanRingIndicator = 0;
2571 CtlP->CtlNum = CtlNum;
2572 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2573 CtlP->BusType = isISA;
2574 CtlP->MBaseIO = MudbacIO;
2575 CtlP->MReg1IO = MudbacIO + 1;
2576 CtlP->MReg2IO = MudbacIO + 2;
2577 CtlP->MReg3IO = MudbacIO + 3;
2578#if 1
2579 CtlP->MReg2 = 0; /* interrupt disable */
2580 CtlP->MReg3 = 0; /* no periodic interrupts */
2581#else
2582 if (sIRQMap[IRQNum] == 0) { /* interrupts globally disabled */
2583 CtlP->MReg2 = 0; /* interrupt disable */
2584 CtlP->MReg3 = 0; /* no periodic interrupts */
2585 } else {
2586 CtlP->MReg2 = sIRQMap[IRQNum]; /* set IRQ number */
2587 CtlP->MReg3 = Frequency; /* set frequency */
2588 if (PeriodicOnly) { /* periodic interrupt only */
2589 CtlP->MReg3 |= PERIODIC_ONLY;
2590 }
2591 }
2592#endif
2593 sOutB(CtlP->MReg2IO, CtlP->MReg2);
2594 sOutB(CtlP->MReg3IO, CtlP->MReg3);
2595 sControllerEOI(CtlP); /* clear EOI if warm init */
2596 /* Init AIOPs */
2597 CtlP->NumAiop = 0;
2598 for (i = done = 0; i < AiopIOListSize; i++) {
2599 io = AiopIOList[i];
2600 CtlP->AiopIO[i] = (WordIO_t) io;
2601 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2602 sOutB(CtlP->MReg2IO, CtlP->MReg2 | (i & 0x03)); /* AIOP index */
2603 sOutB(MudbacIO, (Byte_t) (io >> 6)); /* set up AIOP I/O in MUDBAC */
2604 if (done)
2605 continue;
2606 sEnAiop(CtlP, i); /* enable the AIOP */
2607 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2608 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2609 done = 1; /* done looking for AIOPs */
2610 else {
2611 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2612 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2613 sOutB(io + _INDX_DATA, sClockPrescale);
2614 CtlP->NumAiop++; /* bump count of AIOPs */
2615 }
2616 sDisAiop(CtlP, i); /* disable AIOP */
2617 }
2618
2619 if (CtlP->NumAiop == 0)
2620 return (-1);
2621 else
2622 return (CtlP->NumAiop);
2623}
2624
1da177e4
LT		 2625/***************************************************************************
2626Function: sReadAiopID
2627Purpose: Read the AIOP idenfication number directly from an AIOP.
2628Call: sReadAiopID(io)
2629 ByteIO_t io: AIOP base I/O address
2630Return: int: Flag AIOPID_XXXX if a valid AIOP is found, where X
2631 is replace by an identifying number.
2632 Flag AIOPID_NULL if no valid AIOP is found
2633Warnings: No context switches are allowed while executing this function.
2634
2635*/
f15313bf 2636static int sReadAiopID(ByteIO_t io)
1da177e4
LT		 2637{
2638 Byte_t AiopID; /* ID byte from AIOP */
2639
2640 sOutB(io + _CMD_REG, RESET_ALL); /* reset AIOP */
2641 sOutB(io + _CMD_REG, 0x0);
2642 AiopID = sInW(io + _CHN_STAT0) & 0x07;
2643 if (AiopID == 0x06)
2644 return (1);
2645 else /* AIOP does not exist */
2646 return (-1);
2647}
2648
2649/***************************************************************************
2650Function: sReadAiopNumChan
2651Purpose: Read the number of channels available in an AIOP directly from
2652 an AIOP.
2653Call: sReadAiopNumChan(io)
2654 WordIO_t io: AIOP base I/O address
2655Return: int: The number of channels available
2656Comments: The number of channels is determined by write/reads from identical
2657 offsets within the SRAM address spaces for channels 0 and 4.
2658 If the channel 4 space is mirrored to channel 0 it is a 4 channel
2659 AIOP, otherwise it is an 8 channel.
2660Warnings: No context switches are allowed while executing this function.
2661*/
f15313bf 2662static int sReadAiopNumChan(WordIO_t io)
1da177e4
LT		 2663{
2664 Word_t x;
2665 static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 };
2666
2667 /* write to chan 0 SRAM */
457fb605 2668 out32((DWordIO_t) io + _INDX_ADDR, R);
1da177e4
LT		 2669 sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */
2670 x = sInW(io + _INDX_DATA);
2671 sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
2672 if (x != sInW(io + _INDX_DATA)) /* if different must be 8 chan */
2673 return (8);
2674 else
2675 return (4);
2676}
2677
2678/***************************************************************************
2679Function: sInitChan
2680Purpose: Initialization of a channel and channel structure
2681Call: sInitChan(CtlP,ChP,AiopNum,ChanNum)
2682 CONTROLLER_T *CtlP; Ptr to controller structure
2683 CHANNEL_T *ChP; Ptr to channel structure
2684 int AiopNum; AIOP number within controller
2685 int ChanNum; Channel number within AIOP
f15313bf 2686Return: int: 1 if initialization succeeded, 0 if it fails because channel
1da177e4
LT		 2687 number exceeds number of channels available in AIOP.
2688Comments: This function must be called before a channel can be used.
2689Warnings: No range checking on any of the parameters is done.
2690
2691 No context switches are allowed while executing this function.
2692*/
f15313bf
AB		 2693static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2694 int ChanNum)
1da177e4
LT		 2695{
2696 int i;
2697 WordIO_t AiopIO;
2698 WordIO_t ChIOOff;
2699 Byte_t *ChR;
2700 Word_t ChOff;
2701 static Byte_t R[4];
2702 int brd9600;
2703
2704 if (ChanNum >= CtlP->AiopNumChan[AiopNum])
f15313bf 2705 return 0; /* exceeds num chans in AIOP */
1da177e4
LT		 2706
2707 /* Channel, AIOP, and controller identifiers */
2708 ChP->CtlP = CtlP;
2709 ChP->ChanID = CtlP->AiopID[AiopNum];
2710 ChP->AiopNum = AiopNum;
2711 ChP->ChanNum = ChanNum;
2712
2713 /* Global direct addresses */
2714 AiopIO = CtlP->AiopIO[AiopNum];
2715 ChP->Cmd = (ByteIO_t) AiopIO + _CMD_REG;
2716 ChP->IntChan = (ByteIO_t) AiopIO + _INT_CHAN;
2717 ChP->IntMask = (ByteIO_t) AiopIO + _INT_MASK;
2718 ChP->IndexAddr = (DWordIO_t) AiopIO + _INDX_ADDR;
2719 ChP->IndexData = AiopIO + _INDX_DATA;
2720
2721 /* Channel direct addresses */
2722 ChIOOff = AiopIO + ChP->ChanNum * 2;
2723 ChP->TxRxData = ChIOOff + _TD0;
2724 ChP->ChanStat = ChIOOff + _CHN_STAT0;
2725 ChP->TxRxCount = ChIOOff + _FIFO_CNT0;
2726 ChP->IntID = (ByteIO_t) AiopIO + ChP->ChanNum + _INT_ID0;
2727
2728 /* Initialize the channel from the RData array */
2729 for (i = 0; i < RDATASIZE; i += 4) {
2730 R[0] = RData[i];
2731 R[1] = RData[i + 1] + 0x10 * ChanNum;
2732 R[2] = RData[i + 2];
2733 R[3] = RData[i + 3];
457fb605 2734 out32(ChP->IndexAddr, R);
1da177e4
LT		 2735 }
2736
2737 ChR = ChP->R;
2738 for (i = 0; i < RREGDATASIZE; i += 4) {
2739 ChR[i] = RRegData[i];
2740 ChR[i + 1] = RRegData[i + 1] + 0x10 * ChanNum;
2741 ChR[i + 2] = RRegData[i + 2];
2742 ChR[i + 3] = RRegData[i + 3];
2743 }
2744
2745 /* Indexed registers */
2746 ChOff = (Word_t) ChanNum *0x1000;
2747
2748 if (sClockPrescale == 0x14)
2749 brd9600 = 47;
2750 else
2751 brd9600 = 23;
2752
2753 ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD);
2754 ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
2755 ChP->BaudDiv[2] = (Byte_t) brd9600;
2756 ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
457fb605 2757 out32(ChP->IndexAddr, ChP->BaudDiv);
1da177e4
LT		 2758
2759 ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
2760 ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
2761 ChP->TxControl[2] = 0;
2762 ChP->TxControl[3] = 0;
457fb605 2763 out32(ChP->IndexAddr, ChP->TxControl);
1da177e4
LT		 2764
2765 ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
2766 ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
2767 ChP->RxControl[2] = 0;
2768 ChP->RxControl[3] = 0;
457fb605 2769 out32(ChP->IndexAddr, ChP->RxControl);
1da177e4
LT		 2770
2771 ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
2772 ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
2773 ChP->TxEnables[2] = 0;
2774 ChP->TxEnables[3] = 0;
457fb605 2775 out32(ChP->IndexAddr, ChP->TxEnables);
1da177e4
LT		 2776
2777 ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
2778 ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
2779 ChP->TxCompare[2] = 0;
2780 ChP->TxCompare[3] = 0;
457fb605 2781 out32(ChP->IndexAddr, ChP->TxCompare);
1da177e4
LT		 2782
2783 ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
2784 ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
2785 ChP->TxReplace1[2] = 0;
2786 ChP->TxReplace1[3] = 0;
457fb605 2787 out32(ChP->IndexAddr, ChP->TxReplace1);
1da177e4
LT		 2788
2789 ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
2790 ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
2791 ChP->TxReplace2[2] = 0;
2792 ChP->TxReplace2[3] = 0;
457fb605 2793 out32(ChP->IndexAddr, ChP->TxReplace2);
1da177e4
LT		 2794
2795 ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
2796 ChP->TxFIFO = ChOff + _TX_FIFO;
2797
2798 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT); /* apply reset Tx FIFO count */
2799 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Tx FIFO count */
2800 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2801 sOutW(ChP->IndexData, 0);
2802 ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
2803 ChP->RxFIFO = ChOff + _RX_FIFO;
2804
2805 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT); /* apply reset Rx FIFO count */
2806 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Rx FIFO count */
2807 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2808 sOutW(ChP->IndexData, 0);
2809 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2810 sOutW(ChP->IndexData, 0);
2811 ChP->TxPrioCnt = ChOff + _TXP_CNT;
2812 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt);
2813 sOutB(ChP->IndexData, 0);
2814 ChP->TxPrioPtr = ChOff + _TXP_PNTR;
2815 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr);
2816 sOutB(ChP->IndexData, 0);
2817 ChP->TxPrioBuf = ChOff + _TXP_BUF;
2818 sEnRxProcessor(ChP); /* start the Rx processor */
2819
f15313bf 2820 return 1;
1da177e4
LT		 2821}
2822
2823/***************************************************************************
2824Function: sStopRxProcessor
2825Purpose: Stop the receive processor from processing a channel.
2826Call: sStopRxProcessor(ChP)
2827 CHANNEL_T *ChP; Ptr to channel structure
2828
2829Comments: The receive processor can be started again with sStartRxProcessor().
2830 This function causes the receive processor to skip over the
2831 stopped channel. It does not stop it from processing other channels.
2832
2833Warnings: No context switches are allowed while executing this function.
2834
2835 Do not leave the receive processor stopped for more than one
2836 character time.
2837
2838 After calling this function a delay of 4 uS is required to ensure
2839 that the receive processor is no longer processing this channel.
2840*/
f15313bf 2841static void sStopRxProcessor(CHANNEL_T * ChP)
1da177e4
LT		 2842{
2843 Byte_t R[4];
2844
2845 R[0] = ChP->R[0];
2846 R[1] = ChP->R[1];
2847 R[2] = 0x0a;
2848 R[3] = ChP->R[3];
457fb605 2849 out32(ChP->IndexAddr, R);
1da177e4
LT		 2850}
2851
2852/***************************************************************************
2853Function: sFlushRxFIFO
2854Purpose: Flush the Rx FIFO
2855Call: sFlushRxFIFO(ChP)
2856 CHANNEL_T *ChP; Ptr to channel structure
2857Return: void
2858Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2859 while it is being flushed the receive processor is stopped
2860 and the transmitter is disabled. After these operations a
2861 4 uS delay is done before clearing the pointers to allow
2862 the receive processor to stop. These items are handled inside
2863 this function.
2864Warnings: No context switches are allowed while executing this function.
2865*/
f15313bf 2866static void sFlushRxFIFO(CHANNEL_T * ChP)
1da177e4
LT		 2867{
2868 int i;
2869 Byte_t Ch; /* channel number within AIOP */
f15313bf 2870 int RxFIFOEnabled; /* 1 if Rx FIFO enabled */
1da177e4
LT		 2871
2872 if (sGetRxCnt(ChP) == 0) /* Rx FIFO empty */
2873 return; /* don't need to flush */
2874
f15313bf 2875 RxFIFOEnabled = 0;
1da177e4 2876 if (ChP->R[0x32] == 0x08) { /* Rx FIFO is enabled */
f15313bf 2877 RxFIFOEnabled = 1;
1da177e4
LT		 2878 sDisRxFIFO(ChP); /* disable it */
2879 for (i = 0; i < 2000 / 200; i++) /* delay 2 uS to allow proc to disable FIFO */
2880 sInB(ChP->IntChan); /* depends on bus i/o timing */
2881 }
2882 sGetChanStatus(ChP); /* clear any pending Rx errors in chan stat */
2883 Ch = (Byte_t) sGetChanNum(ChP);
2884 sOutB(ChP->Cmd, Ch | RESRXFCNT); /* apply reset Rx FIFO count */
2885 sOutB(ChP->Cmd, Ch); /* remove reset Rx FIFO count */
2886 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2887 sOutW(ChP->IndexData, 0);
2888 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2889 sOutW(ChP->IndexData, 0);
2890 if (RxFIFOEnabled)
2891 sEnRxFIFO(ChP); /* enable Rx FIFO */
2892}
2893
2894/***************************************************************************
2895Function: sFlushTxFIFO
2896Purpose: Flush the Tx FIFO
2897Call: sFlushTxFIFO(ChP)
2898 CHANNEL_T *ChP; Ptr to channel structure
2899Return: void
2900Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2901 while it is being flushed the receive processor is stopped
2902 and the transmitter is disabled. After these operations a
2903 4 uS delay is done before clearing the pointers to allow
2904 the receive processor to stop. These items are handled inside
2905 this function.
2906Warnings: No context switches are allowed while executing this function.
2907*/
f15313bf 2908static void sFlushTxFIFO(CHANNEL_T * ChP)
1da177e4
LT		 2909{
2910 int i;
2911 Byte_t Ch; /* channel number within AIOP */
f15313bf 2912 int TxEnabled; /* 1 if transmitter enabled */
1da177e4
LT		 2913
2914 if (sGetTxCnt(ChP) == 0) /* Tx FIFO empty */
2915 return; /* don't need to flush */
2916
f15313bf 2917 TxEnabled = 0;
1da177e4 2918 if (ChP->TxControl[3] & TX_ENABLE) {
f15313bf 2919 TxEnabled = 1;
1da177e4
LT		 2920 sDisTransmit(ChP); /* disable transmitter */
2921 }
2922 sStopRxProcessor(ChP); /* stop Rx processor */
2923 for (i = 0; i < 4000 / 200; i++) /* delay 4 uS to allow proc to stop */
2924 sInB(ChP->IntChan); /* depends on bus i/o timing */
2925 Ch = (Byte_t) sGetChanNum(ChP);
2926 sOutB(ChP->Cmd, Ch | RESTXFCNT); /* apply reset Tx FIFO count */
2927 sOutB(ChP->Cmd, Ch); /* remove reset Tx FIFO count */
2928 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2929 sOutW(ChP->IndexData, 0);
2930 if (TxEnabled)
2931 sEnTransmit(ChP); /* enable transmitter */
2932 sStartRxProcessor(ChP); /* restart Rx processor */
2933}
2934
2935/***************************************************************************
2936Function: sWriteTxPrioByte
2937Purpose: Write a byte of priority transmit data to a channel
2938Call: sWriteTxPrioByte(ChP,Data)
2939 CHANNEL_T *ChP; Ptr to channel structure
2940 Byte_t Data; The transmit data byte
2941
2942Return: int: 1 if the bytes is successfully written, otherwise 0.
2943
2944Comments: The priority byte is transmitted before any data in the Tx FIFO.
2945
2946Warnings: No context switches are allowed while executing this function.
2947*/
f15313bf 2948static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
1da177e4
LT		 2949{
2950 Byte_t DWBuf[4]; /* buffer for double word writes */
2951 Word_t *WordPtr; /* must be far because Win SS != DS */
2952 register DWordIO_t IndexAddr;
2953
2954 if (sGetTxCnt(ChP) > 1) { /* write it to Tx priority buffer */
2955 IndexAddr = ChP->IndexAddr;
2956 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt); /* get priority buffer status */
2957 if (sInB((ByteIO_t) ChP->IndexData) & PRI_PEND) /* priority buffer busy */
2958 return (0); /* nothing sent */
2959
2960 WordPtr = (Word_t *) (&DWBuf[0]);
2961 *WordPtr = ChP->TxPrioBuf; /* data byte address */
2962
2963 DWBuf[2] = Data; /* data byte value */
457fb605 2964 out32(IndexAddr, DWBuf); /* write it out */
1da177e4
LT		 2965
2966 *WordPtr = ChP->TxPrioCnt; /* Tx priority count address */
2967
2968 DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */
2969 DWBuf[3] = 0; /* priority buffer pointer */
457fb605 2970 out32(IndexAddr, DWBuf); /* write it out */
1da177e4
LT		 2971 } else { /* write it to Tx FIFO */
2972
2973 sWriteTxByte(sGetTxRxDataIO(ChP), Data);
2974 }
2975 return (1); /* 1 byte sent */
2976}
2977
2978/***************************************************************************
2979Function: sEnInterrupts
2980Purpose: Enable one or more interrupts for a channel
2981Call: sEnInterrupts(ChP,Flags)
2982 CHANNEL_T *ChP; Ptr to channel structure
2983 Word_t Flags: Interrupt enable flags, can be any combination
2984 of the following flags:
2985 TXINT_EN: Interrupt on Tx FIFO empty
2986 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
2987 sSetRxTrigger())
2988 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
2989 MCINT_EN: Interrupt on modem input change
2990 CHANINT_EN: Allow channel interrupt signal to the AIOP's
2991 Interrupt Channel Register.
2992Return: void
2993Comments: If an interrupt enable flag is set in Flags, that interrupt will be
2994 enabled. If an interrupt enable flag is not set in Flags, that
2995 interrupt will not be changed. Interrupts can be disabled with
2996 function sDisInterrupts().
2997
2998 This function sets the appropriate bit for the channel in the AIOP's
2999 Interrupt Mask Register if the CHANINT_EN flag is set. This allows
3000 this channel's bit to be set in the AIOP's Interrupt Channel Register.
3001
3002 Interrupts must also be globally enabled before channel interrupts
3003 will be passed on to the host. This is done with function
3004 sEnGlobalInt().
3005
3006 In some cases it may be desirable to disable interrupts globally but
3007 enable channel interrupts. This would allow the global interrupt
3008 status register to be used to determine which AIOPs need service.
3009*/
f15313bf 3010static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
1da177e4
LT		 3011{
3012 Byte_t Mask; /* Interrupt Mask Register */
3013
3014 ChP->RxControl[2] |=
3015 ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3016
457fb605 3017 out32(ChP->IndexAddr, ChP->RxControl);
1da177e4
LT		 3018
3019 ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
3020
457fb605 3021 out32(ChP->IndexAddr, ChP->TxControl);
1da177e4
LT		 3022
3023 if (Flags & CHANINT_EN) {
3024 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
3025 sOutB(ChP->IntMask, Mask);
3026 }
3027}
3028
3029/***************************************************************************
3030Function: sDisInterrupts
3031Purpose: Disable one or more interrupts for a channel
3032Call: sDisInterrupts(ChP,Flags)
3033 CHANNEL_T *ChP; Ptr to channel structure
3034 Word_t Flags: Interrupt flags, can be any combination
3035 of the following flags:
3036 TXINT_EN: Interrupt on Tx FIFO empty
3037 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3038 sSetRxTrigger())
3039 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3040 MCINT_EN: Interrupt on modem input change
3041 CHANINT_EN: Disable channel interrupt signal to the
3042 AIOP's Interrupt Channel Register.
3043Return: void
3044Comments: If an interrupt flag is set in Flags, that interrupt will be
3045 disabled. If an interrupt flag is not set in Flags, that
3046 interrupt will not be changed. Interrupts can be enabled with
3047 function sEnInterrupts().
3048
3049 This function clears the appropriate bit for the channel in the AIOP's
3050 Interrupt Mask Register if the CHANINT_EN flag is set. This blocks
3051 this channel's bit from being set in the AIOP's Interrupt Channel
3052 Register.
3053*/
f15313bf 3054static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
1da177e4
LT		 3055{
3056 Byte_t Mask; /* Interrupt Mask Register */
3057
3058 ChP->RxControl[2] &=
3059 ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
457fb605 3060 out32(ChP->IndexAddr, ChP->RxControl);
1da177e4 3061 ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
457fb605 3062 out32(ChP->IndexAddr, ChP->TxControl);
1da177e4
LT		 3063
3064 if (Flags & CHANINT_EN) {
3065 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];
3066 sOutB(ChP->IntMask, Mask);
3067 }
3068}
3069
f15313bf 3070static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
1da177e4
LT		 3071{
3072 sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum);
3073}
3074
3075/*
3076 * Not an official SSCI function, but how to reset RocketModems.
3077 * ISA bus version
3078 */
f15313bf 3079static void sModemReset(CONTROLLER_T * CtlP, int chan, int on)
1da177e4
LT		 3080{
3081 ByteIO_t addr;
3082 Byte_t val;
3083
3084 addr = CtlP->AiopIO[0] + 0x400;
3085 val = sInB(CtlP->MReg3IO);
3086 /* if AIOP[1] is not enabled, enable it */
3087 if ((val & 2) == 0) {
3088 val = sInB(CtlP->MReg2IO);
3089 sOutB(CtlP->MReg2IO, (val & 0xfc) | (1 & 0x03));
3090 sOutB(CtlP->MBaseIO, (unsigned char) (addr >> 6));
3091 }
3092
3093 sEnAiop(CtlP, 1);
3094 if (!on)
3095 addr += 8;
3096 sOutB(addr + chan, 0); /* apply or remove reset */
3097 sDisAiop(CtlP, 1);
3098}
3099
3100/*
3101 * Not an official SSCI function, but how to reset RocketModems.
3102 * PCI bus version
3103 */
f15313bf 3104static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on)
1da177e4
LT		 3105{
3106 ByteIO_t addr;
3107
3108 addr = CtlP->AiopIO[0] + 0x40; /* 2nd AIOP */
3109 if (!on)
3110 addr += 8;
3111 sOutB(addr + chan, 0); /* apply or remove reset */
3112}
3113
1da177e4
LT		 3114/* Returns the line number given the controller (board), aiop and channel number */
3115static unsigned char GetLineNumber(int ctrl, int aiop, int ch)
3116{
3117 return lineNumbers[(ctrl << 5) | (aiop << 3) | ch];
3118}
3119
3120/*
3121 * Stores the line number associated with a given controller (board), aiop
3122 * and channel number.
3123 * Returns: The line number assigned
3124 */
3125static unsigned char SetLineNumber(int ctrl, int aiop, int ch)
3126{
3127 lineNumbers[(ctrl << 5) | (aiop << 3) | ch] = nextLineNumber++;
3128 return (nextLineNumber - 1);
3129}
A mirror of Linus' kernel repository