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[thirdparty/kernel/linux.git] / drivers / tty / serial / 8250.c
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1da177e4
LT		 1/*
2 * linux/drivers/char/8250.c
3 *
4 * Driver for 8250/16550-type serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
1da177e4
LT		 15 * A note about mapbase / membase
16 *
17 * mapbase is the physical address of the IO port.
18 * membase is an 'ioremapped' cookie.
19 */
1da177e4
LT		 20
21#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22#define SUPPORT_SYSRQ
23#endif
24
25#include <linux/module.h>
26#include <linux/moduleparam.h>
27#include <linux/ioport.h>
28#include <linux/init.h>
29#include <linux/console.h>
30#include <linux/sysrq.h>
1da177e4 31#include <linux/delay.h>
d052d1be 32#include <linux/platform_device.h>
1da177e4 33#include <linux/tty.h>
cd3ecad1 34#include <linux/ratelimit.h>
1da177e4
LT		 35#include <linux/tty_flip.h>
36#include <linux/serial_reg.h>
37#include <linux/serial_core.h>
38#include <linux/serial.h>
39#include <linux/serial_8250.h>
78512ece 40#include <linux/nmi.h>
f392ecfa 41#include <linux/mutex.h>
5a0e3ad6 42#include <linux/slab.h>
1da177e4
LT		 43
44#include <asm/io.h>
45#include <asm/irq.h>
46
47#include "8250.h"
48
b70ac771
DM		 49#ifdef CONFIG_SPARC
50#include "suncore.h"
51#endif
52
1da177e4
LT		 53/*
54 * Configuration:
40663cc7 55 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
1da177e4
LT		 56 * is unsafe when used on edge-triggered interrupts.
57 */
408b664a 58static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
1da177e4 59
a61c2d78
DJ		 60static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
61
8440838b
DM		 62static struct uart_driver serial8250_reg;
63
64static int serial_index(struct uart_port *port)
65{
66 return (serial8250_reg.minor - 64) + port->line;
67}
68
d41a4b51
CE		 69static unsigned int skip_txen_test; /* force skip of txen test at init time */
70
1da177e4
LT		 71/*
72 * Debugging.
73 */
74#if 0
75#define DEBUG_AUTOCONF(fmt...) printk(fmt)
76#else
77#define DEBUG_AUTOCONF(fmt...) do { } while (0)
78#endif
79
80#if 0
81#define DEBUG_INTR(fmt...) printk(fmt)
82#else
83#define DEBUG_INTR(fmt...) do { } while (0)
84#endif
85
86#define PASS_LIMIT 256
87
bca47613
DH		 88#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
89
90
1da177e4
LT		 91/*
92 * We default to IRQ0 for the "no irq" hack. Some
93 * machine types want others as well - they're free
94 * to redefine this in their header file.
95 */
96#define is_real_interrupt(irq) ((irq) != 0)
97
1da177e4
LT		 98#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
99#define CONFIG_SERIAL_DETECT_IRQ 1
100#endif
1da177e4
LT		 101#ifdef CONFIG_SERIAL_8250_MANY_PORTS
102#define CONFIG_SERIAL_MANY_PORTS 1
103#endif
104
105/*
106 * HUB6 is always on. This will be removed once the header
107 * files have been cleaned.
108 */
109#define CONFIG_HUB6 1
110
a4ed1e41 111#include <asm/serial.h>
1da177e4
LT		 112/*
113 * SERIAL_PORT_DFNS tells us about built-in ports that have no
114 * standard enumeration mechanism. Platforms that can find all
115 * serial ports via mechanisms like ACPI or PCI need not supply it.
116 */
117#ifndef SERIAL_PORT_DFNS
118#define SERIAL_PORT_DFNS
119#endif
120
cb3592be 121static const struct old_serial_port old_serial_port[] = {
1da177e4
LT		 122 SERIAL_PORT_DFNS /* defined in asm/serial.h */
123};
124
026d02a2 125#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
1da177e4
LT		 126
127#ifdef CONFIG_SERIAL_8250_RSA
128
129#define PORT_RSA_MAX 4
130static unsigned long probe_rsa[PORT_RSA_MAX];
131static unsigned int probe_rsa_count;
132#endif /* CONFIG_SERIAL_8250_RSA */
133
134struct uart_8250_port {
135 struct uart_port port;
136 struct timer_list timer; /* "no irq" timer */
137 struct list_head list; /* ports on this IRQ */
4ba5e35d
RK		 138 unsigned short capabilities; /* port capabilities */
139 unsigned short bugs; /* port bugs */
1da177e4 140 unsigned int tx_loadsz; /* transmit fifo load size */
1da177e4
LT		 141 unsigned char acr;
142 unsigned char ier;
143 unsigned char lcr;
144 unsigned char mcr;
145 unsigned char mcr_mask; /* mask of user bits */
146 unsigned char mcr_force; /* mask of forced bits */
b8e7e40a 147 unsigned char cur_iotype; /* Running I/O type */
ad4c2aa6
CM		 148
149 /*
150 * Some bits in registers are cleared on a read, so they must
151 * be saved whenever the register is read but the bits will not
152 * be immediately processed.
153 */
154#define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
155 unsigned char lsr_saved_flags;
156#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
157 unsigned char msr_saved_flags;
1da177e4
LT		 158};
159
160struct irq_info {
25db8ad5
AC		 161 struct hlist_node node;
162 int irq;
163 spinlock_t lock; /* Protects list not the hash */
1da177e4
LT		 164 struct list_head *head;
165};
166
25db8ad5
AC		 167#define NR_IRQ_HASH 32 /* Can be adjusted later */
168static struct hlist_head irq_lists[NR_IRQ_HASH];
169static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
1da177e4
LT		 170
171/*
172 * Here we define the default xmit fifo size used for each type of UART.
173 */
174static const struct serial8250_config uart_config[] = {
175 [PORT_UNKNOWN] = {
176 .name = "unknown",
177 .fifo_size = 1,
178 .tx_loadsz = 1,
179 },
180 [PORT_8250] = {
181 .name = "8250",
182 .fifo_size = 1,
183 .tx_loadsz = 1,
184 },
185 [PORT_16450] = {
186 .name = "16450",
187 .fifo_size = 1,
188 .tx_loadsz = 1,
189 },
190 [PORT_16550] = {
191 .name = "16550",
192 .fifo_size = 1,
193 .tx_loadsz = 1,
194 },
195 [PORT_16550A] = {
196 .name = "16550A",
197 .fifo_size = 16,
198 .tx_loadsz = 16,
199 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
200 .flags = UART_CAP_FIFO,
201 },
202 [PORT_CIRRUS] = {
203 .name = "Cirrus",
204 .fifo_size = 1,
205 .tx_loadsz = 1,
206 },
207 [PORT_16650] = {
208 .name = "ST16650",
209 .fifo_size = 1,
210 .tx_loadsz = 1,
211 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
212 },
213 [PORT_16650V2] = {
214 .name = "ST16650V2",
215 .fifo_size = 32,
216 .tx_loadsz = 16,
217 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
218 UART_FCR_T_TRIG_00,
219 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
220 },
221 [PORT_16750] = {
222 .name = "TI16750",
223 .fifo_size = 64,
224 .tx_loadsz = 64,
225 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
226 UART_FCR7_64BYTE,
227 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
228 },
229 [PORT_STARTECH] = {
230 .name = "Startech",
231 .fifo_size = 1,
232 .tx_loadsz = 1,
233 },
234 [PORT_16C950] = {
235 .name = "16C950/954",
236 .fifo_size = 128,
237 .tx_loadsz = 128,
238 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
d0694e2a
PM		 239 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
240 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
1da177e4
LT		 241 },
242 [PORT_16654] = {
243 .name = "ST16654",
244 .fifo_size = 64,
245 .tx_loadsz = 32,
246 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
247 UART_FCR_T_TRIG_10,
248 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
249 },
250 [PORT_16850] = {
251 .name = "XR16850",
252 .fifo_size = 128,
253 .tx_loadsz = 128,
254 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
255 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
256 },
257 [PORT_RSA] = {
258 .name = "RSA",
259 .fifo_size = 2048,
260 .tx_loadsz = 2048,
261 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
262 .flags = UART_CAP_FIFO,
263 },
264 [PORT_NS16550A] = {
265 .name = "NS16550A",
266 .fifo_size = 16,
267 .tx_loadsz = 16,
268 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
269 .flags = UART_CAP_FIFO | UART_NATSEMI,
270 },
271 [PORT_XSCALE] = {
272 .name = "XScale",
273 .fifo_size = 32,
274 .tx_loadsz = 32,
275 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
276 .flags = UART_CAP_FIFO | UART_CAP_UUE,
277 },
bd71c182
TK		 278 [PORT_RM9000] = {
279 .name = "RM9000",
280 .fifo_size = 16,
281 .tx_loadsz = 16,
282 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
6b06f191
DD		 283 .flags = UART_CAP_FIFO,
284 },
285 [PORT_OCTEON] = {
286 .name = "OCTEON",
287 .fifo_size = 64,
288 .tx_loadsz = 64,
289 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
bd71c182
TK		 290 .flags = UART_CAP_FIFO,
291 },
08e0992f
FF		 292 [PORT_AR7] = {
293 .name = "AR7",
294 .fifo_size = 16,
295 .tx_loadsz = 16,
296 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
297 .flags = UART_CAP_FIFO | UART_CAP_AFE,
298 },
235dae5d
PL		 299 [PORT_U6_16550A] = {
300 .name = "U6_16550A",
301 .fifo_size = 64,
302 .tx_loadsz = 64,
303 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
304 .flags = UART_CAP_FIFO | UART_CAP_AFE,
305 },
1da177e4
LT		 306};
307
12bf3f24 308#if defined(CONFIG_MIPS_ALCHEMY)
21c614a7
PA		 309
310/* Au1x00 UART hardware has a weird register layout */
311static const u8 au_io_in_map[] = {
312 [UART_RX] = 0,
313 [UART_IER] = 2,
314 [UART_IIR] = 3,
315 [UART_LCR] = 5,
316 [UART_MCR] = 6,
317 [UART_LSR] = 7,
318 [UART_MSR] = 8,
319};
320
321static const u8 au_io_out_map[] = {
322 [UART_TX] = 1,
323 [UART_IER] = 2,
324 [UART_FCR] = 4,
325 [UART_LCR] = 5,
326 [UART_MCR] = 6,
327};
328
329/* sane hardware needs no mapping */
7d6a07d1 330static inline int map_8250_in_reg(struct uart_port *p, int offset)
21c614a7 331{
7d6a07d1 332 if (p->iotype != UPIO_AU)
21c614a7
PA		 333 return offset;
334 return au_io_in_map[offset];
335}
336
7d6a07d1 337static inline int map_8250_out_reg(struct uart_port *p, int offset)
21c614a7 338{
7d6a07d1 339 if (p->iotype != UPIO_AU)
21c614a7
PA		 340 return offset;
341 return au_io_out_map[offset];
342}
343
6f803cd0 344#elif defined(CONFIG_SERIAL_8250_RM9K)
bd71c182
TK		 345
346static const u8
347 regmap_in[8] = {
348 [UART_RX] = 0x00,
349 [UART_IER] = 0x0c,
350 [UART_IIR] = 0x14,
351 [UART_LCR] = 0x1c,
352 [UART_MCR] = 0x20,
353 [UART_LSR] = 0x24,
354 [UART_MSR] = 0x28,
355 [UART_SCR] = 0x2c
356 },
357 regmap_out[8] = {
358 [UART_TX] = 0x04,
359 [UART_IER] = 0x0c,
360 [UART_FCR] = 0x18,
361 [UART_LCR] = 0x1c,
362 [UART_MCR] = 0x20,
363 [UART_LSR] = 0x24,
364 [UART_MSR] = 0x28,
365 [UART_SCR] = 0x2c
366 };
367
7d6a07d1 368static inline int map_8250_in_reg(struct uart_port *p, int offset)
bd71c182 369{
7d6a07d1 370 if (p->iotype != UPIO_RM9000)
bd71c182
TK		 371 return offset;
372 return regmap_in[offset];
373}
374
7d6a07d1 375static inline int map_8250_out_reg(struct uart_port *p, int offset)
bd71c182 376{
7d6a07d1 377 if (p->iotype != UPIO_RM9000)
bd71c182
TK		 378 return offset;
379 return regmap_out[offset];
380}
381
21c614a7
PA		 382#else
383
384/* sane hardware needs no mapping */
385#define map_8250_in_reg(up, offset) (offset)
386#define map_8250_out_reg(up, offset) (offset)
387
388#endif
389
7d6a07d1 390static unsigned int hub6_serial_in(struct uart_port *p, int offset)
1da177e4 391{
7d6a07d1
DD		 392 offset = map_8250_in_reg(p, offset) << p->regshift;
393 outb(p->hub6 - 1 + offset, p->iobase);
394 return inb(p->iobase + 1);
395}
1da177e4 396
7d6a07d1
DD		 397static void hub6_serial_out(struct uart_port *p, int offset, int value)
398{
399 offset = map_8250_out_reg(p, offset) << p->regshift;
400 outb(p->hub6 - 1 + offset, p->iobase);
401 outb(value, p->iobase + 1);
402}
1da177e4 403
7d6a07d1
DD		 404static unsigned int mem_serial_in(struct uart_port *p, int offset)
405{
406 offset = map_8250_in_reg(p, offset) << p->regshift;
407 return readb(p->membase + offset);
408}
1da177e4 409
7d6a07d1
DD		 410static void mem_serial_out(struct uart_port *p, int offset, int value)
411{
412 offset = map_8250_out_reg(p, offset) << p->regshift;
413 writeb(value, p->membase + offset);
414}
415
416static void mem32_serial_out(struct uart_port *p, int offset, int value)
417{
418 offset = map_8250_out_reg(p, offset) << p->regshift;
419 writel(value, p->membase + offset);
420}
421
422static unsigned int mem32_serial_in(struct uart_port *p, int offset)
423{
424 offset = map_8250_in_reg(p, offset) << p->regshift;
425 return readl(p->membase + offset);
426}
1da177e4 427
7d6a07d1
DD		 428static unsigned int au_serial_in(struct uart_port *p, int offset)
429{
430 offset = map_8250_in_reg(p, offset) << p->regshift;
431 return __raw_readl(p->membase + offset);
432}
433
434static void au_serial_out(struct uart_port *p, int offset, int value)
435{
436 offset = map_8250_out_reg(p, offset) << p->regshift;
437 __raw_writel(value, p->membase + offset);
438}
21c614a7 439
7d6a07d1
DD		 440static unsigned int tsi_serial_in(struct uart_port *p, int offset)
441{
442 unsigned int tmp;
443 offset = map_8250_in_reg(p, offset) << p->regshift;
444 if (offset == UART_IIR) {
445 tmp = readl(p->membase + (UART_IIR & ~3));
446 return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
447 } else
448 return readb(p->membase + offset);
449}
3be91ec7 450
7d6a07d1
DD		 451static void tsi_serial_out(struct uart_port *p, int offset, int value)
452{
453 offset = map_8250_out_reg(p, offset) << p->regshift;
454 if (!((offset == UART_IER) && (value & UART_IER_UUE)))
455 writeb(value, p->membase + offset);
1da177e4
LT		 456}
457
a3ae0fc3
JI		 458/* Save the LCR value so it can be re-written when a Busy Detect IRQ occurs. */
459static inline void dwapb_save_out_value(struct uart_port *p, int offset,
460 int value)
461{
462 struct uart_8250_port *up =
463 container_of(p, struct uart_8250_port, port);
464
465 if (offset == UART_LCR)
466 up->lcr = value;
467}
468
469/* Read the IER to ensure any interrupt is cleared before returning from ISR. */
470static inline void dwapb_check_clear_ier(struct uart_port *p, int offset)
471{
472 if (offset == UART_TX || offset == UART_IER)
473 p->serial_in(p, UART_IER);
474}
475
7d6a07d1 476static void dwapb_serial_out(struct uart_port *p, int offset, int value)
1da177e4 477{
beab697a 478 int save_offset = offset;
7d6a07d1 479 offset = map_8250_out_reg(p, offset) << p->regshift;
a3ae0fc3 480 dwapb_save_out_value(p, save_offset, value);
7d6a07d1 481 writeb(value, p->membase + offset);
a3ae0fc3
JI		 482 dwapb_check_clear_ier(p, save_offset);
483}
484
485static void dwapb32_serial_out(struct uart_port *p, int offset, int value)
486{
487 int save_offset = offset;
488 offset = map_8250_out_reg(p, offset) << p->regshift;
489 dwapb_save_out_value(p, save_offset, value);
490 writel(value, p->membase + offset);
491 dwapb_check_clear_ier(p, save_offset);
7d6a07d1 492}
1da177e4 493
7d6a07d1
DD		 494static unsigned int io_serial_in(struct uart_port *p, int offset)
495{
496 offset = map_8250_in_reg(p, offset) << p->regshift;
497 return inb(p->iobase + offset);
498}
499
500static void io_serial_out(struct uart_port *p, int offset, int value)
501{
502 offset = map_8250_out_reg(p, offset) << p->regshift;
503 outb(value, p->iobase + offset);
504}
505
506static void set_io_from_upio(struct uart_port *p)
507{
49d5741b
JI		 508 struct uart_8250_port *up =
509 container_of(p, struct uart_8250_port, port);
7d6a07d1 510 switch (p->iotype) {
1da177e4 511 case UPIO_HUB6:
7d6a07d1
DD		 512 p->serial_in = hub6_serial_in;
513 p->serial_out = hub6_serial_out;
1da177e4
LT		 514 break;
515
516 case UPIO_MEM:
7d6a07d1
DD		 517 p->serial_in = mem_serial_in;
518 p->serial_out = mem_serial_out;
1da177e4
LT		 519 break;
520
bd71c182 521 case UPIO_RM9000:
1da177e4 522 case UPIO_MEM32:
7d6a07d1
DD		 523 p->serial_in = mem32_serial_in;
524 p->serial_out = mem32_serial_out;
1da177e4
LT		 525 break;
526
21c614a7 527 case UPIO_AU:
7d6a07d1
DD		 528 p->serial_in = au_serial_in;
529 p->serial_out = au_serial_out;
21c614a7 530 break;
12bf3f24 531
3be91ec7 532 case UPIO_TSI:
7d6a07d1
DD		 533 p->serial_in = tsi_serial_in;
534 p->serial_out = tsi_serial_out;
3be91ec7 535 break;
21c614a7 536
beab697a 537 case UPIO_DWAPB:
7d6a07d1
DD		 538 p->serial_in = mem_serial_in;
539 p->serial_out = dwapb_serial_out;
beab697a
MSJ		 540 break;
541
a3ae0fc3
JI		 542 case UPIO_DWAPB32:
543 p->serial_in = mem32_serial_in;
544 p->serial_out = dwapb32_serial_out;
545 break;
546
1da177e4 547 default:
7d6a07d1
DD		 548 p->serial_in = io_serial_in;
549 p->serial_out = io_serial_out;
550 break;
1da177e4 551 }
b8e7e40a
AC		 552 /* Remember loaded iotype */
553 up->cur_iotype = p->iotype;
1da177e4
LT		 554}
555
40b36daa
AW		 556static void
557serial_out_sync(struct uart_8250_port *up, int offset, int value)
558{
7d6a07d1
DD		 559 struct uart_port *p = &up->port;
560 switch (p->iotype) {
40b36daa
AW		 561 case UPIO_MEM:
562 case UPIO_MEM32:
40b36daa 563 case UPIO_AU:
beab697a 564 case UPIO_DWAPB:
a3ae0fc3 565 case UPIO_DWAPB32:
7d6a07d1
DD		 566 p->serial_out(p, offset, value);
567 p->serial_in(p, UART_LCR); /* safe, no side-effects */
40b36daa
AW		 568 break;
569 default:
7d6a07d1 570 p->serial_out(p, offset, value);
40b36daa
AW		 571 }
572}
573
7d6a07d1
DD		 574#define serial_in(up, offset) \
575 (up->port.serial_in(&(up)->port, (offset)))
576#define serial_out(up, offset, value) \
577 (up->port.serial_out(&(up)->port, (offset), (value)))
1da177e4
LT		 578/*
579 * We used to support using pause I/O for certain machines. We
580 * haven't supported this for a while, but just in case it's badly
581 * needed for certain old 386 machines, I've left these #define's
582 * in....
583 */
584#define serial_inp(up, offset) serial_in(up, offset)
585#define serial_outp(up, offset, value) serial_out(up, offset, value)
586
b32b19b8
JAH		 587/* Uart divisor latch read */
588static inline int _serial_dl_read(struct uart_8250_port *up)
589{
590 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
591}
592
593/* Uart divisor latch write */
594static inline void _serial_dl_write(struct uart_8250_port *up, int value)
595{
596 serial_outp(up, UART_DLL, value & 0xff);
597 serial_outp(up, UART_DLM, value >> 8 & 0xff);
598}
599
12bf3f24 600#if defined(CONFIG_MIPS_ALCHEMY)
b32b19b8
JAH		 601/* Au1x00 haven't got a standard divisor latch */
602static int serial_dl_read(struct uart_8250_port *up)
603{
604 if (up->port.iotype == UPIO_AU)
605 return __raw_readl(up->port.membase + 0x28);
606 else
607 return _serial_dl_read(up);
608}
609
610static void serial_dl_write(struct uart_8250_port *up, int value)
611{
612 if (up->port.iotype == UPIO_AU)
613 __raw_writel(value, up->port.membase + 0x28);
614 else
615 _serial_dl_write(up, value);
616}
6f803cd0 617#elif defined(CONFIG_SERIAL_8250_RM9K)
bd71c182
TK		 618static int serial_dl_read(struct uart_8250_port *up)
619{
620 return (up->port.iotype == UPIO_RM9000) ?
621 (((__raw_readl(up->port.membase + 0x10) << 8) |
622 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
623 _serial_dl_read(up);
624}
625
626static void serial_dl_write(struct uart_8250_port *up, int value)
627{
628 if (up->port.iotype == UPIO_RM9000) {
629 __raw_writel(value, up->port.membase + 0x08);
630 __raw_writel(value >> 8, up->port.membase + 0x10);
631 } else {
632 _serial_dl_write(up, value);
633 }
634}
b32b19b8
JAH		 635#else
636#define serial_dl_read(up) _serial_dl_read(up)
637#define serial_dl_write(up, value) _serial_dl_write(up, value)
638#endif
1da177e4
LT		 639
640/*
641 * For the 16C950
642 */
643static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
644{
645 serial_out(up, UART_SCR, offset);
646 serial_out(up, UART_ICR, value);
647}
648
649static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
650{
651 unsigned int value;
652
653 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
654 serial_out(up, UART_SCR, offset);
655 value = serial_in(up, UART_ICR);
656 serial_icr_write(up, UART_ACR, up->acr);
657
658 return value;
659}
660
661/*
662 * FIFO support.
663 */
b5d674ab 664static void serial8250_clear_fifos(struct uart_8250_port *p)
1da177e4
LT		 665{
666 if (p->capabilities & UART_CAP_FIFO) {
667 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
668 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
669 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
670 serial_outp(p, UART_FCR, 0);
671 }
672}
673
674/*
675 * IER sleep support. UARTs which have EFRs need the "extended
676 * capability" bit enabled. Note that on XR16C850s, we need to
677 * reset LCR to write to IER.
678 */
b5d674ab 679static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
1da177e4
LT		 680{
681 if (p->capabilities & UART_CAP_SLEEP) {
682 if (p->capabilities & UART_CAP_EFR) {
662b083a 683 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 684 serial_outp(p, UART_EFR, UART_EFR_ECB);
685 serial_outp(p, UART_LCR, 0);
686 }
687 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
688 if (p->capabilities & UART_CAP_EFR) {
662b083a 689 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 690 serial_outp(p, UART_EFR, 0);
691 serial_outp(p, UART_LCR, 0);
692 }
693 }
694}
695
696#ifdef CONFIG_SERIAL_8250_RSA
697/*
698 * Attempts to turn on the RSA FIFO. Returns zero on failure.
699 * We set the port uart clock rate if we succeed.
700 */
701static int __enable_rsa(struct uart_8250_port *up)
702{
703 unsigned char mode;
704 int result;
705
706 mode = serial_inp(up, UART_RSA_MSR);
707 result = mode & UART_RSA_MSR_FIFO;
708
709 if (!result) {
710 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
711 mode = serial_inp(up, UART_RSA_MSR);
712 result = mode & UART_RSA_MSR_FIFO;
713 }
714
715 if (result)
716 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
717
718 return result;
719}
720
721static void enable_rsa(struct uart_8250_port *up)
722{
723 if (up->port.type == PORT_RSA) {
724 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
725 spin_lock_irq(&up->port.lock);
726 __enable_rsa(up);
727 spin_unlock_irq(&up->port.lock);
728 }
729 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
730 serial_outp(up, UART_RSA_FRR, 0);
731 }
732}
733
734/*
735 * Attempts to turn off the RSA FIFO. Returns zero on failure.
736 * It is unknown why interrupts were disabled in here. However,
737 * the caller is expected to preserve this behaviour by grabbing
738 * the spinlock before calling this function.
739 */
740static void disable_rsa(struct uart_8250_port *up)
741{
742 unsigned char mode;
743 int result;
744
745 if (up->port.type == PORT_RSA &&
746 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
747 spin_lock_irq(&up->port.lock);
748
749 mode = serial_inp(up, UART_RSA_MSR);
750 result = !(mode & UART_RSA_MSR_FIFO);
751
752 if (!result) {
753 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
754 mode = serial_inp(up, UART_RSA_MSR);
755 result = !(mode & UART_RSA_MSR_FIFO);
756 }
757
758 if (result)
759 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
760 spin_unlock_irq(&up->port.lock);
761 }
762}
763#endif /* CONFIG_SERIAL_8250_RSA */
764
765/*
766 * This is a quickie test to see how big the FIFO is.
767 * It doesn't work at all the time, more's the pity.
768 */
769static int size_fifo(struct uart_8250_port *up)
770{
b32b19b8
JAH		 771 unsigned char old_fcr, old_mcr, old_lcr;
772 unsigned short old_dl;
1da177e4
LT		 773 int count;
774
775 old_lcr = serial_inp(up, UART_LCR);
776 serial_outp(up, UART_LCR, 0);
777 old_fcr = serial_inp(up, UART_FCR);
778 old_mcr = serial_inp(up, UART_MCR);
779 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
780 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
781 serial_outp(up, UART_MCR, UART_MCR_LOOP);
662b083a 782 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
b32b19b8
JAH		 783 old_dl = serial_dl_read(up);
784 serial_dl_write(up, 0x0001);
1da177e4
LT		 785 serial_outp(up, UART_LCR, 0x03);
786 for (count = 0; count < 256; count++)
787 serial_outp(up, UART_TX, count);
788 mdelay(20);/* FIXME - schedule_timeout */
789 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
790 (count < 256); count++)
791 serial_inp(up, UART_RX);
792 serial_outp(up, UART_FCR, old_fcr);
793 serial_outp(up, UART_MCR, old_mcr);
662b083a 794 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
b32b19b8 795 serial_dl_write(up, old_dl);
1da177e4
LT		 796 serial_outp(up, UART_LCR, old_lcr);
797
798 return count;
799}
800
801/*
802 * Read UART ID using the divisor method - set DLL and DLM to zero
803 * and the revision will be in DLL and device type in DLM. We
804 * preserve the device state across this.
805 */
806static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
807{
808 unsigned char old_dll, old_dlm, old_lcr;
809 unsigned int id;
810
811 old_lcr = serial_inp(p, UART_LCR);
662b083a 812 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_A);
1da177e4
LT		 813
814 old_dll = serial_inp(p, UART_DLL);
815 old_dlm = serial_inp(p, UART_DLM);
816
817 serial_outp(p, UART_DLL, 0);
818 serial_outp(p, UART_DLM, 0);
819
820 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
821
822 serial_outp(p, UART_DLL, old_dll);
823 serial_outp(p, UART_DLM, old_dlm);
824 serial_outp(p, UART_LCR, old_lcr);
825
826 return id;
827}
828
829/*
830 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
831 * When this function is called we know it is at least a StarTech
832 * 16650 V2, but it might be one of several StarTech UARTs, or one of
833 * its clones. (We treat the broken original StarTech 16650 V1 as a
834 * 16550, and why not? Startech doesn't seem to even acknowledge its
835 * existence.)
bd71c182 836 *
1da177e4
LT		 837 * What evil have men's minds wrought...
838 */
839static void autoconfig_has_efr(struct uart_8250_port *up)
840{
841 unsigned int id1, id2, id3, rev;
842
843 /*
844 * Everything with an EFR has SLEEP
845 */
846 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
847
848 /*
849 * First we check to see if it's an Oxford Semiconductor UART.
850 *
851 * If we have to do this here because some non-National
852 * Semiconductor clone chips lock up if you try writing to the
853 * LSR register (which serial_icr_read does)
854 */
855
856 /*
857 * Check for Oxford Semiconductor 16C950.
858 *
859 * EFR [4] must be set else this test fails.
860 *
861 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
862 * claims that it's needed for 952 dual UART's (which are not
863 * recommended for new designs).
864 */
865 up->acr = 0;
662b083a 866 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 867 serial_out(up, UART_EFR, UART_EFR_ECB);
868 serial_out(up, UART_LCR, 0x00);
869 id1 = serial_icr_read(up, UART_ID1);
870 id2 = serial_icr_read(up, UART_ID2);
871 id3 = serial_icr_read(up, UART_ID3);
872 rev = serial_icr_read(up, UART_REV);
873
874 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
875
876 if (id1 == 0x16 && id2 == 0xC9 &&
877 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
878 up->port.type = PORT_16C950;
4ba5e35d
RK		 879
880 /*
881 * Enable work around for the Oxford Semiconductor 952 rev B
882 * chip which causes it to seriously miscalculate baud rates
883 * when DLL is 0.
884 */
885 if (id3 == 0x52 && rev == 0x01)
886 up->bugs |= UART_BUG_QUOT;
1da177e4
LT		 887 return;
888 }
bd71c182 889
1da177e4
LT		 890 /*
891 * We check for a XR16C850 by setting DLL and DLM to 0, and then
892 * reading back DLL and DLM. The chip type depends on the DLM
893 * value read back:
894 * 0x10 - XR16C850 and the DLL contains the chip revision.
895 * 0x12 - XR16C2850.
896 * 0x14 - XR16C854.
897 */
898 id1 = autoconfig_read_divisor_id(up);
899 DEBUG_AUTOCONF("850id=%04x ", id1);
900
901 id2 = id1 >> 8;
902 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
1da177e4
LT		 903 up->port.type = PORT_16850;
904 return;
905 }
906
907 /*
908 * It wasn't an XR16C850.
909 *
910 * We distinguish between the '654 and the '650 by counting
911 * how many bytes are in the FIFO. I'm using this for now,
912 * since that's the technique that was sent to me in the
913 * serial driver update, but I'm not convinced this works.
914 * I've had problems doing this in the past. -TYT
915 */
916 if (size_fifo(up) == 64)
917 up->port.type = PORT_16654;
918 else
919 up->port.type = PORT_16650V2;
920}
921
922/*
923 * We detected a chip without a FIFO. Only two fall into
924 * this category - the original 8250 and the 16450. The
925 * 16450 has a scratch register (accessible with LCR=0)
926 */
927static void autoconfig_8250(struct uart_8250_port *up)
928{
929 unsigned char scratch, status1, status2;
930
931 up->port.type = PORT_8250;
932
933 scratch = serial_in(up, UART_SCR);
934 serial_outp(up, UART_SCR, 0xa5);
935 status1 = serial_in(up, UART_SCR);
936 serial_outp(up, UART_SCR, 0x5a);
937 status2 = serial_in(up, UART_SCR);
938 serial_outp(up, UART_SCR, scratch);
939
940 if (status1 == 0xa5 && status2 == 0x5a)
941 up->port.type = PORT_16450;
942}
943
944static int broken_efr(struct uart_8250_port *up)
945{
946 /*
947 * Exar ST16C2550 "A2" devices incorrectly detect as
948 * having an EFR, and report an ID of 0x0201. See
631dd1a8 949 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
1da177e4
LT		 950 */
951 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
952 return 1;
953
954 return 0;
955}
956
0d0389e5
YK		 957static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
958{
959 unsigned char status;
960
961 status = serial_in(up, 0x04); /* EXCR2 */
962#define PRESL(x) ((x) & 0x30)
963 if (PRESL(status) == 0x10) {
964 /* already in high speed mode */
965 return 0;
966 } else {
967 status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
968 status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
969 serial_outp(up, 0x04, status);
970 }
971 return 1;
972}
973
1da177e4
LT		 974/*
975 * We know that the chip has FIFOs. Does it have an EFR? The
976 * EFR is located in the same register position as the IIR and
977 * we know the top two bits of the IIR are currently set. The
978 * EFR should contain zero. Try to read the EFR.
979 */
980static void autoconfig_16550a(struct uart_8250_port *up)
981{
982 unsigned char status1, status2;
983 unsigned int iersave;
984
985 up->port.type = PORT_16550A;
986 up->capabilities |= UART_CAP_FIFO;
987
988 /*
989 * Check for presence of the EFR when DLAB is set.
990 * Only ST16C650V1 UARTs pass this test.
991 */
662b083a 992 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
1da177e4
LT		 993 if (serial_in(up, UART_EFR) == 0) {
994 serial_outp(up, UART_EFR, 0xA8);
995 if (serial_in(up, UART_EFR) != 0) {
996 DEBUG_AUTOCONF("EFRv1 ");
997 up->port.type = PORT_16650;
998 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
999 } else {
1000 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1001 }
1002 serial_outp(up, UART_EFR, 0);
1003 return;
1004 }
1005
1006 /*
1007 * Maybe it requires 0xbf to be written to the LCR.
1008 * (other ST16C650V2 UARTs, TI16C752A, etc)
1009 */
662b083a 1010 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 1011 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
1012 DEBUG_AUTOCONF("EFRv2 ");
1013 autoconfig_has_efr(up);
1014 return;
1015 }
1016
1017 /*
1018 * Check for a National Semiconductor SuperIO chip.
1019 * Attempt to switch to bank 2, read the value of the LOOP bit
1020 * from EXCR1. Switch back to bank 0, change it in MCR. Then
1021 * switch back to bank 2, read it from EXCR1 again and check
1022 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1da177e4
LT		 1023 */
1024 serial_outp(up, UART_LCR, 0);
1025 status1 = serial_in(up, UART_MCR);
1026 serial_outp(up, UART_LCR, 0xE0);
1027 status2 = serial_in(up, 0x02); /* EXCR1 */
1028
1029 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1030 serial_outp(up, UART_LCR, 0);
1031 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
1032 serial_outp(up, UART_LCR, 0xE0);
1033 status2 = serial_in(up, 0x02); /* EXCR1 */
1034 serial_outp(up, UART_LCR, 0);
1035 serial_outp(up, UART_MCR, status1);
1036
1037 if ((status2 ^ status1) & UART_MCR_LOOP) {
857dde2e
DW		 1038 unsigned short quot;
1039
1da177e4 1040 serial_outp(up, UART_LCR, 0xE0);
857dde2e 1041
b32b19b8 1042 quot = serial_dl_read(up);
857dde2e
DW		 1043 quot <<= 3;
1044
0d0389e5
YK		 1045 if (ns16550a_goto_highspeed(up))
1046 serial_dl_write(up, quot);
857dde2e 1047
1da177e4 1048 serial_outp(up, UART_LCR, 0);
1da177e4 1049
857dde2e 1050 up->port.uartclk = 921600*16;
1da177e4
LT		 1051 up->port.type = PORT_NS16550A;
1052 up->capabilities |= UART_NATSEMI;
1053 return;
1054 }
1055 }
1056
1057 /*
1058 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1059 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1060 * Try setting it with and without DLAB set. Cheap clones
1061 * set bit 5 without DLAB set.
1062 */
1063 serial_outp(up, UART_LCR, 0);
1064 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1065 status1 = serial_in(up, UART_IIR) >> 5;
1066 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
662b083a 1067 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
1da177e4
LT		 1068 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1069 status2 = serial_in(up, UART_IIR) >> 5;
1070 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1071 serial_outp(up, UART_LCR, 0);
1072
1073 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1074
1075 if (status1 == 6 && status2 == 7) {
1076 up->port.type = PORT_16750;
1077 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1078 return;
1079 }
1080
1081 /*
1082 * Try writing and reading the UART_IER_UUE bit (b6).
1083 * If it works, this is probably one of the Xscale platform's
1084 * internal UARTs.
1085 * We're going to explicitly set the UUE bit to 0 before
1086 * trying to write and read a 1 just to make sure it's not
1087 * already a 1 and maybe locked there before we even start start.
1088 */
1089 iersave = serial_in(up, UART_IER);
1090 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
1091 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1092 /*
1093 * OK it's in a known zero state, try writing and reading
1094 * without disturbing the current state of the other bits.
1095 */
1096 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
1097 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1098 /*
1099 * It's an Xscale.
1100 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1101 */
1102 DEBUG_AUTOCONF("Xscale ");
1103 up->port.type = PORT_XSCALE;
1104 up->capabilities |= UART_CAP_UUE;
1105 return;
1106 }
1107 } else {
1108 /*
1109 * If we got here we couldn't force the IER_UUE bit to 0.
1110 * Log it and continue.
1111 */
1112 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1113 }
1114 serial_outp(up, UART_IER, iersave);
235dae5d
PL		 1115
1116 /*
1117 * We distinguish between 16550A and U6 16550A by counting
1118 * how many bytes are in the FIFO.
1119 */
1120 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1121 up->port.type = PORT_U6_16550A;
1122 up->capabilities |= UART_CAP_AFE;
1123 }
1da177e4
LT		 1124}
1125
1126/*
1127 * This routine is called by rs_init() to initialize a specific serial
1128 * port. It determines what type of UART chip this serial port is
1129 * using: 8250, 16450, 16550, 16550A. The important question is
1130 * whether or not this UART is a 16550A or not, since this will
1131 * determine whether or not we can use its FIFO features or not.
1132 */
1133static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1134{
1135 unsigned char status1, scratch, scratch2, scratch3;
1136 unsigned char save_lcr, save_mcr;
1137 unsigned long flags;
1138
1139 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
1140 return;
1141
80647b95 1142 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
8440838b 1143 serial_index(&up->port), up->port.iobase, up->port.membase);
1da177e4
LT		 1144
1145 /*
1146 * We really do need global IRQs disabled here - we're going to
1147 * be frobbing the chips IRQ enable register to see if it exists.
1148 */
1149 spin_lock_irqsave(&up->port.lock, flags);
1da177e4
LT		 1150
1151 up->capabilities = 0;
4ba5e35d 1152 up->bugs = 0;
1da177e4
LT		 1153
1154 if (!(up->port.flags & UPF_BUGGY_UART)) {
1155 /*
1156 * Do a simple existence test first; if we fail this,
1157 * there's no point trying anything else.
bd71c182 1158 *
1da177e4
LT		 1159 * 0x80 is used as a nonsense port to prevent against
1160 * false positives due to ISA bus float. The
1161 * assumption is that 0x80 is a non-existent port;
1162 * which should be safe since include/asm/io.h also
1163 * makes this assumption.
1164 *
1165 * Note: this is safe as long as MCR bit 4 is clear
1166 * and the device is in "PC" mode.
1167 */
1168 scratch = serial_inp(up, UART_IER);
1169 serial_outp(up, UART_IER, 0);
1170#ifdef __i386__
1171 outb(0xff, 0x080);
1172#endif
48212008
TH		 1173 /*
1174 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1175 * 16C754B) allow only to modify them if an EFR bit is set.
1176 */
1177 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1da177e4
LT		 1178 serial_outp(up, UART_IER, 0x0F);
1179#ifdef __i386__
1180 outb(0, 0x080);
1181#endif
48212008 1182 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1da177e4
LT		 1183 serial_outp(up, UART_IER, scratch);
1184 if (scratch2 != 0 || scratch3 != 0x0F) {
1185 /*
1186 * We failed; there's nothing here
1187 */
1188 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1189 scratch2, scratch3);
1190 goto out;
1191 }
1192 }
1193
1194 save_mcr = serial_in(up, UART_MCR);
1195 save_lcr = serial_in(up, UART_LCR);
1196
bd71c182 1197 /*
1da177e4
LT		 1198 * Check to see if a UART is really there. Certain broken
1199 * internal modems based on the Rockwell chipset fail this
1200 * test, because they apparently don't implement the loopback
1201 * test mode. So this test is skipped on the COM 1 through
1202 * COM 4 ports. This *should* be safe, since no board
1203 * manufacturer would be stupid enough to design a board
1204 * that conflicts with COM 1-4 --- we hope!
1205 */
1206 if (!(up->port.flags & UPF_SKIP_TEST)) {
1207 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1208 status1 = serial_inp(up, UART_MSR) & 0xF0;
1209 serial_outp(up, UART_MCR, save_mcr);
1210 if (status1 != 0x90) {
1211 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1212 status1);
1213 goto out;
1214 }
1215 }
1216
1217 /*
1218 * We're pretty sure there's a port here. Lets find out what
1219 * type of port it is. The IIR top two bits allows us to find
6f0d618f 1220 * out if it's 8250 or 16450, 16550, 16550A or later. This
1da177e4
LT		 1221 * determines what we test for next.
1222 *
1223 * We also initialise the EFR (if any) to zero for later. The
1224 * EFR occupies the same register location as the FCR and IIR.
1225 */
662b083a 1226 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 1227 serial_outp(up, UART_EFR, 0);
1228 serial_outp(up, UART_LCR, 0);
1229
1230 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1231 scratch = serial_in(up, UART_IIR) >> 6;
1232
1233 DEBUG_AUTOCONF("iir=%d ", scratch);
1234
1235 switch (scratch) {
1236 case 0:
1237 autoconfig_8250(up);
1238 break;
1239 case 1:
1240 up->port.type = PORT_UNKNOWN;
1241 break;
1242 case 2:
1243 up->port.type = PORT_16550;
1244 break;
1245 case 3:
1246 autoconfig_16550a(up);
1247 break;
1248 }
1249
1250#ifdef CONFIG_SERIAL_8250_RSA
1251 /*
1252 * Only probe for RSA ports if we got the region.
1253 */
1254 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1255 int i;
1256
1257 for (i = 0 ; i < probe_rsa_count; ++i) {
1258 if (probe_rsa[i] == up->port.iobase &&
1259 __enable_rsa(up)) {
1260 up->port.type = PORT_RSA;
1261 break;
1262 }
1263 }
1264 }
1265#endif
21c614a7 1266
1da177e4
LT		 1267 serial_outp(up, UART_LCR, save_lcr);
1268
1269 if (up->capabilities != uart_config[up->port.type].flags) {
1270 printk(KERN_WARNING
1271 "ttyS%d: detected caps %08x should be %08x\n",
8440838b
DM		 1272 serial_index(&up->port), up->capabilities,
1273 uart_config[up->port.type].flags);
1da177e4
LT		 1274 }
1275
1276 up->port.fifosize = uart_config[up->port.type].fifo_size;
1277 up->capabilities = uart_config[up->port.type].flags;
1278 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1279
1280 if (up->port.type == PORT_UNKNOWN)
1281 goto out;
1282
1283 /*
1284 * Reset the UART.
1285 */
1286#ifdef CONFIG_SERIAL_8250_RSA
1287 if (up->port.type == PORT_RSA)
1288 serial_outp(up, UART_RSA_FRR, 0);
1289#endif
1290 serial_outp(up, UART_MCR, save_mcr);
1291 serial8250_clear_fifos(up);
40b36daa 1292 serial_in(up, UART_RX);
5c8c755c
LB		 1293 if (up->capabilities & UART_CAP_UUE)
1294 serial_outp(up, UART_IER, UART_IER_UUE);
1295 else
1296 serial_outp(up, UART_IER, 0);
1da177e4 1297
bd71c182 1298 out:
1da177e4 1299 spin_unlock_irqrestore(&up->port.lock, flags);
1da177e4
LT		 1300 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1301}
1302
1303static void autoconfig_irq(struct uart_8250_port *up)
1304{
1305 unsigned char save_mcr, save_ier;
1306 unsigned char save_ICP = 0;
1307 unsigned int ICP = 0;
1308 unsigned long irqs;
1309 int irq;
1310
1311 if (up->port.flags & UPF_FOURPORT) {
1312 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1313 save_ICP = inb_p(ICP);
1314 outb_p(0x80, ICP);
1315 (void) inb_p(ICP);
1316 }
1317
1318 /* forget possible initially masked and pending IRQ */
1319 probe_irq_off(probe_irq_on());
1320 save_mcr = serial_inp(up, UART_MCR);
1321 save_ier = serial_inp(up, UART_IER);
1322 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
bd71c182 1323
1da177e4
LT		 1324 irqs = probe_irq_on();
1325 serial_outp(up, UART_MCR, 0);
6f803cd0
AC		 1326 udelay(10);
1327 if (up->port.flags & UPF_FOURPORT) {
1da177e4
LT		 1328 serial_outp(up, UART_MCR,
1329 UART_MCR_DTR | UART_MCR_RTS);
1330 } else {
1331 serial_outp(up, UART_MCR,
1332 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1333 }
1334 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1335 (void)serial_inp(up, UART_LSR);
1336 (void)serial_inp(up, UART_RX);
1337 (void)serial_inp(up, UART_IIR);
1338 (void)serial_inp(up, UART_MSR);
1339 serial_outp(up, UART_TX, 0xFF);
6f803cd0 1340 udelay(20);
1da177e4
LT		 1341 irq = probe_irq_off(irqs);
1342
1343 serial_outp(up, UART_MCR, save_mcr);
1344 serial_outp(up, UART_IER, save_ier);
1345
1346 if (up->port.flags & UPF_FOURPORT)
1347 outb_p(save_ICP, ICP);
1348
1349 up->port.irq = (irq > 0) ? irq : 0;
1350}
1351
e763b90c
RK		 1352static inline void __stop_tx(struct uart_8250_port *p)
1353{
1354 if (p->ier & UART_IER_THRI) {
1355 p->ier &= ~UART_IER_THRI;
1356 serial_out(p, UART_IER, p->ier);
1357 }
1358}
1359
b129a8cc 1360static void serial8250_stop_tx(struct uart_port *port)
1da177e4 1361{
49d5741b
JI		 1362 struct uart_8250_port *up =
1363 container_of(port, struct uart_8250_port, port);
1da177e4 1364
e763b90c 1365 __stop_tx(up);
1da177e4
LT		 1366
1367 /*
e763b90c 1368 * We really want to stop the transmitter from sending.
1da177e4 1369 */
e763b90c 1370 if (up->port.type == PORT_16C950) {
1da177e4
LT		 1371 up->acr |= UART_ACR_TXDIS;
1372 serial_icr_write(up, UART_ACR, up->acr);
1373 }
1374}
1375
55d3b282
RK		 1376static void transmit_chars(struct uart_8250_port *up);
1377
b129a8cc 1378static void serial8250_start_tx(struct uart_port *port)
1da177e4 1379{
49d5741b
JI		 1380 struct uart_8250_port *up =
1381 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1382
1383 if (!(up->ier & UART_IER_THRI)) {
1384 up->ier |= UART_IER_THRI;
1385 serial_out(up, UART_IER, up->ier);
55d3b282 1386
67f7654e 1387 if (up->bugs & UART_BUG_TXEN) {
68cb4f8e 1388 unsigned char lsr;
55d3b282 1389 lsr = serial_in(up, UART_LSR);
ad4c2aa6 1390 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
bd71c182 1391 if ((up->port.type == PORT_RM9000) ?
68cb4f8e
IJ		 1392 (lsr & UART_LSR_THRE) :
1393 (lsr & UART_LSR_TEMT))
55d3b282
RK		 1394 transmit_chars(up);
1395 }
1da177e4 1396 }
e763b90c 1397
1da177e4 1398 /*
e763b90c 1399 * Re-enable the transmitter if we disabled it.
1da177e4 1400 */
e763b90c 1401 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1da177e4
LT		 1402 up->acr &= ~UART_ACR_TXDIS;
1403 serial_icr_write(up, UART_ACR, up->acr);
1404 }
1405}
1406
1407static void serial8250_stop_rx(struct uart_port *port)
1408{
49d5741b
JI		 1409 struct uart_8250_port *up =
1410 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1411
1412 up->ier &= ~UART_IER_RLSI;
1413 up->port.read_status_mask &= ~UART_LSR_DR;
1414 serial_out(up, UART_IER, up->ier);
1415}
1416
1417static void serial8250_enable_ms(struct uart_port *port)
1418{
49d5741b
JI		 1419 struct uart_8250_port *up =
1420 container_of(port, struct uart_8250_port, port);
1da177e4 1421
21c614a7
PA		 1422 /* no MSR capabilities */
1423 if (up->bugs & UART_BUG_NOMSR)
1424 return;
1425
1da177e4
LT		 1426 up->ier |= UART_IER_MSI;
1427 serial_out(up, UART_IER, up->ier);
1428}
1429
ea8874dc 1430static void
cc79aa9d 1431receive_chars(struct uart_8250_port *up, unsigned int *status)
1da177e4 1432{
ebd2c8f6 1433 struct tty_struct *tty = up->port.state->port.tty;
1da177e4
LT		 1434 unsigned char ch, lsr = *status;
1435 int max_count = 256;
1436 char flag;
1437
1438 do {
7500b1f6
AR		 1439 if (likely(lsr & UART_LSR_DR))
1440 ch = serial_inp(up, UART_RX);
1441 else
1442 /*
1443 * Intel 82571 has a Serial Over Lan device that will
1444 * set UART_LSR_BI without setting UART_LSR_DR when
1445 * it receives a break. To avoid reading from the
1446 * receive buffer without UART_LSR_DR bit set, we
1447 * just force the read character to be 0
1448 */
1449 ch = 0;
1450
1da177e4
LT		 1451 flag = TTY_NORMAL;
1452 up->port.icount.rx++;
1453
ad4c2aa6
CM		 1454 lsr |= up->lsr_saved_flags;
1455 up->lsr_saved_flags = 0;
1da177e4 1456
ad4c2aa6 1457 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1da177e4
LT		 1458 /*
1459 * For statistics only
1460 */
1461 if (lsr & UART_LSR_BI) {
1462 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1463 up->port.icount.brk++;
1464 /*
1465 * We do the SysRQ and SAK checking
1466 * here because otherwise the break
1467 * may get masked by ignore_status_mask
1468 * or read_status_mask.
1469 */
1470 if (uart_handle_break(&up->port))
1471 goto ignore_char;
1472 } else if (lsr & UART_LSR_PE)
1473 up->port.icount.parity++;
1474 else if (lsr & UART_LSR_FE)
1475 up->port.icount.frame++;
1476 if (lsr & UART_LSR_OE)
1477 up->port.icount.overrun++;
1478
1479 /*
23907eb8 1480 * Mask off conditions which should be ignored.
1da177e4
LT		 1481 */
1482 lsr &= up->port.read_status_mask;
1483
1484 if (lsr & UART_LSR_BI) {
1485 DEBUG_INTR("handling break....");
1486 flag = TTY_BREAK;
1487 } else if (lsr & UART_LSR_PE)
1488 flag = TTY_PARITY;
1489 else if (lsr & UART_LSR_FE)
1490 flag = TTY_FRAME;
1491 }
7d12e780 1492 if (uart_handle_sysrq_char(&up->port, ch))
1da177e4 1493 goto ignore_char;
05ab3014
RK		 1494
1495 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1496
6f803cd0 1497ignore_char:
1da177e4 1498 lsr = serial_inp(up, UART_LSR);
7500b1f6 1499 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1da177e4
LT		 1500 spin_unlock(&up->port.lock);
1501 tty_flip_buffer_push(tty);
1502 spin_lock(&up->port.lock);
1503 *status = lsr;
1504}
1505
ea8874dc 1506static void transmit_chars(struct uart_8250_port *up)
1da177e4 1507{
ebd2c8f6 1508 struct circ_buf *xmit = &up->port.state->xmit;
1da177e4
LT		 1509 int count;
1510
1511 if (up->port.x_char) {
1512 serial_outp(up, UART_TX, up->port.x_char);
1513 up->port.icount.tx++;
1514 up->port.x_char = 0;
1515 return;
1516 }
b129a8cc
RK		 1517 if (uart_tx_stopped(&up->port)) {
1518 serial8250_stop_tx(&up->port);
1519 return;
1520 }
1521 if (uart_circ_empty(xmit)) {
e763b90c 1522 __stop_tx(up);
1da177e4
LT		 1523 return;
1524 }
1525
1526 count = up->tx_loadsz;
1527 do {
1528 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1529 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1530 up->port.icount.tx++;
1531 if (uart_circ_empty(xmit))
1532 break;
1533 } while (--count > 0);
1534
1535 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1536 uart_write_wakeup(&up->port);
1537
1538 DEBUG_INTR("THRE...");
1539
1540 if (uart_circ_empty(xmit))
e763b90c 1541 __stop_tx(up);
1da177e4
LT		 1542}
1543
2af7cd68 1544static unsigned int check_modem_status(struct uart_8250_port *up)
1da177e4 1545{
2af7cd68
RK		 1546 unsigned int status = serial_in(up, UART_MSR);
1547
ad4c2aa6
CM		 1548 status |= up->msr_saved_flags;
1549 up->msr_saved_flags = 0;
fdc30b3d 1550 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
ebd2c8f6 1551 up->port.state != NULL) {
2af7cd68
RK		 1552 if (status & UART_MSR_TERI)
1553 up->port.icount.rng++;
1554 if (status & UART_MSR_DDSR)
1555 up->port.icount.dsr++;
1556 if (status & UART_MSR_DDCD)
1557 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1558 if (status & UART_MSR_DCTS)
1559 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1560
bdc04e31 1561 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
2af7cd68 1562 }
1da177e4 1563
2af7cd68 1564 return status;
1da177e4
LT		 1565}
1566
1567/*
1568 * This handles the interrupt from one port.
1569 */
b5d674ab 1570static void serial8250_handle_port(struct uart_8250_port *up)
1da177e4 1571{
45e24601 1572 unsigned int status;
4bf3631c 1573 unsigned long flags;
45e24601 1574
4bf3631c 1575 spin_lock_irqsave(&up->port.lock, flags);
45e24601
RK		 1576
1577 status = serial_inp(up, UART_LSR);
1da177e4
LT		 1578
1579 DEBUG_INTR("status = %x...", status);
1580
7500b1f6 1581 if (status & (UART_LSR_DR | UART_LSR_BI))
7d12e780 1582 receive_chars(up, &status);
1da177e4
LT		 1583 check_modem_status(up);
1584 if (status & UART_LSR_THRE)
1585 transmit_chars(up);
45e24601 1586
4bf3631c 1587 spin_unlock_irqrestore(&up->port.lock, flags);
1da177e4
LT		 1588}
1589
1590/*
1591 * This is the serial driver's interrupt routine.
1592 *
1593 * Arjan thinks the old way was overly complex, so it got simplified.
1594 * Alan disagrees, saying that need the complexity to handle the weird
1595 * nature of ISA shared interrupts. (This is a special exception.)
1596 *
1597 * In order to handle ISA shared interrupts properly, we need to check
1598 * that all ports have been serviced, and therefore the ISA interrupt
1599 * line has been de-asserted.
1600 *
1601 * This means we need to loop through all ports. checking that they
1602 * don't have an interrupt pending.
1603 */
7d12e780 1604static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1da177e4
LT		 1605{
1606 struct irq_info *i = dev_id;
1607 struct list_head *l, *end = NULL;
1608 int pass_counter = 0, handled = 0;
1609
1610 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1611
1612 spin_lock(&i->lock);
1613
1614 l = i->head;
1615 do {
1616 struct uart_8250_port *up;
1617 unsigned int iir;
1618
1619 up = list_entry(l, struct uart_8250_port, list);
1620
1621 iir = serial_in(up, UART_IIR);
1622 if (!(iir & UART_IIR_NO_INT)) {
7d12e780 1623 serial8250_handle_port(up);
1da177e4
LT		 1624
1625 handled = 1;
1626
beab697a 1627 end = NULL;
a3ae0fc3
JI		 1628 } else if ((up->port.iotype == UPIO_DWAPB ||
1629 up->port.iotype == UPIO_DWAPB32) &&
beab697a
MSJ		 1630 (iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
1631 /* The DesignWare APB UART has an Busy Detect (0x07)
25985edc 1632 * interrupt meaning an LCR write attempt occurred while the
beab697a
MSJ		 1633 * UART was busy. The interrupt must be cleared by reading
1634 * the UART status register (USR) and the LCR re-written. */
1635 unsigned int status;
1636 status = *(volatile u32 *)up->port.private_data;
1637 serial_out(up, UART_LCR, up->lcr);
1638
1639 handled = 1;
1640
1da177e4
LT		 1641 end = NULL;
1642 } else if (end == NULL)
1643 end = l;
1644
1645 l = l->next;
1646
1647 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1648 /* If we hit this, we're dead. */
cd3ecad1
DD		 1649 printk_ratelimited(KERN_ERR
1650 "serial8250: too much work for irq%d\n", irq);
1da177e4
LT		 1651 break;
1652 }
1653 } while (l != end);
1654
1655 spin_unlock(&i->lock);
1656
1657 DEBUG_INTR("end.\n");
1658
1659 return IRQ_RETVAL(handled);
1660}
1661
1662/*
1663 * To support ISA shared interrupts, we need to have one interrupt
1664 * handler that ensures that the IRQ line has been deasserted
1665 * before returning. Failing to do this will result in the IRQ
1666 * line being stuck active, and, since ISA irqs are edge triggered,
1667 * no more IRQs will be seen.
1668 */
1669static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1670{
1671 spin_lock_irq(&i->lock);
1672
1673 if (!list_empty(i->head)) {
1674 if (i->head == &up->list)
1675 i->head = i->head->next;
1676 list_del(&up->list);
1677 } else {
1678 BUG_ON(i->head != &up->list);
1679 i->head = NULL;
1680 }
1da177e4 1681 spin_unlock_irq(&i->lock);
25db8ad5
AC		 1682 /* List empty so throw away the hash node */
1683 if (i->head == NULL) {
1684 hlist_del(&i->node);
1685 kfree(i);
1686 }
1da177e4
LT		 1687}
1688
1689static int serial_link_irq_chain(struct uart_8250_port *up)
1690{
25db8ad5
AC		 1691 struct hlist_head *h;
1692 struct hlist_node *n;
1693 struct irq_info *i;
40663cc7 1694 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1da177e4 1695
25db8ad5
AC		 1696 mutex_lock(&hash_mutex);
1697
1698 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1699
1700 hlist_for_each(n, h) {
1701 i = hlist_entry(n, struct irq_info, node);
1702 if (i->irq == up->port.irq)
1703 break;
1704 }
1705
1706 if (n == NULL) {
1707 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1708 if (i == NULL) {
1709 mutex_unlock(&hash_mutex);
1710 return -ENOMEM;
1711 }
1712 spin_lock_init(&i->lock);
1713 i->irq = up->port.irq;
1714 hlist_add_head(&i->node, h);
1715 }
1716 mutex_unlock(&hash_mutex);
1717
1da177e4
LT		 1718 spin_lock_irq(&i->lock);
1719
1720 if (i->head) {
1721 list_add(&up->list, i->head);
1722 spin_unlock_irq(&i->lock);
1723
1724 ret = 0;
1725 } else {
1726 INIT_LIST_HEAD(&up->list);
1727 i->head = &up->list;
1728 spin_unlock_irq(&i->lock);
1c2f0493 1729 irq_flags |= up->port.irqflags;
1da177e4
LT		 1730 ret = request_irq(up->port.irq, serial8250_interrupt,
1731 irq_flags, "serial", i);
1732 if (ret < 0)
1733 serial_do_unlink(i, up);
1734 }
1735
1736 return ret;
1737}
1738
1739static void serial_unlink_irq_chain(struct uart_8250_port *up)
1740{
25db8ad5
AC		 1741 struct irq_info *i;
1742 struct hlist_node *n;
1743 struct hlist_head *h;
1da177e4 1744
25db8ad5
AC		 1745 mutex_lock(&hash_mutex);
1746
1747 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1748
1749 hlist_for_each(n, h) {
1750 i = hlist_entry(n, struct irq_info, node);
1751 if (i->irq == up->port.irq)
1752 break;
1753 }
1754
1755 BUG_ON(n == NULL);
1da177e4
LT		 1756 BUG_ON(i->head == NULL);
1757
1758 if (list_empty(i->head))
1759 free_irq(up->port.irq, i);
1760
1761 serial_do_unlink(i, up);
25db8ad5 1762 mutex_unlock(&hash_mutex);
1da177e4
LT		 1763}
1764
1765/*
1766 * This function is used to handle ports that do not have an
1767 * interrupt. This doesn't work very well for 16450's, but gives
1768 * barely passable results for a 16550A. (Although at the expense
1769 * of much CPU overhead).
1770 */
1771static void serial8250_timeout(unsigned long data)
1772{
1773 struct uart_8250_port *up = (struct uart_8250_port *)data;
1da177e4
LT		 1774 unsigned int iir;
1775
1776 iir = serial_in(up, UART_IIR);
45e24601 1777 if (!(iir & UART_IIR_NO_INT))
7d12e780 1778 serial8250_handle_port(up);
54381067 1779 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
40b36daa
AW		 1780}
1781
1782static void serial8250_backup_timeout(unsigned long data)
1783{
1784 struct uart_8250_port *up = (struct uart_8250_port *)data;
ad4c2aa6
CM		 1785 unsigned int iir, ier = 0, lsr;
1786 unsigned long flags;
40b36daa
AW		 1787
1788 /*
1789 * Must disable interrupts or else we risk racing with the interrupt
1790 * based handler.
1791 */
1792 if (is_real_interrupt(up->port.irq)) {
1793 ier = serial_in(up, UART_IER);
1794 serial_out(up, UART_IER, 0);
1795 }
1da177e4 1796
40b36daa
AW		 1797 iir = serial_in(up, UART_IIR);
1798
1799 /*
1800 * This should be a safe test for anyone who doesn't trust the
1801 * IIR bits on their UART, but it's specifically designed for
1802 * the "Diva" UART used on the management processor on many HP
1803 * ia64 and parisc boxes.
1804 */
ad4c2aa6
CM		 1805 spin_lock_irqsave(&up->port.lock, flags);
1806 lsr = serial_in(up, UART_LSR);
1807 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1808 spin_unlock_irqrestore(&up->port.lock, flags);
40b36daa 1809 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
ebd2c8f6 1810 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
ad4c2aa6 1811 (lsr & UART_LSR_THRE)) {
40b36daa
AW		 1812 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1813 iir |= UART_IIR_THRI;
1814 }
1815
1816 if (!(iir & UART_IIR_NO_INT))
1817 serial8250_handle_port(up);
1818
1819 if (is_real_interrupt(up->port.irq))
1820 serial_out(up, UART_IER, ier);
1821
1822 /* Standard timer interval plus 0.2s to keep the port running */
6f803cd0 1823 mod_timer(&up->timer,
54381067 1824 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1da177e4
LT		 1825}
1826
1827static unsigned int serial8250_tx_empty(struct uart_port *port)
1828{
49d5741b
JI		 1829 struct uart_8250_port *up =
1830 container_of(port, struct uart_8250_port, port);
1da177e4 1831 unsigned long flags;
ad4c2aa6 1832 unsigned int lsr;
1da177e4
LT		 1833
1834 spin_lock_irqsave(&up->port.lock, flags);
ad4c2aa6
CM		 1835 lsr = serial_in(up, UART_LSR);
1836 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1da177e4
LT		 1837 spin_unlock_irqrestore(&up->port.lock, flags);
1838
bca47613 1839 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1da177e4
LT		 1840}
1841
1842static unsigned int serial8250_get_mctrl(struct uart_port *port)
1843{
49d5741b
JI		 1844 struct uart_8250_port *up =
1845 container_of(port, struct uart_8250_port, port);
2af7cd68 1846 unsigned int status;
1da177e4
LT		 1847 unsigned int ret;
1848
2af7cd68 1849 status = check_modem_status(up);
1da177e4
LT		 1850
1851 ret = 0;
1852 if (status & UART_MSR_DCD)
1853 ret |= TIOCM_CAR;
1854 if (status & UART_MSR_RI)
1855 ret |= TIOCM_RNG;
1856 if (status & UART_MSR_DSR)
1857 ret |= TIOCM_DSR;
1858 if (status & UART_MSR_CTS)
1859 ret |= TIOCM_CTS;
1860 return ret;
1861}
1862
1863static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1864{
49d5741b
JI		 1865 struct uart_8250_port *up =
1866 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1867 unsigned char mcr = 0;
1868
1869 if (mctrl & TIOCM_RTS)
1870 mcr |= UART_MCR_RTS;
1871 if (mctrl & TIOCM_DTR)
1872 mcr |= UART_MCR_DTR;
1873 if (mctrl & TIOCM_OUT1)
1874 mcr |= UART_MCR_OUT1;
1875 if (mctrl & TIOCM_OUT2)
1876 mcr |= UART_MCR_OUT2;
1877 if (mctrl & TIOCM_LOOP)
1878 mcr |= UART_MCR_LOOP;
1879
1880 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1881
1882 serial_out(up, UART_MCR, mcr);
1883}
1884
1885static void serial8250_break_ctl(struct uart_port *port, int break_state)
1886{
49d5741b
JI		 1887 struct uart_8250_port *up =
1888 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1889 unsigned long flags;
1890
1891 spin_lock_irqsave(&up->port.lock, flags);
1892 if (break_state == -1)
1893 up->lcr |= UART_LCR_SBC;
1894 else
1895 up->lcr &= ~UART_LCR_SBC;
1896 serial_out(up, UART_LCR, up->lcr);
1897 spin_unlock_irqrestore(&up->port.lock, flags);
1898}
1899
40b36daa
AW		 1900/*
1901 * Wait for transmitter & holding register to empty
1902 */
b5d674ab 1903static void wait_for_xmitr(struct uart_8250_port *up, int bits)
40b36daa
AW		 1904{
1905 unsigned int status, tmout = 10000;
1906
1907 /* Wait up to 10ms for the character(s) to be sent. */
97d303b7 1908 for (;;) {
40b36daa
AW		 1909 status = serial_in(up, UART_LSR);
1910
ad4c2aa6 1911 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
40b36daa 1912
97d303b7
DD		 1913 if ((status & bits) == bits)
1914 break;
40b36daa
AW		 1915 if (--tmout == 0)
1916 break;
1917 udelay(1);
97d303b7 1918 }
40b36daa
AW		 1919
1920 /* Wait up to 1s for flow control if necessary */
1921 if (up->port.flags & UPF_CONS_FLOW) {
ad4c2aa6
CM		 1922 unsigned int tmout;
1923 for (tmout = 1000000; tmout; tmout--) {
1924 unsigned int msr = serial_in(up, UART_MSR);
1925 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1926 if (msr & UART_MSR_CTS)
1927 break;
40b36daa
AW		 1928 udelay(1);
1929 touch_nmi_watchdog();
1930 }
1931 }
1932}
1933
f2d937f3
JW		 1934#ifdef CONFIG_CONSOLE_POLL
1935/*
1936 * Console polling routines for writing and reading from the uart while
1937 * in an interrupt or debug context.
1938 */
1939
1940static int serial8250_get_poll_char(struct uart_port *port)
1941{
49d5741b
JI		 1942 struct uart_8250_port *up =
1943 container_of(port, struct uart_8250_port, port);
f2d937f3
JW		 1944 unsigned char lsr = serial_inp(up, UART_LSR);
1945
f5316b4a
JW		 1946 if (!(lsr & UART_LSR_DR))
1947 return NO_POLL_CHAR;
f2d937f3
JW		 1948
1949 return serial_inp(up, UART_RX);
1950}
1951
1952
1953static void serial8250_put_poll_char(struct uart_port *port,
1954 unsigned char c)
1955{
1956 unsigned int ier;
49d5741b
JI		 1957 struct uart_8250_port *up =
1958 container_of(port, struct uart_8250_port, port);
f2d937f3
JW		 1959
1960 /*
1961 * First save the IER then disable the interrupts
1962 */
1963 ier = serial_in(up, UART_IER);
1964 if (up->capabilities & UART_CAP_UUE)
1965 serial_out(up, UART_IER, UART_IER_UUE);
1966 else
1967 serial_out(up, UART_IER, 0);
1968
1969 wait_for_xmitr(up, BOTH_EMPTY);
1970 /*
1971 * Send the character out.
1972 * If a LF, also do CR...
1973 */
1974 serial_out(up, UART_TX, c);
1975 if (c == 10) {
1976 wait_for_xmitr(up, BOTH_EMPTY);
1977 serial_out(up, UART_TX, 13);
1978 }
1979
1980 /*
1981 * Finally, wait for transmitter to become empty
1982 * and restore the IER
1983 */
1984 wait_for_xmitr(up, BOTH_EMPTY);
1985 serial_out(up, UART_IER, ier);
1986}
1987
1988#endif /* CONFIG_CONSOLE_POLL */
1989
1da177e4
LT		 1990static int serial8250_startup(struct uart_port *port)
1991{
49d5741b
JI		 1992 struct uart_8250_port *up =
1993 container_of(port, struct uart_8250_port, port);
1da177e4 1994 unsigned long flags;
55d3b282 1995 unsigned char lsr, iir;
1da177e4
LT		 1996 int retval;
1997
e4f05af1
OP		 1998 up->port.fifosize = uart_config[up->port.type].fifo_size;
1999 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1da177e4
LT		 2000 up->capabilities = uart_config[up->port.type].flags;
2001 up->mcr = 0;
2002
b8e7e40a
AC		 2003 if (up->port.iotype != up->cur_iotype)
2004 set_io_from_upio(port);
2005
1da177e4
LT		 2006 if (up->port.type == PORT_16C950) {
2007 /* Wake up and initialize UART */
2008 up->acr = 0;
662b083a 2009 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 2010 serial_outp(up, UART_EFR, UART_EFR_ECB);
2011 serial_outp(up, UART_IER, 0);
2012 serial_outp(up, UART_LCR, 0);
2013 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2014 serial_outp(up, UART_LCR, 0xBF);
2015 serial_outp(up, UART_EFR, UART_EFR_ECB);
2016 serial_outp(up, UART_LCR, 0);
2017 }
2018
2019#ifdef CONFIG_SERIAL_8250_RSA
2020 /*
2021 * If this is an RSA port, see if we can kick it up to the
2022 * higher speed clock.
2023 */
2024 enable_rsa(up);
2025#endif
2026
2027 /*
2028 * Clear the FIFO buffers and disable them.
7f927fcc 2029 * (they will be reenabled in set_termios())
1da177e4
LT		 2030 */
2031 serial8250_clear_fifos(up);
2032
2033 /*
2034 * Clear the interrupt registers.
2035 */
2036 (void) serial_inp(up, UART_LSR);
2037 (void) serial_inp(up, UART_RX);
2038 (void) serial_inp(up, UART_IIR);
2039 (void) serial_inp(up, UART_MSR);
2040
2041 /*
2042 * At this point, there's no way the LSR could still be 0xff;
2043 * if it is, then bail out, because there's likely no UART
2044 * here.
2045 */
2046 if (!(up->port.flags & UPF_BUGGY_UART) &&
2047 (serial_inp(up, UART_LSR) == 0xff)) {
8440838b
DM		 2048 printk(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2049 serial_index(&up->port));
1da177e4
LT		 2050 return -ENODEV;
2051 }
2052
2053 /*
2054 * For a XR16C850, we need to set the trigger levels
2055 */
2056 if (up->port.type == PORT_16850) {
2057 unsigned char fctr;
2058
662b083a 2059 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 2060
2061 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2062 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2063 serial_outp(up, UART_TRG, UART_TRG_96);
2064 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2065 serial_outp(up, UART_TRG, UART_TRG_96);
2066
2067 serial_outp(up, UART_LCR, 0);
2068 }
2069
40b36daa 2070 if (is_real_interrupt(up->port.irq)) {
01c194d9 2071 unsigned char iir1;
40b36daa
AW		 2072 /*
2073 * Test for UARTs that do not reassert THRE when the
2074 * transmitter is idle and the interrupt has already
2075 * been cleared. Real 16550s should always reassert
2076 * this interrupt whenever the transmitter is idle and
2077 * the interrupt is enabled. Delays are necessary to
2078 * allow register changes to become visible.
2079 */
c389d27b 2080 spin_lock_irqsave(&up->port.lock, flags);
1c2f0493 2081 if (up->port.irqflags & IRQF_SHARED)
768aec0b 2082 disable_irq_nosync(up->port.irq);
40b36daa
AW		 2083
2084 wait_for_xmitr(up, UART_LSR_THRE);
2085 serial_out_sync(up, UART_IER, UART_IER_THRI);
2086 udelay(1); /* allow THRE to set */
01c194d9 2087 iir1 = serial_in(up, UART_IIR);
40b36daa
AW		 2088 serial_out(up, UART_IER, 0);
2089 serial_out_sync(up, UART_IER, UART_IER_THRI);
2090 udelay(1); /* allow a working UART time to re-assert THRE */
2091 iir = serial_in(up, UART_IIR);
2092 serial_out(up, UART_IER, 0);
2093
1c2f0493 2094 if (up->port.irqflags & IRQF_SHARED)
768aec0b 2095 enable_irq(up->port.irq);
c389d27b 2096 spin_unlock_irqrestore(&up->port.lock, flags);
40b36daa
AW		 2097
2098 /*
2099 * If the interrupt is not reasserted, setup a timer to
2100 * kick the UART on a regular basis.
2101 */
01c194d9 2102 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
363f66fe 2103 up->bugs |= UART_BUG_THRE;
8440838b
DM		 2104 pr_debug("ttyS%d - using backup timer\n",
2105 serial_index(port));
40b36daa
AW		 2106 }
2107 }
2108
363f66fe
WN		 2109 /*
2110 * The above check will only give an accurate result the first time
2111 * the port is opened so this value needs to be preserved.
2112 */
2113 if (up->bugs & UART_BUG_THRE) {
2114 up->timer.function = serial8250_backup_timeout;
2115 up->timer.data = (unsigned long)up;
2116 mod_timer(&up->timer, jiffies +
54381067 2117 uart_poll_timeout(port) + HZ / 5);
363f66fe
WN		 2118 }
2119
1da177e4
LT		 2120 /*
2121 * If the "interrupt" for this port doesn't correspond with any
2122 * hardware interrupt, we use a timer-based system. The original
2123 * driver used to do this with IRQ0.
2124 */
2125 if (!is_real_interrupt(up->port.irq)) {
1da177e4 2126 up->timer.data = (unsigned long)up;
54381067 2127 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
1da177e4
LT		 2128 } else {
2129 retval = serial_link_irq_chain(up);
2130 if (retval)
2131 return retval;
2132 }
2133
2134 /*
2135 * Now, initialize the UART
2136 */
2137 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
2138
2139 spin_lock_irqsave(&up->port.lock, flags);
2140 if (up->port.flags & UPF_FOURPORT) {
2141 if (!is_real_interrupt(up->port.irq))
2142 up->port.mctrl |= TIOCM_OUT1;
2143 } else
2144 /*
2145 * Most PC uarts need OUT2 raised to enable interrupts.
2146 */
2147 if (is_real_interrupt(up->port.irq))
2148 up->port.mctrl |= TIOCM_OUT2;
2149
2150 serial8250_set_mctrl(&up->port, up->port.mctrl);
55d3b282 2151
b6adea33
MCC		 2152 /* Serial over Lan (SoL) hack:
2153 Intel 8257x Gigabit ethernet chips have a
2154 16550 emulation, to be used for Serial Over Lan.
2155 Those chips take a longer time than a normal
2156 serial device to signalize that a transmission
2157 data was queued. Due to that, the above test generally
2158 fails. One solution would be to delay the reading of
2159 iir. However, this is not reliable, since the timeout
2160 is variable. So, let's just don't test if we receive
2161 TX irq. This way, we'll never enable UART_BUG_TXEN.
2162 */
d41a4b51 2163 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
b6adea33
MCC		 2164 goto dont_test_tx_en;
2165
55d3b282
RK		 2166 /*
2167 * Do a quick test to see if we receive an
2168 * interrupt when we enable the TX irq.
2169 */
2170 serial_outp(up, UART_IER, UART_IER_THRI);
2171 lsr = serial_in(up, UART_LSR);
2172 iir = serial_in(up, UART_IIR);
2173 serial_outp(up, UART_IER, 0);
2174
2175 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
67f7654e
RK		 2176 if (!(up->bugs & UART_BUG_TXEN)) {
2177 up->bugs |= UART_BUG_TXEN;
55d3b282 2178 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
8440838b 2179 serial_index(port));
55d3b282
RK		 2180 }
2181 } else {
67f7654e 2182 up->bugs &= ~UART_BUG_TXEN;
55d3b282
RK		 2183 }
2184
b6adea33 2185dont_test_tx_en:
1da177e4
LT		 2186 spin_unlock_irqrestore(&up->port.lock, flags);
2187
ad4c2aa6
CM		 2188 /*
2189 * Clear the interrupt registers again for luck, and clear the
2190 * saved flags to avoid getting false values from polling
2191 * routines or the previous session.
2192 */
2193 serial_inp(up, UART_LSR);
2194 serial_inp(up, UART_RX);
2195 serial_inp(up, UART_IIR);
2196 serial_inp(up, UART_MSR);
2197 up->lsr_saved_flags = 0;
2198 up->msr_saved_flags = 0;
2199
1da177e4
LT		 2200 /*
2201 * Finally, enable interrupts. Note: Modem status interrupts
2202 * are set via set_termios(), which will be occurring imminently
2203 * anyway, so we don't enable them here.
2204 */
2205 up->ier = UART_IER_RLSI | UART_IER_RDI;
2206 serial_outp(up, UART_IER, up->ier);
2207
2208 if (up->port.flags & UPF_FOURPORT) {
2209 unsigned int icp;
2210 /*
2211 * Enable interrupts on the AST Fourport board
2212 */
2213 icp = (up->port.iobase & 0xfe0) | 0x01f;
2214 outb_p(0x80, icp);
2215 (void) inb_p(icp);
2216 }
2217
1da177e4
LT		 2218 return 0;
2219}
2220
2221static void serial8250_shutdown(struct uart_port *port)
2222{
49d5741b
JI		 2223 struct uart_8250_port *up =
2224 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2225 unsigned long flags;
2226
2227 /*
2228 * Disable interrupts from this port
2229 */
2230 up->ier = 0;
2231 serial_outp(up, UART_IER, 0);
2232
2233 spin_lock_irqsave(&up->port.lock, flags);
2234 if (up->port.flags & UPF_FOURPORT) {
2235 /* reset interrupts on the AST Fourport board */
2236 inb((up->port.iobase & 0xfe0) | 0x1f);
2237 up->port.mctrl |= TIOCM_OUT1;
2238 } else
2239 up->port.mctrl &= ~TIOCM_OUT2;
2240
2241 serial8250_set_mctrl(&up->port, up->port.mctrl);
2242 spin_unlock_irqrestore(&up->port.lock, flags);
2243
2244 /*
2245 * Disable break condition and FIFOs
2246 */
2247 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2248 serial8250_clear_fifos(up);
2249
2250#ifdef CONFIG_SERIAL_8250_RSA
2251 /*
2252 * Reset the RSA board back to 115kbps compat mode.
2253 */
2254 disable_rsa(up);
2255#endif
2256
2257 /*
2258 * Read data port to reset things, and then unlink from
2259 * the IRQ chain.
2260 */
2261 (void) serial_in(up, UART_RX);
2262
40b36daa
AW		 2263 del_timer_sync(&up->timer);
2264 up->timer.function = serial8250_timeout;
2265 if (is_real_interrupt(up->port.irq))
1da177e4
LT		 2266 serial_unlink_irq_chain(up);
2267}
2268
2269static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2270{
2271 unsigned int quot;
2272
2273 /*
2274 * Handle magic divisors for baud rates above baud_base on
2275 * SMSC SuperIO chips.
2276 */
2277 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2278 baud == (port->uartclk/4))
2279 quot = 0x8001;
2280 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2281 baud == (port->uartclk/8))
2282 quot = 0x8002;
2283 else
2284 quot = uart_get_divisor(port, baud);
2285
2286 return quot;
2287}
2288
235dae5d
PL		 2289void
2290serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2291 struct ktermios *old)
1da177e4 2292{
49d5741b
JI		 2293 struct uart_8250_port *up =
2294 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2295 unsigned char cval, fcr = 0;
2296 unsigned long flags;
2297 unsigned int baud, quot;
2298
2299 switch (termios->c_cflag & CSIZE) {
2300 case CS5:
0a8b80c5 2301 cval = UART_LCR_WLEN5;
1da177e4
LT		 2302 break;
2303 case CS6:
0a8b80c5 2304 cval = UART_LCR_WLEN6;
1da177e4
LT		 2305 break;
2306 case CS7:
0a8b80c5 2307 cval = UART_LCR_WLEN7;
1da177e4
LT		 2308 break;
2309 default:
2310 case CS8:
0a8b80c5 2311 cval = UART_LCR_WLEN8;
1da177e4
LT		 2312 break;
2313 }
2314
2315 if (termios->c_cflag & CSTOPB)
0a8b80c5 2316 cval |= UART_LCR_STOP;
1da177e4
LT		 2317 if (termios->c_cflag & PARENB)
2318 cval |= UART_LCR_PARITY;
2319 if (!(termios->c_cflag & PARODD))
2320 cval |= UART_LCR_EPAR;
2321#ifdef CMSPAR
2322 if (termios->c_cflag & CMSPAR)
2323 cval |= UART_LCR_SPAR;
2324#endif
2325
2326 /*
2327 * Ask the core to calculate the divisor for us.
2328 */
24d481ec
AV		 2329 baud = uart_get_baud_rate(port, termios, old,
2330 port->uartclk / 16 / 0xffff,
2331 port->uartclk / 16);
1da177e4
LT		 2332 quot = serial8250_get_divisor(port, baud);
2333
2334 /*
4ba5e35d 2335 * Oxford Semi 952 rev B workaround
1da177e4 2336 */
4ba5e35d 2337 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
3e8d4e20 2338 quot++;
1da177e4
LT		 2339
2340 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2341 if (baud < 2400)
2342 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2343 else
2344 fcr = uart_config[up->port.type].fcr;
2345 }
2346
2347 /*
2348 * MCR-based auto flow control. When AFE is enabled, RTS will be
2349 * deasserted when the receive FIFO contains more characters than
2350 * the trigger, or the MCR RTS bit is cleared. In the case where
2351 * the remote UART is not using CTS auto flow control, we must
2352 * have sufficient FIFO entries for the latency of the remote
2353 * UART to respond. IOW, at least 32 bytes of FIFO.
2354 */
2355 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2356 up->mcr &= ~UART_MCR_AFE;
2357 if (termios->c_cflag & CRTSCTS)
2358 up->mcr |= UART_MCR_AFE;
2359 }
2360
2361 /*
2362 * Ok, we're now changing the port state. Do it with
2363 * interrupts disabled.
2364 */
2365 spin_lock_irqsave(&up->port.lock, flags);
2366
2367 /*
2368 * Update the per-port timeout.
2369 */
2370 uart_update_timeout(port, termios->c_cflag, baud);
2371
2372 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2373 if (termios->c_iflag & INPCK)
2374 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2375 if (termios->c_iflag & (BRKINT | PARMRK))
2376 up->port.read_status_mask |= UART_LSR_BI;
2377
2378 /*
2379 * Characteres to ignore
2380 */
2381 up->port.ignore_status_mask = 0;
2382 if (termios->c_iflag & IGNPAR)
2383 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2384 if (termios->c_iflag & IGNBRK) {
2385 up->port.ignore_status_mask |= UART_LSR_BI;
2386 /*
2387 * If we're ignoring parity and break indicators,
2388 * ignore overruns too (for real raw support).
2389 */
2390 if (termios->c_iflag & IGNPAR)
2391 up->port.ignore_status_mask |= UART_LSR_OE;
2392 }
2393
2394 /*
2395 * ignore all characters if CREAD is not set
2396 */
2397 if ((termios->c_cflag & CREAD) == 0)
2398 up->port.ignore_status_mask |= UART_LSR_DR;
2399
2400 /*
2401 * CTS flow control flag and modem status interrupts
2402 */
f8b372a1 2403 up->ier &= ~UART_IER_MSI;
21c614a7
PA		 2404 if (!(up->bugs & UART_BUG_NOMSR) &&
2405 UART_ENABLE_MS(&up->port, termios->c_cflag))
1da177e4
LT		 2406 up->ier |= UART_IER_MSI;
2407 if (up->capabilities & UART_CAP_UUE)
2408 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
2409
2410 serial_out(up, UART_IER, up->ier);
2411
2412 if (up->capabilities & UART_CAP_EFR) {
2413 unsigned char efr = 0;
2414 /*
2415 * TI16C752/Startech hardware flow control. FIXME:
2416 * - TI16C752 requires control thresholds to be set.
2417 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2418 */
2419 if (termios->c_cflag & CRTSCTS)
2420 efr |= UART_EFR_CTS;
2421
662b083a 2422 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 2423 serial_outp(up, UART_EFR, efr);
2424 }
2425
f2eda27d 2426#ifdef CONFIG_ARCH_OMAP
255341c6 2427 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
5668545a 2428 if (cpu_is_omap1510() && is_omap_port(up)) {
255341c6
JM		 2429 if (baud == 115200) {
2430 quot = 1;
2431 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2432 } else
2433 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2434 }
2435#endif
2436
1da177e4
LT		 2437 if (up->capabilities & UART_NATSEMI) {
2438 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2439 serial_outp(up, UART_LCR, 0xe0);
2440 } else {
2441 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2442 }
2443
b32b19b8 2444 serial_dl_write(up, quot);
1da177e4
LT		 2445
2446 /*
2447 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2448 * is written without DLAB set, this mode will be disabled.
2449 */
2450 if (up->port.type == PORT_16750)
2451 serial_outp(up, UART_FCR, fcr);
2452
2453 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2454 up->lcr = cval; /* Save LCR */
2455 if (up->port.type != PORT_16750) {
2456 if (fcr & UART_FCR_ENABLE_FIFO) {
2457 /* emulated UARTs (Lucent Venus 167x) need two steps */
2458 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2459 }
2460 serial_outp(up, UART_FCR, fcr); /* set fcr */
2461 }
2462 serial8250_set_mctrl(&up->port, up->port.mctrl);
2463 spin_unlock_irqrestore(&up->port.lock, flags);
e991a2bd
AC		 2464 /* Don't rewrite B0 */
2465 if (tty_termios_baud_rate(termios))
2466 tty_termios_encode_baud_rate(termios, baud, baud);
1da177e4 2467}
235dae5d
PL		 2468EXPORT_SYMBOL(serial8250_do_set_termios);
2469
2470static void
2471serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2472 struct ktermios *old)
2473{
2474 if (port->set_termios)
2475 port->set_termios(port, termios, old);
2476 else
2477 serial8250_do_set_termios(port, termios, old);
2478}
1da177e4 2479
dc77f161 2480static void
a0821df6 2481serial8250_set_ldisc(struct uart_port *port, int new)
dc77f161 2482{
a0821df6 2483 if (new == N_PPS) {
dc77f161
RG		 2484 port->flags |= UPF_HARDPPS_CD;
2485 serial8250_enable_ms(port);
2486 } else
2487 port->flags &= ~UPF_HARDPPS_CD;
2488}
2489
c161afe9
ML		 2490
2491void serial8250_do_pm(struct uart_port *port, unsigned int state,
2492 unsigned int oldstate)
1da177e4 2493{
49d5741b
JI		 2494 struct uart_8250_port *p =
2495 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2496
2497 serial8250_set_sleep(p, state != 0);
c161afe9
ML		 2498}
2499EXPORT_SYMBOL(serial8250_do_pm);
1da177e4 2500
c161afe9
ML		 2501static void
2502serial8250_pm(struct uart_port *port, unsigned int state,
2503 unsigned int oldstate)
2504{
2505 if (port->pm)
2506 port->pm(port, state, oldstate);
2507 else
2508 serial8250_do_pm(port, state, oldstate);
1da177e4
LT		 2509}
2510
f2eda27d
RK		 2511static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2512{
2513 if (pt->port.iotype == UPIO_AU)
b2b13cdf 2514 return 0x1000;
f2eda27d
RK		 2515#ifdef CONFIG_ARCH_OMAP
2516 if (is_omap_port(pt))
2517 return 0x16 << pt->port.regshift;
2518#endif
2519 return 8 << pt->port.regshift;
2520}
2521
1da177e4
LT		 2522/*
2523 * Resource handling.
2524 */
2525static int serial8250_request_std_resource(struct uart_8250_port *up)
2526{
f2eda27d 2527 unsigned int size = serial8250_port_size(up);
1da177e4
LT		 2528 int ret = 0;
2529
2530 switch (up->port.iotype) {
85835f44 2531 case UPIO_AU:
0b30d668
SS		 2532 case UPIO_TSI:
2533 case UPIO_MEM32:
1da177e4 2534 case UPIO_MEM:
beab697a 2535 case UPIO_DWAPB:
a3ae0fc3 2536 case UPIO_DWAPB32:
1da177e4
LT		 2537 if (!up->port.mapbase)
2538 break;
2539
2540 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2541 ret = -EBUSY;
2542 break;
2543 }
2544
2545 if (up->port.flags & UPF_IOREMAP) {
6f441fe9
AC		 2546 up->port.membase = ioremap_nocache(up->port.mapbase,
2547 size);
1da177e4
LT		 2548 if (!up->port.membase) {
2549 release_mem_region(up->port.mapbase, size);
2550 ret = -ENOMEM;
2551 }
2552 }
2553 break;
2554
2555 case UPIO_HUB6:
2556 case UPIO_PORT:
2557 if (!request_region(up->port.iobase, size, "serial"))
2558 ret = -EBUSY;
2559 break;
2560 }
2561 return ret;
2562}
2563
2564static void serial8250_release_std_resource(struct uart_8250_port *up)
2565{
f2eda27d 2566 unsigned int size = serial8250_port_size(up);
1da177e4
LT		 2567
2568 switch (up->port.iotype) {
85835f44 2569 case UPIO_AU:
0b30d668
SS		 2570 case UPIO_TSI:
2571 case UPIO_MEM32:
1da177e4 2572 case UPIO_MEM:
beab697a 2573 case UPIO_DWAPB:
a3ae0fc3 2574 case UPIO_DWAPB32:
1da177e4
LT		 2575 if (!up->port.mapbase)
2576 break;
2577
2578 if (up->port.flags & UPF_IOREMAP) {
2579 iounmap(up->port.membase);
2580 up->port.membase = NULL;
2581 }
2582
2583 release_mem_region(up->port.mapbase, size);
2584 break;
2585
2586 case UPIO_HUB6:
2587 case UPIO_PORT:
2588 release_region(up->port.iobase, size);
2589 break;
2590 }
2591}
2592
2593static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2594{
2595 unsigned long start = UART_RSA_BASE << up->port.regshift;
2596 unsigned int size = 8 << up->port.regshift;
0b30d668 2597 int ret = -EINVAL;
1da177e4
LT		 2598
2599 switch (up->port.iotype) {
1da177e4
LT		 2600 case UPIO_HUB6:
2601 case UPIO_PORT:
2602 start += up->port.iobase;
0b30d668
SS		 2603 if (request_region(start, size, "serial-rsa"))
2604 ret = 0;
2605 else
1da177e4
LT		 2606 ret = -EBUSY;
2607 break;
2608 }
2609
2610 return ret;
2611}
2612
2613static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2614{
2615 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2616 unsigned int size = 8 << up->port.regshift;
2617
2618 switch (up->port.iotype) {
1da177e4
LT		 2619 case UPIO_HUB6:
2620 case UPIO_PORT:
2621 release_region(up->port.iobase + offset, size);
2622 break;
2623 }
2624}
2625
2626static void serial8250_release_port(struct uart_port *port)
2627{
49d5741b
JI		 2628 struct uart_8250_port *up =
2629 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2630
2631 serial8250_release_std_resource(up);
2632 if (up->port.type == PORT_RSA)
2633 serial8250_release_rsa_resource(up);
2634}
2635
2636static int serial8250_request_port(struct uart_port *port)
2637{
49d5741b
JI		 2638 struct uart_8250_port *up =
2639 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2640 int ret = 0;
2641
2642 ret = serial8250_request_std_resource(up);
2643 if (ret == 0 && up->port.type == PORT_RSA) {
2644 ret = serial8250_request_rsa_resource(up);
2645 if (ret < 0)
2646 serial8250_release_std_resource(up);
2647 }
2648
2649 return ret;
2650}
2651
2652static void serial8250_config_port(struct uart_port *port, int flags)
2653{
49d5741b
JI		 2654 struct uart_8250_port *up =
2655 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2656 int probeflags = PROBE_ANY;
2657 int ret;
2658
1da177e4
LT		 2659 /*
2660 * Find the region that we can probe for. This in turn
2661 * tells us whether we can probe for the type of port.
2662 */
2663 ret = serial8250_request_std_resource(up);
2664 if (ret < 0)
2665 return;
2666
2667 ret = serial8250_request_rsa_resource(up);
2668 if (ret < 0)
2669 probeflags &= ~PROBE_RSA;
2670
b8e7e40a
AC		 2671 if (up->port.iotype != up->cur_iotype)
2672 set_io_from_upio(port);
2673
1da177e4
LT		 2674 if (flags & UART_CONFIG_TYPE)
2675 autoconfig(up, probeflags);
b2b13cdf 2676
b2b13cdf
ML		 2677 /* if access method is AU, it is a 16550 with a quirk */
2678 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
2679 up->bugs |= UART_BUG_NOMSR;
b2b13cdf 2680
1da177e4
LT		 2681 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2682 autoconfig_irq(up);
2683
2684 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2685 serial8250_release_rsa_resource(up);
2686 if (up->port.type == PORT_UNKNOWN)
2687 serial8250_release_std_resource(up);
2688}
2689
2690static int
2691serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2692{
a62c4133 2693 if (ser->irq >= nr_irqs || ser->irq < 0 ||
1da177e4
LT		 2694 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2695 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2696 ser->type == PORT_STARTECH)
2697 return -EINVAL;
2698 return 0;
2699}
2700
2701static const char *
2702serial8250_type(struct uart_port *port)
2703{
2704 int type = port->type;
2705
2706 if (type >= ARRAY_SIZE(uart_config))
2707 type = 0;
2708 return uart_config[type].name;
2709}
2710
2711static struct uart_ops serial8250_pops = {
2712 .tx_empty = serial8250_tx_empty,
2713 .set_mctrl = serial8250_set_mctrl,
2714 .get_mctrl = serial8250_get_mctrl,
2715 .stop_tx = serial8250_stop_tx,
2716 .start_tx = serial8250_start_tx,
2717 .stop_rx = serial8250_stop_rx,
2718 .enable_ms = serial8250_enable_ms,
2719 .break_ctl = serial8250_break_ctl,
2720 .startup = serial8250_startup,
2721 .shutdown = serial8250_shutdown,
2722 .set_termios = serial8250_set_termios,
dc77f161 2723 .set_ldisc = serial8250_set_ldisc,
1da177e4
LT		 2724 .pm = serial8250_pm,
2725 .type = serial8250_type,
2726 .release_port = serial8250_release_port,
2727 .request_port = serial8250_request_port,
2728 .config_port = serial8250_config_port,
2729 .verify_port = serial8250_verify_port,
f2d937f3
JW		 2730#ifdef CONFIG_CONSOLE_POLL
2731 .poll_get_char = serial8250_get_poll_char,
2732 .poll_put_char = serial8250_put_poll_char,
2733#endif
1da177e4
LT		 2734};
2735
2736static struct uart_8250_port serial8250_ports[UART_NR];
2737
af7f3743
AC		 2738static void (*serial8250_isa_config)(int port, struct uart_port *up,
2739 unsigned short *capabilities);
2740
2741void serial8250_set_isa_configurator(
2742 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2743{
2744 serial8250_isa_config = v;
2745}
2746EXPORT_SYMBOL(serial8250_set_isa_configurator);
2747
1da177e4
LT		 2748static void __init serial8250_isa_init_ports(void)
2749{
2750 struct uart_8250_port *up;
2751 static int first = 1;
4c0ebb80 2752 int i, irqflag = 0;
1da177e4
LT		 2753
2754 if (!first)
2755 return;
2756 first = 0;
2757
a61c2d78 2758 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2759 struct uart_8250_port *up = &serial8250_ports[i];
2760
2761 up->port.line = i;
2762 spin_lock_init(&up->port.lock);
2763
2764 init_timer(&up->timer);
2765 up->timer.function = serial8250_timeout;
2766
2767 /*
2768 * ALPHA_KLUDGE_MCR needs to be killed.
2769 */
2770 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2771 up->mcr_force = ALPHA_KLUDGE_MCR;
2772
2773 up->port.ops = &serial8250_pops;
2774 }
2775
4c0ebb80
AGR		 2776 if (share_irqs)
2777 irqflag = IRQF_SHARED;
2778
44454bcd 2779 for (i = 0, up = serial8250_ports;
a61c2d78 2780 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
1da177e4
LT		 2781 i++, up++) {
2782 up->port.iobase = old_serial_port[i].port;
2783 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
1c2f0493 2784 up->port.irqflags = old_serial_port[i].irqflags;
1da177e4
LT		 2785 up->port.uartclk = old_serial_port[i].baud_base * 16;
2786 up->port.flags = old_serial_port[i].flags;
2787 up->port.hub6 = old_serial_port[i].hub6;
2788 up->port.membase = old_serial_port[i].iomem_base;
2789 up->port.iotype = old_serial_port[i].io_type;
2790 up->port.regshift = old_serial_port[i].iomem_reg_shift;
7d6a07d1 2791 set_io_from_upio(&up->port);
4c0ebb80 2792 up->port.irqflags |= irqflag;
af7f3743
AC		 2793 if (serial8250_isa_config != NULL)
2794 serial8250_isa_config(i, &up->port, &up->capabilities);
2795
1da177e4
LT		 2796 }
2797}
2798
b5d228cc
SL		 2799static void
2800serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2801{
2802 up->port.type = type;
2803 up->port.fifosize = uart_config[type].fifo_size;
2804 up->capabilities = uart_config[type].flags;
2805 up->tx_loadsz = uart_config[type].tx_loadsz;
2806}
2807
1da177e4
LT		 2808static void __init
2809serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2810{
2811 int i;
2812
b8e7e40a
AC		 2813 for (i = 0; i < nr_uarts; i++) {
2814 struct uart_8250_port *up = &serial8250_ports[i];
2815 up->cur_iotype = 0xFF;
2816 }
2817
1da177e4
LT		 2818 serial8250_isa_init_ports();
2819
a61c2d78 2820 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2821 struct uart_8250_port *up = &serial8250_ports[i];
2822
2823 up->port.dev = dev;
b5d228cc
SL		 2824
2825 if (up->port.flags & UPF_FIXED_TYPE)
2826 serial8250_init_fixed_type_port(up, up->port.type);
2827
1da177e4
LT		 2828 uart_add_one_port(drv, &up->port);
2829 }
2830}
2831
2832#ifdef CONFIG_SERIAL_8250_CONSOLE
2833
d358788f
RK		 2834static void serial8250_console_putchar(struct uart_port *port, int ch)
2835{
49d5741b
JI		 2836 struct uart_8250_port *up =
2837 container_of(port, struct uart_8250_port, port);
d358788f
RK		 2838
2839 wait_for_xmitr(up, UART_LSR_THRE);
2840 serial_out(up, UART_TX, ch);
2841}
2842
1da177e4
LT		 2843/*
2844 * Print a string to the serial port trying not to disturb
2845 * any possible real use of the port...
2846 *
2847 * The console_lock must be held when we get here.
2848 */
2849static void
2850serial8250_console_write(struct console *co, const char *s, unsigned int count)
2851{
2852 struct uart_8250_port *up = &serial8250_ports[co->index];
d8a5a8d7 2853 unsigned long flags;
1da177e4 2854 unsigned int ier;
d8a5a8d7 2855 int locked = 1;
1da177e4 2856
78512ece
AM		 2857 touch_nmi_watchdog();
2858
68aa2c0d
AM		 2859 local_irq_save(flags);
2860 if (up->port.sysrq) {
2861 /* serial8250_handle_port() already took the lock */
2862 locked = 0;
2863 } else if (oops_in_progress) {
2864 locked = spin_trylock(&up->port.lock);
d8a5a8d7 2865 } else
68aa2c0d 2866 spin_lock(&up->port.lock);
d8a5a8d7 2867
1da177e4 2868 /*
dc7bf130 2869 * First save the IER then disable the interrupts
1da177e4
LT		 2870 */
2871 ier = serial_in(up, UART_IER);
2872
2873 if (up->capabilities & UART_CAP_UUE)
2874 serial_out(up, UART_IER, UART_IER_UUE);
2875 else
2876 serial_out(up, UART_IER, 0);
2877
d358788f 2878 uart_console_write(&up->port, s, count, serial8250_console_putchar);
1da177e4
LT		 2879
2880 /*
2881 * Finally, wait for transmitter to become empty
2882 * and restore the IER
2883 */
f91a3715 2884 wait_for_xmitr(up, BOTH_EMPTY);
a88d75b2 2885 serial_out(up, UART_IER, ier);
d8a5a8d7 2886
ad4c2aa6
CM		 2887 /*
2888 * The receive handling will happen properly because the
2889 * receive ready bit will still be set; it is not cleared
2890 * on read. However, modem control will not, we must
2891 * call it if we have saved something in the saved flags
2892 * while processing with interrupts off.
2893 */
2894 if (up->msr_saved_flags)
2895 check_modem_status(up);
2896
d8a5a8d7 2897 if (locked)
68aa2c0d
AM		 2898 spin_unlock(&up->port.lock);
2899 local_irq_restore(flags);
1da177e4
LT		 2900}
2901
118c0ace 2902static int __init serial8250_console_setup(struct console *co, char *options)
1da177e4
LT		 2903{
2904 struct uart_port *port;
2905 int baud = 9600;
2906 int bits = 8;
2907 int parity = 'n';
2908 int flow = 'n';
2909
2910 /*
2911 * Check whether an invalid uart number has been specified, and
2912 * if so, search for the first available port that does have
2913 * console support.
2914 */
a61c2d78 2915 if (co->index >= nr_uarts)
1da177e4
LT		 2916 co->index = 0;
2917 port = &serial8250_ports[co->index].port;
2918 if (!port->iobase && !port->membase)
2919 return -ENODEV;
2920
2921 if (options)
2922 uart_parse_options(options, &baud, &parity, &bits, &flow);
2923
2924 return uart_set_options(port, co, baud, parity, bits, flow);
2925}
2926
b6b1d877 2927static int serial8250_console_early_setup(void)
18a8bd94
YL		 2928{
2929 return serial8250_find_port_for_earlycon();
2930}
2931
1da177e4
LT		 2932static struct console serial8250_console = {
2933 .name = "ttyS",
2934 .write = serial8250_console_write,
2935 .device = uart_console_device,
2936 .setup = serial8250_console_setup,
18a8bd94 2937 .early_setup = serial8250_console_early_setup,
a80c49db 2938 .flags = CON_PRINTBUFFER | CON_ANYTIME,
1da177e4
LT		 2939 .index = -1,
2940 .data = &serial8250_reg,
2941};
2942
2943static int __init serial8250_console_init(void)
2944{
05d81d22
EB		 2945 if (nr_uarts > UART_NR)
2946 nr_uarts = UART_NR;
2947
1da177e4
LT		 2948 serial8250_isa_init_ports();
2949 register_console(&serial8250_console);
2950 return 0;
2951}
2952console_initcall(serial8250_console_init);
2953
18a8bd94 2954int serial8250_find_port(struct uart_port *p)
1da177e4
LT		 2955{
2956 int line;
2957 struct uart_port *port;
2958
a61c2d78 2959 for (line = 0; line < nr_uarts; line++) {
1da177e4 2960 port = &serial8250_ports[line].port;
50aec3b5 2961 if (uart_match_port(p, port))
1da177e4
LT		 2962 return line;
2963 }
2964 return -ENODEV;
2965}
2966
1da177e4
LT		 2967#define SERIAL8250_CONSOLE &serial8250_console
2968#else
2969#define SERIAL8250_CONSOLE NULL
2970#endif
2971
2972static struct uart_driver serial8250_reg = {
2973 .owner = THIS_MODULE,
2974 .driver_name = "serial",
1da177e4
LT		 2975 .dev_name = "ttyS",
2976 .major = TTY_MAJOR,
2977 .minor = 64,
1da177e4
LT		 2978 .cons = SERIAL8250_CONSOLE,
2979};
2980
d856c666
RK		 2981/*
2982 * early_serial_setup - early registration for 8250 ports
2983 *
2984 * Setup an 8250 port structure prior to console initialisation. Use
2985 * after console initialisation will cause undefined behaviour.
2986 */
1da177e4
LT		 2987int __init early_serial_setup(struct uart_port *port)
2988{
b430428a
DD		 2989 struct uart_port *p;
2990
1da177e4
LT		 2991 if (port->line >= ARRAY_SIZE(serial8250_ports))
2992 return -ENODEV;
2993
2994 serial8250_isa_init_ports();
b430428a
DD		 2995 p = &serial8250_ports[port->line].port;
2996 p->iobase = port->iobase;
2997 p->membase = port->membase;
2998 p->irq = port->irq;
1c2f0493 2999 p->irqflags = port->irqflags;
b430428a
DD		 3000 p->uartclk = port->uartclk;
3001 p->fifosize = port->fifosize;
3002 p->regshift = port->regshift;
3003 p->iotype = port->iotype;
3004 p->flags = port->flags;
3005 p->mapbase = port->mapbase;
3006 p->private_data = port->private_data;
125c97d8
HD		 3007 p->type = port->type;
3008 p->line = port->line;
7d6a07d1
DD		 3009
3010 set_io_from_upio(p);
3011 if (port->serial_in)
3012 p->serial_in = port->serial_in;
3013 if (port->serial_out)
3014 p->serial_out = port->serial_out;
3015
1da177e4
LT		 3016 return 0;
3017}
3018
3019/**
3020 * serial8250_suspend_port - suspend one serial port
3021 * @line: serial line number
1da177e4
LT		 3022 *
3023 * Suspend one serial port.
3024 */
3025void serial8250_suspend_port(int line)
3026{
3027 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
3028}
3029
3030/**
3031 * serial8250_resume_port - resume one serial port
3032 * @line: serial line number
1da177e4
LT		 3033 *
3034 * Resume one serial port.
3035 */
3036void serial8250_resume_port(int line)
3037{
b5b82df6
DW		 3038 struct uart_8250_port *up = &serial8250_ports[line];
3039
3040 if (up->capabilities & UART_NATSEMI) {
b5b82df6
DW		 3041 /* Ensure it's still in high speed mode */
3042 serial_outp(up, UART_LCR, 0xE0);
3043
0d0389e5 3044 ns16550a_goto_highspeed(up);
b5b82df6
DW		 3045
3046 serial_outp(up, UART_LCR, 0);
95926d2d 3047 up->port.uartclk = 921600*16;
b5b82df6
DW		 3048 }
3049 uart_resume_port(&serial8250_reg, &up->port);
1da177e4
LT		 3050}
3051
3052/*
3053 * Register a set of serial devices attached to a platform device. The
3054 * list is terminated with a zero flags entry, which means we expect
3055 * all entries to have at least UPF_BOOT_AUTOCONF set.
3056 */
3ae5eaec 3057static int __devinit serial8250_probe(struct platform_device *dev)
1da177e4 3058{
3ae5eaec 3059 struct plat_serial8250_port *p = dev->dev.platform_data;
1da177e4 3060 struct uart_port port;
4c0ebb80 3061 int ret, i, irqflag = 0;
1da177e4
LT		 3062
3063 memset(&port, 0, sizeof(struct uart_port));
3064
4c0ebb80
AGR		 3065 if (share_irqs)
3066 irqflag = IRQF_SHARED;
3067
ec9f47cd 3068 for (i = 0; p && p->flags != 0; p++, i++) {
74a19741
WN		 3069 port.iobase = p->iobase;
3070 port.membase = p->membase;
3071 port.irq = p->irq;
1c2f0493 3072 port.irqflags = p->irqflags;
74a19741
WN		 3073 port.uartclk = p->uartclk;
3074 port.regshift = p->regshift;
3075 port.iotype = p->iotype;
3076 port.flags = p->flags;
3077 port.mapbase = p->mapbase;
3078 port.hub6 = p->hub6;
3079 port.private_data = p->private_data;
8e23fcc8 3080 port.type = p->type;
7d6a07d1
DD		 3081 port.serial_in = p->serial_in;
3082 port.serial_out = p->serial_out;
235dae5d 3083 port.set_termios = p->set_termios;
c161afe9 3084 port.pm = p->pm;
74a19741 3085 port.dev = &dev->dev;
4c0ebb80 3086 port.irqflags |= irqflag;
ec9f47cd
RK		 3087 ret = serial8250_register_port(&port);
3088 if (ret < 0) {
3ae5eaec 3089 dev_err(&dev->dev, "unable to register port at index %d "
4f640efb
JB		 3090 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3091 p->iobase, (unsigned long long)p->mapbase,
3092 p->irq, ret);
ec9f47cd 3093 }
1da177e4
LT		 3094 }
3095 return 0;
3096}
3097
3098/*
3099 * Remove serial ports registered against a platform device.
3100 */
3ae5eaec 3101static int __devexit serial8250_remove(struct platform_device *dev)
1da177e4
LT		 3102{
3103 int i;
3104
a61c2d78 3105 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 3106 struct uart_8250_port *up = &serial8250_ports[i];
3107
3ae5eaec 3108 if (up->port.dev == &dev->dev)
1da177e4
LT		 3109 serial8250_unregister_port(i);
3110 }
3111 return 0;
3112}
3113
3ae5eaec 3114static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
1da177e4
LT		 3115{
3116 int i;
3117
1da177e4
LT		 3118 for (i = 0; i < UART_NR; i++) {
3119 struct uart_8250_port *up = &serial8250_ports[i];
3120
3ae5eaec 3121 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1da177e4
LT		 3122 uart_suspend_port(&serial8250_reg, &up->port);
3123 }
3124
3125 return 0;
3126}
3127
3ae5eaec 3128static int serial8250_resume(struct platform_device *dev)
1da177e4
LT		 3129{
3130 int i;
3131
1da177e4
LT		 3132 for (i = 0; i < UART_NR; i++) {
3133 struct uart_8250_port *up = &serial8250_ports[i];
3134
3ae5eaec 3135 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
b5b82df6 3136 serial8250_resume_port(i);
1da177e4
LT		 3137 }
3138
3139 return 0;
3140}
3141
3ae5eaec 3142static struct platform_driver serial8250_isa_driver = {
1da177e4
LT		 3143 .probe = serial8250_probe,
3144 .remove = __devexit_p(serial8250_remove),
3145 .suspend = serial8250_suspend,
3146 .resume = serial8250_resume,
3ae5eaec
RK		 3147 .driver = {
3148 .name = "serial8250",
7493a314 3149 .owner = THIS_MODULE,
3ae5eaec 3150 },
1da177e4
LT		 3151};
3152
3153/*
3154 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3155 * in the table in include/asm/serial.h
3156 */
3157static struct platform_device *serial8250_isa_devs;
3158
3159/*
3160 * serial8250_register_port and serial8250_unregister_port allows for
3161 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3162 * modems and PCI multiport cards.
3163 */
f392ecfa 3164static DEFINE_MUTEX(serial_mutex);
1da177e4
LT		 3165
3166static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3167{
3168 int i;
3169
3170 /*
3171 * First, find a port entry which matches.
3172 */
a61c2d78 3173 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3174 if (uart_match_port(&serial8250_ports[i].port, port))
3175 return &serial8250_ports[i];
3176
3177 /*
3178 * We didn't find a matching entry, so look for the first
3179 * free entry. We look for one which hasn't been previously
3180 * used (indicated by zero iobase).
3181 */
a61c2d78 3182 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3183 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3184 serial8250_ports[i].port.iobase == 0)
3185 return &serial8250_ports[i];
3186
3187 /*
3188 * That also failed. Last resort is to find any entry which
3189 * doesn't have a real port associated with it.
3190 */
a61c2d78 3191 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3192 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3193 return &serial8250_ports[i];
3194
3195 return NULL;
3196}
3197
3198/**
3199 * serial8250_register_port - register a serial port
3200 * @port: serial port template
3201 *
3202 * Configure the serial port specified by the request. If the
3203 * port exists and is in use, it is hung up and unregistered
3204 * first.
3205 *
3206 * The port is then probed and if necessary the IRQ is autodetected
3207 * If this fails an error is returned.
3208 *
3209 * On success the port is ready to use and the line number is returned.
3210 */
3211int serial8250_register_port(struct uart_port *port)
3212{
3213 struct uart_8250_port *uart;
3214 int ret = -ENOSPC;
3215
3216 if (port->uartclk == 0)
3217 return -EINVAL;
3218
f392ecfa 3219 mutex_lock(&serial_mutex);
1da177e4
LT		 3220
3221 uart = serial8250_find_match_or_unused(port);
3222 if (uart) {
3223 uart_remove_one_port(&serial8250_reg, &uart->port);
3224
74a19741
WN		 3225 uart->port.iobase = port->iobase;
3226 uart->port.membase = port->membase;
3227 uart->port.irq = port->irq;
1c2f0493 3228 uart->port.irqflags = port->irqflags;
74a19741
WN		 3229 uart->port.uartclk = port->uartclk;
3230 uart->port.fifosize = port->fifosize;
3231 uart->port.regshift = port->regshift;
3232 uart->port.iotype = port->iotype;
3233 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3234 uart->port.mapbase = port->mapbase;
3235 uart->port.private_data = port->private_data;
1da177e4
LT		 3236 if (port->dev)
3237 uart->port.dev = port->dev;
8e23fcc8 3238
b5d228cc
SL		 3239 if (port->flags & UPF_FIXED_TYPE)
3240 serial8250_init_fixed_type_port(uart, port->type);
8e23fcc8 3241
7d6a07d1
DD		 3242 set_io_from_upio(&uart->port);
3243 /* Possibly override default I/O functions. */
3244 if (port->serial_in)
3245 uart->port.serial_in = port->serial_in;
3246 if (port->serial_out)
3247 uart->port.serial_out = port->serial_out;
235dae5d
PL		 3248 /* Possibly override set_termios call */
3249 if (port->set_termios)
3250 uart->port.set_termios = port->set_termios;
c161afe9
ML		 3251 if (port->pm)
3252 uart->port.pm = port->pm;
1da177e4 3253
af7f3743
AC		 3254 if (serial8250_isa_config != NULL)
3255 serial8250_isa_config(0, &uart->port,
3256 &uart->capabilities);
3257
1da177e4
LT		 3258 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3259 if (ret == 0)
3260 ret = uart->port.line;
3261 }
f392ecfa 3262 mutex_unlock(&serial_mutex);
1da177e4
LT		 3263
3264 return ret;
3265}
3266EXPORT_SYMBOL(serial8250_register_port);
3267
3268/**
3269 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3270 * @line: serial line number
3271 *
3272 * Remove one serial port. This may not be called from interrupt
3273 * context. We hand the port back to the our control.
3274 */
3275void serial8250_unregister_port(int line)
3276{
3277 struct uart_8250_port *uart = &serial8250_ports[line];
3278
f392ecfa 3279 mutex_lock(&serial_mutex);
1da177e4
LT		 3280 uart_remove_one_port(&serial8250_reg, &uart->port);
3281 if (serial8250_isa_devs) {
3282 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3283 uart->port.type = PORT_UNKNOWN;
3284 uart->port.dev = &serial8250_isa_devs->dev;
3285 uart_add_one_port(&serial8250_reg, &uart->port);
3286 } else {
3287 uart->port.dev = NULL;
3288 }
f392ecfa 3289 mutex_unlock(&serial_mutex);
1da177e4
LT		 3290}
3291EXPORT_SYMBOL(serial8250_unregister_port);
3292
3293static int __init serial8250_init(void)
3294{
25db8ad5 3295 int ret;
1da177e4 3296
a61c2d78
DJ		 3297 if (nr_uarts > UART_NR)
3298 nr_uarts = UART_NR;
3299
f1fb9bb8 3300 printk(KERN_INFO "Serial: 8250/16550 driver, "
a61c2d78 3301 "%d ports, IRQ sharing %sabled\n", nr_uarts,
1da177e4
LT		 3302 share_irqs ? "en" : "dis");
3303
b70ac771
DM		 3304#ifdef CONFIG_SPARC
3305 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3306#else
3307 serial8250_reg.nr = UART_NR;
1da177e4 3308 ret = uart_register_driver(&serial8250_reg);
b70ac771 3309#endif
1da177e4
LT		 3310 if (ret)
3311 goto out;
3312
7493a314
DT		 3313 serial8250_isa_devs = platform_device_alloc("serial8250",
3314 PLAT8250_DEV_LEGACY);
3315 if (!serial8250_isa_devs) {
3316 ret = -ENOMEM;
bc965a7f 3317 goto unreg_uart_drv;
1da177e4
LT		 3318 }
3319
7493a314
DT		 3320 ret = platform_device_add(serial8250_isa_devs);
3321 if (ret)
3322 goto put_dev;
3323
1da177e4
LT		 3324 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3325
bc965a7f
RK		 3326 ret = platform_driver_register(&serial8250_isa_driver);
3327 if (ret == 0)
3328 goto out;
1da177e4 3329
bc965a7f 3330 platform_device_del(serial8250_isa_devs);
25db8ad5 3331put_dev:
7493a314 3332 platform_device_put(serial8250_isa_devs);
25db8ad5 3333unreg_uart_drv:
b70ac771
DM		 3334#ifdef CONFIG_SPARC
3335 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3336#else
1da177e4 3337 uart_unregister_driver(&serial8250_reg);
b70ac771 3338#endif
25db8ad5 3339out:
1da177e4
LT		 3340 return ret;
3341}
3342
3343static void __exit serial8250_exit(void)
3344{
3345 struct platform_device *isa_dev = serial8250_isa_devs;
3346
3347 /*
3348 * This tells serial8250_unregister_port() not to re-register
3349 * the ports (thereby making serial8250_isa_driver permanently
3350 * in use.)
3351 */
3352 serial8250_isa_devs = NULL;
3353
3ae5eaec 3354 platform_driver_unregister(&serial8250_isa_driver);
1da177e4
LT		 3355 platform_device_unregister(isa_dev);
3356
b70ac771
DM		 3357#ifdef CONFIG_SPARC
3358 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3359#else
1da177e4 3360 uart_unregister_driver(&serial8250_reg);
b70ac771 3361#endif
1da177e4
LT		 3362}
3363
3364module_init(serial8250_init);
3365module_exit(serial8250_exit);
3366
3367EXPORT_SYMBOL(serial8250_suspend_port);
3368EXPORT_SYMBOL(serial8250_resume_port);
3369
3370MODULE_LICENSE("GPL");
d87a6d95 3371MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
1da177e4
LT		 3372
3373module_param(share_irqs, uint, 0644);
3374MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3375 " (unsafe)");
3376
a61c2d78
DJ		 3377module_param(nr_uarts, uint, 0644);
3378MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3379
d41a4b51
CE		 3380module_param(skip_txen_test, uint, 0644);
3381MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3382
1da177e4
LT		 3383#ifdef CONFIG_SERIAL_8250_RSA
3384module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3385MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3386#endif
3387MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
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