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1e6c9c28 | 1 | /* |
7192f92c | 2 | * Driver for Atmel AT91 / AT32 Serial ports |
1e6c9c28 AV |
3 | * Copyright (C) 2003 Rick Bronson |
4 | * | |
5 | * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd. | |
6 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
7 | * | |
a6670615 CC |
8 | * DMA support added by Chip Coldwell. |
9 | * | |
1e6c9c28 AV |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | * | |
24 | */ | |
1e6c9c28 AV |
25 | #include <linux/tty.h> |
26 | #include <linux/ioport.h> | |
27 | #include <linux/slab.h> | |
28 | #include <linux/init.h> | |
29 | #include <linux/serial.h> | |
afefc415 | 30 | #include <linux/clk.h> |
1e6c9c28 AV |
31 | #include <linux/console.h> |
32 | #include <linux/sysrq.h> | |
33 | #include <linux/tty_flip.h> | |
afefc415 | 34 | #include <linux/platform_device.h> |
5fbe46b6 NF |
35 | #include <linux/of.h> |
36 | #include <linux/of_device.h> | |
354e57f3 | 37 | #include <linux/of_gpio.h> |
a6670615 | 38 | #include <linux/dma-mapping.h> |
6b997bab | 39 | #include <linux/dmaengine.h> |
93a3ddc2 | 40 | #include <linux/atmel_pdc.h> |
fa3218d8 | 41 | #include <linux/atmel_serial.h> |
e8faff73 | 42 | #include <linux/uaccess.h> |
bcd2360c | 43 | #include <linux/platform_data/atmel.h> |
2e68c22f | 44 | #include <linux/timer.h> |
354e57f3 | 45 | #include <linux/gpio.h> |
e0b0baad RG |
46 | #include <linux/gpio/consumer.h> |
47 | #include <linux/err.h> | |
ab5e4e41 | 48 | #include <linux/irq.h> |
2c7af5ba | 49 | #include <linux/suspend.h> |
1e6c9c28 AV |
50 | |
51 | #include <asm/io.h> | |
f7512e7c | 52 | #include <asm/ioctls.h> |
1e6c9c28 | 53 | |
a6670615 CC |
54 | #define PDC_BUFFER_SIZE 512 |
55 | /* Revisit: We should calculate this based on the actual port settings */ | |
56 | #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */ | |
57 | ||
b5199d46 CP |
58 | /* The minium number of data FIFOs should be able to contain */ |
59 | #define ATMEL_MIN_FIFO_SIZE 8 | |
60 | /* | |
61 | * These two offsets are substracted from the RX FIFO size to define the RTS | |
62 | * high and low thresholds | |
63 | */ | |
64 | #define ATMEL_RTS_HIGH_OFFSET 16 | |
65 | #define ATMEL_RTS_LOW_OFFSET 20 | |
66 | ||
749c4e60 | 67 | #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
1e6c9c28 AV |
68 | #define SUPPORT_SYSRQ |
69 | #endif | |
70 | ||
71 | #include <linux/serial_core.h> | |
72 | ||
e0b0baad RG |
73 | #include "serial_mctrl_gpio.h" |
74 | ||
e8faff73 CS |
75 | static void atmel_start_rx(struct uart_port *port); |
76 | static void atmel_stop_rx(struct uart_port *port); | |
77 | ||
749c4e60 | 78 | #ifdef CONFIG_SERIAL_ATMEL_TTYAT |
1e6c9c28 AV |
79 | |
80 | /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we | |
81 | * should coexist with the 8250 driver, such as if we have an external 16C550 | |
82 | * UART. */ | |
7192f92c | 83 | #define SERIAL_ATMEL_MAJOR 204 |
1e6c9c28 | 84 | #define MINOR_START 154 |
7192f92c | 85 | #define ATMEL_DEVICENAME "ttyAT" |
1e6c9c28 AV |
86 | |
87 | #else | |
88 | ||
89 | /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port | |
90 | * name, but it is legally reserved for the 8250 driver. */ | |
7192f92c | 91 | #define SERIAL_ATMEL_MAJOR TTY_MAJOR |
1e6c9c28 | 92 | #define MINOR_START 64 |
7192f92c | 93 | #define ATMEL_DEVICENAME "ttyS" |
1e6c9c28 AV |
94 | |
95 | #endif | |
96 | ||
7192f92c | 97 | #define ATMEL_ISR_PASS_LIMIT 256 |
1e6c9c28 | 98 | |
a6670615 CC |
99 | struct atmel_dma_buffer { |
100 | unsigned char *buf; | |
101 | dma_addr_t dma_addr; | |
102 | unsigned int dma_size; | |
103 | unsigned int ofs; | |
104 | }; | |
105 | ||
1ecc26bd RB |
106 | struct atmel_uart_char { |
107 | u16 status; | |
108 | u16 ch; | |
109 | }; | |
110 | ||
637ba54f LD |
111 | /* |
112 | * Be careful, the real size of the ring buffer is | |
113 | * sizeof(atmel_uart_char) * ATMEL_SERIAL_RINGSIZE. It means that ring buffer | |
114 | * can contain up to 1024 characters in PIO mode and up to 4096 characters in | |
115 | * DMA mode. | |
116 | */ | |
1ecc26bd RB |
117 | #define ATMEL_SERIAL_RINGSIZE 1024 |
118 | ||
9af92fbf AB |
119 | /* |
120 | * at91: 6 USARTs and one DBGU port (SAM9260) | |
121 | * avr32: 4 | |
122 | */ | |
123 | #define ATMEL_MAX_UART 7 | |
124 | ||
afefc415 AV |
125 | /* |
126 | * We wrap our port structure around the generic uart_port. | |
127 | */ | |
7192f92c | 128 | struct atmel_uart_port { |
afefc415 AV |
129 | struct uart_port uart; /* uart */ |
130 | struct clk *clk; /* uart clock */ | |
f05596db AS |
131 | int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */ |
132 | u32 backup_imr; /* IMR saved during suspend */ | |
9e6077bd | 133 | int break_active; /* break being received */ |
1ecc26bd | 134 | |
34df42f5 | 135 | bool use_dma_rx; /* enable DMA receiver */ |
64e22ebe | 136 | bool use_pdc_rx; /* enable PDC receiver */ |
a6670615 CC |
137 | short pdc_rx_idx; /* current PDC RX buffer */ |
138 | struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */ | |
139 | ||
08f738be | 140 | bool use_dma_tx; /* enable DMA transmitter */ |
64e22ebe | 141 | bool use_pdc_tx; /* enable PDC transmitter */ |
a6670615 CC |
142 | struct atmel_dma_buffer pdc_tx; /* PDC transmitter */ |
143 | ||
08f738be | 144 | spinlock_t lock_tx; /* port lock */ |
34df42f5 | 145 | spinlock_t lock_rx; /* port lock */ |
08f738be | 146 | struct dma_chan *chan_tx; |
34df42f5 | 147 | struct dma_chan *chan_rx; |
08f738be | 148 | struct dma_async_tx_descriptor *desc_tx; |
34df42f5 | 149 | struct dma_async_tx_descriptor *desc_rx; |
08f738be | 150 | dma_cookie_t cookie_tx; |
34df42f5 | 151 | dma_cookie_t cookie_rx; |
08f738be | 152 | struct scatterlist sg_tx; |
34df42f5 | 153 | struct scatterlist sg_rx; |
00e8e658 NF |
154 | struct tasklet_struct tasklet_rx; |
155 | struct tasklet_struct tasklet_tx; | |
98f2082c | 156 | atomic_t tasklet_shutdown; |
1ecc26bd | 157 | unsigned int irq_status_prev; |
5f258b3e | 158 | unsigned int tx_len; |
1ecc26bd RB |
159 | |
160 | struct circ_buf rx_ring; | |
e8faff73 | 161 | |
e0b0baad | 162 | struct mctrl_gpios *gpios; |
e8faff73 | 163 | unsigned int tx_done_mask; |
b5199d46 CP |
164 | u32 fifo_size; |
165 | u32 rts_high; | |
166 | u32 rts_low; | |
ab5e4e41 | 167 | bool ms_irq_enabled; |
2958ccee | 168 | u32 rtor; /* address of receiver timeout register if it exists */ |
5bf5635a | 169 | bool has_frac_baudrate; |
4b769371 NF |
170 | bool has_hw_timer; |
171 | struct timer_list uart_timer; | |
2c7af5ba BB |
172 | |
173 | bool suspended; | |
174 | unsigned int pending; | |
175 | unsigned int pending_status; | |
176 | spinlock_t lock_suspended; | |
177 | ||
a930e528 ES |
178 | int (*prepare_rx)(struct uart_port *port); |
179 | int (*prepare_tx)(struct uart_port *port); | |
180 | void (*schedule_rx)(struct uart_port *port); | |
181 | void (*schedule_tx)(struct uart_port *port); | |
182 | void (*release_rx)(struct uart_port *port); | |
183 | void (*release_tx)(struct uart_port *port); | |
afefc415 AV |
184 | }; |
185 | ||
7192f92c | 186 | static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART]; |
503bded9 | 187 | static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART); |
afefc415 | 188 | |
1e6c9c28 | 189 | #ifdef SUPPORT_SYSRQ |
7192f92c | 190 | static struct console atmel_console; |
1e6c9c28 AV |
191 | #endif |
192 | ||
5fbe46b6 NF |
193 | #if defined(CONFIG_OF) |
194 | static const struct of_device_id atmel_serial_dt_ids[] = { | |
195 | { .compatible = "atmel,at91rm9200-usart" }, | |
196 | { .compatible = "atmel,at91sam9260-usart" }, | |
197 | { /* sentinel */ } | |
198 | }; | |
5fbe46b6 NF |
199 | #endif |
200 | ||
c811ab8c HS |
201 | static inline struct atmel_uart_port * |
202 | to_atmel_uart_port(struct uart_port *uart) | |
203 | { | |
204 | return container_of(uart, struct atmel_uart_port, uart); | |
205 | } | |
206 | ||
4e7decda CP |
207 | static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg) |
208 | { | |
209 | return __raw_readl(port->membase + reg); | |
210 | } | |
211 | ||
212 | static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value) | |
213 | { | |
214 | __raw_writel(value, port->membase + reg); | |
215 | } | |
216 | ||
a6499435 CP |
217 | #ifdef CONFIG_AVR32 |
218 | ||
219 | /* AVR32 cannot handle 8 or 16bit I/O accesses but only 32bit I/O accesses */ | |
220 | static inline u8 atmel_uart_read_char(struct uart_port *port) | |
221 | { | |
222 | return __raw_readl(port->membase + ATMEL_US_RHR); | |
223 | } | |
224 | ||
225 | static inline void atmel_uart_write_char(struct uart_port *port, u8 value) | |
b5199d46 | 226 | { |
a6499435 | 227 | __raw_writel(value, port->membase + ATMEL_US_THR); |
b5199d46 CP |
228 | } |
229 | ||
a6499435 CP |
230 | #else |
231 | ||
232 | static inline u8 atmel_uart_read_char(struct uart_port *port) | |
b5199d46 | 233 | { |
a6499435 | 234 | return __raw_readb(port->membase + ATMEL_US_RHR); |
b5199d46 CP |
235 | } |
236 | ||
a6499435 CP |
237 | static inline void atmel_uart_write_char(struct uart_port *port, u8 value) |
238 | { | |
239 | __raw_writeb(value, port->membase + ATMEL_US_THR); | |
240 | } | |
241 | ||
242 | #endif | |
243 | ||
a6670615 | 244 | #ifdef CONFIG_SERIAL_ATMEL_PDC |
64e22ebe | 245 | static bool atmel_use_pdc_rx(struct uart_port *port) |
a6670615 | 246 | { |
c811ab8c | 247 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
a6670615 | 248 | |
64e22ebe | 249 | return atmel_port->use_pdc_rx; |
a6670615 CC |
250 | } |
251 | ||
64e22ebe | 252 | static bool atmel_use_pdc_tx(struct uart_port *port) |
a6670615 | 253 | { |
c811ab8c | 254 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
a6670615 | 255 | |
64e22ebe | 256 | return atmel_port->use_pdc_tx; |
a6670615 CC |
257 | } |
258 | #else | |
64e22ebe | 259 | static bool atmel_use_pdc_rx(struct uart_port *port) |
a6670615 CC |
260 | { |
261 | return false; | |
262 | } | |
263 | ||
64e22ebe | 264 | static bool atmel_use_pdc_tx(struct uart_port *port) |
a6670615 CC |
265 | { |
266 | return false; | |
267 | } | |
268 | #endif | |
269 | ||
08f738be ES |
270 | static bool atmel_use_dma_tx(struct uart_port *port) |
271 | { | |
272 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
273 | ||
274 | return atmel_port->use_dma_tx; | |
275 | } | |
276 | ||
34df42f5 ES |
277 | static bool atmel_use_dma_rx(struct uart_port *port) |
278 | { | |
279 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
280 | ||
281 | return atmel_port->use_dma_rx; | |
282 | } | |
283 | ||
5be605ac AB |
284 | static bool atmel_use_fifo(struct uart_port *port) |
285 | { | |
286 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
287 | ||
288 | return atmel_port->fifo_size; | |
289 | } | |
290 | ||
98f2082c NF |
291 | static void atmel_tasklet_schedule(struct atmel_uart_port *atmel_port, |
292 | struct tasklet_struct *t) | |
293 | { | |
294 | if (!atomic_read(&atmel_port->tasklet_shutdown)) | |
295 | tasklet_schedule(t); | |
296 | } | |
297 | ||
e0b0baad RG |
298 | static unsigned int atmel_get_lines_status(struct uart_port *port) |
299 | { | |
300 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
301 | unsigned int status, ret = 0; | |
302 | ||
4e7decda | 303 | status = atmel_uart_readl(port, ATMEL_US_CSR); |
e0b0baad RG |
304 | |
305 | mctrl_gpio_get(atmel_port->gpios, &ret); | |
306 | ||
307 | if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios, | |
308 | UART_GPIO_CTS))) { | |
309 | if (ret & TIOCM_CTS) | |
310 | status &= ~ATMEL_US_CTS; | |
311 | else | |
312 | status |= ATMEL_US_CTS; | |
313 | } | |
314 | ||
315 | if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios, | |
316 | UART_GPIO_DSR))) { | |
317 | if (ret & TIOCM_DSR) | |
318 | status &= ~ATMEL_US_DSR; | |
319 | else | |
320 | status |= ATMEL_US_DSR; | |
321 | } | |
322 | ||
323 | if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios, | |
324 | UART_GPIO_RI))) { | |
325 | if (ret & TIOCM_RI) | |
326 | status &= ~ATMEL_US_RI; | |
327 | else | |
328 | status |= ATMEL_US_RI; | |
329 | } | |
330 | ||
331 | if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios, | |
332 | UART_GPIO_DCD))) { | |
333 | if (ret & TIOCM_CD) | |
334 | status &= ~ATMEL_US_DCD; | |
335 | else | |
336 | status |= ATMEL_US_DCD; | |
337 | } | |
338 | ||
339 | return status; | |
340 | } | |
341 | ||
e8faff73 | 342 | /* Enable or disable the rs485 support */ |
13bd3e6f RRD |
343 | static int atmel_config_rs485(struct uart_port *port, |
344 | struct serial_rs485 *rs485conf) | |
e8faff73 CS |
345 | { |
346 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
347 | unsigned int mode; | |
e8faff73 CS |
348 | |
349 | /* Disable interrupts */ | |
4e7decda | 350 | atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask); |
e8faff73 | 351 | |
4e7decda | 352 | mode = atmel_uart_readl(port, ATMEL_US_MR); |
e8faff73 CS |
353 | |
354 | /* Resetting serial mode to RS232 (0x0) */ | |
355 | mode &= ~ATMEL_US_USMODE; | |
356 | ||
13bd3e6f | 357 | port->rs485 = *rs485conf; |
e8faff73 CS |
358 | |
359 | if (rs485conf->flags & SER_RS485_ENABLED) { | |
360 | dev_dbg(port->dev, "Setting UART to RS485\n"); | |
361 | atmel_port->tx_done_mask = ATMEL_US_TXEMPTY; | |
4e7decda CP |
362 | atmel_uart_writel(port, ATMEL_US_TTGR, |
363 | rs485conf->delay_rts_after_send); | |
e8faff73 CS |
364 | mode |= ATMEL_US_USMODE_RS485; |
365 | } else { | |
366 | dev_dbg(port->dev, "Setting UART to RS232\n"); | |
64e22ebe | 367 | if (atmel_use_pdc_tx(port)) |
e8faff73 CS |
368 | atmel_port->tx_done_mask = ATMEL_US_ENDTX | |
369 | ATMEL_US_TXBUFE; | |
370 | else | |
371 | atmel_port->tx_done_mask = ATMEL_US_TXRDY; | |
372 | } | |
4e7decda | 373 | atmel_uart_writel(port, ATMEL_US_MR, mode); |
e8faff73 CS |
374 | |
375 | /* Enable interrupts */ | |
4e7decda | 376 | atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask); |
e8faff73 | 377 | |
13bd3e6f | 378 | return 0; |
e8faff73 CS |
379 | } |
380 | ||
1e6c9c28 AV |
381 | /* |
382 | * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty. | |
383 | */ | |
7192f92c | 384 | static u_int atmel_tx_empty(struct uart_port *port) |
1e6c9c28 | 385 | { |
4e7decda CP |
386 | return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ? |
387 | TIOCSER_TEMT : | |
388 | 0; | |
1e6c9c28 AV |
389 | } |
390 | ||
391 | /* | |
392 | * Set state of the modem control output lines | |
393 | */ | |
7192f92c | 394 | static void atmel_set_mctrl(struct uart_port *port, u_int mctrl) |
1e6c9c28 AV |
395 | { |
396 | unsigned int control = 0; | |
4e7decda | 397 | unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR); |
1cf6e8fc | 398 | unsigned int rts_paused, rts_ready; |
e8faff73 | 399 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1e6c9c28 | 400 | |
1cf6e8fc CP |
401 | /* override mode to RS485 if needed, otherwise keep the current mode */ |
402 | if (port->rs485.flags & SER_RS485_ENABLED) { | |
4e7decda CP |
403 | atmel_uart_writel(port, ATMEL_US_TTGR, |
404 | port->rs485.delay_rts_after_send); | |
1cf6e8fc CP |
405 | mode &= ~ATMEL_US_USMODE; |
406 | mode |= ATMEL_US_USMODE_RS485; | |
407 | } | |
408 | ||
409 | /* set the RTS line state according to the mode */ | |
410 | if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) { | |
411 | /* force RTS line to high level */ | |
412 | rts_paused = ATMEL_US_RTSEN; | |
413 | ||
414 | /* give the control of the RTS line back to the hardware */ | |
415 | rts_ready = ATMEL_US_RTSDIS; | |
416 | } else { | |
417 | /* force RTS line to high level */ | |
418 | rts_paused = ATMEL_US_RTSDIS; | |
419 | ||
420 | /* force RTS line to low level */ | |
421 | rts_ready = ATMEL_US_RTSEN; | |
422 | } | |
423 | ||
1e6c9c28 | 424 | if (mctrl & TIOCM_RTS) |
1cf6e8fc | 425 | control |= rts_ready; |
1e6c9c28 | 426 | else |
1cf6e8fc | 427 | control |= rts_paused; |
1e6c9c28 AV |
428 | |
429 | if (mctrl & TIOCM_DTR) | |
7192f92c | 430 | control |= ATMEL_US_DTREN; |
1e6c9c28 | 431 | else |
7192f92c | 432 | control |= ATMEL_US_DTRDIS; |
1e6c9c28 | 433 | |
4e7decda | 434 | atmel_uart_writel(port, ATMEL_US_CR, control); |
afefc415 | 435 | |
e0b0baad RG |
436 | mctrl_gpio_set(atmel_port->gpios, mctrl); |
437 | ||
afefc415 | 438 | /* Local loopback mode? */ |
1cf6e8fc | 439 | mode &= ~ATMEL_US_CHMODE; |
afefc415 | 440 | if (mctrl & TIOCM_LOOP) |
7192f92c | 441 | mode |= ATMEL_US_CHMODE_LOC_LOOP; |
afefc415 | 442 | else |
7192f92c | 443 | mode |= ATMEL_US_CHMODE_NORMAL; |
e8faff73 | 444 | |
4e7decda | 445 | atmel_uart_writel(port, ATMEL_US_MR, mode); |
1e6c9c28 AV |
446 | } |
447 | ||
448 | /* | |
449 | * Get state of the modem control input lines | |
450 | */ | |
7192f92c | 451 | static u_int atmel_get_mctrl(struct uart_port *port) |
1e6c9c28 | 452 | { |
e0b0baad RG |
453 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
454 | unsigned int ret = 0, status; | |
1e6c9c28 | 455 | |
4e7decda | 456 | status = atmel_uart_readl(port, ATMEL_US_CSR); |
1e6c9c28 AV |
457 | |
458 | /* | |
459 | * The control signals are active low. | |
460 | */ | |
7192f92c | 461 | if (!(status & ATMEL_US_DCD)) |
1e6c9c28 | 462 | ret |= TIOCM_CD; |
7192f92c | 463 | if (!(status & ATMEL_US_CTS)) |
1e6c9c28 | 464 | ret |= TIOCM_CTS; |
7192f92c | 465 | if (!(status & ATMEL_US_DSR)) |
1e6c9c28 | 466 | ret |= TIOCM_DSR; |
7192f92c | 467 | if (!(status & ATMEL_US_RI)) |
1e6c9c28 AV |
468 | ret |= TIOCM_RI; |
469 | ||
e0b0baad | 470 | return mctrl_gpio_get(atmel_port->gpios, &ret); |
1e6c9c28 AV |
471 | } |
472 | ||
473 | /* | |
474 | * Stop transmitting. | |
475 | */ | |
7192f92c | 476 | static void atmel_stop_tx(struct uart_port *port) |
1e6c9c28 | 477 | { |
e8faff73 CS |
478 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
479 | ||
64e22ebe | 480 | if (atmel_use_pdc_tx(port)) { |
a6670615 | 481 | /* disable PDC transmit */ |
4e7decda | 482 | atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS); |
e8faff73 | 483 | } |
ba04d869 RG |
484 | |
485 | /* | |
486 | * Disable the transmitter. | |
487 | * This is mandatory when DMA is used, otherwise the DMA buffer | |
488 | * is fully transmitted. | |
489 | */ | |
490 | atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS); | |
491 | ||
e8faff73 | 492 | /* Disable interrupts */ |
4e7decda | 493 | atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask); |
e8faff73 | 494 | |
13bd3e6f RRD |
495 | if ((port->rs485.flags & SER_RS485_ENABLED) && |
496 | !(port->rs485.flags & SER_RS485_RX_DURING_TX)) | |
e8faff73 | 497 | atmel_start_rx(port); |
1e6c9c28 AV |
498 | } |
499 | ||
500 | /* | |
501 | * Start transmitting. | |
502 | */ | |
7192f92c | 503 | static void atmel_start_tx(struct uart_port *port) |
1e6c9c28 | 504 | { |
e8faff73 CS |
505 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
506 | ||
0058f087 AB |
507 | if (atmel_use_pdc_tx(port) && (atmel_uart_readl(port, ATMEL_PDC_PTSR) |
508 | & ATMEL_PDC_TXTEN)) | |
509 | /* The transmitter is already running. Yes, we | |
510 | really need this.*/ | |
511 | return; | |
a6670615 | 512 | |
0058f087 | 513 | if (atmel_use_pdc_tx(port) || atmel_use_dma_tx(port)) |
13bd3e6f RRD |
514 | if ((port->rs485.flags & SER_RS485_ENABLED) && |
515 | !(port->rs485.flags & SER_RS485_RX_DURING_TX)) | |
e8faff73 CS |
516 | atmel_stop_rx(port); |
517 | ||
0058f087 | 518 | if (atmel_use_pdc_tx(port)) |
a6670615 | 519 | /* re-enable PDC transmit */ |
4e7decda | 520 | atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN); |
0058f087 | 521 | |
e8faff73 | 522 | /* Enable interrupts */ |
4e7decda | 523 | atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask); |
ba04d869 RG |
524 | |
525 | /* re-enable the transmitter */ | |
526 | atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN); | |
e8faff73 CS |
527 | } |
528 | ||
529 | /* | |
530 | * start receiving - port is in process of being opened. | |
531 | */ | |
532 | static void atmel_start_rx(struct uart_port *port) | |
533 | { | |
4e7decda CP |
534 | /* reset status and receiver */ |
535 | atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA); | |
e8faff73 | 536 | |
4e7decda | 537 | atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN); |
57c36868 | 538 | |
64e22ebe | 539 | if (atmel_use_pdc_rx(port)) { |
e8faff73 | 540 | /* enable PDC controller */ |
4e7decda CP |
541 | atmel_uart_writel(port, ATMEL_US_IER, |
542 | ATMEL_US_ENDRX | ATMEL_US_TIMEOUT | | |
543 | port->read_status_mask); | |
544 | atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN); | |
e8faff73 | 545 | } else { |
4e7decda | 546 | atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY); |
e8faff73 | 547 | } |
1e6c9c28 AV |
548 | } |
549 | ||
550 | /* | |
551 | * Stop receiving - port is in process of being closed. | |
552 | */ | |
7192f92c | 553 | static void atmel_stop_rx(struct uart_port *port) |
1e6c9c28 | 554 | { |
4e7decda | 555 | atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS); |
57c36868 | 556 | |
64e22ebe | 557 | if (atmel_use_pdc_rx(port)) { |
a6670615 | 558 | /* disable PDC receive */ |
4e7decda CP |
559 | atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS); |
560 | atmel_uart_writel(port, ATMEL_US_IDR, | |
561 | ATMEL_US_ENDRX | ATMEL_US_TIMEOUT | | |
562 | port->read_status_mask); | |
e8faff73 | 563 | } else { |
4e7decda | 564 | atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY); |
e8faff73 | 565 | } |
1e6c9c28 AV |
566 | } |
567 | ||
568 | /* | |
569 | * Enable modem status interrupts | |
570 | */ | |
7192f92c | 571 | static void atmel_enable_ms(struct uart_port *port) |
1e6c9c28 | 572 | { |
ab5e4e41 RG |
573 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
574 | uint32_t ier = 0; | |
575 | ||
576 | /* | |
577 | * Interrupt should not be enabled twice | |
578 | */ | |
579 | if (atmel_port->ms_irq_enabled) | |
580 | return; | |
581 | ||
582 | atmel_port->ms_irq_enabled = true; | |
583 | ||
18dfef9c | 584 | if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) |
ab5e4e41 RG |
585 | ier |= ATMEL_US_CTSIC; |
586 | ||
18dfef9c | 587 | if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR)) |
ab5e4e41 RG |
588 | ier |= ATMEL_US_DSRIC; |
589 | ||
18dfef9c | 590 | if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI)) |
ab5e4e41 RG |
591 | ier |= ATMEL_US_RIIC; |
592 | ||
18dfef9c | 593 | if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD)) |
ab5e4e41 RG |
594 | ier |= ATMEL_US_DCDIC; |
595 | ||
4e7decda | 596 | atmel_uart_writel(port, ATMEL_US_IER, ier); |
18dfef9c UKK |
597 | |
598 | mctrl_gpio_enable_ms(atmel_port->gpios); | |
1e6c9c28 AV |
599 | } |
600 | ||
35b675b9 RG |
601 | /* |
602 | * Disable modem status interrupts | |
603 | */ | |
604 | static void atmel_disable_ms(struct uart_port *port) | |
605 | { | |
606 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
607 | uint32_t idr = 0; | |
608 | ||
609 | /* | |
610 | * Interrupt should not be disabled twice | |
611 | */ | |
612 | if (!atmel_port->ms_irq_enabled) | |
613 | return; | |
614 | ||
615 | atmel_port->ms_irq_enabled = false; | |
616 | ||
18dfef9c UKK |
617 | mctrl_gpio_disable_ms(atmel_port->gpios); |
618 | ||
619 | if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) | |
35b675b9 RG |
620 | idr |= ATMEL_US_CTSIC; |
621 | ||
18dfef9c | 622 | if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR)) |
35b675b9 RG |
623 | idr |= ATMEL_US_DSRIC; |
624 | ||
18dfef9c | 625 | if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI)) |
35b675b9 RG |
626 | idr |= ATMEL_US_RIIC; |
627 | ||
18dfef9c | 628 | if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD)) |
35b675b9 RG |
629 | idr |= ATMEL_US_DCDIC; |
630 | ||
4e7decda | 631 | atmel_uart_writel(port, ATMEL_US_IDR, idr); |
35b675b9 RG |
632 | } |
633 | ||
1e6c9c28 AV |
634 | /* |
635 | * Control the transmission of a break signal | |
636 | */ | |
7192f92c | 637 | static void atmel_break_ctl(struct uart_port *port, int break_state) |
1e6c9c28 AV |
638 | { |
639 | if (break_state != 0) | |
4e7decda CP |
640 | /* start break */ |
641 | atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK); | |
1e6c9c28 | 642 | else |
4e7decda CP |
643 | /* stop break */ |
644 | atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK); | |
1e6c9c28 AV |
645 | } |
646 | ||
1ecc26bd RB |
647 | /* |
648 | * Stores the incoming character in the ring buffer | |
649 | */ | |
650 | static void | |
651 | atmel_buffer_rx_char(struct uart_port *port, unsigned int status, | |
652 | unsigned int ch) | |
653 | { | |
c811ab8c | 654 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd RB |
655 | struct circ_buf *ring = &atmel_port->rx_ring; |
656 | struct atmel_uart_char *c; | |
657 | ||
658 | if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE)) | |
659 | /* Buffer overflow, ignore char */ | |
660 | return; | |
661 | ||
662 | c = &((struct atmel_uart_char *)ring->buf)[ring->head]; | |
663 | c->status = status; | |
664 | c->ch = ch; | |
665 | ||
666 | /* Make sure the character is stored before we update head. */ | |
667 | smp_wmb(); | |
668 | ||
669 | ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1); | |
670 | } | |
671 | ||
a6670615 CC |
672 | /* |
673 | * Deal with parity, framing and overrun errors. | |
674 | */ | |
675 | static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status) | |
676 | { | |
677 | /* clear error */ | |
4e7decda | 678 | atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA); |
a6670615 CC |
679 | |
680 | if (status & ATMEL_US_RXBRK) { | |
681 | /* ignore side-effect */ | |
682 | status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); | |
683 | port->icount.brk++; | |
684 | } | |
685 | if (status & ATMEL_US_PARE) | |
686 | port->icount.parity++; | |
687 | if (status & ATMEL_US_FRAME) | |
688 | port->icount.frame++; | |
689 | if (status & ATMEL_US_OVRE) | |
690 | port->icount.overrun++; | |
691 | } | |
692 | ||
1e6c9c28 AV |
693 | /* |
694 | * Characters received (called from interrupt handler) | |
695 | */ | |
7d12e780 | 696 | static void atmel_rx_chars(struct uart_port *port) |
1e6c9c28 | 697 | { |
c811ab8c | 698 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd | 699 | unsigned int status, ch; |
1e6c9c28 | 700 | |
4e7decda | 701 | status = atmel_uart_readl(port, ATMEL_US_CSR); |
7192f92c | 702 | while (status & ATMEL_US_RXRDY) { |
a6499435 | 703 | ch = atmel_uart_read_char(port); |
1e6c9c28 | 704 | |
1e6c9c28 AV |
705 | /* |
706 | * note that the error handling code is | |
707 | * out of the main execution path | |
708 | */ | |
9e6077bd HS |
709 | if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME |
710 | | ATMEL_US_OVRE | ATMEL_US_RXBRK) | |
711 | || atmel_port->break_active)) { | |
1ecc26bd | 712 | |
b843aa21 | 713 | /* clear error */ |
4e7decda | 714 | atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA); |
1ecc26bd | 715 | |
9e6077bd HS |
716 | if (status & ATMEL_US_RXBRK |
717 | && !atmel_port->break_active) { | |
9e6077bd | 718 | atmel_port->break_active = 1; |
4e7decda CP |
719 | atmel_uart_writel(port, ATMEL_US_IER, |
720 | ATMEL_US_RXBRK); | |
9e6077bd HS |
721 | } else { |
722 | /* | |
723 | * This is either the end-of-break | |
724 | * condition or we've received at | |
725 | * least one character without RXBRK | |
726 | * being set. In both cases, the next | |
727 | * RXBRK will indicate start-of-break. | |
728 | */ | |
4e7decda CP |
729 | atmel_uart_writel(port, ATMEL_US_IDR, |
730 | ATMEL_US_RXBRK); | |
9e6077bd HS |
731 | status &= ~ATMEL_US_RXBRK; |
732 | atmel_port->break_active = 0; | |
afefc415 | 733 | } |
1e6c9c28 AV |
734 | } |
735 | ||
1ecc26bd | 736 | atmel_buffer_rx_char(port, status, ch); |
4e7decda | 737 | status = atmel_uart_readl(port, ATMEL_US_CSR); |
1e6c9c28 AV |
738 | } |
739 | ||
98f2082c | 740 | atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx); |
1e6c9c28 AV |
741 | } |
742 | ||
743 | /* | |
1ecc26bd RB |
744 | * Transmit characters (called from tasklet with TXRDY interrupt |
745 | * disabled) | |
1e6c9c28 | 746 | */ |
7192f92c | 747 | static void atmel_tx_chars(struct uart_port *port) |
1e6c9c28 | 748 | { |
ebd2c8f6 | 749 | struct circ_buf *xmit = &port->state->xmit; |
e8faff73 | 750 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1e6c9c28 | 751 | |
4e7decda CP |
752 | if (port->x_char && |
753 | (atmel_uart_readl(port, ATMEL_US_CSR) & atmel_port->tx_done_mask)) { | |
a6499435 | 754 | atmel_uart_write_char(port, port->x_char); |
1e6c9c28 AV |
755 | port->icount.tx++; |
756 | port->x_char = 0; | |
1e6c9c28 | 757 | } |
1ecc26bd | 758 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) |
1e6c9c28 | 759 | return; |
1e6c9c28 | 760 | |
4e7decda CP |
761 | while (atmel_uart_readl(port, ATMEL_US_CSR) & |
762 | atmel_port->tx_done_mask) { | |
a6499435 | 763 | atmel_uart_write_char(port, xmit->buf[xmit->tail]); |
1e6c9c28 AV |
764 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); |
765 | port->icount.tx++; | |
766 | if (uart_circ_empty(xmit)) | |
767 | break; | |
768 | } | |
769 | ||
770 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
771 | uart_write_wakeup(port); | |
772 | ||
1ecc26bd | 773 | if (!uart_circ_empty(xmit)) |
e8faff73 | 774 | /* Enable interrupts */ |
4e7decda CP |
775 | atmel_uart_writel(port, ATMEL_US_IER, |
776 | atmel_port->tx_done_mask); | |
1e6c9c28 AV |
777 | } |
778 | ||
08f738be ES |
779 | static void atmel_complete_tx_dma(void *arg) |
780 | { | |
781 | struct atmel_uart_port *atmel_port = arg; | |
782 | struct uart_port *port = &atmel_port->uart; | |
783 | struct circ_buf *xmit = &port->state->xmit; | |
784 | struct dma_chan *chan = atmel_port->chan_tx; | |
785 | unsigned long flags; | |
786 | ||
787 | spin_lock_irqsave(&port->lock, flags); | |
788 | ||
789 | if (chan) | |
790 | dmaengine_terminate_all(chan); | |
5f258b3e | 791 | xmit->tail += atmel_port->tx_len; |
08f738be ES |
792 | xmit->tail &= UART_XMIT_SIZE - 1; |
793 | ||
5f258b3e | 794 | port->icount.tx += atmel_port->tx_len; |
08f738be ES |
795 | |
796 | spin_lock_irq(&atmel_port->lock_tx); | |
797 | async_tx_ack(atmel_port->desc_tx); | |
798 | atmel_port->cookie_tx = -EINVAL; | |
799 | atmel_port->desc_tx = NULL; | |
800 | spin_unlock_irq(&atmel_port->lock_tx); | |
801 | ||
802 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
803 | uart_write_wakeup(port); | |
804 | ||
1842dc2e CP |
805 | /* |
806 | * xmit is a circular buffer so, if we have just send data from | |
807 | * xmit->tail to the end of xmit->buf, now we have to transmit the | |
808 | * remaining data from the beginning of xmit->buf to xmit->head. | |
809 | */ | |
08f738be | 810 | if (!uart_circ_empty(xmit)) |
98f2082c | 811 | atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx); |
2d789bd1 RG |
812 | else if ((port->rs485.flags & SER_RS485_ENABLED) && |
813 | !(port->rs485.flags & SER_RS485_RX_DURING_TX)) { | |
814 | /* DMA done, stop TX, start RX for RS485 */ | |
815 | atmel_start_rx(port); | |
816 | } | |
08f738be ES |
817 | |
818 | spin_unlock_irqrestore(&port->lock, flags); | |
819 | } | |
820 | ||
821 | static void atmel_release_tx_dma(struct uart_port *port) | |
822 | { | |
823 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
824 | struct dma_chan *chan = atmel_port->chan_tx; | |
825 | ||
826 | if (chan) { | |
827 | dmaengine_terminate_all(chan); | |
828 | dma_release_channel(chan); | |
829 | dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1, | |
48479148 | 830 | DMA_TO_DEVICE); |
08f738be ES |
831 | } |
832 | ||
833 | atmel_port->desc_tx = NULL; | |
834 | atmel_port->chan_tx = NULL; | |
835 | atmel_port->cookie_tx = -EINVAL; | |
836 | } | |
837 | ||
838 | /* | |
839 | * Called from tasklet with TXRDY interrupt is disabled. | |
840 | */ | |
841 | static void atmel_tx_dma(struct uart_port *port) | |
842 | { | |
843 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
844 | struct circ_buf *xmit = &port->state->xmit; | |
845 | struct dma_chan *chan = atmel_port->chan_tx; | |
846 | struct dma_async_tx_descriptor *desc; | |
5f258b3e CP |
847 | struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx; |
848 | unsigned int tx_len, part1_len, part2_len, sg_len; | |
849 | dma_addr_t phys_addr; | |
08f738be ES |
850 | |
851 | /* Make sure we have an idle channel */ | |
852 | if (atmel_port->desc_tx != NULL) | |
853 | return; | |
854 | ||
855 | if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) { | |
856 | /* | |
857 | * DMA is idle now. | |
858 | * Port xmit buffer is already mapped, | |
859 | * and it is one page... Just adjust | |
860 | * offsets and lengths. Since it is a circular buffer, | |
861 | * we have to transmit till the end, and then the rest. | |
862 | * Take the port lock to get a | |
863 | * consistent xmit buffer state. | |
864 | */ | |
5f258b3e CP |
865 | tx_len = CIRC_CNT_TO_END(xmit->head, |
866 | xmit->tail, | |
867 | UART_XMIT_SIZE); | |
868 | ||
869 | if (atmel_port->fifo_size) { | |
870 | /* multi data mode */ | |
871 | part1_len = (tx_len & ~0x3); /* DWORD access */ | |
872 | part2_len = (tx_len & 0x3); /* BYTE access */ | |
873 | } else { | |
874 | /* single data (legacy) mode */ | |
875 | part1_len = 0; | |
876 | part2_len = tx_len; /* BYTE access only */ | |
877 | } | |
878 | ||
879 | sg_init_table(sgl, 2); | |
880 | sg_len = 0; | |
881 | phys_addr = sg_dma_address(sg_tx) + xmit->tail; | |
882 | if (part1_len) { | |
883 | sg = &sgl[sg_len++]; | |
884 | sg_dma_address(sg) = phys_addr; | |
885 | sg_dma_len(sg) = part1_len; | |
886 | ||
887 | phys_addr += part1_len; | |
888 | } | |
889 | ||
890 | if (part2_len) { | |
891 | sg = &sgl[sg_len++]; | |
892 | sg_dma_address(sg) = phys_addr; | |
893 | sg_dma_len(sg) = part2_len; | |
894 | } | |
895 | ||
896 | /* | |
897 | * save tx_len so atmel_complete_tx_dma() will increase | |
898 | * xmit->tail correctly | |
899 | */ | |
900 | atmel_port->tx_len = tx_len; | |
08f738be ES |
901 | |
902 | desc = dmaengine_prep_slave_sg(chan, | |
5f258b3e CP |
903 | sgl, |
904 | sg_len, | |
1842dc2e CP |
905 | DMA_MEM_TO_DEV, |
906 | DMA_PREP_INTERRUPT | | |
907 | DMA_CTRL_ACK); | |
08f738be ES |
908 | if (!desc) { |
909 | dev_err(port->dev, "Failed to send via dma!\n"); | |
910 | return; | |
911 | } | |
912 | ||
5f258b3e | 913 | dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE); |
08f738be ES |
914 | |
915 | atmel_port->desc_tx = desc; | |
916 | desc->callback = atmel_complete_tx_dma; | |
917 | desc->callback_param = atmel_port; | |
918 | atmel_port->cookie_tx = dmaengine_submit(desc); | |
08f738be ES |
919 | } |
920 | ||
921 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
922 | uart_write_wakeup(port); | |
923 | } | |
924 | ||
925 | static int atmel_prepare_tx_dma(struct uart_port *port) | |
926 | { | |
927 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
928 | dma_cap_mask_t mask; | |
929 | struct dma_slave_config config; | |
930 | int ret, nent; | |
931 | ||
932 | dma_cap_zero(mask); | |
933 | dma_cap_set(DMA_SLAVE, mask); | |
934 | ||
935 | atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx"); | |
936 | if (atmel_port->chan_tx == NULL) | |
937 | goto chan_err; | |
938 | dev_info(port->dev, "using %s for tx DMA transfers\n", | |
939 | dma_chan_name(atmel_port->chan_tx)); | |
940 | ||
941 | spin_lock_init(&atmel_port->lock_tx); | |
942 | sg_init_table(&atmel_port->sg_tx, 1); | |
943 | /* UART circular tx buffer is an aligned page. */ | |
2c277054 | 944 | BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf)); |
08f738be ES |
945 | sg_set_page(&atmel_port->sg_tx, |
946 | virt_to_page(port->state->xmit.buf), | |
947 | UART_XMIT_SIZE, | |
c8d1f022 | 948 | (unsigned long)port->state->xmit.buf & ~PAGE_MASK); |
08f738be ES |
949 | nent = dma_map_sg(port->dev, |
950 | &atmel_port->sg_tx, | |
951 | 1, | |
48479148 | 952 | DMA_TO_DEVICE); |
08f738be ES |
953 | |
954 | if (!nent) { | |
955 | dev_dbg(port->dev, "need to release resource of dma\n"); | |
956 | goto chan_err; | |
957 | } else { | |
c8d1f022 | 958 | dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__, |
08f738be ES |
959 | sg_dma_len(&atmel_port->sg_tx), |
960 | port->state->xmit.buf, | |
c8d1f022 | 961 | &sg_dma_address(&atmel_port->sg_tx)); |
08f738be ES |
962 | } |
963 | ||
964 | /* Configure the slave DMA */ | |
965 | memset(&config, 0, sizeof(config)); | |
966 | config.direction = DMA_MEM_TO_DEV; | |
5f258b3e CP |
967 | config.dst_addr_width = (atmel_port->fifo_size) ? |
968 | DMA_SLAVE_BUSWIDTH_4_BYTES : | |
969 | DMA_SLAVE_BUSWIDTH_1_BYTE; | |
08f738be | 970 | config.dst_addr = port->mapbase + ATMEL_US_THR; |
a8d4e016 | 971 | config.dst_maxburst = 1; |
08f738be | 972 | |
5483c10e MR |
973 | ret = dmaengine_slave_config(atmel_port->chan_tx, |
974 | &config); | |
08f738be ES |
975 | if (ret) { |
976 | dev_err(port->dev, "DMA tx slave configuration failed\n"); | |
977 | goto chan_err; | |
978 | } | |
979 | ||
980 | return 0; | |
981 | ||
982 | chan_err: | |
983 | dev_err(port->dev, "TX channel not available, switch to pio\n"); | |
984 | atmel_port->use_dma_tx = 0; | |
985 | if (atmel_port->chan_tx) | |
986 | atmel_release_tx_dma(port); | |
987 | return -EINVAL; | |
988 | } | |
989 | ||
34df42f5 ES |
990 | static void atmel_complete_rx_dma(void *arg) |
991 | { | |
992 | struct uart_port *port = arg; | |
993 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
994 | ||
98f2082c | 995 | atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx); |
34df42f5 ES |
996 | } |
997 | ||
998 | static void atmel_release_rx_dma(struct uart_port *port) | |
999 | { | |
1000 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
1001 | struct dma_chan *chan = atmel_port->chan_rx; | |
1002 | ||
1003 | if (chan) { | |
1004 | dmaengine_terminate_all(chan); | |
1005 | dma_release_channel(chan); | |
1006 | dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1, | |
48479148 | 1007 | DMA_FROM_DEVICE); |
34df42f5 ES |
1008 | } |
1009 | ||
1010 | atmel_port->desc_rx = NULL; | |
1011 | atmel_port->chan_rx = NULL; | |
1012 | atmel_port->cookie_rx = -EINVAL; | |
1013 | } | |
1014 | ||
1015 | static void atmel_rx_from_dma(struct uart_port *port) | |
1016 | { | |
1017 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
66f37aaf | 1018 | struct tty_port *tport = &port->state->port; |
34df42f5 ES |
1019 | struct circ_buf *ring = &atmel_port->rx_ring; |
1020 | struct dma_chan *chan = atmel_port->chan_rx; | |
1021 | struct dma_tx_state state; | |
1022 | enum dma_status dmastat; | |
66f37aaf | 1023 | size_t count; |
34df42f5 ES |
1024 | |
1025 | ||
1026 | /* Reset the UART timeout early so that we don't miss one */ | |
4e7decda | 1027 | atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO); |
34df42f5 ES |
1028 | dmastat = dmaengine_tx_status(chan, |
1029 | atmel_port->cookie_rx, | |
1030 | &state); | |
1031 | /* Restart a new tasklet if DMA status is error */ | |
1032 | if (dmastat == DMA_ERROR) { | |
1033 | dev_dbg(port->dev, "Get residue error, restart tasklet\n"); | |
4e7decda | 1034 | atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT); |
98f2082c | 1035 | atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx); |
34df42f5 ES |
1036 | return; |
1037 | } | |
34df42f5 | 1038 | |
66f37aaf CP |
1039 | /* CPU claims ownership of RX DMA buffer */ |
1040 | dma_sync_sg_for_cpu(port->dev, | |
1041 | &atmel_port->sg_rx, | |
1042 | 1, | |
485819b5 | 1043 | DMA_FROM_DEVICE); |
66f37aaf CP |
1044 | |
1045 | /* | |
1046 | * ring->head points to the end of data already written by the DMA. | |
1047 | * ring->tail points to the beginning of data to be read by the | |
1048 | * framework. | |
1049 | * The current transfer size should not be larger than the dma buffer | |
1050 | * length. | |
1051 | */ | |
1052 | ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue; | |
1053 | BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx)); | |
34df42f5 | 1054 | /* |
66f37aaf CP |
1055 | * At this point ring->head may point to the first byte right after the |
1056 | * last byte of the dma buffer: | |
1057 | * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx) | |
1058 | * | |
1059 | * However ring->tail must always points inside the dma buffer: | |
1060 | * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1 | |
1061 | * | |
1062 | * Since we use a ring buffer, we have to handle the case | |
1063 | * where head is lower than tail. In such a case, we first read from | |
1064 | * tail to the end of the buffer then reset tail. | |
34df42f5 | 1065 | */ |
66f37aaf CP |
1066 | if (ring->head < ring->tail) { |
1067 | count = sg_dma_len(&atmel_port->sg_rx) - ring->tail; | |
34df42f5 | 1068 | |
66f37aaf CP |
1069 | tty_insert_flip_string(tport, ring->buf + ring->tail, count); |
1070 | ring->tail = 0; | |
1071 | port->icount.rx += count; | |
1072 | } | |
34df42f5 | 1073 | |
66f37aaf CP |
1074 | /* Finally we read data from tail to head */ |
1075 | if (ring->tail < ring->head) { | |
1076 | count = ring->head - ring->tail; | |
34df42f5 | 1077 | |
66f37aaf CP |
1078 | tty_insert_flip_string(tport, ring->buf + ring->tail, count); |
1079 | /* Wrap ring->head if needed */ | |
1080 | if (ring->head >= sg_dma_len(&atmel_port->sg_rx)) | |
1081 | ring->head = 0; | |
1082 | ring->tail = ring->head; | |
34df42f5 ES |
1083 | port->icount.rx += count; |
1084 | } | |
1085 | ||
66f37aaf CP |
1086 | /* USART retreives ownership of RX DMA buffer */ |
1087 | dma_sync_sg_for_device(port->dev, | |
1088 | &atmel_port->sg_rx, | |
1089 | 1, | |
485819b5 | 1090 | DMA_FROM_DEVICE); |
66f37aaf CP |
1091 | |
1092 | /* | |
1093 | * Drop the lock here since it might end up calling | |
1094 | * uart_start(), which takes the lock. | |
1095 | */ | |
1096 | spin_unlock(&port->lock); | |
1097 | tty_flip_buffer_push(tport); | |
1098 | spin_lock(&port->lock); | |
1099 | ||
4e7decda | 1100 | atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT); |
34df42f5 ES |
1101 | } |
1102 | ||
1103 | static int atmel_prepare_rx_dma(struct uart_port *port) | |
1104 | { | |
1105 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
1106 | struct dma_async_tx_descriptor *desc; | |
1107 | dma_cap_mask_t mask; | |
1108 | struct dma_slave_config config; | |
1109 | struct circ_buf *ring; | |
1110 | int ret, nent; | |
1111 | ||
1112 | ring = &atmel_port->rx_ring; | |
1113 | ||
1114 | dma_cap_zero(mask); | |
1115 | dma_cap_set(DMA_CYCLIC, mask); | |
1116 | ||
1117 | atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx"); | |
1118 | if (atmel_port->chan_rx == NULL) | |
1119 | goto chan_err; | |
1120 | dev_info(port->dev, "using %s for rx DMA transfers\n", | |
1121 | dma_chan_name(atmel_port->chan_rx)); | |
1122 | ||
1123 | spin_lock_init(&atmel_port->lock_rx); | |
1124 | sg_init_table(&atmel_port->sg_rx, 1); | |
1125 | /* UART circular rx buffer is an aligned page. */ | |
2c277054 | 1126 | BUG_ON(!PAGE_ALIGNED(ring->buf)); |
34df42f5 | 1127 | sg_set_page(&atmel_port->sg_rx, |
1842dc2e | 1128 | virt_to_page(ring->buf), |
a510880f | 1129 | sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE, |
c8d1f022 | 1130 | (unsigned long)ring->buf & ~PAGE_MASK); |
1842dc2e CP |
1131 | nent = dma_map_sg(port->dev, |
1132 | &atmel_port->sg_rx, | |
1133 | 1, | |
1134 | DMA_FROM_DEVICE); | |
34df42f5 ES |
1135 | |
1136 | if (!nent) { | |
1137 | dev_dbg(port->dev, "need to release resource of dma\n"); | |
1138 | goto chan_err; | |
1139 | } else { | |
c8d1f022 | 1140 | dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__, |
34df42f5 ES |
1141 | sg_dma_len(&atmel_port->sg_rx), |
1142 | ring->buf, | |
c8d1f022 | 1143 | &sg_dma_address(&atmel_port->sg_rx)); |
34df42f5 ES |
1144 | } |
1145 | ||
1146 | /* Configure the slave DMA */ | |
1147 | memset(&config, 0, sizeof(config)); | |
1148 | config.direction = DMA_DEV_TO_MEM; | |
1149 | config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
1150 | config.src_addr = port->mapbase + ATMEL_US_RHR; | |
a8d4e016 | 1151 | config.src_maxburst = 1; |
34df42f5 | 1152 | |
5483c10e MR |
1153 | ret = dmaengine_slave_config(atmel_port->chan_rx, |
1154 | &config); | |
34df42f5 ES |
1155 | if (ret) { |
1156 | dev_err(port->dev, "DMA rx slave configuration failed\n"); | |
1157 | goto chan_err; | |
1158 | } | |
1159 | /* | |
1160 | * Prepare a cyclic dma transfer, assign 2 descriptors, | |
1161 | * each one is half ring buffer size | |
1162 | */ | |
1163 | desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx, | |
1842dc2e CP |
1164 | sg_dma_address(&atmel_port->sg_rx), |
1165 | sg_dma_len(&atmel_port->sg_rx), | |
1166 | sg_dma_len(&atmel_port->sg_rx)/2, | |
1167 | DMA_DEV_TO_MEM, | |
1168 | DMA_PREP_INTERRUPT); | |
fe186fdd KL |
1169 | if (!desc) { |
1170 | dev_err(port->dev, "Preparing DMA cyclic failed\n"); | |
1171 | goto chan_err; | |
1172 | } | |
34df42f5 ES |
1173 | desc->callback = atmel_complete_rx_dma; |
1174 | desc->callback_param = port; | |
1175 | atmel_port->desc_rx = desc; | |
1176 | atmel_port->cookie_rx = dmaengine_submit(desc); | |
1177 | ||
1178 | return 0; | |
1179 | ||
1180 | chan_err: | |
1181 | dev_err(port->dev, "RX channel not available, switch to pio\n"); | |
1182 | atmel_port->use_dma_rx = 0; | |
1183 | if (atmel_port->chan_rx) | |
1184 | atmel_release_rx_dma(port); | |
1185 | return -EINVAL; | |
1186 | } | |
1187 | ||
2e68c22f ES |
1188 | static void atmel_uart_timer_callback(unsigned long data) |
1189 | { | |
1190 | struct uart_port *port = (void *)data; | |
1191 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
1192 | ||
98f2082c NF |
1193 | if (!atomic_read(&atmel_port->tasklet_shutdown)) { |
1194 | tasklet_schedule(&atmel_port->tasklet_rx); | |
1195 | mod_timer(&atmel_port->uart_timer, | |
1196 | jiffies + uart_poll_timeout(port)); | |
1197 | } | |
2e68c22f ES |
1198 | } |
1199 | ||
b843aa21 RB |
1200 | /* |
1201 | * receive interrupt handler. | |
1202 | */ | |
1203 | static void | |
1204 | atmel_handle_receive(struct uart_port *port, unsigned int pending) | |
1205 | { | |
c811ab8c | 1206 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
b843aa21 | 1207 | |
64e22ebe | 1208 | if (atmel_use_pdc_rx(port)) { |
a6670615 CC |
1209 | /* |
1210 | * PDC receive. Just schedule the tasklet and let it | |
1211 | * figure out the details. | |
1212 | * | |
1213 | * TODO: We're not handling error flags correctly at | |
1214 | * the moment. | |
1215 | */ | |
1216 | if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) { | |
4e7decda CP |
1217 | atmel_uart_writel(port, ATMEL_US_IDR, |
1218 | (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)); | |
98f2082c NF |
1219 | atmel_tasklet_schedule(atmel_port, |
1220 | &atmel_port->tasklet_rx); | |
a6670615 CC |
1221 | } |
1222 | ||
1223 | if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE | | |
1224 | ATMEL_US_FRAME | ATMEL_US_PARE)) | |
1225 | atmel_pdc_rxerr(port, pending); | |
1226 | } | |
1227 | ||
34df42f5 ES |
1228 | if (atmel_use_dma_rx(port)) { |
1229 | if (pending & ATMEL_US_TIMEOUT) { | |
4e7decda CP |
1230 | atmel_uart_writel(port, ATMEL_US_IDR, |
1231 | ATMEL_US_TIMEOUT); | |
98f2082c NF |
1232 | atmel_tasklet_schedule(atmel_port, |
1233 | &atmel_port->tasklet_rx); | |
34df42f5 ES |
1234 | } |
1235 | } | |
1236 | ||
b843aa21 RB |
1237 | /* Interrupt receive */ |
1238 | if (pending & ATMEL_US_RXRDY) | |
1239 | atmel_rx_chars(port); | |
1240 | else if (pending & ATMEL_US_RXBRK) { | |
1241 | /* | |
1242 | * End of break detected. If it came along with a | |
1243 | * character, atmel_rx_chars will handle it. | |
1244 | */ | |
4e7decda CP |
1245 | atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA); |
1246 | atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK); | |
b843aa21 RB |
1247 | atmel_port->break_active = 0; |
1248 | } | |
1249 | } | |
1250 | ||
1251 | /* | |
1ecc26bd | 1252 | * transmit interrupt handler. (Transmit is IRQF_NODELAY safe) |
b843aa21 RB |
1253 | */ |
1254 | static void | |
1255 | atmel_handle_transmit(struct uart_port *port, unsigned int pending) | |
1256 | { | |
c811ab8c | 1257 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd | 1258 | |
e8faff73 CS |
1259 | if (pending & atmel_port->tx_done_mask) { |
1260 | /* Either PDC or interrupt transmission */ | |
4e7decda CP |
1261 | atmel_uart_writel(port, ATMEL_US_IDR, |
1262 | atmel_port->tx_done_mask); | |
98f2082c | 1263 | atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx); |
1ecc26bd | 1264 | } |
b843aa21 RB |
1265 | } |
1266 | ||
1267 | /* | |
1268 | * status flags interrupt handler. | |
1269 | */ | |
1270 | static void | |
1271 | atmel_handle_status(struct uart_port *port, unsigned int pending, | |
1272 | unsigned int status) | |
1273 | { | |
c811ab8c | 1274 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
9205218e | 1275 | unsigned int status_change; |
1ecc26bd | 1276 | |
b843aa21 | 1277 | if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC |
1ecc26bd | 1278 | | ATMEL_US_CTSIC)) { |
9205218e | 1279 | status_change = status ^ atmel_port->irq_status_prev; |
d033e82d | 1280 | atmel_port->irq_status_prev = status; |
9205218e NF |
1281 | |
1282 | if (status_change & (ATMEL_US_RI | ATMEL_US_DSR | |
1283 | | ATMEL_US_DCD | ATMEL_US_CTS)) { | |
1284 | /* TODO: All reads to CSR will clear these interrupts! */ | |
1285 | if (status_change & ATMEL_US_RI) | |
1286 | port->icount.rng++; | |
1287 | if (status_change & ATMEL_US_DSR) | |
1288 | port->icount.dsr++; | |
1289 | if (status_change & ATMEL_US_DCD) | |
1290 | uart_handle_dcd_change(port, !(status & ATMEL_US_DCD)); | |
1291 | if (status_change & ATMEL_US_CTS) | |
1292 | uart_handle_cts_change(port, !(status & ATMEL_US_CTS)); | |
1293 | ||
1294 | wake_up_interruptible(&port->state->port.delta_msr_wait); | |
1295 | } | |
1ecc26bd | 1296 | } |
b843aa21 RB |
1297 | } |
1298 | ||
1e6c9c28 AV |
1299 | /* |
1300 | * Interrupt handler | |
1301 | */ | |
7d12e780 | 1302 | static irqreturn_t atmel_interrupt(int irq, void *dev_id) |
1e6c9c28 AV |
1303 | { |
1304 | struct uart_port *port = dev_id; | |
ab5e4e41 | 1305 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
2c7af5ba | 1306 | unsigned int status, pending, mask, pass_counter = 0; |
1e6c9c28 | 1307 | |
2c7af5ba BB |
1308 | spin_lock(&atmel_port->lock_suspended); |
1309 | ||
a6670615 | 1310 | do { |
e0b0baad | 1311 | status = atmel_get_lines_status(port); |
4e7decda | 1312 | mask = atmel_uart_readl(port, ATMEL_US_IMR); |
2c7af5ba | 1313 | pending = status & mask; |
a6670615 CC |
1314 | if (!pending) |
1315 | break; | |
1316 | ||
2c7af5ba BB |
1317 | if (atmel_port->suspended) { |
1318 | atmel_port->pending |= pending; | |
1319 | atmel_port->pending_status = status; | |
4e7decda | 1320 | atmel_uart_writel(port, ATMEL_US_IDR, mask); |
2c7af5ba BB |
1321 | pm_system_wakeup(); |
1322 | break; | |
1323 | } | |
1324 | ||
b843aa21 RB |
1325 | atmel_handle_receive(port, pending); |
1326 | atmel_handle_status(port, pending, status); | |
1327 | atmel_handle_transmit(port, pending); | |
a6670615 | 1328 | } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT); |
afefc415 | 1329 | |
2c7af5ba BB |
1330 | spin_unlock(&atmel_port->lock_suspended); |
1331 | ||
0400b697 | 1332 | return pass_counter ? IRQ_HANDLED : IRQ_NONE; |
a6670615 | 1333 | } |
1e6c9c28 | 1334 | |
a930e528 ES |
1335 | static void atmel_release_tx_pdc(struct uart_port *port) |
1336 | { | |
1337 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
1338 | struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; | |
1339 | ||
1340 | dma_unmap_single(port->dev, | |
1341 | pdc->dma_addr, | |
1342 | pdc->dma_size, | |
1343 | DMA_TO_DEVICE); | |
1344 | } | |
1345 | ||
a6670615 CC |
1346 | /* |
1347 | * Called from tasklet with ENDTX and TXBUFE interrupts disabled. | |
1348 | */ | |
64e22ebe | 1349 | static void atmel_tx_pdc(struct uart_port *port) |
a6670615 | 1350 | { |
c811ab8c | 1351 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
ebd2c8f6 | 1352 | struct circ_buf *xmit = &port->state->xmit; |
a6670615 CC |
1353 | struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; |
1354 | int count; | |
1355 | ||
ba0657ff | 1356 | /* nothing left to transmit? */ |
4e7decda | 1357 | if (atmel_uart_readl(port, ATMEL_PDC_TCR)) |
ba0657ff MT |
1358 | return; |
1359 | ||
a6670615 CC |
1360 | xmit->tail += pdc->ofs; |
1361 | xmit->tail &= UART_XMIT_SIZE - 1; | |
1362 | ||
1363 | port->icount.tx += pdc->ofs; | |
1364 | pdc->ofs = 0; | |
1365 | ||
ba0657ff | 1366 | /* more to transmit - setup next transfer */ |
a6670615 | 1367 | |
ba0657ff | 1368 | /* disable PDC transmit */ |
4e7decda | 1369 | atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS); |
ba0657ff | 1370 | |
1f14081d | 1371 | if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) { |
a6670615 CC |
1372 | dma_sync_single_for_device(port->dev, |
1373 | pdc->dma_addr, | |
1374 | pdc->dma_size, | |
1375 | DMA_TO_DEVICE); | |
1376 | ||
1377 | count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); | |
1378 | pdc->ofs = count; | |
1379 | ||
4e7decda CP |
1380 | atmel_uart_writel(port, ATMEL_PDC_TPR, |
1381 | pdc->dma_addr + xmit->tail); | |
1382 | atmel_uart_writel(port, ATMEL_PDC_TCR, count); | |
e8faff73 | 1383 | /* re-enable PDC transmit */ |
4e7decda | 1384 | atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN); |
e8faff73 | 1385 | /* Enable interrupts */ |
4e7decda CP |
1386 | atmel_uart_writel(port, ATMEL_US_IER, |
1387 | atmel_port->tx_done_mask); | |
e8faff73 | 1388 | } else { |
13bd3e6f RRD |
1389 | if ((port->rs485.flags & SER_RS485_ENABLED) && |
1390 | !(port->rs485.flags & SER_RS485_RX_DURING_TX)) { | |
e8faff73 CS |
1391 | /* DMA done, stop TX, start RX for RS485 */ |
1392 | atmel_start_rx(port); | |
1393 | } | |
1e6c9c28 | 1394 | } |
a6670615 CC |
1395 | |
1396 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
1397 | uart_write_wakeup(port); | |
1e6c9c28 AV |
1398 | } |
1399 | ||
a930e528 ES |
1400 | static int atmel_prepare_tx_pdc(struct uart_port *port) |
1401 | { | |
1402 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
1403 | struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; | |
1404 | struct circ_buf *xmit = &port->state->xmit; | |
1405 | ||
1406 | pdc->buf = xmit->buf; | |
1407 | pdc->dma_addr = dma_map_single(port->dev, | |
1408 | pdc->buf, | |
1409 | UART_XMIT_SIZE, | |
1410 | DMA_TO_DEVICE); | |
1411 | pdc->dma_size = UART_XMIT_SIZE; | |
1412 | pdc->ofs = 0; | |
1413 | ||
1414 | return 0; | |
1415 | } | |
1416 | ||
1ecc26bd RB |
1417 | static void atmel_rx_from_ring(struct uart_port *port) |
1418 | { | |
c811ab8c | 1419 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd RB |
1420 | struct circ_buf *ring = &atmel_port->rx_ring; |
1421 | unsigned int flg; | |
1422 | unsigned int status; | |
1423 | ||
1424 | while (ring->head != ring->tail) { | |
1425 | struct atmel_uart_char c; | |
1426 | ||
1427 | /* Make sure c is loaded after head. */ | |
1428 | smp_rmb(); | |
1429 | ||
1430 | c = ((struct atmel_uart_char *)ring->buf)[ring->tail]; | |
1431 | ||
1432 | ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1); | |
1433 | ||
1434 | port->icount.rx++; | |
1435 | status = c.status; | |
1436 | flg = TTY_NORMAL; | |
1437 | ||
1438 | /* | |
1439 | * note that the error handling code is | |
1440 | * out of the main execution path | |
1441 | */ | |
1442 | if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME | |
1443 | | ATMEL_US_OVRE | ATMEL_US_RXBRK))) { | |
1444 | if (status & ATMEL_US_RXBRK) { | |
1445 | /* ignore side-effect */ | |
1446 | status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); | |
1447 | ||
1448 | port->icount.brk++; | |
1449 | if (uart_handle_break(port)) | |
1450 | continue; | |
1451 | } | |
1452 | if (status & ATMEL_US_PARE) | |
1453 | port->icount.parity++; | |
1454 | if (status & ATMEL_US_FRAME) | |
1455 | port->icount.frame++; | |
1456 | if (status & ATMEL_US_OVRE) | |
1457 | port->icount.overrun++; | |
1458 | ||
1459 | status &= port->read_status_mask; | |
1460 | ||
1461 | if (status & ATMEL_US_RXBRK) | |
1462 | flg = TTY_BREAK; | |
1463 | else if (status & ATMEL_US_PARE) | |
1464 | flg = TTY_PARITY; | |
1465 | else if (status & ATMEL_US_FRAME) | |
1466 | flg = TTY_FRAME; | |
1467 | } | |
1468 | ||
1469 | ||
1470 | if (uart_handle_sysrq_char(port, c.ch)) | |
1471 | continue; | |
1472 | ||
1473 | uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg); | |
1474 | } | |
1475 | ||
1476 | /* | |
1477 | * Drop the lock here since it might end up calling | |
1478 | * uart_start(), which takes the lock. | |
1479 | */ | |
1480 | spin_unlock(&port->lock); | |
2e124b4a | 1481 | tty_flip_buffer_push(&port->state->port); |
1ecc26bd RB |
1482 | spin_lock(&port->lock); |
1483 | } | |
1484 | ||
a930e528 ES |
1485 | static void atmel_release_rx_pdc(struct uart_port *port) |
1486 | { | |
1487 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
1488 | int i; | |
1489 | ||
1490 | for (i = 0; i < 2; i++) { | |
1491 | struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; | |
1492 | ||
1493 | dma_unmap_single(port->dev, | |
1494 | pdc->dma_addr, | |
1495 | pdc->dma_size, | |
1496 | DMA_FROM_DEVICE); | |
1497 | kfree(pdc->buf); | |
1498 | } | |
1499 | } | |
1500 | ||
64e22ebe | 1501 | static void atmel_rx_from_pdc(struct uart_port *port) |
a6670615 | 1502 | { |
c811ab8c | 1503 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
05c7cd39 | 1504 | struct tty_port *tport = &port->state->port; |
a6670615 CC |
1505 | struct atmel_dma_buffer *pdc; |
1506 | int rx_idx = atmel_port->pdc_rx_idx; | |
1507 | unsigned int head; | |
1508 | unsigned int tail; | |
1509 | unsigned int count; | |
1510 | ||
1511 | do { | |
1512 | /* Reset the UART timeout early so that we don't miss one */ | |
4e7decda | 1513 | atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO); |
a6670615 CC |
1514 | |
1515 | pdc = &atmel_port->pdc_rx[rx_idx]; | |
4e7decda | 1516 | head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr; |
a6670615 CC |
1517 | tail = pdc->ofs; |
1518 | ||
1519 | /* If the PDC has switched buffers, RPR won't contain | |
1520 | * any address within the current buffer. Since head | |
1521 | * is unsigned, we just need a one-way comparison to | |
1522 | * find out. | |
1523 | * | |
1524 | * In this case, we just need to consume the entire | |
1525 | * buffer and resubmit it for DMA. This will clear the | |
1526 | * ENDRX bit as well, so that we can safely re-enable | |
1527 | * all interrupts below. | |
1528 | */ | |
1529 | head = min(head, pdc->dma_size); | |
1530 | ||
1531 | if (likely(head != tail)) { | |
1532 | dma_sync_single_for_cpu(port->dev, pdc->dma_addr, | |
1533 | pdc->dma_size, DMA_FROM_DEVICE); | |
1534 | ||
1535 | /* | |
1536 | * head will only wrap around when we recycle | |
1537 | * the DMA buffer, and when that happens, we | |
1538 | * explicitly set tail to 0. So head will | |
1539 | * always be greater than tail. | |
1540 | */ | |
1541 | count = head - tail; | |
1542 | ||
05c7cd39 JS |
1543 | tty_insert_flip_string(tport, pdc->buf + pdc->ofs, |
1544 | count); | |
a6670615 CC |
1545 | |
1546 | dma_sync_single_for_device(port->dev, pdc->dma_addr, | |
1547 | pdc->dma_size, DMA_FROM_DEVICE); | |
1548 | ||
1549 | port->icount.rx += count; | |
1550 | pdc->ofs = head; | |
1551 | } | |
1552 | ||
1553 | /* | |
1554 | * If the current buffer is full, we need to check if | |
1555 | * the next one contains any additional data. | |
1556 | */ | |
1557 | if (head >= pdc->dma_size) { | |
1558 | pdc->ofs = 0; | |
4e7decda CP |
1559 | atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr); |
1560 | atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size); | |
a6670615 CC |
1561 | |
1562 | rx_idx = !rx_idx; | |
1563 | atmel_port->pdc_rx_idx = rx_idx; | |
1564 | } | |
1565 | } while (head >= pdc->dma_size); | |
1566 | ||
1567 | /* | |
1568 | * Drop the lock here since it might end up calling | |
1569 | * uart_start(), which takes the lock. | |
1570 | */ | |
1571 | spin_unlock(&port->lock); | |
2e124b4a | 1572 | tty_flip_buffer_push(tport); |
a6670615 CC |
1573 | spin_lock(&port->lock); |
1574 | ||
4e7decda CP |
1575 | atmel_uart_writel(port, ATMEL_US_IER, |
1576 | ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); | |
a6670615 CC |
1577 | } |
1578 | ||
a930e528 ES |
1579 | static int atmel_prepare_rx_pdc(struct uart_port *port) |
1580 | { | |
1581 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
1582 | int i; | |
1583 | ||
1584 | for (i = 0; i < 2; i++) { | |
1585 | struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; | |
1586 | ||
1587 | pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL); | |
1588 | if (pdc->buf == NULL) { | |
1589 | if (i != 0) { | |
1590 | dma_unmap_single(port->dev, | |
1591 | atmel_port->pdc_rx[0].dma_addr, | |
1592 | PDC_BUFFER_SIZE, | |
1593 | DMA_FROM_DEVICE); | |
1594 | kfree(atmel_port->pdc_rx[0].buf); | |
1595 | } | |
1596 | atmel_port->use_pdc_rx = 0; | |
1597 | return -ENOMEM; | |
1598 | } | |
1599 | pdc->dma_addr = dma_map_single(port->dev, | |
1600 | pdc->buf, | |
1601 | PDC_BUFFER_SIZE, | |
1602 | DMA_FROM_DEVICE); | |
1603 | pdc->dma_size = PDC_BUFFER_SIZE; | |
1604 | pdc->ofs = 0; | |
1605 | } | |
1606 | ||
1607 | atmel_port->pdc_rx_idx = 0; | |
1608 | ||
4e7decda CP |
1609 | atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr); |
1610 | atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE); | |
a930e528 | 1611 | |
4e7decda CP |
1612 | atmel_uart_writel(port, ATMEL_PDC_RNPR, |
1613 | atmel_port->pdc_rx[1].dma_addr); | |
1614 | atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE); | |
a930e528 ES |
1615 | |
1616 | return 0; | |
1617 | } | |
1618 | ||
1ecc26bd RB |
1619 | /* |
1620 | * tasklet handling tty stuff outside the interrupt handler. | |
1621 | */ | |
00e8e658 | 1622 | static void atmel_tasklet_rx_func(unsigned long data) |
1ecc26bd RB |
1623 | { |
1624 | struct uart_port *port = (struct uart_port *)data; | |
c811ab8c | 1625 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd RB |
1626 | |
1627 | /* The interrupt handler does not take the lock */ | |
1628 | spin_lock(&port->lock); | |
a930e528 | 1629 | atmel_port->schedule_rx(port); |
00e8e658 NF |
1630 | spin_unlock(&port->lock); |
1631 | } | |
1ecc26bd | 1632 | |
00e8e658 NF |
1633 | static void atmel_tasklet_tx_func(unsigned long data) |
1634 | { | |
1635 | struct uart_port *port = (struct uart_port *)data; | |
1636 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
1637 | ||
1638 | /* The interrupt handler does not take the lock */ | |
1639 | spin_lock(&port->lock); | |
1640 | atmel_port->schedule_tx(port); | |
1ecc26bd RB |
1641 | spin_unlock(&port->lock); |
1642 | } | |
1643 | ||
4a1e8888 | 1644 | static void atmel_init_property(struct atmel_uart_port *atmel_port, |
33d64c4f ES |
1645 | struct platform_device *pdev) |
1646 | { | |
1647 | struct device_node *np = pdev->dev.of_node; | |
574de559 | 1648 | struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); |
33d64c4f ES |
1649 | |
1650 | if (np) { | |
1651 | /* DMA/PDC usage specification */ | |
490d5ce2 JL |
1652 | if (of_property_read_bool(np, "atmel,use-dma-rx")) { |
1653 | if (of_property_read_bool(np, "dmas")) { | |
33d64c4f ES |
1654 | atmel_port->use_dma_rx = true; |
1655 | atmel_port->use_pdc_rx = false; | |
1656 | } else { | |
1657 | atmel_port->use_dma_rx = false; | |
1658 | atmel_port->use_pdc_rx = true; | |
1659 | } | |
1660 | } else { | |
1661 | atmel_port->use_dma_rx = false; | |
1662 | atmel_port->use_pdc_rx = false; | |
1663 | } | |
1664 | ||
490d5ce2 JL |
1665 | if (of_property_read_bool(np, "atmel,use-dma-tx")) { |
1666 | if (of_property_read_bool(np, "dmas")) { | |
33d64c4f ES |
1667 | atmel_port->use_dma_tx = true; |
1668 | atmel_port->use_pdc_tx = false; | |
1669 | } else { | |
1670 | atmel_port->use_dma_tx = false; | |
1671 | atmel_port->use_pdc_tx = true; | |
1672 | } | |
1673 | } else { | |
1674 | atmel_port->use_dma_tx = false; | |
1675 | atmel_port->use_pdc_tx = false; | |
1676 | } | |
1677 | ||
1678 | } else { | |
1679 | atmel_port->use_pdc_rx = pdata->use_dma_rx; | |
1680 | atmel_port->use_pdc_tx = pdata->use_dma_tx; | |
1681 | atmel_port->use_dma_rx = false; | |
1682 | atmel_port->use_dma_tx = false; | |
1683 | } | |
1684 | ||
33d64c4f ES |
1685 | } |
1686 | ||
13bd3e6f | 1687 | static void atmel_init_rs485(struct uart_port *port, |
33d64c4f ES |
1688 | struct platform_device *pdev) |
1689 | { | |
1690 | struct device_node *np = pdev->dev.of_node; | |
574de559 | 1691 | struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); |
33d64c4f ES |
1692 | |
1693 | if (np) { | |
77bdec6f | 1694 | struct serial_rs485 *rs485conf = &port->rs485; |
33d64c4f ES |
1695 | u32 rs485_delay[2]; |
1696 | /* rs485 properties */ | |
1697 | if (of_property_read_u32_array(np, "rs485-rts-delay", | |
1698 | rs485_delay, 2) == 0) { | |
33d64c4f ES |
1699 | rs485conf->delay_rts_before_send = rs485_delay[0]; |
1700 | rs485conf->delay_rts_after_send = rs485_delay[1]; | |
1701 | rs485conf->flags = 0; | |
77bdec6f | 1702 | } |
33d64c4f ES |
1703 | |
1704 | if (of_get_property(np, "rs485-rx-during-tx", NULL)) | |
1705 | rs485conf->flags |= SER_RS485_RX_DURING_TX; | |
1706 | ||
1707 | if (of_get_property(np, "linux,rs485-enabled-at-boot-time", | |
1708 | NULL)) | |
1709 | rs485conf->flags |= SER_RS485_ENABLED; | |
33d64c4f | 1710 | } else { |
13bd3e6f | 1711 | port->rs485 = pdata->rs485; |
33d64c4f ES |
1712 | } |
1713 | ||
1714 | } | |
1715 | ||
a930e528 ES |
1716 | static void atmel_set_ops(struct uart_port *port) |
1717 | { | |
1718 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
1719 | ||
34df42f5 ES |
1720 | if (atmel_use_dma_rx(port)) { |
1721 | atmel_port->prepare_rx = &atmel_prepare_rx_dma; | |
1722 | atmel_port->schedule_rx = &atmel_rx_from_dma; | |
1723 | atmel_port->release_rx = &atmel_release_rx_dma; | |
1724 | } else if (atmel_use_pdc_rx(port)) { | |
a930e528 ES |
1725 | atmel_port->prepare_rx = &atmel_prepare_rx_pdc; |
1726 | atmel_port->schedule_rx = &atmel_rx_from_pdc; | |
1727 | atmel_port->release_rx = &atmel_release_rx_pdc; | |
1728 | } else { | |
1729 | atmel_port->prepare_rx = NULL; | |
1730 | atmel_port->schedule_rx = &atmel_rx_from_ring; | |
1731 | atmel_port->release_rx = NULL; | |
1732 | } | |
1733 | ||
08f738be ES |
1734 | if (atmel_use_dma_tx(port)) { |
1735 | atmel_port->prepare_tx = &atmel_prepare_tx_dma; | |
1736 | atmel_port->schedule_tx = &atmel_tx_dma; | |
1737 | atmel_port->release_tx = &atmel_release_tx_dma; | |
1738 | } else if (atmel_use_pdc_tx(port)) { | |
a930e528 ES |
1739 | atmel_port->prepare_tx = &atmel_prepare_tx_pdc; |
1740 | atmel_port->schedule_tx = &atmel_tx_pdc; | |
1741 | atmel_port->release_tx = &atmel_release_tx_pdc; | |
1742 | } else { | |
1743 | atmel_port->prepare_tx = NULL; | |
1744 | atmel_port->schedule_tx = &atmel_tx_chars; | |
1745 | atmel_port->release_tx = NULL; | |
1746 | } | |
1747 | } | |
1748 | ||
055560b0 ES |
1749 | /* |
1750 | * Get ip name usart or uart | |
1751 | */ | |
892db58b | 1752 | static void atmel_get_ip_name(struct uart_port *port) |
055560b0 ES |
1753 | { |
1754 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
4e7decda | 1755 | int name = atmel_uart_readl(port, ATMEL_US_NAME); |
731d9cae | 1756 | u32 version; |
1d673fb9 | 1757 | u32 usart, dbgu_uart, new_uart; |
4b769371 NF |
1758 | /* ASCII decoding for IP version */ |
1759 | usart = 0x55534152; /* USAR(T) */ | |
1760 | dbgu_uart = 0x44424755; /* DBGU */ | |
1d673fb9 | 1761 | new_uart = 0x55415254; /* UART */ |
055560b0 | 1762 | |
5bf5635a LD |
1763 | /* |
1764 | * Only USART devices from at91sam9260 SOC implement fractional | |
1765 | * baudrate. | |
1766 | */ | |
1767 | atmel_port->has_frac_baudrate = false; | |
4b769371 | 1768 | atmel_port->has_hw_timer = false; |
055560b0 | 1769 | |
2958ccee LD |
1770 | if (name == new_uart) { |
1771 | dev_dbg(port->dev, "Uart with hw timer"); | |
4b769371 | 1772 | atmel_port->has_hw_timer = true; |
2958ccee LD |
1773 | atmel_port->rtor = ATMEL_UA_RTOR; |
1774 | } else if (name == usart) { | |
1775 | dev_dbg(port->dev, "Usart\n"); | |
5bf5635a | 1776 | atmel_port->has_frac_baudrate = true; |
2958ccee LD |
1777 | atmel_port->has_hw_timer = true; |
1778 | atmel_port->rtor = ATMEL_US_RTOR; | |
4b769371 NF |
1779 | } else if (name == dbgu_uart) { |
1780 | dev_dbg(port->dev, "Dbgu or uart without hw timer\n"); | |
055560b0 | 1781 | } else { |
731d9cae | 1782 | /* fallback for older SoCs: use version field */ |
4e7decda | 1783 | version = atmel_uart_readl(port, ATMEL_US_VERSION); |
731d9cae NF |
1784 | switch (version) { |
1785 | case 0x302: | |
1786 | case 0x10213: | |
85afaf5e | 1787 | case 0x10302: |
731d9cae | 1788 | dev_dbg(port->dev, "This version is usart\n"); |
5bf5635a | 1789 | atmel_port->has_frac_baudrate = true; |
4b769371 | 1790 | atmel_port->has_hw_timer = true; |
2958ccee | 1791 | atmel_port->rtor = ATMEL_US_RTOR; |
731d9cae NF |
1792 | break; |
1793 | case 0x203: | |
1794 | case 0x10202: | |
1795 | dev_dbg(port->dev, "This version is uart\n"); | |
731d9cae NF |
1796 | break; |
1797 | default: | |
1798 | dev_err(port->dev, "Not supported ip name nor version, set to uart\n"); | |
1799 | } | |
055560b0 | 1800 | } |
055560b0 ES |
1801 | } |
1802 | ||
1e6c9c28 AV |
1803 | /* |
1804 | * Perform initialization and enable port for reception | |
1805 | */ | |
7192f92c | 1806 | static int atmel_startup(struct uart_port *port) |
1e6c9c28 | 1807 | { |
33d64c4f | 1808 | struct platform_device *pdev = to_platform_device(port->dev); |
c811ab8c | 1809 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1e6c9c28 AV |
1810 | int retval; |
1811 | ||
1812 | /* | |
1813 | * Ensure that no interrupts are enabled otherwise when | |
1814 | * request_irq() is called we could get stuck trying to | |
1815 | * handle an unexpected interrupt | |
1816 | */ | |
4e7decda | 1817 | atmel_uart_writel(port, ATMEL_US_IDR, -1); |
ab5e4e41 | 1818 | atmel_port->ms_irq_enabled = false; |
1e6c9c28 AV |
1819 | |
1820 | /* | |
1821 | * Allocate the IRQ | |
1822 | */ | |
2c7af5ba | 1823 | retval = request_irq(port->irq, atmel_interrupt, |
41bdf970 SAS |
1824 | IRQF_SHARED | IRQF_COND_SUSPEND, |
1825 | dev_name(&pdev->dev), port); | |
1e6c9c28 | 1826 | if (retval) { |
ddaa6037 | 1827 | dev_err(port->dev, "atmel_startup - Can't get irq\n"); |
1e6c9c28 AV |
1828 | return retval; |
1829 | } | |
1830 | ||
98f2082c NF |
1831 | atomic_set(&atmel_port->tasklet_shutdown, 0); |
1832 | tasklet_init(&atmel_port->tasklet_rx, atmel_tasklet_rx_func, | |
1833 | (unsigned long)port); | |
1834 | tasklet_init(&atmel_port->tasklet_tx, atmel_tasklet_tx_func, | |
1835 | (unsigned long)port); | |
1e125786 | 1836 | |
a6670615 CC |
1837 | /* |
1838 | * Initialize DMA (if necessary) | |
1839 | */ | |
33d64c4f | 1840 | atmel_init_property(atmel_port, pdev); |
4d9628a1 | 1841 | atmel_set_ops(port); |
33d64c4f | 1842 | |
a930e528 ES |
1843 | if (atmel_port->prepare_rx) { |
1844 | retval = atmel_port->prepare_rx(port); | |
1845 | if (retval < 0) | |
1846 | atmel_set_ops(port); | |
a6670615 | 1847 | } |
a6670615 | 1848 | |
a930e528 ES |
1849 | if (atmel_port->prepare_tx) { |
1850 | retval = atmel_port->prepare_tx(port); | |
1851 | if (retval < 0) | |
1852 | atmel_set_ops(port); | |
a6670615 | 1853 | } |
1e6c9c28 | 1854 | |
b5199d46 CP |
1855 | /* |
1856 | * Enable FIFO when available | |
1857 | */ | |
1858 | if (atmel_port->fifo_size) { | |
1859 | unsigned int txrdym = ATMEL_US_ONE_DATA; | |
1860 | unsigned int rxrdym = ATMEL_US_ONE_DATA; | |
1861 | unsigned int fmr; | |
1862 | ||
1863 | atmel_uart_writel(port, ATMEL_US_CR, | |
1864 | ATMEL_US_FIFOEN | | |
1865 | ATMEL_US_RXFCLR | | |
1866 | ATMEL_US_TXFLCLR); | |
1867 | ||
5f258b3e CP |
1868 | if (atmel_use_dma_tx(port)) |
1869 | txrdym = ATMEL_US_FOUR_DATA; | |
1870 | ||
b5199d46 CP |
1871 | fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym); |
1872 | if (atmel_port->rts_high && | |
1873 | atmel_port->rts_low) | |
1874 | fmr |= ATMEL_US_FRTSC | | |
1875 | ATMEL_US_RXFTHRES(atmel_port->rts_high) | | |
1876 | ATMEL_US_RXFTHRES2(atmel_port->rts_low); | |
1877 | ||
1878 | atmel_uart_writel(port, ATMEL_US_FMR, fmr); | |
1879 | } | |
1880 | ||
27c0c8e5 | 1881 | /* Save current CSR for comparison in atmel_tasklet_func() */ |
e0b0baad | 1882 | atmel_port->irq_status_prev = atmel_get_lines_status(port); |
27c0c8e5 | 1883 | |
1e6c9c28 AV |
1884 | /* |
1885 | * Finally, enable the serial port | |
1886 | */ | |
4e7decda | 1887 | atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); |
b843aa21 | 1888 | /* enable xmit & rcvr */ |
4e7decda | 1889 | atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN); |
afefc415 | 1890 | |
8bc661bf MR |
1891 | setup_timer(&atmel_port->uart_timer, |
1892 | atmel_uart_timer_callback, | |
1893 | (unsigned long)port); | |
1894 | ||
64e22ebe | 1895 | if (atmel_use_pdc_rx(port)) { |
a6670615 | 1896 | /* set UART timeout */ |
4b769371 | 1897 | if (!atmel_port->has_hw_timer) { |
2e68c22f ES |
1898 | mod_timer(&atmel_port->uart_timer, |
1899 | jiffies + uart_poll_timeout(port)); | |
1900 | /* set USART timeout */ | |
1901 | } else { | |
2958ccee LD |
1902 | atmel_uart_writel(port, atmel_port->rtor, |
1903 | PDC_RX_TIMEOUT); | |
4e7decda | 1904 | atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO); |
a6670615 | 1905 | |
4e7decda CP |
1906 | atmel_uart_writel(port, ATMEL_US_IER, |
1907 | ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); | |
2e68c22f | 1908 | } |
a6670615 | 1909 | /* enable PDC controller */ |
4e7decda | 1910 | atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN); |
34df42f5 | 1911 | } else if (atmel_use_dma_rx(port)) { |
2e68c22f | 1912 | /* set UART timeout */ |
4b769371 | 1913 | if (!atmel_port->has_hw_timer) { |
2e68c22f ES |
1914 | mod_timer(&atmel_port->uart_timer, |
1915 | jiffies + uart_poll_timeout(port)); | |
1916 | /* set USART timeout */ | |
1917 | } else { | |
2958ccee LD |
1918 | atmel_uart_writel(port, atmel_port->rtor, |
1919 | PDC_RX_TIMEOUT); | |
4e7decda | 1920 | atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO); |
34df42f5 | 1921 | |
4e7decda CP |
1922 | atmel_uart_writel(port, ATMEL_US_IER, |
1923 | ATMEL_US_TIMEOUT); | |
2e68c22f | 1924 | } |
a6670615 CC |
1925 | } else { |
1926 | /* enable receive only */ | |
4e7decda | 1927 | atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY); |
a6670615 | 1928 | } |
afefc415 | 1929 | |
1e6c9c28 AV |
1930 | return 0; |
1931 | } | |
1932 | ||
479e9b94 PH |
1933 | /* |
1934 | * Flush any TX data submitted for DMA. Called when the TX circular | |
1935 | * buffer is reset. | |
1936 | */ | |
1937 | static void atmel_flush_buffer(struct uart_port *port) | |
1938 | { | |
1939 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
1940 | ||
1941 | if (atmel_use_pdc_tx(port)) { | |
4e7decda | 1942 | atmel_uart_writel(port, ATMEL_PDC_TCR, 0); |
479e9b94 PH |
1943 | atmel_port->pdc_tx.ofs = 0; |
1944 | } | |
e087ae68 RG |
1945 | /* |
1946 | * in uart_flush_buffer(), the xmit circular buffer has just | |
1947 | * been cleared, so we have to reset tx_len accordingly. | |
1948 | */ | |
1949 | atmel_port->tx_len = 0; | |
479e9b94 PH |
1950 | } |
1951 | ||
1e6c9c28 AV |
1952 | /* |
1953 | * Disable the port | |
1954 | */ | |
7192f92c | 1955 | static void atmel_shutdown(struct uart_port *port) |
1e6c9c28 | 1956 | { |
c811ab8c | 1957 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
0cc7c6c7 | 1958 | |
0ae9fdef RG |
1959 | /* Disable modem control lines interrupts */ |
1960 | atmel_disable_ms(port); | |
1961 | ||
98f2082c NF |
1962 | /* Disable interrupts at device level */ |
1963 | atmel_uart_writel(port, ATMEL_US_IDR, -1); | |
1964 | ||
1965 | /* Prevent spurious interrupts from scheduling the tasklet */ | |
1966 | atomic_inc(&atmel_port->tasklet_shutdown); | |
1967 | ||
8bc661bf MR |
1968 | /* |
1969 | * Prevent any tasklets being scheduled during | |
1970 | * cleanup | |
1971 | */ | |
1972 | del_timer_sync(&atmel_port->uart_timer); | |
1973 | ||
98f2082c NF |
1974 | /* Make sure that no interrupt is on the fly */ |
1975 | synchronize_irq(port->irq); | |
1976 | ||
0cc7c6c7 MR |
1977 | /* |
1978 | * Clear out any scheduled tasklets before | |
1979 | * we destroy the buffers | |
1980 | */ | |
00e8e658 NF |
1981 | tasklet_kill(&atmel_port->tasklet_rx); |
1982 | tasklet_kill(&atmel_port->tasklet_tx); | |
0cc7c6c7 | 1983 | |
a6670615 | 1984 | /* |
0cc7c6c7 | 1985 | * Ensure everything is stopped and |
98f2082c | 1986 | * disable port and break condition. |
a6670615 CC |
1987 | */ |
1988 | atmel_stop_rx(port); | |
1989 | atmel_stop_tx(port); | |
1990 | ||
4e7decda | 1991 | atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA); |
0cc7c6c7 | 1992 | |
a6670615 CC |
1993 | /* |
1994 | * Shut-down the DMA. | |
1995 | */ | |
a930e528 ES |
1996 | if (atmel_port->release_rx) |
1997 | atmel_port->release_rx(port); | |
1998 | if (atmel_port->release_tx) | |
1999 | atmel_port->release_tx(port); | |
a6670615 | 2000 | |
bb7e73c5 MD |
2001 | /* |
2002 | * Reset ring buffer pointers | |
2003 | */ | |
2004 | atmel_port->rx_ring.head = 0; | |
2005 | atmel_port->rx_ring.tail = 0; | |
2006 | ||
1e6c9c28 | 2007 | /* |
ab5e4e41 | 2008 | * Free the interrupts |
1e6c9c28 AV |
2009 | */ |
2010 | free_irq(port->irq, port); | |
ab5e4e41 | 2011 | |
479e9b94 | 2012 | atmel_flush_buffer(port); |
9afd561a HS |
2013 | } |
2014 | ||
1e6c9c28 AV |
2015 | /* |
2016 | * Power / Clock management. | |
2017 | */ | |
b843aa21 RB |
2018 | static void atmel_serial_pm(struct uart_port *port, unsigned int state, |
2019 | unsigned int oldstate) | |
1e6c9c28 | 2020 | { |
c811ab8c | 2021 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
afefc415 | 2022 | |
1e6c9c28 | 2023 | switch (state) { |
b843aa21 RB |
2024 | case 0: |
2025 | /* | |
2026 | * Enable the peripheral clock for this serial port. | |
2027 | * This is called on uart_open() or a resume event. | |
2028 | */ | |
91f8c2d8 | 2029 | clk_prepare_enable(atmel_port->clk); |
f05596db AS |
2030 | |
2031 | /* re-enable interrupts if we disabled some on suspend */ | |
4e7decda | 2032 | atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr); |
b843aa21 RB |
2033 | break; |
2034 | case 3: | |
f05596db | 2035 | /* Back up the interrupt mask and disable all interrupts */ |
4e7decda CP |
2036 | atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR); |
2037 | atmel_uart_writel(port, ATMEL_US_IDR, -1); | |
f05596db | 2038 | |
b843aa21 RB |
2039 | /* |
2040 | * Disable the peripheral clock for this serial port. | |
2041 | * This is called on uart_close() or a suspend event. | |
2042 | */ | |
91f8c2d8 | 2043 | clk_disable_unprepare(atmel_port->clk); |
b843aa21 RB |
2044 | break; |
2045 | default: | |
ddaa6037 | 2046 | dev_err(port->dev, "atmel_serial: unknown pm %d\n", state); |
1e6c9c28 AV |
2047 | } |
2048 | } | |
2049 | ||
2050 | /* | |
2051 | * Change the port parameters | |
2052 | */ | |
b843aa21 RB |
2053 | static void atmel_set_termios(struct uart_port *port, struct ktermios *termios, |
2054 | struct ktermios *old) | |
1e6c9c28 | 2055 | { |
5bf5635a | 2056 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1e6c9c28 | 2057 | unsigned long flags; |
5bf5635a | 2058 | unsigned int old_mode, mode, imr, quot, baud, div, cd, fp = 0; |
1cf6e8fc CP |
2059 | |
2060 | /* save the current mode register */ | |
4e7decda | 2061 | mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR); |
1e6c9c28 | 2062 | |
1cf6e8fc CP |
2063 | /* reset the mode, clock divisor, parity, stop bits and data size */ |
2064 | mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP | | |
2065 | ATMEL_US_PAR | ATMEL_US_USMODE); | |
03abeac0 | 2066 | |
b843aa21 | 2067 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); |
1e6c9c28 AV |
2068 | |
2069 | /* byte size */ | |
2070 | switch (termios->c_cflag & CSIZE) { | |
2071 | case CS5: | |
7192f92c | 2072 | mode |= ATMEL_US_CHRL_5; |
1e6c9c28 AV |
2073 | break; |
2074 | case CS6: | |
7192f92c | 2075 | mode |= ATMEL_US_CHRL_6; |
1e6c9c28 AV |
2076 | break; |
2077 | case CS7: | |
7192f92c | 2078 | mode |= ATMEL_US_CHRL_7; |
1e6c9c28 AV |
2079 | break; |
2080 | default: | |
7192f92c | 2081 | mode |= ATMEL_US_CHRL_8; |
1e6c9c28 AV |
2082 | break; |
2083 | } | |
2084 | ||
2085 | /* stop bits */ | |
2086 | if (termios->c_cflag & CSTOPB) | |
7192f92c | 2087 | mode |= ATMEL_US_NBSTOP_2; |
1e6c9c28 AV |
2088 | |
2089 | /* parity */ | |
2090 | if (termios->c_cflag & PARENB) { | |
b843aa21 RB |
2091 | /* Mark or Space parity */ |
2092 | if (termios->c_cflag & CMSPAR) { | |
1e6c9c28 | 2093 | if (termios->c_cflag & PARODD) |
7192f92c | 2094 | mode |= ATMEL_US_PAR_MARK; |
1e6c9c28 | 2095 | else |
7192f92c | 2096 | mode |= ATMEL_US_PAR_SPACE; |
b843aa21 | 2097 | } else if (termios->c_cflag & PARODD) |
7192f92c | 2098 | mode |= ATMEL_US_PAR_ODD; |
1e6c9c28 | 2099 | else |
7192f92c | 2100 | mode |= ATMEL_US_PAR_EVEN; |
b843aa21 | 2101 | } else |
7192f92c | 2102 | mode |= ATMEL_US_PAR_NONE; |
1e6c9c28 AV |
2103 | |
2104 | spin_lock_irqsave(&port->lock, flags); | |
2105 | ||
7192f92c | 2106 | port->read_status_mask = ATMEL_US_OVRE; |
1e6c9c28 | 2107 | if (termios->c_iflag & INPCK) |
7192f92c | 2108 | port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); |
ef8b9ddc | 2109 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
7192f92c | 2110 | port->read_status_mask |= ATMEL_US_RXBRK; |
1e6c9c28 | 2111 | |
64e22ebe | 2112 | if (atmel_use_pdc_rx(port)) |
a6670615 | 2113 | /* need to enable error interrupts */ |
4e7decda | 2114 | atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask); |
a6670615 | 2115 | |
1e6c9c28 AV |
2116 | /* |
2117 | * Characters to ignore | |
2118 | */ | |
2119 | port->ignore_status_mask = 0; | |
2120 | if (termios->c_iflag & IGNPAR) | |
7192f92c | 2121 | port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); |
1e6c9c28 | 2122 | if (termios->c_iflag & IGNBRK) { |
7192f92c | 2123 | port->ignore_status_mask |= ATMEL_US_RXBRK; |
1e6c9c28 AV |
2124 | /* |
2125 | * If we're ignoring parity and break indicators, | |
2126 | * ignore overruns too (for real raw support). | |
2127 | */ | |
2128 | if (termios->c_iflag & IGNPAR) | |
7192f92c | 2129 | port->ignore_status_mask |= ATMEL_US_OVRE; |
1e6c9c28 | 2130 | } |
b843aa21 | 2131 | /* TODO: Ignore all characters if CREAD is set.*/ |
1e6c9c28 AV |
2132 | |
2133 | /* update the per-port timeout */ | |
2134 | uart_update_timeout(port, termios->c_cflag, baud); | |
2135 | ||
0ccad870 HS |
2136 | /* |
2137 | * save/disable interrupts. The tty layer will ensure that the | |
2138 | * transmitter is empty if requested by the caller, so there's | |
2139 | * no need to wait for it here. | |
2140 | */ | |
4e7decda CP |
2141 | imr = atmel_uart_readl(port, ATMEL_US_IMR); |
2142 | atmel_uart_writel(port, ATMEL_US_IDR, -1); | |
1e6c9c28 AV |
2143 | |
2144 | /* disable receiver and transmitter */ | |
4e7decda | 2145 | atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS); |
1e6c9c28 | 2146 | |
1cf6e8fc | 2147 | /* mode */ |
13bd3e6f | 2148 | if (port->rs485.flags & SER_RS485_ENABLED) { |
4e7decda CP |
2149 | atmel_uart_writel(port, ATMEL_US_TTGR, |
2150 | port->rs485.delay_rts_after_send); | |
e8faff73 | 2151 | mode |= ATMEL_US_USMODE_RS485; |
1cf6e8fc CP |
2152 | } else if (termios->c_cflag & CRTSCTS) { |
2153 | /* RS232 with hardware handshake (RTS/CTS) */ | |
9bcffe75 RG |
2154 | if (atmel_use_fifo(port) && |
2155 | !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) { | |
2156 | /* | |
2157 | * with ATMEL_US_USMODE_HWHS set, the controller will | |
2158 | * be able to drive the RTS pin high/low when the RX | |
2159 | * FIFO is above RXFTHRES/below RXFTHRES2. | |
2160 | * It will also disable the transmitter when the CTS | |
2161 | * pin is high. | |
2162 | * This mode is not activated if CTS pin is a GPIO | |
2163 | * because in this case, the transmitter is always | |
2164 | * disabled (there must be an internal pull-up | |
2165 | * responsible for this behaviour). | |
2166 | * If the RTS pin is a GPIO, the controller won't be | |
2167 | * able to drive it according to the FIFO thresholds, | |
2168 | * but it will be handled by the driver. | |
2169 | */ | |
5be605ac | 2170 | mode |= ATMEL_US_USMODE_HWHS; |
9bcffe75 RG |
2171 | } else { |
2172 | /* | |
2173 | * For platforms without FIFO, the flow control is | |
2174 | * handled by the driver. | |
2175 | */ | |
2176 | mode |= ATMEL_US_USMODE_NORMAL; | |
5be605ac | 2177 | } |
1cf6e8fc CP |
2178 | } else { |
2179 | /* RS232 without hadware handshake */ | |
2180 | mode |= ATMEL_US_USMODE_NORMAL; | |
e8faff73 CS |
2181 | } |
2182 | ||
1cf6e8fc | 2183 | /* set the mode, clock divisor, parity, stop bits and data size */ |
4e7decda | 2184 | atmel_uart_writel(port, ATMEL_US_MR, mode); |
1e6c9c28 | 2185 | |
1cf6e8fc CP |
2186 | /* |
2187 | * when switching the mode, set the RTS line state according to the | |
2188 | * new mode, otherwise keep the former state | |
2189 | */ | |
2190 | if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) { | |
2191 | unsigned int rts_state; | |
2192 | ||
2193 | if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) { | |
2194 | /* let the hardware control the RTS line */ | |
2195 | rts_state = ATMEL_US_RTSDIS; | |
2196 | } else { | |
2197 | /* force RTS line to low level */ | |
2198 | rts_state = ATMEL_US_RTSEN; | |
2199 | } | |
2200 | ||
4e7decda | 2201 | atmel_uart_writel(port, ATMEL_US_CR, rts_state); |
1cf6e8fc CP |
2202 | } |
2203 | ||
5bf5635a LD |
2204 | /* |
2205 | * Set the baud rate: | |
2206 | * Fractional baudrate allows to setup output frequency more | |
2207 | * accurately. This feature is enabled only when using normal mode. | |
2208 | * baudrate = selected clock / (8 * (2 - OVER) * (CD + FP / 8)) | |
2209 | * Currently, OVER is always set to 0 so we get | |
36131cdf AS |
2210 | * baudrate = selected clock / (16 * (CD + FP / 8)) |
2211 | * then | |
2212 | * 8 CD + FP = selected clock / (2 * baudrate) | |
5bf5635a LD |
2213 | */ |
2214 | if (atmel_port->has_frac_baudrate && | |
2215 | (mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_NORMAL) { | |
36131cdf AS |
2216 | div = DIV_ROUND_CLOSEST(port->uartclk, baud * 2); |
2217 | cd = div >> 3; | |
2218 | fp = div & ATMEL_US_FP_MASK; | |
5bf5635a LD |
2219 | } else { |
2220 | cd = uart_get_divisor(port, baud); | |
2221 | } | |
2222 | ||
2223 | if (cd > 65535) { /* BRGR is 16-bit, so switch to slower clock */ | |
2224 | cd /= 8; | |
2225 | mode |= ATMEL_US_USCLKS_MCK_DIV8; | |
2226 | } | |
2227 | quot = cd | fp << ATMEL_US_FP_OFFSET; | |
2228 | ||
4e7decda CP |
2229 | atmel_uart_writel(port, ATMEL_US_BRGR, quot); |
2230 | atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); | |
2231 | atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN); | |
1e6c9c28 AV |
2232 | |
2233 | /* restore interrupts */ | |
4e7decda | 2234 | atmel_uart_writel(port, ATMEL_US_IER, imr); |
1e6c9c28 AV |
2235 | |
2236 | /* CTS flow-control and modem-status interrupts */ | |
2237 | if (UART_ENABLE_MS(port, termios->c_cflag)) | |
35b675b9 RG |
2238 | atmel_enable_ms(port); |
2239 | else | |
2240 | atmel_disable_ms(port); | |
1e6c9c28 AV |
2241 | |
2242 | spin_unlock_irqrestore(&port->lock, flags); | |
2243 | } | |
2244 | ||
732a84a0 | 2245 | static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios) |
42bd7a4f | 2246 | { |
732a84a0 | 2247 | if (termios->c_line == N_PPS) { |
42bd7a4f | 2248 | port->flags |= UPF_HARDPPS_CD; |
d41510ce | 2249 | spin_lock_irq(&port->lock); |
42bd7a4f | 2250 | atmel_enable_ms(port); |
d41510ce | 2251 | spin_unlock_irq(&port->lock); |
42bd7a4f VP |
2252 | } else { |
2253 | port->flags &= ~UPF_HARDPPS_CD; | |
cab68f89 PH |
2254 | if (!UART_ENABLE_MS(port, termios->c_cflag)) { |
2255 | spin_lock_irq(&port->lock); | |
2256 | atmel_disable_ms(port); | |
2257 | spin_unlock_irq(&port->lock); | |
2258 | } | |
42bd7a4f VP |
2259 | } |
2260 | } | |
2261 | ||
1e6c9c28 AV |
2262 | /* |
2263 | * Return string describing the specified port | |
2264 | */ | |
7192f92c | 2265 | static const char *atmel_type(struct uart_port *port) |
1e6c9c28 | 2266 | { |
9ab4f88b | 2267 | return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL; |
1e6c9c28 AV |
2268 | } |
2269 | ||
2270 | /* | |
2271 | * Release the memory region(s) being used by 'port'. | |
2272 | */ | |
7192f92c | 2273 | static void atmel_release_port(struct uart_port *port) |
1e6c9c28 | 2274 | { |
afefc415 AV |
2275 | struct platform_device *pdev = to_platform_device(port->dev); |
2276 | int size = pdev->resource[0].end - pdev->resource[0].start + 1; | |
2277 | ||
2278 | release_mem_region(port->mapbase, size); | |
2279 | ||
2280 | if (port->flags & UPF_IOREMAP) { | |
2281 | iounmap(port->membase); | |
2282 | port->membase = NULL; | |
2283 | } | |
1e6c9c28 AV |
2284 | } |
2285 | ||
2286 | /* | |
2287 | * Request the memory region(s) being used by 'port'. | |
2288 | */ | |
7192f92c | 2289 | static int atmel_request_port(struct uart_port *port) |
1e6c9c28 | 2290 | { |
afefc415 AV |
2291 | struct platform_device *pdev = to_platform_device(port->dev); |
2292 | int size = pdev->resource[0].end - pdev->resource[0].start + 1; | |
2293 | ||
7192f92c | 2294 | if (!request_mem_region(port->mapbase, size, "atmel_serial")) |
afefc415 AV |
2295 | return -EBUSY; |
2296 | ||
2297 | if (port->flags & UPF_IOREMAP) { | |
2298 | port->membase = ioremap(port->mapbase, size); | |
2299 | if (port->membase == NULL) { | |
2300 | release_mem_region(port->mapbase, size); | |
2301 | return -ENOMEM; | |
2302 | } | |
2303 | } | |
1e6c9c28 | 2304 | |
afefc415 | 2305 | return 0; |
1e6c9c28 AV |
2306 | } |
2307 | ||
2308 | /* | |
2309 | * Configure/autoconfigure the port. | |
2310 | */ | |
7192f92c | 2311 | static void atmel_config_port(struct uart_port *port, int flags) |
1e6c9c28 AV |
2312 | { |
2313 | if (flags & UART_CONFIG_TYPE) { | |
9ab4f88b | 2314 | port->type = PORT_ATMEL; |
7192f92c | 2315 | atmel_request_port(port); |
1e6c9c28 AV |
2316 | } |
2317 | } | |
2318 | ||
2319 | /* | |
2320 | * Verify the new serial_struct (for TIOCSSERIAL). | |
2321 | */ | |
7192f92c | 2322 | static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser) |
1e6c9c28 AV |
2323 | { |
2324 | int ret = 0; | |
9ab4f88b | 2325 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL) |
1e6c9c28 AV |
2326 | ret = -EINVAL; |
2327 | if (port->irq != ser->irq) | |
2328 | ret = -EINVAL; | |
2329 | if (ser->io_type != SERIAL_IO_MEM) | |
2330 | ret = -EINVAL; | |
2331 | if (port->uartclk / 16 != ser->baud_base) | |
2332 | ret = -EINVAL; | |
270c2ade | 2333 | if (port->mapbase != (unsigned long)ser->iomem_base) |
1e6c9c28 AV |
2334 | ret = -EINVAL; |
2335 | if (port->iobase != ser->port) | |
2336 | ret = -EINVAL; | |
2337 | if (ser->hub6 != 0) | |
2338 | ret = -EINVAL; | |
2339 | return ret; | |
2340 | } | |
2341 | ||
8fe2d541 AT |
2342 | #ifdef CONFIG_CONSOLE_POLL |
2343 | static int atmel_poll_get_char(struct uart_port *port) | |
2344 | { | |
4e7decda | 2345 | while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY)) |
8fe2d541 AT |
2346 | cpu_relax(); |
2347 | ||
a6499435 | 2348 | return atmel_uart_read_char(port); |
8fe2d541 AT |
2349 | } |
2350 | ||
2351 | static void atmel_poll_put_char(struct uart_port *port, unsigned char ch) | |
2352 | { | |
4e7decda | 2353 | while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY)) |
8fe2d541 AT |
2354 | cpu_relax(); |
2355 | ||
a6499435 | 2356 | atmel_uart_write_char(port, ch); |
8fe2d541 AT |
2357 | } |
2358 | #endif | |
2359 | ||
5c7dcdb6 | 2360 | static const struct uart_ops atmel_pops = { |
7192f92c HS |
2361 | .tx_empty = atmel_tx_empty, |
2362 | .set_mctrl = atmel_set_mctrl, | |
2363 | .get_mctrl = atmel_get_mctrl, | |
2364 | .stop_tx = atmel_stop_tx, | |
2365 | .start_tx = atmel_start_tx, | |
2366 | .stop_rx = atmel_stop_rx, | |
2367 | .enable_ms = atmel_enable_ms, | |
2368 | .break_ctl = atmel_break_ctl, | |
2369 | .startup = atmel_startup, | |
2370 | .shutdown = atmel_shutdown, | |
9afd561a | 2371 | .flush_buffer = atmel_flush_buffer, |
7192f92c | 2372 | .set_termios = atmel_set_termios, |
42bd7a4f | 2373 | .set_ldisc = atmel_set_ldisc, |
7192f92c HS |
2374 | .type = atmel_type, |
2375 | .release_port = atmel_release_port, | |
2376 | .request_port = atmel_request_port, | |
2377 | .config_port = atmel_config_port, | |
2378 | .verify_port = atmel_verify_port, | |
2379 | .pm = atmel_serial_pm, | |
8fe2d541 AT |
2380 | #ifdef CONFIG_CONSOLE_POLL |
2381 | .poll_get_char = atmel_poll_get_char, | |
2382 | .poll_put_char = atmel_poll_put_char, | |
2383 | #endif | |
1e6c9c28 AV |
2384 | }; |
2385 | ||
afefc415 AV |
2386 | /* |
2387 | * Configure the port from the platform device resource info. | |
2388 | */ | |
91f8c2d8 | 2389 | static int atmel_init_port(struct atmel_uart_port *atmel_port, |
b843aa21 | 2390 | struct platform_device *pdev) |
1e6c9c28 | 2391 | { |
91f8c2d8 | 2392 | int ret; |
7192f92c | 2393 | struct uart_port *port = &atmel_port->uart; |
574de559 | 2394 | struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); |
afefc415 | 2395 | |
4a1e8888 LZ |
2396 | atmel_init_property(atmel_port, pdev); |
2397 | atmel_set_ops(port); | |
afefc415 | 2398 | |
13bd3e6f | 2399 | atmel_init_rs485(port, pdev); |
a930e528 | 2400 | |
e8faff73 CS |
2401 | port->iotype = UPIO_MEM; |
2402 | port->flags = UPF_BOOT_AUTOCONF; | |
2403 | port->ops = &atmel_pops; | |
2404 | port->fifosize = 1; | |
e8faff73 | 2405 | port->dev = &pdev->dev; |
afefc415 AV |
2406 | port->mapbase = pdev->resource[0].start; |
2407 | port->irq = pdev->resource[1].start; | |
13bd3e6f | 2408 | port->rs485_config = atmel_config_rs485; |
afefc415 | 2409 | |
1ecc26bd RB |
2410 | memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring)); |
2411 | ||
5fbe46b6 | 2412 | if (pdata && pdata->regs) { |
75d35213 | 2413 | /* Already mapped by setup code */ |
1acfc7ec | 2414 | port->membase = pdata->regs; |
588edbf3 | 2415 | } else { |
afefc415 AV |
2416 | port->flags |= UPF_IOREMAP; |
2417 | port->membase = NULL; | |
2418 | } | |
1e6c9c28 | 2419 | |
b843aa21 RB |
2420 | /* for console, the clock could already be configured */ |
2421 | if (!atmel_port->clk) { | |
7192f92c | 2422 | atmel_port->clk = clk_get(&pdev->dev, "usart"); |
91f8c2d8 BB |
2423 | if (IS_ERR(atmel_port->clk)) { |
2424 | ret = PTR_ERR(atmel_port->clk); | |
2425 | atmel_port->clk = NULL; | |
2426 | return ret; | |
2427 | } | |
2428 | ret = clk_prepare_enable(atmel_port->clk); | |
2429 | if (ret) { | |
2430 | clk_put(atmel_port->clk); | |
2431 | atmel_port->clk = NULL; | |
2432 | return ret; | |
2433 | } | |
7192f92c | 2434 | port->uartclk = clk_get_rate(atmel_port->clk); |
91f8c2d8 | 2435 | clk_disable_unprepare(atmel_port->clk); |
06a7f058 | 2436 | /* only enable clock when USART is in use */ |
afefc415 | 2437 | } |
a6670615 | 2438 | |
e8faff73 | 2439 | /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */ |
13bd3e6f | 2440 | if (port->rs485.flags & SER_RS485_ENABLED) |
e8faff73 | 2441 | atmel_port->tx_done_mask = ATMEL_US_TXEMPTY; |
64e22ebe | 2442 | else if (atmel_use_pdc_tx(port)) { |
a6670615 | 2443 | port->fifosize = PDC_BUFFER_SIZE; |
e8faff73 CS |
2444 | atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE; |
2445 | } else { | |
2446 | atmel_port->tx_done_mask = ATMEL_US_TXRDY; | |
2447 | } | |
91f8c2d8 BB |
2448 | |
2449 | return 0; | |
1e6c9c28 AV |
2450 | } |
2451 | ||
69f6a27b JCPV |
2452 | struct platform_device *atmel_default_console_device; /* the serial console device */ |
2453 | ||
749c4e60 | 2454 | #ifdef CONFIG_SERIAL_ATMEL_CONSOLE |
7192f92c | 2455 | static void atmel_console_putchar(struct uart_port *port, int ch) |
d358788f | 2456 | { |
4e7decda | 2457 | while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY)) |
829dd811 | 2458 | cpu_relax(); |
a6499435 | 2459 | atmel_uart_write_char(port, ch); |
d358788f | 2460 | } |
1e6c9c28 AV |
2461 | |
2462 | /* | |
2463 | * Interrupts are disabled on entering | |
2464 | */ | |
7192f92c | 2465 | static void atmel_console_write(struct console *co, const char *s, u_int count) |
1e6c9c28 | 2466 | { |
7192f92c | 2467 | struct uart_port *port = &atmel_ports[co->index].uart; |
e8faff73 | 2468 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
d358788f | 2469 | unsigned int status, imr; |
39d4c922 | 2470 | unsigned int pdc_tx; |
1e6c9c28 AV |
2471 | |
2472 | /* | |
b843aa21 | 2473 | * First, save IMR and then disable interrupts |
1e6c9c28 | 2474 | */ |
4e7decda CP |
2475 | imr = atmel_uart_readl(port, ATMEL_US_IMR); |
2476 | atmel_uart_writel(port, ATMEL_US_IDR, | |
2477 | ATMEL_US_RXRDY | atmel_port->tx_done_mask); | |
1e6c9c28 | 2478 | |
39d4c922 | 2479 | /* Store PDC transmit status and disable it */ |
4e7decda CP |
2480 | pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN; |
2481 | atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS); | |
39d4c922 | 2482 | |
1f1c9e29 NF |
2483 | /* Make sure that tx path is actually able to send characters */ |
2484 | atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN); | |
2485 | ||
7192f92c | 2486 | uart_console_write(port, s, count, atmel_console_putchar); |
1e6c9c28 AV |
2487 | |
2488 | /* | |
b843aa21 RB |
2489 | * Finally, wait for transmitter to become empty |
2490 | * and restore IMR | |
1e6c9c28 AV |
2491 | */ |
2492 | do { | |
4e7decda | 2493 | status = atmel_uart_readl(port, ATMEL_US_CSR); |
7192f92c | 2494 | } while (!(status & ATMEL_US_TXRDY)); |
39d4c922 MP |
2495 | |
2496 | /* Restore PDC transmit status */ | |
2497 | if (pdc_tx) | |
4e7decda | 2498 | atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN); |
39d4c922 | 2499 | |
b843aa21 | 2500 | /* set interrupts back the way they were */ |
4e7decda | 2501 | atmel_uart_writel(port, ATMEL_US_IER, imr); |
1e6c9c28 AV |
2502 | } |
2503 | ||
2504 | /* | |
b843aa21 RB |
2505 | * If the port was already initialised (eg, by a boot loader), |
2506 | * try to determine the current setup. | |
1e6c9c28 | 2507 | */ |
b843aa21 RB |
2508 | static void __init atmel_console_get_options(struct uart_port *port, int *baud, |
2509 | int *parity, int *bits) | |
1e6c9c28 AV |
2510 | { |
2511 | unsigned int mr, quot; | |
2512 | ||
1c0fd82f HS |
2513 | /* |
2514 | * If the baud rate generator isn't running, the port wasn't | |
2515 | * initialized by the boot loader. | |
2516 | */ | |
4e7decda | 2517 | quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD; |
1c0fd82f HS |
2518 | if (!quot) |
2519 | return; | |
1e6c9c28 | 2520 | |
4e7decda | 2521 | mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL; |
7192f92c | 2522 | if (mr == ATMEL_US_CHRL_8) |
1e6c9c28 AV |
2523 | *bits = 8; |
2524 | else | |
2525 | *bits = 7; | |
2526 | ||
4e7decda | 2527 | mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR; |
7192f92c | 2528 | if (mr == ATMEL_US_PAR_EVEN) |
1e6c9c28 | 2529 | *parity = 'e'; |
7192f92c | 2530 | else if (mr == ATMEL_US_PAR_ODD) |
1e6c9c28 AV |
2531 | *parity = 'o'; |
2532 | ||
4d5e392c HS |
2533 | /* |
2534 | * The serial core only rounds down when matching this to a | |
2535 | * supported baud rate. Make sure we don't end up slightly | |
2536 | * lower than one of those, as it would make us fall through | |
2537 | * to a much lower baud rate than we really want. | |
2538 | */ | |
4d5e392c | 2539 | *baud = port->uartclk / (16 * (quot - 1)); |
1e6c9c28 AV |
2540 | } |
2541 | ||
7192f92c | 2542 | static int __init atmel_console_setup(struct console *co, char *options) |
1e6c9c28 | 2543 | { |
91f8c2d8 | 2544 | int ret; |
7192f92c | 2545 | struct uart_port *port = &atmel_ports[co->index].uart; |
1e6c9c28 AV |
2546 | int baud = 115200; |
2547 | int bits = 8; | |
2548 | int parity = 'n'; | |
2549 | int flow = 'n'; | |
2550 | ||
b843aa21 RB |
2551 | if (port->membase == NULL) { |
2552 | /* Port not initialized yet - delay setup */ | |
afefc415 | 2553 | return -ENODEV; |
b843aa21 | 2554 | } |
1e6c9c28 | 2555 | |
91f8c2d8 BB |
2556 | ret = clk_prepare_enable(atmel_ports[co->index].clk); |
2557 | if (ret) | |
2558 | return ret; | |
06a7f058 | 2559 | |
4e7decda CP |
2560 | atmel_uart_writel(port, ATMEL_US_IDR, -1); |
2561 | atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); | |
2562 | atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN); | |
1e6c9c28 AV |
2563 | |
2564 | if (options) | |
2565 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
2566 | else | |
7192f92c | 2567 | atmel_console_get_options(port, &baud, &parity, &bits); |
1e6c9c28 AV |
2568 | |
2569 | return uart_set_options(port, co, baud, parity, bits, flow); | |
2570 | } | |
2571 | ||
7192f92c | 2572 | static struct uart_driver atmel_uart; |
1e6c9c28 | 2573 | |
7192f92c HS |
2574 | static struct console atmel_console = { |
2575 | .name = ATMEL_DEVICENAME, | |
2576 | .write = atmel_console_write, | |
1e6c9c28 | 2577 | .device = uart_console_device, |
7192f92c | 2578 | .setup = atmel_console_setup, |
1e6c9c28 AV |
2579 | .flags = CON_PRINTBUFFER, |
2580 | .index = -1, | |
7192f92c | 2581 | .data = &atmel_uart, |
1e6c9c28 AV |
2582 | }; |
2583 | ||
06a7f058 | 2584 | #define ATMEL_CONSOLE_DEVICE (&atmel_console) |
1e6c9c28 | 2585 | |
afefc415 AV |
2586 | /* |
2587 | * Early console initialization (before VM subsystem initialized). | |
2588 | */ | |
7192f92c | 2589 | static int __init atmel_console_init(void) |
1e6c9c28 | 2590 | { |
91f8c2d8 | 2591 | int ret; |
73e2798b | 2592 | if (atmel_default_console_device) { |
0d0a3cc1 | 2593 | struct atmel_uart_data *pdata = |
574de559 | 2594 | dev_get_platdata(&atmel_default_console_device->dev); |
efb8d21b | 2595 | int id = pdata->num; |
b78cd169 | 2596 | struct atmel_uart_port *atmel_port = &atmel_ports[id]; |
4cbf9f48 | 2597 | |
b78cd169 JA |
2598 | atmel_port->backup_imr = 0; |
2599 | atmel_port->uart.line = id; | |
0d0a3cc1 | 2600 | |
4cbf9f48 | 2601 | add_preferred_console(ATMEL_DEVICENAME, id, NULL); |
b78cd169 | 2602 | ret = atmel_init_port(atmel_port, atmel_default_console_device); |
91f8c2d8 BB |
2603 | if (ret) |
2604 | return ret; | |
7192f92c | 2605 | register_console(&atmel_console); |
afefc415 | 2606 | } |
1e6c9c28 | 2607 | |
1e6c9c28 AV |
2608 | return 0; |
2609 | } | |
b843aa21 | 2610 | |
7192f92c | 2611 | console_initcall(atmel_console_init); |
1e6c9c28 | 2612 | |
afefc415 AV |
2613 | /* |
2614 | * Late console initialization. | |
2615 | */ | |
7192f92c | 2616 | static int __init atmel_late_console_init(void) |
afefc415 | 2617 | { |
b843aa21 RB |
2618 | if (atmel_default_console_device |
2619 | && !(atmel_console.flags & CON_ENABLED)) | |
7192f92c | 2620 | register_console(&atmel_console); |
afefc415 AV |
2621 | |
2622 | return 0; | |
2623 | } | |
b843aa21 | 2624 | |
7192f92c | 2625 | core_initcall(atmel_late_console_init); |
afefc415 | 2626 | |
dfa7f343 HS |
2627 | static inline bool atmel_is_console_port(struct uart_port *port) |
2628 | { | |
2629 | return port->cons && port->cons->index == port->line; | |
2630 | } | |
2631 | ||
1e6c9c28 | 2632 | #else |
7192f92c | 2633 | #define ATMEL_CONSOLE_DEVICE NULL |
dfa7f343 HS |
2634 | |
2635 | static inline bool atmel_is_console_port(struct uart_port *port) | |
2636 | { | |
2637 | return false; | |
2638 | } | |
1e6c9c28 AV |
2639 | #endif |
2640 | ||
7192f92c | 2641 | static struct uart_driver atmel_uart = { |
b843aa21 RB |
2642 | .owner = THIS_MODULE, |
2643 | .driver_name = "atmel_serial", | |
2644 | .dev_name = ATMEL_DEVICENAME, | |
2645 | .major = SERIAL_ATMEL_MAJOR, | |
2646 | .minor = MINOR_START, | |
2647 | .nr = ATMEL_MAX_UART, | |
2648 | .cons = ATMEL_CONSOLE_DEVICE, | |
1e6c9c28 AV |
2649 | }; |
2650 | ||
afefc415 | 2651 | #ifdef CONFIG_PM |
f826caa4 HS |
2652 | static bool atmel_serial_clk_will_stop(void) |
2653 | { | |
2654 | #ifdef CONFIG_ARCH_AT91 | |
2655 | return at91_suspend_entering_slow_clock(); | |
2656 | #else | |
2657 | return false; | |
2658 | #endif | |
2659 | } | |
2660 | ||
b843aa21 RB |
2661 | static int atmel_serial_suspend(struct platform_device *pdev, |
2662 | pm_message_t state) | |
1e6c9c28 | 2663 | { |
afefc415 | 2664 | struct uart_port *port = platform_get_drvdata(pdev); |
c811ab8c | 2665 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
afefc415 | 2666 | |
e1c609ef HS |
2667 | if (atmel_is_console_port(port) && console_suspend_enabled) { |
2668 | /* Drain the TX shifter */ | |
4e7decda CP |
2669 | while (!(atmel_uart_readl(port, ATMEL_US_CSR) & |
2670 | ATMEL_US_TXEMPTY)) | |
e1c609ef HS |
2671 | cpu_relax(); |
2672 | } | |
2673 | ||
f05596db AS |
2674 | /* we can not wake up if we're running on slow clock */ |
2675 | atmel_port->may_wakeup = device_may_wakeup(&pdev->dev); | |
2c7af5ba BB |
2676 | if (atmel_serial_clk_will_stop()) { |
2677 | unsigned long flags; | |
2678 | ||
2679 | spin_lock_irqsave(&atmel_port->lock_suspended, flags); | |
2680 | atmel_port->suspended = true; | |
2681 | spin_unlock_irqrestore(&atmel_port->lock_suspended, flags); | |
f05596db | 2682 | device_set_wakeup_enable(&pdev->dev, 0); |
2c7af5ba | 2683 | } |
f05596db AS |
2684 | |
2685 | uart_suspend_port(&atmel_uart, port); | |
1e6c9c28 | 2686 | |
afefc415 AV |
2687 | return 0; |
2688 | } | |
1e6c9c28 | 2689 | |
7192f92c | 2690 | static int atmel_serial_resume(struct platform_device *pdev) |
afefc415 AV |
2691 | { |
2692 | struct uart_port *port = platform_get_drvdata(pdev); | |
c811ab8c | 2693 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
2c7af5ba BB |
2694 | unsigned long flags; |
2695 | ||
2696 | spin_lock_irqsave(&atmel_port->lock_suspended, flags); | |
2697 | if (atmel_port->pending) { | |
2698 | atmel_handle_receive(port, atmel_port->pending); | |
2699 | atmel_handle_status(port, atmel_port->pending, | |
2700 | atmel_port->pending_status); | |
2701 | atmel_handle_transmit(port, atmel_port->pending); | |
2702 | atmel_port->pending = 0; | |
2703 | } | |
2704 | atmel_port->suspended = false; | |
2705 | spin_unlock_irqrestore(&atmel_port->lock_suspended, flags); | |
1e6c9c28 | 2706 | |
f05596db AS |
2707 | uart_resume_port(&atmel_uart, port); |
2708 | device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup); | |
1e6c9c28 AV |
2709 | |
2710 | return 0; | |
2711 | } | |
afefc415 | 2712 | #else |
7192f92c HS |
2713 | #define atmel_serial_suspend NULL |
2714 | #define atmel_serial_resume NULL | |
afefc415 | 2715 | #endif |
1e6c9c28 | 2716 | |
b78cd169 | 2717 | static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port, |
b5199d46 CP |
2718 | struct platform_device *pdev) |
2719 | { | |
b78cd169 JA |
2720 | atmel_port->fifo_size = 0; |
2721 | atmel_port->rts_low = 0; | |
2722 | atmel_port->rts_high = 0; | |
b5199d46 CP |
2723 | |
2724 | if (of_property_read_u32(pdev->dev.of_node, | |
2725 | "atmel,fifo-size", | |
b78cd169 | 2726 | &atmel_port->fifo_size)) |
b5199d46 CP |
2727 | return; |
2728 | ||
b78cd169 | 2729 | if (!atmel_port->fifo_size) |
b5199d46 CP |
2730 | return; |
2731 | ||
b78cd169 JA |
2732 | if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) { |
2733 | atmel_port->fifo_size = 0; | |
b5199d46 CP |
2734 | dev_err(&pdev->dev, "Invalid FIFO size\n"); |
2735 | return; | |
2736 | } | |
2737 | ||
2738 | /* | |
2739 | * 0 <= rts_low <= rts_high <= fifo_size | |
2740 | * Once their CTS line asserted by the remote peer, some x86 UARTs tend | |
2741 | * to flush their internal TX FIFO, commonly up to 16 data, before | |
2742 | * actually stopping to send new data. So we try to set the RTS High | |
2743 | * Threshold to a reasonably high value respecting this 16 data | |
2744 | * empirical rule when possible. | |
2745 | */ | |
b78cd169 JA |
2746 | atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1, |
2747 | atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET); | |
2748 | atmel_port->rts_low = max_t(int, atmel_port->fifo_size >> 2, | |
2749 | atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET); | |
b5199d46 CP |
2750 | |
2751 | dev_info(&pdev->dev, "Using FIFO (%u data)\n", | |
b78cd169 | 2752 | atmel_port->fifo_size); |
b5199d46 | 2753 | dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n", |
b78cd169 | 2754 | atmel_port->rts_high); |
b5199d46 | 2755 | dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n", |
b78cd169 | 2756 | atmel_port->rts_low); |
b5199d46 CP |
2757 | } |
2758 | ||
9671f099 | 2759 | static int atmel_serial_probe(struct platform_device *pdev) |
1e6c9c28 | 2760 | { |
b78cd169 | 2761 | struct atmel_uart_port *atmel_port; |
5fbe46b6 | 2762 | struct device_node *np = pdev->dev.of_node; |
574de559 | 2763 | struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); |
1ecc26bd | 2764 | void *data; |
4cbf9f48 | 2765 | int ret = -ENODEV; |
bd737f87 | 2766 | bool rs485_enabled; |
1e6c9c28 | 2767 | |
9d09daf8 | 2768 | BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1)); |
1ecc26bd | 2769 | |
5fbe46b6 NF |
2770 | if (np) |
2771 | ret = of_alias_get_id(np, "serial"); | |
2772 | else | |
2773 | if (pdata) | |
2774 | ret = pdata->num; | |
4cbf9f48 NF |
2775 | |
2776 | if (ret < 0) | |
5fbe46b6 | 2777 | /* port id not found in platform data nor device-tree aliases: |
4cbf9f48 | 2778 | * auto-enumerate it */ |
503bded9 | 2779 | ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART); |
4cbf9f48 | 2780 | |
503bded9 | 2781 | if (ret >= ATMEL_MAX_UART) { |
4cbf9f48 NF |
2782 | ret = -ENODEV; |
2783 | goto err; | |
2784 | } | |
2785 | ||
503bded9 | 2786 | if (test_and_set_bit(ret, atmel_ports_in_use)) { |
4cbf9f48 NF |
2787 | /* port already in use */ |
2788 | ret = -EBUSY; | |
2789 | goto err; | |
2790 | } | |
2791 | ||
b78cd169 JA |
2792 | atmel_port = &atmel_ports[ret]; |
2793 | atmel_port->backup_imr = 0; | |
2794 | atmel_port->uart.line = ret; | |
2795 | atmel_serial_probe_fifos(atmel_port, pdev); | |
e0b0baad | 2796 | |
98f2082c | 2797 | atomic_set(&atmel_port->tasklet_shutdown, 0); |
b78cd169 | 2798 | spin_lock_init(&atmel_port->lock_suspended); |
2c7af5ba | 2799 | |
b78cd169 | 2800 | ret = atmel_init_port(atmel_port, pdev); |
91f8c2d8 | 2801 | if (ret) |
6fbb9bdf | 2802 | goto err_clear_bit; |
1e6c9c28 | 2803 | |
b78cd169 JA |
2804 | atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0); |
2805 | if (IS_ERR(atmel_port->gpios)) { | |
2806 | ret = PTR_ERR(atmel_port->gpios); | |
18dfef9c UKK |
2807 | goto err_clear_bit; |
2808 | } | |
2809 | ||
b78cd169 | 2810 | if (!atmel_use_pdc_rx(&atmel_port->uart)) { |
a6670615 | 2811 | ret = -ENOMEM; |
6433471d HS |
2812 | data = kmalloc(sizeof(struct atmel_uart_char) |
2813 | * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL); | |
a6670615 CC |
2814 | if (!data) |
2815 | goto err_alloc_ring; | |
b78cd169 | 2816 | atmel_port->rx_ring.buf = data; |
a6670615 | 2817 | } |
1ecc26bd | 2818 | |
b78cd169 | 2819 | rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED; |
bd737f87 | 2820 | |
b78cd169 | 2821 | ret = uart_add_one_port(&atmel_uart, &atmel_port->uart); |
dfa7f343 HS |
2822 | if (ret) |
2823 | goto err_add_port; | |
2824 | ||
8da14b5f | 2825 | #ifdef CONFIG_SERIAL_ATMEL_CONSOLE |
b78cd169 | 2826 | if (atmel_is_console_port(&atmel_port->uart) |
06a7f058 DB |
2827 | && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) { |
2828 | /* | |
2829 | * The serial core enabled the clock for us, so undo | |
91f8c2d8 | 2830 | * the clk_prepare_enable() in atmel_console_setup() |
06a7f058 | 2831 | */ |
b78cd169 | 2832 | clk_disable_unprepare(atmel_port->clk); |
06a7f058 | 2833 | } |
8da14b5f | 2834 | #endif |
06a7f058 | 2835 | |
dfa7f343 | 2836 | device_init_wakeup(&pdev->dev, 1); |
b78cd169 | 2837 | platform_set_drvdata(pdev, atmel_port); |
dfa7f343 | 2838 | |
d4f64187 CP |
2839 | /* |
2840 | * The peripheral clock has been disabled by atmel_init_port(): | |
2841 | * enable it before accessing I/O registers | |
2842 | */ | |
b78cd169 | 2843 | clk_prepare_enable(atmel_port->clk); |
d4f64187 | 2844 | |
bd737f87 | 2845 | if (rs485_enabled) { |
b78cd169 | 2846 | atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR, |
4e7decda | 2847 | ATMEL_US_USMODE_NORMAL); |
b78cd169 JA |
2848 | atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR, |
2849 | ATMEL_US_RTSEN); | |
5dfbd1d7 CS |
2850 | } |
2851 | ||
055560b0 ES |
2852 | /* |
2853 | * Get port name of usart or uart | |
2854 | */ | |
b78cd169 | 2855 | atmel_get_ip_name(&atmel_port->uart); |
055560b0 | 2856 | |
d4f64187 CP |
2857 | /* |
2858 | * The peripheral clock can now safely be disabled till the port | |
2859 | * is used | |
2860 | */ | |
b78cd169 | 2861 | clk_disable_unprepare(atmel_port->clk); |
d4f64187 | 2862 | |
dfa7f343 HS |
2863 | return 0; |
2864 | ||
2865 | err_add_port: | |
b78cd169 JA |
2866 | kfree(atmel_port->rx_ring.buf); |
2867 | atmel_port->rx_ring.buf = NULL; | |
1ecc26bd | 2868 | err_alloc_ring: |
b78cd169 JA |
2869 | if (!atmel_is_console_port(&atmel_port->uart)) { |
2870 | clk_put(atmel_port->clk); | |
2871 | atmel_port->clk = NULL; | |
afefc415 | 2872 | } |
6fbb9bdf | 2873 | err_clear_bit: |
b78cd169 | 2874 | clear_bit(atmel_port->uart.line, atmel_ports_in_use); |
4cbf9f48 | 2875 | err: |
afefc415 AV |
2876 | return ret; |
2877 | } | |
2878 | ||
f4a8ab04 RI |
2879 | /* |
2880 | * Even if the driver is not modular, it makes sense to be able to | |
2881 | * unbind a device: there can be many bound devices, and there are | |
2882 | * situations where dynamic binding and unbinding can be useful. | |
2883 | * | |
2884 | * For example, a connected device can require a specific firmware update | |
2885 | * protocol that needs bitbanging on IO lines, but use the regular serial | |
2886 | * port in the normal case. | |
2887 | */ | |
2888 | static int atmel_serial_remove(struct platform_device *pdev) | |
2889 | { | |
2890 | struct uart_port *port = platform_get_drvdata(pdev); | |
2891 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
2892 | int ret = 0; | |
2893 | ||
00e8e658 NF |
2894 | tasklet_kill(&atmel_port->tasklet_rx); |
2895 | tasklet_kill(&atmel_port->tasklet_tx); | |
f4a8ab04 RI |
2896 | |
2897 | device_init_wakeup(&pdev->dev, 0); | |
2898 | ||
2899 | ret = uart_remove_one_port(&atmel_uart, port); | |
2900 | ||
2901 | kfree(atmel_port->rx_ring.buf); | |
2902 | ||
2903 | /* "port" is allocated statically, so we shouldn't free it */ | |
2904 | ||
2905 | clear_bit(port->line, atmel_ports_in_use); | |
2906 | ||
2907 | clk_put(atmel_port->clk); | |
2908 | atmel_port->clk = NULL; | |
2909 | ||
2910 | return ret; | |
2911 | } | |
2912 | ||
7192f92c HS |
2913 | static struct platform_driver atmel_serial_driver = { |
2914 | .probe = atmel_serial_probe, | |
f4a8ab04 | 2915 | .remove = atmel_serial_remove, |
7192f92c HS |
2916 | .suspend = atmel_serial_suspend, |
2917 | .resume = atmel_serial_resume, | |
afefc415 | 2918 | .driver = { |
c39dfebc PG |
2919 | .name = "atmel_usart", |
2920 | .of_match_table = of_match_ptr(atmel_serial_dt_ids), | |
afefc415 AV |
2921 | }, |
2922 | }; | |
2923 | ||
7192f92c | 2924 | static int __init atmel_serial_init(void) |
afefc415 AV |
2925 | { |
2926 | int ret; | |
2927 | ||
7192f92c | 2928 | ret = uart_register_driver(&atmel_uart); |
afefc415 AV |
2929 | if (ret) |
2930 | return ret; | |
2931 | ||
7192f92c | 2932 | ret = platform_driver_register(&atmel_serial_driver); |
afefc415 | 2933 | if (ret) |
7192f92c | 2934 | uart_unregister_driver(&atmel_uart); |
afefc415 AV |
2935 | |
2936 | return ret; | |
2937 | } | |
c39dfebc | 2938 | device_initcall(atmel_serial_init); |