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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) |
3 | * | |
f43dc23d | 4 | * Copyright (C) 2002 - 2011 Paul Mundt |
3ea6bc3d | 5 | * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). |
1da177e4 LT |
6 | * |
7 | * based off of the old drivers/char/sh-sci.c by: | |
8 | * | |
9 | * Copyright (C) 1999, 2000 Niibe Yutaka | |
10 | * Copyright (C) 2000 Sugioka Toshinobu | |
11 | * Modified to support multiple serial ports. Stuart Menefy (May 2000). | |
12 | * Modified to support SecureEdge. David McCullough (2002) | |
13 | * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). | |
d89ddd1c | 14 | * Removed SH7300 support (Jul 2007). |
1da177e4 LT |
15 | * |
16 | * This file is subject to the terms and conditions of the GNU General Public | |
17 | * License. See the file "COPYING" in the main directory of this archive | |
18 | * for more details. | |
19 | */ | |
0b3d4ef6 PM |
20 | #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
21 | #define SUPPORT_SYSRQ | |
22 | #endif | |
1da177e4 LT |
23 | |
24 | #undef DEBUG | |
25 | ||
1da177e4 LT |
26 | #include <linux/module.h> |
27 | #include <linux/errno.h> | |
1da177e4 LT |
28 | #include <linux/timer.h> |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/tty.h> | |
31 | #include <linux/tty_flip.h> | |
32 | #include <linux/serial.h> | |
33 | #include <linux/major.h> | |
34 | #include <linux/string.h> | |
35 | #include <linux/sysrq.h> | |
1da177e4 LT |
36 | #include <linux/ioport.h> |
37 | #include <linux/mm.h> | |
1da177e4 LT |
38 | #include <linux/init.h> |
39 | #include <linux/delay.h> | |
40 | #include <linux/console.h> | |
e108b2ca | 41 | #include <linux/platform_device.h> |
96de1a8f | 42 | #include <linux/serial_sci.h> |
1da177e4 | 43 | #include <linux/notifier.h> |
5e50d2d6 | 44 | #include <linux/pm_runtime.h> |
1da177e4 | 45 | #include <linux/cpufreq.h> |
85f094ec | 46 | #include <linux/clk.h> |
fa5da2f7 | 47 | #include <linux/ctype.h> |
7ff731ae | 48 | #include <linux/err.h> |
73a19e4c GL |
49 | #include <linux/dmaengine.h> |
50 | #include <linux/scatterlist.h> | |
5a0e3ad6 | 51 | #include <linux/slab.h> |
85f094ec PM |
52 | |
53 | #ifdef CONFIG_SUPERH | |
1da177e4 LT |
54 | #include <asm/sh_bios.h> |
55 | #endif | |
56 | ||
168f3623 YS |
57 | #ifdef CONFIG_H8300 |
58 | #include <asm/gpio.h> | |
59 | #endif | |
60 | ||
1da177e4 LT |
61 | #include "sh-sci.h" |
62 | ||
e108b2ca PM |
63 | struct sci_port { |
64 | struct uart_port port; | |
65 | ||
ce6738b6 PM |
66 | /* Platform configuration */ |
67 | struct plat_sci_port *cfg; | |
e108b2ca | 68 | |
e108b2ca PM |
69 | /* Port enable callback */ |
70 | void (*enable)(struct uart_port *port); | |
71 | ||
72 | /* Port disable callback */ | |
73 | void (*disable)(struct uart_port *port); | |
74 | ||
75 | /* Break timer */ | |
76 | struct timer_list break_timer; | |
77 | int break_flag; | |
1534a3b3 | 78 | |
501b825d MD |
79 | /* Interface clock */ |
80 | struct clk *iclk; | |
c7ed1ab3 PM |
81 | /* Function clock */ |
82 | struct clk *fclk; | |
edad1f20 | 83 | |
73a19e4c GL |
84 | struct dma_chan *chan_tx; |
85 | struct dma_chan *chan_rx; | |
f43dc23d | 86 | |
73a19e4c | 87 | #ifdef CONFIG_SERIAL_SH_SCI_DMA |
73a19e4c GL |
88 | struct dma_async_tx_descriptor *desc_tx; |
89 | struct dma_async_tx_descriptor *desc_rx[2]; | |
90 | dma_cookie_t cookie_tx; | |
91 | dma_cookie_t cookie_rx[2]; | |
92 | dma_cookie_t active_rx; | |
93 | struct scatterlist sg_tx; | |
94 | unsigned int sg_len_tx; | |
95 | struct scatterlist sg_rx[2]; | |
96 | size_t buf_len_rx; | |
97 | struct sh_dmae_slave param_tx; | |
98 | struct sh_dmae_slave param_rx; | |
99 | struct work_struct work_tx; | |
100 | struct work_struct work_rx; | |
101 | struct timer_list rx_timer; | |
3089f381 | 102 | unsigned int rx_timeout; |
73a19e4c | 103 | #endif |
e552de24 | 104 | |
d535a230 | 105 | struct notifier_block freq_transition; |
e108b2ca PM |
106 | }; |
107 | ||
1da177e4 | 108 | /* Function prototypes */ |
d535a230 | 109 | static void sci_start_tx(struct uart_port *port); |
b129a8cc | 110 | static void sci_stop_tx(struct uart_port *port); |
d535a230 | 111 | static void sci_start_rx(struct uart_port *port); |
1da177e4 | 112 | |
e108b2ca | 113 | #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS |
b7a76e4b | 114 | |
e108b2ca PM |
115 | static struct sci_port sci_ports[SCI_NPORTS]; |
116 | static struct uart_driver sci_uart_driver; | |
1da177e4 | 117 | |
e7c98dc7 MT |
118 | static inline struct sci_port * |
119 | to_sci_port(struct uart_port *uart) | |
120 | { | |
121 | return container_of(uart, struct sci_port, port); | |
122 | } | |
123 | ||
07d2a1a1 | 124 | #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) |
1f6fd5c9 PM |
125 | |
126 | #ifdef CONFIG_CONSOLE_POLL | |
07d2a1a1 | 127 | static int sci_poll_get_char(struct uart_port *port) |
1da177e4 | 128 | { |
1da177e4 LT |
129 | unsigned short status; |
130 | int c; | |
131 | ||
e108b2ca | 132 | do { |
1da177e4 LT |
133 | status = sci_in(port, SCxSR); |
134 | if (status & SCxSR_ERRORS(port)) { | |
94c8b6db | 135 | sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); |
1da177e4 LT |
136 | continue; |
137 | } | |
3f255eb3 JW |
138 | break; |
139 | } while (1); | |
140 | ||
141 | if (!(status & SCxSR_RDxF(port))) | |
142 | return NO_POLL_CHAR; | |
07d2a1a1 | 143 | |
1da177e4 | 144 | c = sci_in(port, SCxRDR); |
07d2a1a1 | 145 | |
e7c98dc7 MT |
146 | /* Dummy read */ |
147 | sci_in(port, SCxSR); | |
1da177e4 | 148 | sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); |
1da177e4 LT |
149 | |
150 | return c; | |
151 | } | |
1f6fd5c9 | 152 | #endif |
1da177e4 | 153 | |
07d2a1a1 | 154 | static void sci_poll_put_char(struct uart_port *port, unsigned char c) |
1da177e4 | 155 | { |
1da177e4 LT |
156 | unsigned short status; |
157 | ||
1da177e4 LT |
158 | do { |
159 | status = sci_in(port, SCxSR); | |
160 | } while (!(status & SCxSR_TDxE(port))); | |
161 | ||
272966c0 | 162 | sci_out(port, SCxTDR, c); |
dd0a3e77 | 163 | sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); |
1da177e4 | 164 | } |
07d2a1a1 | 165 | #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */ |
1da177e4 | 166 | |
15c73aaa | 167 | #if defined(__H8300H__) || defined(__H8300S__) |
d5701647 | 168 | static void sci_init_pins(struct uart_port *port, unsigned int cflag) |
1da177e4 LT |
169 | { |
170 | int ch = (port->mapbase - SMR0) >> 3; | |
171 | ||
172 | /* set DDR regs */ | |
e108b2ca PM |
173 | H8300_GPIO_DDR(h8300_sci_pins[ch].port, |
174 | h8300_sci_pins[ch].rx, | |
175 | H8300_GPIO_INPUT); | |
176 | H8300_GPIO_DDR(h8300_sci_pins[ch].port, | |
177 | h8300_sci_pins[ch].tx, | |
178 | H8300_GPIO_OUTPUT); | |
179 | ||
1da177e4 LT |
180 | /* tx mark output*/ |
181 | H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx; | |
182 | } | |
d5701647 PM |
183 | #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) |
184 | static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) | |
e108b2ca | 185 | { |
d5701647 PM |
186 | if (port->mapbase == 0xA4400000) { |
187 | __raw_writew(__raw_readw(PACR) & 0xffc0, PACR); | |
188 | __raw_writew(__raw_readw(PBCR) & 0x0fff, PBCR); | |
189 | } else if (port->mapbase == 0xA4410000) | |
190 | __raw_writew(__raw_readw(PBCR) & 0xf003, PBCR); | |
9465a54f | 191 | } |
31a49c4b | 192 | #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721) |
d5701647 | 193 | static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) |
3ea6bc3d | 194 | { |
3ea6bc3d MB |
195 | unsigned short data; |
196 | ||
197 | if (cflag & CRTSCTS) { | |
198 | /* enable RTS/CTS */ | |
199 | if (port->mapbase == 0xa4430000) { /* SCIF0 */ | |
200 | /* Clear PTCR bit 9-2; enable all scif pins but sck */ | |
d5701647 PM |
201 | data = __raw_readw(PORT_PTCR); |
202 | __raw_writew((data & 0xfc03), PORT_PTCR); | |
3ea6bc3d MB |
203 | } else if (port->mapbase == 0xa4438000) { /* SCIF1 */ |
204 | /* Clear PVCR bit 9-2 */ | |
d5701647 PM |
205 | data = __raw_readw(PORT_PVCR); |
206 | __raw_writew((data & 0xfc03), PORT_PVCR); | |
3ea6bc3d | 207 | } |
3ea6bc3d MB |
208 | } else { |
209 | if (port->mapbase == 0xa4430000) { /* SCIF0 */ | |
210 | /* Clear PTCR bit 5-2; enable only tx and rx */ | |
d5701647 PM |
211 | data = __raw_readw(PORT_PTCR); |
212 | __raw_writew((data & 0xffc3), PORT_PTCR); | |
3ea6bc3d MB |
213 | } else if (port->mapbase == 0xa4438000) { /* SCIF1 */ |
214 | /* Clear PVCR bit 5-2 */ | |
d5701647 PM |
215 | data = __raw_readw(PORT_PVCR); |
216 | __raw_writew((data & 0xffc3), PORT_PVCR); | |
3ea6bc3d MB |
217 | } |
218 | } | |
3ea6bc3d | 219 | } |
b7a76e4b | 220 | #elif defined(CONFIG_CPU_SH3) |
e108b2ca | 221 | /* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */ |
d5701647 | 222 | static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) |
1da177e4 | 223 | { |
b7a76e4b PM |
224 | unsigned short data; |
225 | ||
226 | /* We need to set SCPCR to enable RTS/CTS */ | |
d5701647 | 227 | data = __raw_readw(SCPCR); |
b7a76e4b | 228 | /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/ |
d5701647 | 229 | __raw_writew(data & 0x0fcf, SCPCR); |
1da177e4 | 230 | |
d5701647 | 231 | if (!(cflag & CRTSCTS)) { |
1da177e4 | 232 | /* We need to set SCPCR to enable RTS/CTS */ |
d5701647 | 233 | data = __raw_readw(SCPCR); |
1da177e4 LT |
234 | /* Clear out SCP7MD1,0, SCP4MD1,0, |
235 | Set SCP6MD1,0 = {01} (output) */ | |
d5701647 | 236 | __raw_writew((data & 0x0fcf) | 0x1000, SCPCR); |
1da177e4 | 237 | |
32b53076 | 238 | data = __raw_readb(SCPDR); |
1da177e4 | 239 | /* Set /RTS2 (bit6) = 0 */ |
32b53076 | 240 | __raw_writeb(data & 0xbf, SCPDR); |
1da177e4 | 241 | } |
1da177e4 | 242 | } |
41504c39 | 243 | #elif defined(CONFIG_CPU_SUBTYPE_SH7722) |
d5701647 | 244 | static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) |
41504c39 | 245 | { |
346b7463 | 246 | unsigned short data; |
41504c39 | 247 | |
346b7463 | 248 | if (port->mapbase == 0xffe00000) { |
d5701647 | 249 | data = __raw_readw(PSCR); |
346b7463 | 250 | data &= ~0x03cf; |
d5701647 | 251 | if (!(cflag & CRTSCTS)) |
346b7463 | 252 | data |= 0x0340; |
41504c39 | 253 | |
d5701647 | 254 | __raw_writew(data, PSCR); |
41504c39 | 255 | } |
178dd0cd | 256 | } |
c01f0f1a YS |
257 | #elif defined(CONFIG_CPU_SUBTYPE_SH7757) || \ |
258 | defined(CONFIG_CPU_SUBTYPE_SH7763) || \ | |
7d740a06 | 259 | defined(CONFIG_CPU_SUBTYPE_SH7780) || \ |
2b1bd1ac | 260 | defined(CONFIG_CPU_SUBTYPE_SH7785) || \ |
55ba99eb | 261 | defined(CONFIG_CPU_SUBTYPE_SH7786) || \ |
2b1bd1ac | 262 | defined(CONFIG_CPU_SUBTYPE_SHX3) |
d5701647 PM |
263 | static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) |
264 | { | |
265 | if (!(cflag & CRTSCTS)) | |
266 | __raw_writew(0x0080, SCSPTR0); /* Set RTS = 1 */ | |
267 | } | |
b0c50ad7 | 268 | #elif defined(CONFIG_CPU_SH4) && !defined(CONFIG_CPU_SH4A) |
d5701647 PM |
269 | static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) |
270 | { | |
271 | if (!(cflag & CRTSCTS)) | |
272 | __raw_writew(0x0080, SCSPTR2); /* Set RTS = 1 */ | |
273 | } | |
b7a76e4b | 274 | #else |
d5701647 PM |
275 | static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) |
276 | { | |
277 | /* Nothing to do */ | |
1da177e4 | 278 | } |
e108b2ca PM |
279 | #endif |
280 | ||
32351a28 PM |
281 | #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \ |
282 | defined(CONFIG_CPU_SUBTYPE_SH7780) || \ | |
55ba99eb KM |
283 | defined(CONFIG_CPU_SUBTYPE_SH7785) || \ |
284 | defined(CONFIG_CPU_SUBTYPE_SH7786) | |
73a19e4c | 285 | static int scif_txfill(struct uart_port *port) |
e108b2ca | 286 | { |
73a19e4c | 287 | return sci_in(port, SCTFDR) & 0xff; |
e108b2ca PM |
288 | } |
289 | ||
73a19e4c | 290 | static int scif_txroom(struct uart_port *port) |
e108b2ca | 291 | { |
73a19e4c | 292 | return SCIF_TXROOM_MAX - scif_txfill(port); |
e108b2ca PM |
293 | } |
294 | ||
73a19e4c | 295 | static int scif_rxfill(struct uart_port *port) |
e108b2ca | 296 | { |
cae167d3 | 297 | return sci_in(port, SCRFDR) & 0xff; |
e108b2ca | 298 | } |
c63847a3 | 299 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) |
73a19e4c | 300 | static int scif_txfill(struct uart_port *port) |
c63847a3 | 301 | { |
73a19e4c GL |
302 | if (port->mapbase == 0xffe00000 || |
303 | port->mapbase == 0xffe08000) | |
e7c98dc7 | 304 | /* SCIF0/1*/ |
73a19e4c GL |
305 | return sci_in(port, SCTFDR) & 0xff; |
306 | else | |
e7c98dc7 | 307 | /* SCIF2 */ |
73a19e4c | 308 | return sci_in(port, SCFDR) >> 8; |
c63847a3 NI |
309 | } |
310 | ||
73a19e4c GL |
311 | static int scif_txroom(struct uart_port *port) |
312 | { | |
313 | if (port->mapbase == 0xffe00000 || | |
314 | port->mapbase == 0xffe08000) | |
315 | /* SCIF0/1*/ | |
316 | return SCIF_TXROOM_MAX - scif_txfill(port); | |
317 | else | |
318 | /* SCIF2 */ | |
319 | return SCIF2_TXROOM_MAX - scif_txfill(port); | |
c63847a3 NI |
320 | } |
321 | ||
73a19e4c | 322 | static int scif_rxfill(struct uart_port *port) |
c63847a3 | 323 | { |
e7c98dc7 MT |
324 | if ((port->mapbase == 0xffe00000) || |
325 | (port->mapbase == 0xffe08000)) { | |
326 | /* SCIF0/1*/ | |
c63847a3 | 327 | return sci_in(port, SCRFDR) & 0xff; |
e7c98dc7 MT |
328 | } else { |
329 | /* SCIF2 */ | |
c63847a3 | 330 | return sci_in(port, SCFDR) & SCIF2_RFDC_MASK; |
e7c98dc7 | 331 | } |
c63847a3 | 332 | } |
d1d4b10c GL |
333 | #elif defined(CONFIG_ARCH_SH7372) |
334 | static int scif_txfill(struct uart_port *port) | |
335 | { | |
336 | if (port->type == PORT_SCIFA) | |
337 | return sci_in(port, SCFDR) >> 8; | |
338 | else | |
339 | return sci_in(port, SCTFDR); | |
340 | } | |
341 | ||
342 | static int scif_txroom(struct uart_port *port) | |
343 | { | |
344 | return port->fifosize - scif_txfill(port); | |
345 | } | |
346 | ||
347 | static int scif_rxfill(struct uart_port *port) | |
348 | { | |
349 | if (port->type == PORT_SCIFA) | |
350 | return sci_in(port, SCFDR) & SCIF_RFDC_MASK; | |
351 | else | |
352 | return sci_in(port, SCRFDR); | |
353 | } | |
e108b2ca | 354 | #else |
73a19e4c | 355 | static int scif_txfill(struct uart_port *port) |
e108b2ca | 356 | { |
73a19e4c | 357 | return sci_in(port, SCFDR) >> 8; |
e108b2ca | 358 | } |
1da177e4 | 359 | |
73a19e4c | 360 | static int scif_txroom(struct uart_port *port) |
e108b2ca | 361 | { |
73a19e4c | 362 | return SCIF_TXROOM_MAX - scif_txfill(port); |
e108b2ca | 363 | } |
1da177e4 | 364 | |
73a19e4c | 365 | static int scif_rxfill(struct uart_port *port) |
e108b2ca PM |
366 | { |
367 | return sci_in(port, SCFDR) & SCIF_RFDC_MASK; | |
368 | } | |
1da177e4 | 369 | #endif |
1da177e4 | 370 | |
73a19e4c | 371 | static int sci_txfill(struct uart_port *port) |
e108b2ca | 372 | { |
73a19e4c | 373 | return !(sci_in(port, SCxSR) & SCI_TDRE); |
e108b2ca PM |
374 | } |
375 | ||
73a19e4c GL |
376 | static int sci_txroom(struct uart_port *port) |
377 | { | |
378 | return !sci_txfill(port); | |
379 | } | |
380 | ||
381 | static int sci_rxfill(struct uart_port *port) | |
e108b2ca | 382 | { |
e7c98dc7 | 383 | return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; |
e108b2ca PM |
384 | } |
385 | ||
1da177e4 LT |
386 | /* ********************************************************************** * |
387 | * the interrupt related routines * | |
388 | * ********************************************************************** */ | |
389 | ||
390 | static void sci_transmit_chars(struct uart_port *port) | |
391 | { | |
ebd2c8f6 | 392 | struct circ_buf *xmit = &port->state->xmit; |
1da177e4 | 393 | unsigned int stopped = uart_tx_stopped(port); |
1da177e4 LT |
394 | unsigned short status; |
395 | unsigned short ctrl; | |
e108b2ca | 396 | int count; |
1da177e4 LT |
397 | |
398 | status = sci_in(port, SCxSR); | |
399 | if (!(status & SCxSR_TDxE(port))) { | |
1da177e4 | 400 | ctrl = sci_in(port, SCSCR); |
e7c98dc7 | 401 | if (uart_circ_empty(xmit)) |
8e698614 | 402 | ctrl &= ~SCSCR_TIE; |
e7c98dc7 | 403 | else |
8e698614 | 404 | ctrl |= SCSCR_TIE; |
1da177e4 | 405 | sci_out(port, SCSCR, ctrl); |
1da177e4 LT |
406 | return; |
407 | } | |
408 | ||
1a22f08d | 409 | if (port->type == PORT_SCI) |
e108b2ca | 410 | count = sci_txroom(port); |
1a22f08d YS |
411 | else |
412 | count = scif_txroom(port); | |
1da177e4 LT |
413 | |
414 | do { | |
415 | unsigned char c; | |
416 | ||
417 | if (port->x_char) { | |
418 | c = port->x_char; | |
419 | port->x_char = 0; | |
420 | } else if (!uart_circ_empty(xmit) && !stopped) { | |
421 | c = xmit->buf[xmit->tail]; | |
422 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
423 | } else { | |
424 | break; | |
425 | } | |
426 | ||
427 | sci_out(port, SCxTDR, c); | |
428 | ||
429 | port->icount.tx++; | |
430 | } while (--count > 0); | |
431 | ||
432 | sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); | |
433 | ||
434 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
435 | uart_write_wakeup(port); | |
436 | if (uart_circ_empty(xmit)) { | |
b129a8cc | 437 | sci_stop_tx(port); |
1da177e4 | 438 | } else { |
1da177e4 LT |
439 | ctrl = sci_in(port, SCSCR); |
440 | ||
1a22f08d | 441 | if (port->type != PORT_SCI) { |
1da177e4 LT |
442 | sci_in(port, SCxSR); /* Dummy read */ |
443 | sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); | |
444 | } | |
1da177e4 | 445 | |
8e698614 | 446 | ctrl |= SCSCR_TIE; |
1da177e4 | 447 | sci_out(port, SCSCR, ctrl); |
1da177e4 LT |
448 | } |
449 | } | |
450 | ||
451 | /* On SH3, SCIF may read end-of-break as a space->mark char */ | |
e7c98dc7 | 452 | #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); }) |
1da177e4 | 453 | |
94c8b6db | 454 | static void sci_receive_chars(struct uart_port *port) |
1da177e4 | 455 | { |
e7c98dc7 | 456 | struct sci_port *sci_port = to_sci_port(port); |
ebd2c8f6 | 457 | struct tty_struct *tty = port->state->port.tty; |
1da177e4 LT |
458 | int i, count, copied = 0; |
459 | unsigned short status; | |
33f0f88f | 460 | unsigned char flag; |
1da177e4 LT |
461 | |
462 | status = sci_in(port, SCxSR); | |
463 | if (!(status & SCxSR_RDxF(port))) | |
464 | return; | |
465 | ||
466 | while (1) { | |
1a22f08d | 467 | if (port->type == PORT_SCI) |
73a19e4c | 468 | count = sci_rxfill(port); |
1a22f08d | 469 | else |
73a19e4c | 470 | count = scif_rxfill(port); |
1da177e4 LT |
471 | |
472 | /* Don't copy more bytes than there is room for in the buffer */ | |
33f0f88f | 473 | count = tty_buffer_request_room(tty, count); |
1da177e4 LT |
474 | |
475 | /* If for any reason we can't copy more data, we're done! */ | |
476 | if (count == 0) | |
477 | break; | |
478 | ||
479 | if (port->type == PORT_SCI) { | |
480 | char c = sci_in(port, SCxRDR); | |
e7c98dc7 MT |
481 | if (uart_handle_sysrq_char(port, c) || |
482 | sci_port->break_flag) | |
1da177e4 | 483 | count = 0; |
e7c98dc7 | 484 | else |
e108b2ca | 485 | tty_insert_flip_char(tty, c, TTY_NORMAL); |
1da177e4 | 486 | } else { |
e7c98dc7 | 487 | for (i = 0; i < count; i++) { |
1da177e4 LT |
488 | char c = sci_in(port, SCxRDR); |
489 | status = sci_in(port, SCxSR); | |
490 | #if defined(CONFIG_CPU_SH3) | |
491 | /* Skip "chars" during break */ | |
e108b2ca | 492 | if (sci_port->break_flag) { |
1da177e4 LT |
493 | if ((c == 0) && |
494 | (status & SCxSR_FER(port))) { | |
495 | count--; i--; | |
496 | continue; | |
497 | } | |
e108b2ca | 498 | |
1da177e4 | 499 | /* Nonzero => end-of-break */ |
762c69e3 | 500 | dev_dbg(port->dev, "debounce<%02x>\n", c); |
e108b2ca PM |
501 | sci_port->break_flag = 0; |
502 | ||
1da177e4 LT |
503 | if (STEPFN(c)) { |
504 | count--; i--; | |
505 | continue; | |
506 | } | |
507 | } | |
508 | #endif /* CONFIG_CPU_SH3 */ | |
7d12e780 | 509 | if (uart_handle_sysrq_char(port, c)) { |
1da177e4 LT |
510 | count--; i--; |
511 | continue; | |
512 | } | |
513 | ||
514 | /* Store data and status */ | |
73a19e4c | 515 | if (status & SCxSR_FER(port)) { |
33f0f88f | 516 | flag = TTY_FRAME; |
762c69e3 | 517 | dev_notice(port->dev, "frame error\n"); |
73a19e4c | 518 | } else if (status & SCxSR_PER(port)) { |
33f0f88f | 519 | flag = TTY_PARITY; |
762c69e3 | 520 | dev_notice(port->dev, "parity error\n"); |
33f0f88f AC |
521 | } else |
522 | flag = TTY_NORMAL; | |
762c69e3 | 523 | |
33f0f88f | 524 | tty_insert_flip_char(tty, c, flag); |
1da177e4 LT |
525 | } |
526 | } | |
527 | ||
528 | sci_in(port, SCxSR); /* dummy read */ | |
529 | sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); | |
530 | ||
1da177e4 LT |
531 | copied += count; |
532 | port->icount.rx += count; | |
533 | } | |
534 | ||
535 | if (copied) { | |
536 | /* Tell the rest of the system the news. New characters! */ | |
537 | tty_flip_buffer_push(tty); | |
538 | } else { | |
539 | sci_in(port, SCxSR); /* dummy read */ | |
540 | sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); | |
541 | } | |
542 | } | |
543 | ||
544 | #define SCI_BREAK_JIFFIES (HZ/20) | |
94c8b6db PM |
545 | |
546 | /* | |
547 | * The sci generates interrupts during the break, | |
1da177e4 LT |
548 | * 1 per millisecond or so during the break period, for 9600 baud. |
549 | * So dont bother disabling interrupts. | |
550 | * But dont want more than 1 break event. | |
551 | * Use a kernel timer to periodically poll the rx line until | |
552 | * the break is finished. | |
553 | */ | |
94c8b6db | 554 | static inline void sci_schedule_break_timer(struct sci_port *port) |
1da177e4 | 555 | { |
bc9b3f5c | 556 | mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES); |
1da177e4 | 557 | } |
94c8b6db | 558 | |
1da177e4 LT |
559 | /* Ensure that two consecutive samples find the break over. */ |
560 | static void sci_break_timer(unsigned long data) | |
561 | { | |
e108b2ca PM |
562 | struct sci_port *port = (struct sci_port *)data; |
563 | ||
5e50d2d6 MD |
564 | if (port->enable) |
565 | port->enable(&port->port); | |
566 | ||
e108b2ca | 567 | if (sci_rxd_in(&port->port) == 0) { |
1da177e4 | 568 | port->break_flag = 1; |
e108b2ca PM |
569 | sci_schedule_break_timer(port); |
570 | } else if (port->break_flag == 1) { | |
1da177e4 LT |
571 | /* break is over. */ |
572 | port->break_flag = 2; | |
e108b2ca PM |
573 | sci_schedule_break_timer(port); |
574 | } else | |
575 | port->break_flag = 0; | |
5e50d2d6 MD |
576 | |
577 | if (port->disable) | |
578 | port->disable(&port->port); | |
1da177e4 LT |
579 | } |
580 | ||
94c8b6db | 581 | static int sci_handle_errors(struct uart_port *port) |
1da177e4 LT |
582 | { |
583 | int copied = 0; | |
584 | unsigned short status = sci_in(port, SCxSR); | |
ebd2c8f6 | 585 | struct tty_struct *tty = port->state->port.tty; |
1da177e4 | 586 | |
e108b2ca | 587 | if (status & SCxSR_ORER(port)) { |
1da177e4 | 588 | /* overrun error */ |
e108b2ca | 589 | if (tty_insert_flip_char(tty, 0, TTY_OVERRUN)) |
33f0f88f | 590 | copied++; |
762c69e3 PM |
591 | |
592 | dev_notice(port->dev, "overrun error"); | |
1da177e4 LT |
593 | } |
594 | ||
e108b2ca | 595 | if (status & SCxSR_FER(port)) { |
1da177e4 LT |
596 | if (sci_rxd_in(port) == 0) { |
597 | /* Notify of BREAK */ | |
e7c98dc7 | 598 | struct sci_port *sci_port = to_sci_port(port); |
e108b2ca PM |
599 | |
600 | if (!sci_port->break_flag) { | |
601 | sci_port->break_flag = 1; | |
602 | sci_schedule_break_timer(sci_port); | |
603 | ||
1da177e4 | 604 | /* Do sysrq handling. */ |
e108b2ca | 605 | if (uart_handle_break(port)) |
1da177e4 | 606 | return 0; |
762c69e3 PM |
607 | |
608 | dev_dbg(port->dev, "BREAK detected\n"); | |
609 | ||
e108b2ca | 610 | if (tty_insert_flip_char(tty, 0, TTY_BREAK)) |
e7c98dc7 MT |
611 | copied++; |
612 | } | |
613 | ||
e108b2ca | 614 | } else { |
1da177e4 | 615 | /* frame error */ |
e108b2ca | 616 | if (tty_insert_flip_char(tty, 0, TTY_FRAME)) |
33f0f88f | 617 | copied++; |
762c69e3 PM |
618 | |
619 | dev_notice(port->dev, "frame error\n"); | |
1da177e4 LT |
620 | } |
621 | } | |
622 | ||
e108b2ca | 623 | if (status & SCxSR_PER(port)) { |
1da177e4 | 624 | /* parity error */ |
e108b2ca PM |
625 | if (tty_insert_flip_char(tty, 0, TTY_PARITY)) |
626 | copied++; | |
762c69e3 PM |
627 | |
628 | dev_notice(port->dev, "parity error"); | |
1da177e4 LT |
629 | } |
630 | ||
33f0f88f | 631 | if (copied) |
1da177e4 | 632 | tty_flip_buffer_push(tty); |
1da177e4 LT |
633 | |
634 | return copied; | |
635 | } | |
636 | ||
94c8b6db | 637 | static int sci_handle_fifo_overrun(struct uart_port *port) |
d830fa45 | 638 | { |
ebd2c8f6 | 639 | struct tty_struct *tty = port->state->port.tty; |
d830fa45 PM |
640 | int copied = 0; |
641 | ||
642 | if (port->type != PORT_SCIF) | |
643 | return 0; | |
644 | ||
645 | if ((sci_in(port, SCLSR) & SCIF_ORER) != 0) { | |
646 | sci_out(port, SCLSR, 0); | |
647 | ||
648 | tty_insert_flip_char(tty, 0, TTY_OVERRUN); | |
649 | tty_flip_buffer_push(tty); | |
650 | ||
651 | dev_notice(port->dev, "overrun error\n"); | |
652 | copied++; | |
653 | } | |
654 | ||
655 | return copied; | |
656 | } | |
657 | ||
94c8b6db | 658 | static int sci_handle_breaks(struct uart_port *port) |
1da177e4 LT |
659 | { |
660 | int copied = 0; | |
661 | unsigned short status = sci_in(port, SCxSR); | |
ebd2c8f6 | 662 | struct tty_struct *tty = port->state->port.tty; |
a5660ada | 663 | struct sci_port *s = to_sci_port(port); |
1da177e4 | 664 | |
0b3d4ef6 PM |
665 | if (uart_handle_break(port)) |
666 | return 0; | |
667 | ||
b7a76e4b | 668 | if (!s->break_flag && status & SCxSR_BRK(port)) { |
1da177e4 LT |
669 | #if defined(CONFIG_CPU_SH3) |
670 | /* Debounce break */ | |
671 | s->break_flag = 1; | |
672 | #endif | |
673 | /* Notify of BREAK */ | |
e108b2ca | 674 | if (tty_insert_flip_char(tty, 0, TTY_BREAK)) |
33f0f88f | 675 | copied++; |
762c69e3 PM |
676 | |
677 | dev_dbg(port->dev, "BREAK detected\n"); | |
1da177e4 LT |
678 | } |
679 | ||
33f0f88f | 680 | if (copied) |
1da177e4 | 681 | tty_flip_buffer_push(tty); |
e108b2ca | 682 | |
d830fa45 PM |
683 | copied += sci_handle_fifo_overrun(port); |
684 | ||
1da177e4 LT |
685 | return copied; |
686 | } | |
687 | ||
73a19e4c | 688 | static irqreturn_t sci_rx_interrupt(int irq, void *ptr) |
1da177e4 | 689 | { |
73a19e4c GL |
690 | #ifdef CONFIG_SERIAL_SH_SCI_DMA |
691 | struct uart_port *port = ptr; | |
692 | struct sci_port *s = to_sci_port(port); | |
693 | ||
694 | if (s->chan_rx) { | |
73a19e4c GL |
695 | u16 scr = sci_in(port, SCSCR); |
696 | u16 ssr = sci_in(port, SCxSR); | |
697 | ||
698 | /* Disable future Rx interrupts */ | |
d1d4b10c | 699 | if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { |
3089f381 GL |
700 | disable_irq_nosync(irq); |
701 | scr |= 0x4000; | |
702 | } else { | |
f43dc23d | 703 | scr &= ~SCSCR_RIE; |
3089f381 GL |
704 | } |
705 | sci_out(port, SCSCR, scr); | |
73a19e4c GL |
706 | /* Clear current interrupt */ |
707 | sci_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port))); | |
3089f381 GL |
708 | dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n", |
709 | jiffies, s->rx_timeout); | |
710 | mod_timer(&s->rx_timer, jiffies + s->rx_timeout); | |
73a19e4c GL |
711 | |
712 | return IRQ_HANDLED; | |
713 | } | |
714 | #endif | |
715 | ||
1da177e4 LT |
716 | /* I think sci_receive_chars has to be called irrespective |
717 | * of whether the I_IXOFF is set, otherwise, how is the interrupt | |
718 | * to be disabled? | |
719 | */ | |
73a19e4c | 720 | sci_receive_chars(ptr); |
1da177e4 LT |
721 | |
722 | return IRQ_HANDLED; | |
723 | } | |
724 | ||
7d12e780 | 725 | static irqreturn_t sci_tx_interrupt(int irq, void *ptr) |
1da177e4 LT |
726 | { |
727 | struct uart_port *port = ptr; | |
fd78a76a | 728 | unsigned long flags; |
1da177e4 | 729 | |
fd78a76a | 730 | spin_lock_irqsave(&port->lock, flags); |
1da177e4 | 731 | sci_transmit_chars(port); |
fd78a76a | 732 | spin_unlock_irqrestore(&port->lock, flags); |
1da177e4 LT |
733 | |
734 | return IRQ_HANDLED; | |
735 | } | |
736 | ||
7d12e780 | 737 | static irqreturn_t sci_er_interrupt(int irq, void *ptr) |
1da177e4 LT |
738 | { |
739 | struct uart_port *port = ptr; | |
740 | ||
741 | /* Handle errors */ | |
742 | if (port->type == PORT_SCI) { | |
743 | if (sci_handle_errors(port)) { | |
744 | /* discard character in rx buffer */ | |
745 | sci_in(port, SCxSR); | |
746 | sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); | |
747 | } | |
748 | } else { | |
d830fa45 | 749 | sci_handle_fifo_overrun(port); |
7d12e780 | 750 | sci_rx_interrupt(irq, ptr); |
1da177e4 LT |
751 | } |
752 | ||
753 | sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); | |
754 | ||
755 | /* Kick the transmission */ | |
7d12e780 | 756 | sci_tx_interrupt(irq, ptr); |
1da177e4 LT |
757 | |
758 | return IRQ_HANDLED; | |
759 | } | |
760 | ||
7d12e780 | 761 | static irqreturn_t sci_br_interrupt(int irq, void *ptr) |
1da177e4 LT |
762 | { |
763 | struct uart_port *port = ptr; | |
764 | ||
765 | /* Handle BREAKs */ | |
766 | sci_handle_breaks(port); | |
767 | sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port)); | |
768 | ||
769 | return IRQ_HANDLED; | |
770 | } | |
771 | ||
f43dc23d PM |
772 | static inline unsigned long port_rx_irq_mask(struct uart_port *port) |
773 | { | |
774 | /* | |
775 | * Not all ports (such as SCIFA) will support REIE. Rather than | |
776 | * special-casing the port type, we check the port initialization | |
777 | * IRQ enable mask to see whether the IRQ is desired at all. If | |
778 | * it's unset, it's logically inferred that there's no point in | |
779 | * testing for it. | |
780 | */ | |
ce6738b6 | 781 | return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); |
f43dc23d PM |
782 | } |
783 | ||
7d12e780 | 784 | static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) |
1da177e4 | 785 | { |
44e18e9e | 786 | unsigned short ssr_status, scr_status, err_enabled; |
a8884e34 | 787 | struct uart_port *port = ptr; |
73a19e4c | 788 | struct sci_port *s = to_sci_port(port); |
a8884e34 | 789 | irqreturn_t ret = IRQ_NONE; |
1da177e4 | 790 | |
e7c98dc7 MT |
791 | ssr_status = sci_in(port, SCxSR); |
792 | scr_status = sci_in(port, SCSCR); | |
f43dc23d | 793 | err_enabled = scr_status & port_rx_irq_mask(port); |
1da177e4 LT |
794 | |
795 | /* Tx Interrupt */ | |
f43dc23d | 796 | if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) && |
73a19e4c | 797 | !s->chan_tx) |
a8884e34 | 798 | ret = sci_tx_interrupt(irq, ptr); |
f43dc23d | 799 | |
73a19e4c GL |
800 | /* |
801 | * Rx Interrupt: if we're using DMA, the DMA controller clears RDF / | |
802 | * DR flags | |
803 | */ | |
804 | if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && | |
f43dc23d | 805 | (scr_status & SCSCR_RIE)) |
a8884e34 | 806 | ret = sci_rx_interrupt(irq, ptr); |
f43dc23d | 807 | |
1da177e4 | 808 | /* Error Interrupt */ |
dd4da3a5 | 809 | if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled) |
a8884e34 | 810 | ret = sci_er_interrupt(irq, ptr); |
f43dc23d | 811 | |
1da177e4 | 812 | /* Break Interrupt */ |
dd4da3a5 | 813 | if ((ssr_status & SCxSR_BRK(port)) && err_enabled) |
a8884e34 | 814 | ret = sci_br_interrupt(irq, ptr); |
1da177e4 | 815 | |
a8884e34 | 816 | return ret; |
1da177e4 LT |
817 | } |
818 | ||
1da177e4 | 819 | /* |
25985edc | 820 | * Here we define a transition notifier so that we can update all of our |
1da177e4 LT |
821 | * ports' baud rate when the peripheral clock changes. |
822 | */ | |
e108b2ca PM |
823 | static int sci_notifier(struct notifier_block *self, |
824 | unsigned long phase, void *p) | |
1da177e4 | 825 | { |
e552de24 MD |
826 | struct sci_port *sci_port; |
827 | unsigned long flags; | |
1da177e4 | 828 | |
d535a230 PM |
829 | sci_port = container_of(self, struct sci_port, freq_transition); |
830 | ||
1da177e4 | 831 | if ((phase == CPUFREQ_POSTCHANGE) || |
e552de24 | 832 | (phase == CPUFREQ_RESUMECHANGE)) { |
d535a230 | 833 | struct uart_port *port = &sci_port->port; |
073e84c9 | 834 | |
d535a230 PM |
835 | spin_lock_irqsave(&port->lock, flags); |
836 | port->uartclk = clk_get_rate(sci_port->iclk); | |
837 | spin_unlock_irqrestore(&port->lock, flags); | |
e552de24 | 838 | } |
1da177e4 | 839 | |
1da177e4 LT |
840 | return NOTIFY_OK; |
841 | } | |
501b825d MD |
842 | |
843 | static void sci_clk_enable(struct uart_port *port) | |
844 | { | |
845 | struct sci_port *sci_port = to_sci_port(port); | |
846 | ||
5e50d2d6 MD |
847 | pm_runtime_get_sync(port->dev); |
848 | ||
c7ed1ab3 PM |
849 | clk_enable(sci_port->iclk); |
850 | sci_port->port.uartclk = clk_get_rate(sci_port->iclk); | |
851 | clk_enable(sci_port->fclk); | |
501b825d MD |
852 | } |
853 | ||
854 | static void sci_clk_disable(struct uart_port *port) | |
855 | { | |
856 | struct sci_port *sci_port = to_sci_port(port); | |
857 | ||
c7ed1ab3 PM |
858 | clk_disable(sci_port->fclk); |
859 | clk_disable(sci_port->iclk); | |
5e50d2d6 MD |
860 | |
861 | pm_runtime_put_sync(port->dev); | |
501b825d | 862 | } |
1da177e4 LT |
863 | |
864 | static int sci_request_irq(struct sci_port *port) | |
865 | { | |
866 | int i; | |
7d12e780 | 867 | irqreturn_t (*handlers[4])(int irq, void *ptr) = { |
1da177e4 LT |
868 | sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt, |
869 | sci_br_interrupt, | |
870 | }; | |
871 | const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full", | |
872 | "SCI Transmit Data Empty", "SCI Break" }; | |
873 | ||
ce6738b6 PM |
874 | if (port->cfg->irqs[0] == port->cfg->irqs[1]) { |
875 | if (unlikely(!port->cfg->irqs[0])) | |
1da177e4 | 876 | return -ENODEV; |
e108b2ca | 877 | |
ce6738b6 | 878 | if (request_irq(port->cfg->irqs[0], sci_mpxed_interrupt, |
35f3c518 | 879 | IRQF_DISABLED, "sci", port)) { |
762c69e3 | 880 | dev_err(port->port.dev, "Can't allocate IRQ\n"); |
1da177e4 LT |
881 | return -ENODEV; |
882 | } | |
883 | } else { | |
884 | for (i = 0; i < ARRAY_SIZE(handlers); i++) { | |
ce6738b6 | 885 | if (unlikely(!port->cfg->irqs[i])) |
1da177e4 | 886 | continue; |
762c69e3 | 887 | |
ce6738b6 | 888 | if (request_irq(port->cfg->irqs[i], handlers[i], |
35f3c518 | 889 | IRQF_DISABLED, desc[i], port)) { |
762c69e3 | 890 | dev_err(port->port.dev, "Can't allocate IRQ\n"); |
1da177e4 LT |
891 | return -ENODEV; |
892 | } | |
893 | } | |
894 | } | |
895 | ||
896 | return 0; | |
897 | } | |
898 | ||
899 | static void sci_free_irq(struct sci_port *port) | |
900 | { | |
901 | int i; | |
902 | ||
ce6738b6 PM |
903 | if (port->cfg->irqs[0] == port->cfg->irqs[1]) |
904 | free_irq(port->cfg->irqs[0], port); | |
762c69e3 | 905 | else { |
ce6738b6 PM |
906 | for (i = 0; i < ARRAY_SIZE(port->cfg->irqs); i++) { |
907 | if (!port->cfg->irqs[i]) | |
1da177e4 LT |
908 | continue; |
909 | ||
ce6738b6 | 910 | free_irq(port->cfg->irqs[i], port); |
1da177e4 LT |
911 | } |
912 | } | |
913 | } | |
914 | ||
915 | static unsigned int sci_tx_empty(struct uart_port *port) | |
916 | { | |
b1516803 | 917 | unsigned short status = sci_in(port, SCxSR); |
73a19e4c GL |
918 | unsigned short in_tx_fifo = scif_txfill(port); |
919 | ||
920 | return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; | |
1da177e4 LT |
921 | } |
922 | ||
923 | static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
924 | { | |
925 | /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */ | |
926 | /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */ | |
927 | /* If you have signals for DTR and DCD, please implement here. */ | |
928 | } | |
929 | ||
930 | static unsigned int sci_get_mctrl(struct uart_port *port) | |
931 | { | |
73a19e4c | 932 | /* This routine is used for getting signals of: DTR, DCD, DSR, RI, |
1da177e4 LT |
933 | and CTS/RTS */ |
934 | ||
935 | return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR; | |
936 | } | |
937 | ||
73a19e4c GL |
938 | #ifdef CONFIG_SERIAL_SH_SCI_DMA |
939 | static void sci_dma_tx_complete(void *arg) | |
940 | { | |
941 | struct sci_port *s = arg; | |
942 | struct uart_port *port = &s->port; | |
943 | struct circ_buf *xmit = &port->state->xmit; | |
944 | unsigned long flags; | |
945 | ||
946 | dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); | |
947 | ||
948 | spin_lock_irqsave(&port->lock, flags); | |
949 | ||
f354a381 | 950 | xmit->tail += sg_dma_len(&s->sg_tx); |
73a19e4c GL |
951 | xmit->tail &= UART_XMIT_SIZE - 1; |
952 | ||
f354a381 | 953 | port->icount.tx += sg_dma_len(&s->sg_tx); |
73a19e4c GL |
954 | |
955 | async_tx_ack(s->desc_tx); | |
956 | s->cookie_tx = -EINVAL; | |
957 | s->desc_tx = NULL; | |
958 | ||
73a19e4c GL |
959 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
960 | uart_write_wakeup(port); | |
961 | ||
3089f381 | 962 | if (!uart_circ_empty(xmit)) { |
73a19e4c | 963 | schedule_work(&s->work_tx); |
d1d4b10c | 964 | } else if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { |
3089f381 | 965 | u16 ctrl = sci_in(port, SCSCR); |
f43dc23d | 966 | sci_out(port, SCSCR, ctrl & ~SCSCR_TIE); |
3089f381 GL |
967 | } |
968 | ||
969 | spin_unlock_irqrestore(&port->lock, flags); | |
73a19e4c GL |
970 | } |
971 | ||
972 | /* Locking: called with port lock held */ | |
973 | static int sci_dma_rx_push(struct sci_port *s, struct tty_struct *tty, | |
974 | size_t count) | |
975 | { | |
976 | struct uart_port *port = &s->port; | |
977 | int i, active, room; | |
978 | ||
979 | room = tty_buffer_request_room(tty, count); | |
980 | ||
981 | if (s->active_rx == s->cookie_rx[0]) { | |
982 | active = 0; | |
983 | } else if (s->active_rx == s->cookie_rx[1]) { | |
984 | active = 1; | |
985 | } else { | |
986 | dev_err(port->dev, "cookie %d not found!\n", s->active_rx); | |
987 | return 0; | |
988 | } | |
989 | ||
990 | if (room < count) | |
991 | dev_warn(port->dev, "Rx overrun: dropping %u bytes\n", | |
992 | count - room); | |
993 | if (!room) | |
994 | return room; | |
995 | ||
996 | for (i = 0; i < room; i++) | |
997 | tty_insert_flip_char(tty, ((u8 *)sg_virt(&s->sg_rx[active]))[i], | |
998 | TTY_NORMAL); | |
999 | ||
1000 | port->icount.rx += room; | |
1001 | ||
1002 | return room; | |
1003 | } | |
1004 | ||
1005 | static void sci_dma_rx_complete(void *arg) | |
1006 | { | |
1007 | struct sci_port *s = arg; | |
1008 | struct uart_port *port = &s->port; | |
1009 | struct tty_struct *tty = port->state->port.tty; | |
1010 | unsigned long flags; | |
1011 | int count; | |
1012 | ||
3089f381 | 1013 | dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx); |
73a19e4c GL |
1014 | |
1015 | spin_lock_irqsave(&port->lock, flags); | |
1016 | ||
1017 | count = sci_dma_rx_push(s, tty, s->buf_len_rx); | |
1018 | ||
3089f381 | 1019 | mod_timer(&s->rx_timer, jiffies + s->rx_timeout); |
73a19e4c GL |
1020 | |
1021 | spin_unlock_irqrestore(&port->lock, flags); | |
1022 | ||
1023 | if (count) | |
1024 | tty_flip_buffer_push(tty); | |
1025 | ||
1026 | schedule_work(&s->work_rx); | |
1027 | } | |
1028 | ||
73a19e4c GL |
1029 | static void sci_rx_dma_release(struct sci_port *s, bool enable_pio) |
1030 | { | |
1031 | struct dma_chan *chan = s->chan_rx; | |
1032 | struct uart_port *port = &s->port; | |
73a19e4c GL |
1033 | |
1034 | s->chan_rx = NULL; | |
1035 | s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL; | |
1036 | dma_release_channel(chan); | |
85b8e3ff GL |
1037 | if (sg_dma_address(&s->sg_rx[0])) |
1038 | dma_free_coherent(port->dev, s->buf_len_rx * 2, | |
1039 | sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0])); | |
73a19e4c GL |
1040 | if (enable_pio) |
1041 | sci_start_rx(port); | |
1042 | } | |
1043 | ||
1044 | static void sci_tx_dma_release(struct sci_port *s, bool enable_pio) | |
1045 | { | |
1046 | struct dma_chan *chan = s->chan_tx; | |
1047 | struct uart_port *port = &s->port; | |
73a19e4c GL |
1048 | |
1049 | s->chan_tx = NULL; | |
1050 | s->cookie_tx = -EINVAL; | |
1051 | dma_release_channel(chan); | |
1052 | if (enable_pio) | |
1053 | sci_start_tx(port); | |
1054 | } | |
1055 | ||
1056 | static void sci_submit_rx(struct sci_port *s) | |
1057 | { | |
1058 | struct dma_chan *chan = s->chan_rx; | |
1059 | int i; | |
1060 | ||
1061 | for (i = 0; i < 2; i++) { | |
1062 | struct scatterlist *sg = &s->sg_rx[i]; | |
1063 | struct dma_async_tx_descriptor *desc; | |
1064 | ||
1065 | desc = chan->device->device_prep_slave_sg(chan, | |
1066 | sg, 1, DMA_FROM_DEVICE, DMA_PREP_INTERRUPT); | |
1067 | ||
1068 | if (desc) { | |
1069 | s->desc_rx[i] = desc; | |
1070 | desc->callback = sci_dma_rx_complete; | |
1071 | desc->callback_param = s; | |
1072 | s->cookie_rx[i] = desc->tx_submit(desc); | |
1073 | } | |
1074 | ||
1075 | if (!desc || s->cookie_rx[i] < 0) { | |
1076 | if (i) { | |
1077 | async_tx_ack(s->desc_rx[0]); | |
1078 | s->cookie_rx[0] = -EINVAL; | |
1079 | } | |
1080 | if (desc) { | |
1081 | async_tx_ack(desc); | |
1082 | s->cookie_rx[i] = -EINVAL; | |
1083 | } | |
1084 | dev_warn(s->port.dev, | |
1085 | "failed to re-start DMA, using PIO\n"); | |
1086 | sci_rx_dma_release(s, true); | |
1087 | return; | |
1088 | } | |
3089f381 GL |
1089 | dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__, |
1090 | s->cookie_rx[i], i); | |
73a19e4c GL |
1091 | } |
1092 | ||
1093 | s->active_rx = s->cookie_rx[0]; | |
1094 | ||
1095 | dma_async_issue_pending(chan); | |
1096 | } | |
1097 | ||
1098 | static void work_fn_rx(struct work_struct *work) | |
1099 | { | |
1100 | struct sci_port *s = container_of(work, struct sci_port, work_rx); | |
1101 | struct uart_port *port = &s->port; | |
1102 | struct dma_async_tx_descriptor *desc; | |
1103 | int new; | |
1104 | ||
1105 | if (s->active_rx == s->cookie_rx[0]) { | |
1106 | new = 0; | |
1107 | } else if (s->active_rx == s->cookie_rx[1]) { | |
1108 | new = 1; | |
1109 | } else { | |
1110 | dev_err(port->dev, "cookie %d not found!\n", s->active_rx); | |
1111 | return; | |
1112 | } | |
1113 | desc = s->desc_rx[new]; | |
1114 | ||
1115 | if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) != | |
1116 | DMA_SUCCESS) { | |
1117 | /* Handle incomplete DMA receive */ | |
1118 | struct tty_struct *tty = port->state->port.tty; | |
1119 | struct dma_chan *chan = s->chan_rx; | |
1120 | struct sh_desc *sh_desc = container_of(desc, struct sh_desc, | |
1121 | async_tx); | |
1122 | unsigned long flags; | |
1123 | int count; | |
1124 | ||
05827630 | 1125 | chan->device->device_control(chan, DMA_TERMINATE_ALL, 0); |
73a19e4c GL |
1126 | dev_dbg(port->dev, "Read %u bytes with cookie %d\n", |
1127 | sh_desc->partial, sh_desc->cookie); | |
1128 | ||
1129 | spin_lock_irqsave(&port->lock, flags); | |
1130 | count = sci_dma_rx_push(s, tty, sh_desc->partial); | |
1131 | spin_unlock_irqrestore(&port->lock, flags); | |
1132 | ||
1133 | if (count) | |
1134 | tty_flip_buffer_push(tty); | |
1135 | ||
1136 | sci_submit_rx(s); | |
1137 | ||
1138 | return; | |
1139 | } | |
1140 | ||
1141 | s->cookie_rx[new] = desc->tx_submit(desc); | |
1142 | if (s->cookie_rx[new] < 0) { | |
1143 | dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); | |
1144 | sci_rx_dma_release(s, true); | |
1145 | return; | |
1146 | } | |
1147 | ||
73a19e4c | 1148 | s->active_rx = s->cookie_rx[!new]; |
3089f381 GL |
1149 | |
1150 | dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__, | |
1151 | s->cookie_rx[new], new, s->active_rx); | |
73a19e4c GL |
1152 | } |
1153 | ||
1154 | static void work_fn_tx(struct work_struct *work) | |
1155 | { | |
1156 | struct sci_port *s = container_of(work, struct sci_port, work_tx); | |
1157 | struct dma_async_tx_descriptor *desc; | |
1158 | struct dma_chan *chan = s->chan_tx; | |
1159 | struct uart_port *port = &s->port; | |
1160 | struct circ_buf *xmit = &port->state->xmit; | |
1161 | struct scatterlist *sg = &s->sg_tx; | |
1162 | ||
1163 | /* | |
1164 | * DMA is idle now. | |
1165 | * Port xmit buffer is already mapped, and it is one page... Just adjust | |
1166 | * offsets and lengths. Since it is a circular buffer, we have to | |
1167 | * transmit till the end, and then the rest. Take the port lock to get a | |
1168 | * consistent xmit buffer state. | |
1169 | */ | |
1170 | spin_lock_irq(&port->lock); | |
1171 | sg->offset = xmit->tail & (UART_XMIT_SIZE - 1); | |
f354a381 | 1172 | sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) + |
73a19e4c | 1173 | sg->offset; |
f354a381 | 1174 | sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE), |
73a19e4c | 1175 | CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE)); |
73a19e4c GL |
1176 | spin_unlock_irq(&port->lock); |
1177 | ||
f354a381 | 1178 | BUG_ON(!sg_dma_len(sg)); |
73a19e4c GL |
1179 | |
1180 | desc = chan->device->device_prep_slave_sg(chan, | |
1181 | sg, s->sg_len_tx, DMA_TO_DEVICE, | |
1182 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
1183 | if (!desc) { | |
1184 | /* switch to PIO */ | |
1185 | sci_tx_dma_release(s, true); | |
1186 | return; | |
1187 | } | |
1188 | ||
1189 | dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE); | |
1190 | ||
1191 | spin_lock_irq(&port->lock); | |
1192 | s->desc_tx = desc; | |
1193 | desc->callback = sci_dma_tx_complete; | |
1194 | desc->callback_param = s; | |
1195 | spin_unlock_irq(&port->lock); | |
1196 | s->cookie_tx = desc->tx_submit(desc); | |
1197 | if (s->cookie_tx < 0) { | |
1198 | dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); | |
1199 | /* switch to PIO */ | |
1200 | sci_tx_dma_release(s, true); | |
1201 | return; | |
1202 | } | |
1203 | ||
1204 | dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__, | |
1205 | xmit->buf, xmit->tail, xmit->head, s->cookie_tx); | |
1206 | ||
1207 | dma_async_issue_pending(chan); | |
1208 | } | |
1209 | #endif | |
1210 | ||
b129a8cc | 1211 | static void sci_start_tx(struct uart_port *port) |
1da177e4 | 1212 | { |
3089f381 | 1213 | struct sci_port *s = to_sci_port(port); |
e108b2ca | 1214 | unsigned short ctrl; |
1da177e4 | 1215 | |
73a19e4c | 1216 | #ifdef CONFIG_SERIAL_SH_SCI_DMA |
d1d4b10c | 1217 | if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { |
3089f381 GL |
1218 | u16 new, scr = sci_in(port, SCSCR); |
1219 | if (s->chan_tx) | |
1220 | new = scr | 0x8000; | |
1221 | else | |
1222 | new = scr & ~0x8000; | |
1223 | if (new != scr) | |
1224 | sci_out(port, SCSCR, new); | |
73a19e4c | 1225 | } |
f43dc23d | 1226 | |
3089f381 GL |
1227 | if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) && |
1228 | s->cookie_tx < 0) | |
1229 | schedule_work(&s->work_tx); | |
73a19e4c | 1230 | #endif |
f43dc23d | 1231 | |
d1d4b10c | 1232 | if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) { |
3089f381 GL |
1233 | /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ |
1234 | ctrl = sci_in(port, SCSCR); | |
f43dc23d | 1235 | sci_out(port, SCSCR, ctrl | SCSCR_TIE); |
3089f381 | 1236 | } |
1da177e4 LT |
1237 | } |
1238 | ||
b129a8cc | 1239 | static void sci_stop_tx(struct uart_port *port) |
1da177e4 | 1240 | { |
1da177e4 LT |
1241 | unsigned short ctrl; |
1242 | ||
1243 | /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ | |
1da177e4 | 1244 | ctrl = sci_in(port, SCSCR); |
f43dc23d | 1245 | |
d1d4b10c | 1246 | if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) |
3089f381 | 1247 | ctrl &= ~0x8000; |
f43dc23d | 1248 | |
8e698614 | 1249 | ctrl &= ~SCSCR_TIE; |
f43dc23d | 1250 | |
1da177e4 | 1251 | sci_out(port, SCSCR, ctrl); |
1da177e4 LT |
1252 | } |
1253 | ||
73a19e4c | 1254 | static void sci_start_rx(struct uart_port *port) |
1da177e4 | 1255 | { |
1da177e4 LT |
1256 | unsigned short ctrl; |
1257 | ||
f43dc23d | 1258 | ctrl = sci_in(port, SCSCR) | port_rx_irq_mask(port); |
1da177e4 | 1259 | |
d1d4b10c | 1260 | if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) |
3089f381 | 1261 | ctrl &= ~0x4000; |
f43dc23d | 1262 | |
1da177e4 | 1263 | sci_out(port, SCSCR, ctrl); |
1da177e4 LT |
1264 | } |
1265 | ||
1266 | static void sci_stop_rx(struct uart_port *port) | |
1267 | { | |
1da177e4 LT |
1268 | unsigned short ctrl; |
1269 | ||
1da177e4 | 1270 | ctrl = sci_in(port, SCSCR); |
f43dc23d | 1271 | |
d1d4b10c | 1272 | if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) |
3089f381 | 1273 | ctrl &= ~0x4000; |
f43dc23d PM |
1274 | |
1275 | ctrl &= ~port_rx_irq_mask(port); | |
1276 | ||
1da177e4 | 1277 | sci_out(port, SCSCR, ctrl); |
1da177e4 LT |
1278 | } |
1279 | ||
1280 | static void sci_enable_ms(struct uart_port *port) | |
1281 | { | |
1282 | /* Nothing here yet .. */ | |
1283 | } | |
1284 | ||
1285 | static void sci_break_ctl(struct uart_port *port, int break_state) | |
1286 | { | |
1287 | /* Nothing here yet .. */ | |
1288 | } | |
1289 | ||
73a19e4c GL |
1290 | #ifdef CONFIG_SERIAL_SH_SCI_DMA |
1291 | static bool filter(struct dma_chan *chan, void *slave) | |
1292 | { | |
1293 | struct sh_dmae_slave *param = slave; | |
1294 | ||
1295 | dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__, | |
1296 | param->slave_id); | |
1297 | ||
1298 | if (param->dma_dev == chan->device->dev) { | |
1299 | chan->private = param; | |
1300 | return true; | |
1301 | } else { | |
1302 | return false; | |
1303 | } | |
1304 | } | |
1305 | ||
1306 | static void rx_timer_fn(unsigned long arg) | |
1307 | { | |
1308 | struct sci_port *s = (struct sci_port *)arg; | |
1309 | struct uart_port *port = &s->port; | |
73a19e4c | 1310 | u16 scr = sci_in(port, SCSCR); |
3089f381 | 1311 | |
d1d4b10c | 1312 | if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { |
3089f381 | 1313 | scr &= ~0x4000; |
ce6738b6 | 1314 | enable_irq(s->cfg->irqs[1]); |
3089f381 | 1315 | } |
f43dc23d | 1316 | sci_out(port, SCSCR, scr | SCSCR_RIE); |
73a19e4c GL |
1317 | dev_dbg(port->dev, "DMA Rx timed out\n"); |
1318 | schedule_work(&s->work_rx); | |
1319 | } | |
1320 | ||
1321 | static void sci_request_dma(struct uart_port *port) | |
1322 | { | |
1323 | struct sci_port *s = to_sci_port(port); | |
1324 | struct sh_dmae_slave *param; | |
1325 | struct dma_chan *chan; | |
1326 | dma_cap_mask_t mask; | |
1327 | int nent; | |
1328 | ||
1329 | dev_dbg(port->dev, "%s: port %d DMA %p\n", __func__, | |
ce6738b6 | 1330 | port->line, s->cfg->dma_dev); |
73a19e4c | 1331 | |
ce6738b6 | 1332 | if (!s->cfg->dma_dev) |
73a19e4c GL |
1333 | return; |
1334 | ||
1335 | dma_cap_zero(mask); | |
1336 | dma_cap_set(DMA_SLAVE, mask); | |
1337 | ||
1338 | param = &s->param_tx; | |
1339 | ||
1340 | /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */ | |
ce6738b6 PM |
1341 | param->slave_id = s->cfg->dma_slave_tx; |
1342 | param->dma_dev = s->cfg->dma_dev; | |
73a19e4c GL |
1343 | |
1344 | s->cookie_tx = -EINVAL; | |
1345 | chan = dma_request_channel(mask, filter, param); | |
1346 | dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); | |
1347 | if (chan) { | |
1348 | s->chan_tx = chan; | |
1349 | sg_init_table(&s->sg_tx, 1); | |
1350 | /* UART circular tx buffer is an aligned page. */ | |
1351 | BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK); | |
1352 | sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf), | |
1353 | UART_XMIT_SIZE, (int)port->state->xmit.buf & ~PAGE_MASK); | |
1354 | nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE); | |
1355 | if (!nent) | |
1356 | sci_tx_dma_release(s, false); | |
1357 | else | |
1358 | dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__, | |
1359 | sg_dma_len(&s->sg_tx), | |
1360 | port->state->xmit.buf, sg_dma_address(&s->sg_tx)); | |
1361 | ||
1362 | s->sg_len_tx = nent; | |
1363 | ||
1364 | INIT_WORK(&s->work_tx, work_fn_tx); | |
1365 | } | |
1366 | ||
1367 | param = &s->param_rx; | |
1368 | ||
1369 | /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */ | |
ce6738b6 PM |
1370 | param->slave_id = s->cfg->dma_slave_rx; |
1371 | param->dma_dev = s->cfg->dma_dev; | |
73a19e4c GL |
1372 | |
1373 | chan = dma_request_channel(mask, filter, param); | |
1374 | dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); | |
1375 | if (chan) { | |
1376 | dma_addr_t dma[2]; | |
1377 | void *buf[2]; | |
1378 | int i; | |
1379 | ||
1380 | s->chan_rx = chan; | |
1381 | ||
1382 | s->buf_len_rx = 2 * max(16, (int)port->fifosize); | |
1383 | buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2, | |
1384 | &dma[0], GFP_KERNEL); | |
1385 | ||
1386 | if (!buf[0]) { | |
1387 | dev_warn(port->dev, | |
1388 | "failed to allocate dma buffer, using PIO\n"); | |
1389 | sci_rx_dma_release(s, true); | |
1390 | return; | |
1391 | } | |
1392 | ||
1393 | buf[1] = buf[0] + s->buf_len_rx; | |
1394 | dma[1] = dma[0] + s->buf_len_rx; | |
1395 | ||
1396 | for (i = 0; i < 2; i++) { | |
1397 | struct scatterlist *sg = &s->sg_rx[i]; | |
1398 | ||
1399 | sg_init_table(sg, 1); | |
1400 | sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx, | |
1401 | (int)buf[i] & ~PAGE_MASK); | |
f354a381 | 1402 | sg_dma_address(sg) = dma[i]; |
73a19e4c GL |
1403 | } |
1404 | ||
1405 | INIT_WORK(&s->work_rx, work_fn_rx); | |
1406 | setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s); | |
1407 | ||
1408 | sci_submit_rx(s); | |
1409 | } | |
1410 | } | |
1411 | ||
1412 | static void sci_free_dma(struct uart_port *port) | |
1413 | { | |
1414 | struct sci_port *s = to_sci_port(port); | |
1415 | ||
ce6738b6 | 1416 | if (!s->cfg->dma_dev) |
73a19e4c GL |
1417 | return; |
1418 | ||
1419 | if (s->chan_tx) | |
1420 | sci_tx_dma_release(s, false); | |
1421 | if (s->chan_rx) | |
1422 | sci_rx_dma_release(s, false); | |
1423 | } | |
27bd1075 PM |
1424 | #else |
1425 | static inline void sci_request_dma(struct uart_port *port) | |
1426 | { | |
1427 | } | |
1428 | ||
1429 | static inline void sci_free_dma(struct uart_port *port) | |
1430 | { | |
1431 | } | |
73a19e4c GL |
1432 | #endif |
1433 | ||
1da177e4 LT |
1434 | static int sci_startup(struct uart_port *port) |
1435 | { | |
a5660ada | 1436 | struct sci_port *s = to_sci_port(port); |
073e84c9 | 1437 | int ret; |
1da177e4 | 1438 | |
73a19e4c GL |
1439 | dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); |
1440 | ||
e108b2ca PM |
1441 | if (s->enable) |
1442 | s->enable(port); | |
1da177e4 | 1443 | |
073e84c9 PM |
1444 | ret = sci_request_irq(s); |
1445 | if (unlikely(ret < 0)) | |
1446 | return ret; | |
1447 | ||
73a19e4c | 1448 | sci_request_dma(port); |
073e84c9 | 1449 | |
d656901b | 1450 | sci_start_tx(port); |
73a19e4c | 1451 | sci_start_rx(port); |
1da177e4 LT |
1452 | |
1453 | return 0; | |
1454 | } | |
1455 | ||
1456 | static void sci_shutdown(struct uart_port *port) | |
1457 | { | |
a5660ada | 1458 | struct sci_port *s = to_sci_port(port); |
1da177e4 | 1459 | |
73a19e4c GL |
1460 | dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); |
1461 | ||
1da177e4 | 1462 | sci_stop_rx(port); |
b129a8cc | 1463 | sci_stop_tx(port); |
073e84c9 | 1464 | |
73a19e4c | 1465 | sci_free_dma(port); |
1da177e4 LT |
1466 | sci_free_irq(s); |
1467 | ||
e108b2ca PM |
1468 | if (s->disable) |
1469 | s->disable(port); | |
1da177e4 LT |
1470 | } |
1471 | ||
26c92f37 PM |
1472 | static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps, |
1473 | unsigned long freq) | |
1474 | { | |
1475 | switch (algo_id) { | |
1476 | case SCBRR_ALGO_1: | |
1477 | return ((freq + 16 * bps) / (16 * bps) - 1); | |
1478 | case SCBRR_ALGO_2: | |
1479 | return ((freq + 16 * bps) / (32 * bps) - 1); | |
1480 | case SCBRR_ALGO_3: | |
1481 | return (((freq * 2) + 16 * bps) / (16 * bps) - 1); | |
1482 | case SCBRR_ALGO_4: | |
1483 | return (((freq * 2) + 16 * bps) / (32 * bps) - 1); | |
1484 | case SCBRR_ALGO_5: | |
1485 | return (((freq * 1000 / 32) / bps) - 1); | |
1486 | } | |
1487 | ||
1488 | /* Warn, but use a safe default */ | |
1489 | WARN_ON(1); | |
e8183a6c | 1490 | |
26c92f37 PM |
1491 | return ((freq + 16 * bps) / (32 * bps) - 1); |
1492 | } | |
1493 | ||
606d099c AC |
1494 | static void sci_set_termios(struct uart_port *port, struct ktermios *termios, |
1495 | struct ktermios *old) | |
1da177e4 | 1496 | { |
00b9de9c | 1497 | struct sci_port *s = to_sci_port(port); |
154280fd | 1498 | unsigned int status, baud, smr_val, max_baud; |
a2159b52 | 1499 | int t = -1; |
3089f381 | 1500 | u16 scfcr = 0; |
1da177e4 | 1501 | |
154280fd MD |
1502 | /* |
1503 | * earlyprintk comes here early on with port->uartclk set to zero. | |
1504 | * the clock framework is not up and running at this point so here | |
1505 | * we assume that 115200 is the maximum baud rate. please note that | |
1506 | * the baud rate is not programmed during earlyprintk - it is assumed | |
1507 | * that the previous boot loader has enabled required clocks and | |
1508 | * setup the baud rate generator hardware for us already. | |
1509 | */ | |
1510 | max_baud = port->uartclk ? port->uartclk / 16 : 115200; | |
1da177e4 | 1511 | |
154280fd MD |
1512 | baud = uart_get_baud_rate(port, termios, old, 0, max_baud); |
1513 | if (likely(baud && port->uartclk)) | |
ce6738b6 | 1514 | t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud, port->uartclk); |
e108b2ca | 1515 | |
36003386 AC |
1516 | if (s->enable) |
1517 | s->enable(port); | |
1518 | ||
1da177e4 LT |
1519 | do { |
1520 | status = sci_in(port, SCxSR); | |
1521 | } while (!(status & SCxSR_TEND(port))); | |
1522 | ||
1523 | sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */ | |
1524 | ||
1a22f08d | 1525 | if (port->type != PORT_SCI) |
3089f381 | 1526 | sci_out(port, SCFCR, scfcr | SCFCR_RFRST | SCFCR_TFRST); |
1da177e4 LT |
1527 | |
1528 | smr_val = sci_in(port, SCSMR) & 3; | |
e8183a6c | 1529 | |
1da177e4 LT |
1530 | if ((termios->c_cflag & CSIZE) == CS7) |
1531 | smr_val |= 0x40; | |
1532 | if (termios->c_cflag & PARENB) | |
1533 | smr_val |= 0x20; | |
1534 | if (termios->c_cflag & PARODD) | |
1535 | smr_val |= 0x30; | |
1536 | if (termios->c_cflag & CSTOPB) | |
1537 | smr_val |= 0x08; | |
1538 | ||
1539 | uart_update_timeout(port, termios->c_cflag, baud); | |
1540 | ||
1541 | sci_out(port, SCSMR, smr_val); | |
1542 | ||
73a19e4c | 1543 | dev_dbg(port->dev, "%s: SMR %x, t %x, SCSCR %x\n", __func__, smr_val, t, |
ce6738b6 | 1544 | s->cfg->scscr); |
73a19e4c | 1545 | |
1da177e4 | 1546 | if (t > 0) { |
e7c98dc7 | 1547 | if (t >= 256) { |
1da177e4 LT |
1548 | sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1); |
1549 | t >>= 2; | |
e7c98dc7 | 1550 | } else |
1da177e4 | 1551 | sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3); |
e7c98dc7 | 1552 | |
1da177e4 LT |
1553 | sci_out(port, SCBRR, t); |
1554 | udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */ | |
1555 | } | |
1556 | ||
d5701647 | 1557 | sci_init_pins(port, termios->c_cflag); |
3089f381 | 1558 | sci_out(port, SCFCR, scfcr | ((termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0)); |
b7a76e4b | 1559 | |
ce6738b6 | 1560 | sci_out(port, SCSCR, s->cfg->scscr); |
1da177e4 | 1561 | |
3089f381 GL |
1562 | #ifdef CONFIG_SERIAL_SH_SCI_DMA |
1563 | /* | |
1564 | * Calculate delay for 1.5 DMA buffers: see | |
1565 | * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits | |
1566 | * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function | |
1567 | * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)." | |
1568 | * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO | |
1569 | * sizes), but it has been found out experimentally, that this is not | |
1570 | * enough: the driver too often needlessly runs on a DMA timeout. 20ms | |
1571 | * as a minimum seem to work perfectly. | |
1572 | */ | |
1573 | if (s->chan_rx) { | |
1574 | s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 / | |
1575 | port->fifosize / 2; | |
1576 | dev_dbg(port->dev, | |
1577 | "DMA Rx t-out %ums, tty t-out %u jiffies\n", | |
1578 | s->rx_timeout * 1000 / HZ, port->timeout); | |
1579 | if (s->rx_timeout < msecs_to_jiffies(20)) | |
1580 | s->rx_timeout = msecs_to_jiffies(20); | |
1581 | } | |
1582 | #endif | |
1583 | ||
1da177e4 | 1584 | if ((termios->c_cflag & CREAD) != 0) |
73a19e4c | 1585 | sci_start_rx(port); |
36003386 AC |
1586 | |
1587 | if (s->disable) | |
1588 | s->disable(port); | |
1da177e4 LT |
1589 | } |
1590 | ||
1591 | static const char *sci_type(struct uart_port *port) | |
1592 | { | |
1593 | switch (port->type) { | |
e7c98dc7 MT |
1594 | case PORT_IRDA: |
1595 | return "irda"; | |
1596 | case PORT_SCI: | |
1597 | return "sci"; | |
1598 | case PORT_SCIF: | |
1599 | return "scif"; | |
1600 | case PORT_SCIFA: | |
1601 | return "scifa"; | |
d1d4b10c GL |
1602 | case PORT_SCIFB: |
1603 | return "scifb"; | |
1da177e4 LT |
1604 | } |
1605 | ||
fa43972f | 1606 | return NULL; |
1da177e4 LT |
1607 | } |
1608 | ||
e2651647 | 1609 | static inline unsigned long sci_port_size(struct uart_port *port) |
1da177e4 | 1610 | { |
e2651647 PM |
1611 | /* |
1612 | * Pick an arbitrary size that encapsulates all of the base | |
1613 | * registers by default. This can be optimized later, or derived | |
1614 | * from platform resource data at such a time that ports begin to | |
1615 | * behave more erratically. | |
1616 | */ | |
1617 | return 64; | |
1da177e4 LT |
1618 | } |
1619 | ||
f6e9495d PM |
1620 | static int sci_remap_port(struct uart_port *port) |
1621 | { | |
1622 | unsigned long size = sci_port_size(port); | |
1623 | ||
1624 | /* | |
1625 | * Nothing to do if there's already an established membase. | |
1626 | */ | |
1627 | if (port->membase) | |
1628 | return 0; | |
1629 | ||
1630 | if (port->flags & UPF_IOREMAP) { | |
1631 | port->membase = ioremap_nocache(port->mapbase, size); | |
1632 | if (unlikely(!port->membase)) { | |
1633 | dev_err(port->dev, "can't remap port#%d\n", port->line); | |
1634 | return -ENXIO; | |
1635 | } | |
1636 | } else { | |
1637 | /* | |
1638 | * For the simple (and majority of) cases where we don't | |
1639 | * need to do any remapping, just cast the cookie | |
1640 | * directly. | |
1641 | */ | |
1642 | port->membase = (void __iomem *)port->mapbase; | |
1643 | } | |
1644 | ||
1645 | return 0; | |
1646 | } | |
1647 | ||
e2651647 | 1648 | static void sci_release_port(struct uart_port *port) |
1da177e4 | 1649 | { |
e2651647 PM |
1650 | if (port->flags & UPF_IOREMAP) { |
1651 | iounmap(port->membase); | |
1652 | port->membase = NULL; | |
1653 | } | |
1654 | ||
1655 | release_mem_region(port->mapbase, sci_port_size(port)); | |
1da177e4 LT |
1656 | } |
1657 | ||
e2651647 | 1658 | static int sci_request_port(struct uart_port *port) |
1da177e4 | 1659 | { |
e2651647 PM |
1660 | unsigned long size = sci_port_size(port); |
1661 | struct resource *res; | |
f6e9495d | 1662 | int ret; |
1da177e4 | 1663 | |
1020520e | 1664 | res = request_mem_region(port->mapbase, size, dev_name(port->dev)); |
e2651647 PM |
1665 | if (unlikely(res == NULL)) |
1666 | return -EBUSY; | |
1da177e4 | 1667 | |
f6e9495d PM |
1668 | ret = sci_remap_port(port); |
1669 | if (unlikely(ret != 0)) { | |
1670 | release_resource(res); | |
1671 | return ret; | |
7ff731ae | 1672 | } |
e2651647 PM |
1673 | |
1674 | return 0; | |
1675 | } | |
1676 | ||
1677 | static void sci_config_port(struct uart_port *port, int flags) | |
1678 | { | |
1679 | if (flags & UART_CONFIG_TYPE) { | |
1680 | struct sci_port *sport = to_sci_port(port); | |
1681 | ||
1682 | port->type = sport->cfg->type; | |
1683 | sci_request_port(port); | |
1684 | } | |
1da177e4 LT |
1685 | } |
1686 | ||
1687 | static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) | |
1688 | { | |
a5660ada | 1689 | struct sci_port *s = to_sci_port(port); |
1da177e4 | 1690 | |
ce6738b6 | 1691 | if (ser->irq != s->cfg->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs) |
1da177e4 LT |
1692 | return -EINVAL; |
1693 | if (ser->baud_base < 2400) | |
1694 | /* No paper tape reader for Mitch.. */ | |
1695 | return -EINVAL; | |
1696 | ||
1697 | return 0; | |
1698 | } | |
1699 | ||
1700 | static struct uart_ops sci_uart_ops = { | |
1701 | .tx_empty = sci_tx_empty, | |
1702 | .set_mctrl = sci_set_mctrl, | |
1703 | .get_mctrl = sci_get_mctrl, | |
1704 | .start_tx = sci_start_tx, | |
1705 | .stop_tx = sci_stop_tx, | |
1706 | .stop_rx = sci_stop_rx, | |
1707 | .enable_ms = sci_enable_ms, | |
1708 | .break_ctl = sci_break_ctl, | |
1709 | .startup = sci_startup, | |
1710 | .shutdown = sci_shutdown, | |
1711 | .set_termios = sci_set_termios, | |
1712 | .type = sci_type, | |
1713 | .release_port = sci_release_port, | |
1714 | .request_port = sci_request_port, | |
1715 | .config_port = sci_config_port, | |
1716 | .verify_port = sci_verify_port, | |
07d2a1a1 PM |
1717 | #ifdef CONFIG_CONSOLE_POLL |
1718 | .poll_get_char = sci_poll_get_char, | |
1719 | .poll_put_char = sci_poll_put_char, | |
1720 | #endif | |
1da177e4 LT |
1721 | }; |
1722 | ||
c7ed1ab3 PM |
1723 | static int __devinit sci_init_single(struct platform_device *dev, |
1724 | struct sci_port *sci_port, | |
1725 | unsigned int index, | |
1726 | struct plat_sci_port *p) | |
e108b2ca | 1727 | { |
73a19e4c | 1728 | struct uart_port *port = &sci_port->port; |
e108b2ca | 1729 | |
73a19e4c GL |
1730 | port->ops = &sci_uart_ops; |
1731 | port->iotype = UPIO_MEM; | |
1732 | port->line = index; | |
75136d48 MP |
1733 | |
1734 | switch (p->type) { | |
d1d4b10c GL |
1735 | case PORT_SCIFB: |
1736 | port->fifosize = 256; | |
1737 | break; | |
75136d48 | 1738 | case PORT_SCIFA: |
73a19e4c | 1739 | port->fifosize = 64; |
75136d48 MP |
1740 | break; |
1741 | case PORT_SCIF: | |
73a19e4c | 1742 | port->fifosize = 16; |
75136d48 MP |
1743 | break; |
1744 | default: | |
73a19e4c | 1745 | port->fifosize = 1; |
75136d48 MP |
1746 | break; |
1747 | } | |
7b6fd3bf MD |
1748 | |
1749 | if (dev) { | |
c7ed1ab3 PM |
1750 | sci_port->iclk = clk_get(&dev->dev, "sci_ick"); |
1751 | if (IS_ERR(sci_port->iclk)) { | |
1752 | sci_port->iclk = clk_get(&dev->dev, "peripheral_clk"); | |
1753 | if (IS_ERR(sci_port->iclk)) { | |
1754 | dev_err(&dev->dev, "can't get iclk\n"); | |
1755 | return PTR_ERR(sci_port->iclk); | |
1756 | } | |
1757 | } | |
1758 | ||
1759 | /* | |
1760 | * The function clock is optional, ignore it if we can't | |
1761 | * find it. | |
1762 | */ | |
1763 | sci_port->fclk = clk_get(&dev->dev, "sci_fck"); | |
1764 | if (IS_ERR(sci_port->fclk)) | |
1765 | sci_port->fclk = NULL; | |
1766 | ||
7b6fd3bf MD |
1767 | sci_port->enable = sci_clk_enable; |
1768 | sci_port->disable = sci_clk_disable; | |
73a19e4c | 1769 | port->dev = &dev->dev; |
5e50d2d6 MD |
1770 | |
1771 | pm_runtime_enable(&dev->dev); | |
7b6fd3bf | 1772 | } |
e108b2ca | 1773 | |
7ed7e071 MD |
1774 | sci_port->break_timer.data = (unsigned long)sci_port; |
1775 | sci_port->break_timer.function = sci_break_timer; | |
1776 | init_timer(&sci_port->break_timer); | |
1777 | ||
ce6738b6 | 1778 | sci_port->cfg = p; |
7ed7e071 | 1779 | |
ce6738b6 PM |
1780 | port->mapbase = p->mapbase; |
1781 | port->type = p->type; | |
f43dc23d | 1782 | port->flags = p->flags; |
73a19e4c | 1783 | |
ce6738b6 PM |
1784 | /* |
1785 | * The UART port needs an IRQ value, so we peg this to the TX IRQ | |
1786 | * for the multi-IRQ ports, which is where we are primarily | |
1787 | * concerned with the shutdown path synchronization. | |
1788 | * | |
1789 | * For the muxed case there's nothing more to do. | |
1790 | */ | |
54aa89ea | 1791 | port->irq = p->irqs[SCIx_RXI_IRQ]; |
73a19e4c | 1792 | |
ce6738b6 PM |
1793 | if (p->dma_dev) |
1794 | dev_dbg(port->dev, "DMA device %p, tx %d, rx %d\n", | |
1795 | p->dma_dev, p->dma_slave_tx, p->dma_slave_rx); | |
7ed7e071 | 1796 | |
c7ed1ab3 | 1797 | return 0; |
e108b2ca PM |
1798 | } |
1799 | ||
1da177e4 | 1800 | #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE |
dc8e6f5b MD |
1801 | static void serial_console_putchar(struct uart_port *port, int ch) |
1802 | { | |
1803 | sci_poll_put_char(port, ch); | |
1804 | } | |
1805 | ||
1da177e4 LT |
1806 | /* |
1807 | * Print a string to the serial port trying not to disturb | |
1808 | * any possible real use of the port... | |
1809 | */ | |
1810 | static void serial_console_write(struct console *co, const char *s, | |
1811 | unsigned count) | |
1812 | { | |
906b17dc PM |
1813 | struct sci_port *sci_port = &sci_ports[co->index]; |
1814 | struct uart_port *port = &sci_port->port; | |
973e5d52 | 1815 | unsigned short bits; |
07d2a1a1 | 1816 | |
501b825d MD |
1817 | if (sci_port->enable) |
1818 | sci_port->enable(port); | |
1819 | ||
1820 | uart_console_write(port, s, count, serial_console_putchar); | |
973e5d52 MD |
1821 | |
1822 | /* wait until fifo is empty and last bit has been transmitted */ | |
1823 | bits = SCxSR_TDxE(port) | SCxSR_TEND(port); | |
1824 | while ((sci_in(port, SCxSR) & bits) != bits) | |
1825 | cpu_relax(); | |
501b825d | 1826 | |
345e5a76 | 1827 | if (sci_port->disable) |
501b825d | 1828 | sci_port->disable(port); |
1da177e4 LT |
1829 | } |
1830 | ||
7b6fd3bf | 1831 | static int __devinit serial_console_setup(struct console *co, char *options) |
1da177e4 | 1832 | { |
dc8e6f5b | 1833 | struct sci_port *sci_port; |
1da177e4 LT |
1834 | struct uart_port *port; |
1835 | int baud = 115200; | |
1836 | int bits = 8; | |
1837 | int parity = 'n'; | |
1838 | int flow = 'n'; | |
1839 | int ret; | |
1840 | ||
e108b2ca | 1841 | /* |
906b17dc | 1842 | * Refuse to handle any bogus ports. |
1da177e4 | 1843 | */ |
906b17dc | 1844 | if (co->index < 0 || co->index >= SCI_NPORTS) |
e108b2ca | 1845 | return -ENODEV; |
e108b2ca | 1846 | |
906b17dc PM |
1847 | sci_port = &sci_ports[co->index]; |
1848 | port = &sci_port->port; | |
1849 | ||
b2267a6b AC |
1850 | /* |
1851 | * Refuse to handle uninitialized ports. | |
1852 | */ | |
1853 | if (!port->ops) | |
1854 | return -ENODEV; | |
1855 | ||
f6e9495d PM |
1856 | ret = sci_remap_port(port); |
1857 | if (unlikely(ret != 0)) | |
1858 | return ret; | |
e108b2ca | 1859 | |
dc8e6f5b MD |
1860 | if (sci_port->enable) |
1861 | sci_port->enable(port); | |
b7a76e4b | 1862 | |
1da177e4 LT |
1863 | if (options) |
1864 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1865 | ||
1866 | ret = uart_set_options(port, co, baud, parity, bits, flow); | |
1867 | #if defined(__H8300H__) || defined(__H8300S__) | |
1868 | /* disable rx interrupt */ | |
1869 | if (ret == 0) | |
1870 | sci_stop_rx(port); | |
1871 | #endif | |
501b825d | 1872 | /* TODO: disable clock */ |
1da177e4 LT |
1873 | return ret; |
1874 | } | |
1875 | ||
1876 | static struct console serial_console = { | |
1877 | .name = "ttySC", | |
906b17dc | 1878 | .device = uart_console_device, |
1da177e4 LT |
1879 | .write = serial_console_write, |
1880 | .setup = serial_console_setup, | |
fa5da2f7 | 1881 | .flags = CON_PRINTBUFFER, |
1da177e4 | 1882 | .index = -1, |
906b17dc | 1883 | .data = &sci_uart_driver, |
1da177e4 LT |
1884 | }; |
1885 | ||
7b6fd3bf MD |
1886 | static struct console early_serial_console = { |
1887 | .name = "early_ttySC", | |
1888 | .write = serial_console_write, | |
1889 | .flags = CON_PRINTBUFFER, | |
906b17dc | 1890 | .index = -1, |
7b6fd3bf | 1891 | }; |
ecdf8a46 | 1892 | |
7b6fd3bf MD |
1893 | static char early_serial_buf[32]; |
1894 | ||
ecdf8a46 PM |
1895 | static int __devinit sci_probe_earlyprintk(struct platform_device *pdev) |
1896 | { | |
1897 | struct plat_sci_port *cfg = pdev->dev.platform_data; | |
1898 | ||
1899 | if (early_serial_console.data) | |
1900 | return -EEXIST; | |
1901 | ||
1902 | early_serial_console.index = pdev->id; | |
ecdf8a46 | 1903 | |
906b17dc | 1904 | sci_init_single(NULL, &sci_ports[pdev->id], pdev->id, cfg); |
ecdf8a46 PM |
1905 | |
1906 | serial_console_setup(&early_serial_console, early_serial_buf); | |
1907 | ||
1908 | if (!strstr(early_serial_buf, "keep")) | |
1909 | early_serial_console.flags |= CON_BOOT; | |
1910 | ||
1911 | register_console(&early_serial_console); | |
1912 | return 0; | |
1913 | } | |
6a8c9799 NI |
1914 | |
1915 | #define SCI_CONSOLE (&serial_console) | |
1916 | ||
ecdf8a46 PM |
1917 | #else |
1918 | static inline int __devinit sci_probe_earlyprintk(struct platform_device *pdev) | |
1919 | { | |
1920 | return -EINVAL; | |
1921 | } | |
1da177e4 | 1922 | |
6a8c9799 NI |
1923 | #define SCI_CONSOLE NULL |
1924 | ||
1925 | #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */ | |
1da177e4 LT |
1926 | |
1927 | static char banner[] __initdata = | |
1928 | KERN_INFO "SuperH SCI(F) driver initialized\n"; | |
1929 | ||
1930 | static struct uart_driver sci_uart_driver = { | |
1931 | .owner = THIS_MODULE, | |
1932 | .driver_name = "sci", | |
1da177e4 LT |
1933 | .dev_name = "ttySC", |
1934 | .major = SCI_MAJOR, | |
1935 | .minor = SCI_MINOR_START, | |
e108b2ca | 1936 | .nr = SCI_NPORTS, |
1da177e4 LT |
1937 | .cons = SCI_CONSOLE, |
1938 | }; | |
1939 | ||
54507f6e | 1940 | static int sci_remove(struct platform_device *dev) |
e552de24 | 1941 | { |
d535a230 | 1942 | struct sci_port *port = platform_get_drvdata(dev); |
e552de24 | 1943 | |
d535a230 PM |
1944 | cpufreq_unregister_notifier(&port->freq_transition, |
1945 | CPUFREQ_TRANSITION_NOTIFIER); | |
e552de24 | 1946 | |
d535a230 PM |
1947 | uart_remove_one_port(&sci_uart_driver, &port->port); |
1948 | ||
1949 | clk_put(port->iclk); | |
1950 | clk_put(port->fclk); | |
e552de24 | 1951 | |
5e50d2d6 | 1952 | pm_runtime_disable(&dev->dev); |
e552de24 MD |
1953 | return 0; |
1954 | } | |
1955 | ||
0ee70712 MD |
1956 | static int __devinit sci_probe_single(struct platform_device *dev, |
1957 | unsigned int index, | |
1958 | struct plat_sci_port *p, | |
1959 | struct sci_port *sciport) | |
1960 | { | |
0ee70712 MD |
1961 | int ret; |
1962 | ||
1963 | /* Sanity check */ | |
1964 | if (unlikely(index >= SCI_NPORTS)) { | |
1965 | dev_notice(&dev->dev, "Attempting to register port " | |
1966 | "%d when only %d are available.\n", | |
1967 | index+1, SCI_NPORTS); | |
1968 | dev_notice(&dev->dev, "Consider bumping " | |
1969 | "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); | |
1970 | return 0; | |
1971 | } | |
1972 | ||
c7ed1ab3 PM |
1973 | ret = sci_init_single(dev, sciport, index, p); |
1974 | if (ret) | |
1975 | return ret; | |
0ee70712 | 1976 | |
d535a230 | 1977 | return uart_add_one_port(&sci_uart_driver, &sciport->port); |
0ee70712 MD |
1978 | } |
1979 | ||
e108b2ca | 1980 | static int __devinit sci_probe(struct platform_device *dev) |
1da177e4 | 1981 | { |
e108b2ca | 1982 | struct plat_sci_port *p = dev->dev.platform_data; |
d535a230 | 1983 | struct sci_port *sp = &sci_ports[dev->id]; |
ecdf8a46 | 1984 | int ret; |
d535a230 | 1985 | |
ecdf8a46 PM |
1986 | /* |
1987 | * If we've come here via earlyprintk initialization, head off to | |
1988 | * the special early probe. We don't have sufficient device state | |
1989 | * to make it beyond this yet. | |
1990 | */ | |
1991 | if (is_early_platform_device(dev)) | |
1992 | return sci_probe_earlyprintk(dev); | |
7b6fd3bf | 1993 | |
d535a230 | 1994 | platform_set_drvdata(dev, sp); |
e552de24 | 1995 | |
906b17dc | 1996 | ret = sci_probe_single(dev, dev->id, p, sp); |
d535a230 PM |
1997 | if (ret) |
1998 | goto err_unreg; | |
e552de24 | 1999 | |
d535a230 | 2000 | sp->freq_transition.notifier_call = sci_notifier; |
1da177e4 | 2001 | |
d535a230 PM |
2002 | ret = cpufreq_register_notifier(&sp->freq_transition, |
2003 | CPUFREQ_TRANSITION_NOTIFIER); | |
2004 | if (unlikely(ret < 0)) | |
2005 | goto err_unreg; | |
1da177e4 LT |
2006 | |
2007 | #ifdef CONFIG_SH_STANDARD_BIOS | |
2008 | sh_bios_gdb_detach(); | |
2009 | #endif | |
2010 | ||
e108b2ca | 2011 | return 0; |
7ff731ae PM |
2012 | |
2013 | err_unreg: | |
e552de24 | 2014 | sci_remove(dev); |
7ff731ae | 2015 | return ret; |
1da177e4 LT |
2016 | } |
2017 | ||
6daa79b3 | 2018 | static int sci_suspend(struct device *dev) |
1da177e4 | 2019 | { |
d535a230 | 2020 | struct sci_port *sport = dev_get_drvdata(dev); |
e108b2ca | 2021 | |
d535a230 PM |
2022 | if (sport) |
2023 | uart_suspend_port(&sci_uart_driver, &sport->port); | |
1da177e4 | 2024 | |
e108b2ca PM |
2025 | return 0; |
2026 | } | |
1da177e4 | 2027 | |
6daa79b3 | 2028 | static int sci_resume(struct device *dev) |
e108b2ca | 2029 | { |
d535a230 | 2030 | struct sci_port *sport = dev_get_drvdata(dev); |
e108b2ca | 2031 | |
d535a230 PM |
2032 | if (sport) |
2033 | uart_resume_port(&sci_uart_driver, &sport->port); | |
e108b2ca PM |
2034 | |
2035 | return 0; | |
2036 | } | |
2037 | ||
47145210 | 2038 | static const struct dev_pm_ops sci_dev_pm_ops = { |
6daa79b3 PM |
2039 | .suspend = sci_suspend, |
2040 | .resume = sci_resume, | |
2041 | }; | |
2042 | ||
e108b2ca PM |
2043 | static struct platform_driver sci_driver = { |
2044 | .probe = sci_probe, | |
b9e39c89 | 2045 | .remove = sci_remove, |
e108b2ca PM |
2046 | .driver = { |
2047 | .name = "sh-sci", | |
2048 | .owner = THIS_MODULE, | |
6daa79b3 | 2049 | .pm = &sci_dev_pm_ops, |
e108b2ca PM |
2050 | }, |
2051 | }; | |
2052 | ||
2053 | static int __init sci_init(void) | |
2054 | { | |
2055 | int ret; | |
2056 | ||
2057 | printk(banner); | |
2058 | ||
e108b2ca PM |
2059 | ret = uart_register_driver(&sci_uart_driver); |
2060 | if (likely(ret == 0)) { | |
2061 | ret = platform_driver_register(&sci_driver); | |
2062 | if (unlikely(ret)) | |
2063 | uart_unregister_driver(&sci_uart_driver); | |
2064 | } | |
2065 | ||
2066 | return ret; | |
2067 | } | |
2068 | ||
2069 | static void __exit sci_exit(void) | |
2070 | { | |
2071 | platform_driver_unregister(&sci_driver); | |
1da177e4 LT |
2072 | uart_unregister_driver(&sci_uart_driver); |
2073 | } | |
2074 | ||
7b6fd3bf MD |
2075 | #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE |
2076 | early_platform_init_buffer("earlyprintk", &sci_driver, | |
2077 | early_serial_buf, ARRAY_SIZE(early_serial_buf)); | |
2078 | #endif | |
1da177e4 LT |
2079 | module_init(sci_init); |
2080 | module_exit(sci_exit); | |
2081 | ||
e108b2ca | 2082 | MODULE_LICENSE("GPL"); |
e169c139 | 2083 | MODULE_ALIAS("platform:sh-sci"); |