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tty: serial: make crisv10 explicitly non-modular
[thirdparty/kernel/stable.git] / drivers / tty / serial / sh-sci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
f43dc23d 4 * Copyright (C) 2002 - 2011 Paul Mundt
f4998e55 5 * Copyright (C) 2015 Glider bvba
3ea6bc3d 6 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 7 *
8 * based off of the old drivers/char/sh-sci.c by:
9 *
10 * Copyright (C) 1999, 2000 Niibe Yutaka
11 * Copyright (C) 2000 Sugioka Toshinobu
12 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
13 * Modified to support SecureEdge. David McCullough (2002)
14 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 15 * Removed SH7300 support (Jul 2007).
1da177e4
LT		 16 *
17 * This file is subject to the terms and conditions of the GNU General Public
18 * License. See the file "COPYING" in the main directory of this archive
19 * for more details.
20 */
0b3d4ef6
PM		 21#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22#define SUPPORT_SYSRQ
23#endif
1da177e4
LT		 24
25#undef DEBUG
26
8fb9631c
LP		 27#include <linux/clk.h>
28#include <linux/console.h>
29#include <linux/ctype.h>
30#include <linux/cpufreq.h>
31#include <linux/delay.h>
32#include <linux/dmaengine.h>
33#include <linux/dma-mapping.h>
34#include <linux/err.h>
1da177e4 35#include <linux/errno.h>
8fb9631c 36#include <linux/init.h>
1da177e4 37#include <linux/interrupt.h>
1da177e4 38#include <linux/ioport.h>
8fb9631c
LP		 39#include <linux/major.h>
40#include <linux/module.h>
1da177e4 41#include <linux/mm.h>
20bdcab8 42#include <linux/of.h>
8fb9631c 43#include <linux/platform_device.h>
5e50d2d6 44#include <linux/pm_runtime.h>
73a19e4c 45#include <linux/scatterlist.h>
8fb9631c
LP		 46#include <linux/serial.h>
47#include <linux/serial_sci.h>
48#include <linux/sh_dma.h>
5a0e3ad6 49#include <linux/slab.h>
8fb9631c
LP		 50#include <linux/string.h>
51#include <linux/sysrq.h>
52#include <linux/timer.h>
53#include <linux/tty.h>
54#include <linux/tty_flip.h>
85f094ec
PM		 55
56#ifdef CONFIG_SUPERH
1da177e4
LT		 57#include <asm/sh_bios.h>
58#endif
59
f907c9ea 60#include "serial_mctrl_gpio.h"
1da177e4
LT		 61#include "sh-sci.h"
62
89b5c1ab
LP		 63/* Offsets into the sci_port->irqs array */
64enum {
65 SCIx_ERI_IRQ,
66 SCIx_RXI_IRQ,
67 SCIx_TXI_IRQ,
68 SCIx_BRI_IRQ,
69 SCIx_NR_IRQS,
70
71 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
72};
73
74#define SCIx_IRQ_IS_MUXED(port) \
75 ((port)->irqs[SCIx_ERI_IRQ] == \
76 (port)->irqs[SCIx_RXI_IRQ]) || \
77 ((port)->irqs[SCIx_ERI_IRQ] && \
78 ((port)->irqs[SCIx_RXI_IRQ] < 0))
79
f4998e55
GU		 80enum SCI_CLKS {
81 SCI_FCK, /* Functional Clock */
6af27bf2 82 SCI_SCK, /* Optional External Clock */
1270f865
GU		 83 SCI_BRG_INT, /* Optional BRG Internal Clock Source */
84 SCI_SCIF_CLK, /* Optional BRG External Clock Source */
f4998e55
GU		 85 SCI_NUM_CLKS
86};
87
69eee8e9
GU		 88/* Bit x set means sampling rate x + 1 is supported */
89#define SCI_SR(x) BIT((x) - 1)
90#define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
91
92a05748
GU		 92#define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
93 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
94 SCI_SR(19) | SCI_SR(27)
95
69eee8e9
GU		 96#define min_sr(_port) ffs((_port)->sampling_rate_mask)
97#define max_sr(_port) fls((_port)->sampling_rate_mask)
98
99/* Iterate over all supported sampling rates, from high to low */
100#define for_each_sr(_sr, _port) \
101 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
102 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
103
e108b2ca
PM		 104struct sci_port {
105 struct uart_port port;
106
ce6738b6
PM		 107 /* Platform configuration */
108 struct plat_sci_port *cfg;
2e0842a1 109 unsigned int overrun_reg;
75c249fd 110 unsigned int overrun_mask;
3ae988d9 111 unsigned int error_mask;
5da0f468 112 unsigned int error_clear;
69eee8e9 113 unsigned int sampling_rate_mask;
e4d6f911 114 resource_size_t reg_size;
f907c9ea 115 struct mctrl_gpios *gpios;
e108b2ca 116
e108b2ca
PM		 117 /* Break timer */
118 struct timer_list break_timer;
119 int break_flag;
1534a3b3 120
f4998e55
GU		 121 /* Clocks */
122 struct clk *clks[SCI_NUM_CLKS];
123 unsigned long clk_rates[SCI_NUM_CLKS];
edad1f20 124
1fcc91a6 125 int irqs[SCIx_NR_IRQS];
9174fc8f
PM		 126 char *irqstr[SCIx_NR_IRQS];
127
73a19e4c
GL		 128 struct dma_chan *chan_tx;
129 struct dma_chan *chan_rx;
f43dc23d 130
73a19e4c 131#ifdef CONFIG_SERIAL_SH_SCI_DMA
73a19e4c
GL		 132 dma_cookie_t cookie_tx;
133 dma_cookie_t cookie_rx[2];
134 dma_cookie_t active_rx;
79904420
GU		 135 dma_addr_t tx_dma_addr;
136 unsigned int tx_dma_len;
73a19e4c 137 struct scatterlist sg_rx[2];
7b39d901 138 void *rx_buf[2];
73a19e4c 139 size_t buf_len_rx;
73a19e4c 140 struct work_struct work_tx;
73a19e4c 141 struct timer_list rx_timer;
3089f381 142 unsigned int rx_timeout;
73a19e4c 143#endif
33f50ffc
GU		 144
145 bool autorts;
e108b2ca
PM		 146};
147
e108b2ca 148#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 149
e108b2ca
PM		 150static struct sci_port sci_ports[SCI_NPORTS];
151static struct uart_driver sci_uart_driver;
1da177e4 152
e7c98dc7
MT		 153static inline struct sci_port *
154to_sci_port(struct uart_port *uart)
155{
156 return container_of(uart, struct sci_port, port);
157}
158
61a6976b
PM		 159struct plat_sci_reg {
160 u8 offset, size;
161};
162
163/* Helper for invalidating specific entries of an inherited map. */
164#define sci_reg_invalid { .offset = 0, .size = 0 }
165
d3184e68 166static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
61a6976b
PM		 167 [SCIx_PROBE_REGTYPE] = {
168 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
169 },
170
171 /*
172 * Common SCI definitions, dependent on the port's regshift
173 * value.
174 */
175 [SCIx_SCI_REGTYPE] = {
176 [SCSMR] = { 0x00, 8 },
177 [SCBRR] = { 0x01, 8 },
178 [SCSCR] = { 0x02, 8 },
179 [SCxTDR] = { 0x03, 8 },
180 [SCxSR] = { 0x04, 8 },
181 [SCxRDR] = { 0x05, 8 },
182 [SCFCR] = sci_reg_invalid,
183 [SCFDR] = sci_reg_invalid,
184 [SCTFDR] = sci_reg_invalid,
185 [SCRFDR] = sci_reg_invalid,
186 [SCSPTR] = sci_reg_invalid,
187 [SCLSR] = sci_reg_invalid,
f303b364 188 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 189 [SCPCR] = sci_reg_invalid,
190 [SCPDR] = sci_reg_invalid,
b8bbd6b2
GU		 191 [SCDL] = sci_reg_invalid,
192 [SCCKS] = sci_reg_invalid,
61a6976b
PM		 193 },
194
195 /*
196 * Common definitions for legacy IrDA ports, dependent on
197 * regshift value.
198 */
199 [SCIx_IRDA_REGTYPE] = {
200 [SCSMR] = { 0x00, 8 },
201 [SCBRR] = { 0x01, 8 },
202 [SCSCR] = { 0x02, 8 },
203 [SCxTDR] = { 0x03, 8 },
204 [SCxSR] = { 0x04, 8 },
205 [SCxRDR] = { 0x05, 8 },
206 [SCFCR] = { 0x06, 8 },
207 [SCFDR] = { 0x07, 16 },
208 [SCTFDR] = sci_reg_invalid,
209 [SCRFDR] = sci_reg_invalid,
210 [SCSPTR] = sci_reg_invalid,
211 [SCLSR] = sci_reg_invalid,
f303b364 212 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 213 [SCPCR] = sci_reg_invalid,
214 [SCPDR] = sci_reg_invalid,
b8bbd6b2
GU		 215 [SCDL] = sci_reg_invalid,
216 [SCCKS] = sci_reg_invalid,
61a6976b
PM		 217 },
218
219 /*
220 * Common SCIFA definitions.
221 */
222 [SCIx_SCIFA_REGTYPE] = {
223 [SCSMR] = { 0x00, 16 },
224 [SCBRR] = { 0x04, 8 },
225 [SCSCR] = { 0x08, 16 },
226 [SCxTDR] = { 0x20, 8 },
227 [SCxSR] = { 0x14, 16 },
228 [SCxRDR] = { 0x24, 8 },
229 [SCFCR] = { 0x18, 16 },
230 [SCFDR] = { 0x1c, 16 },
231 [SCTFDR] = sci_reg_invalid,
232 [SCRFDR] = sci_reg_invalid,
233 [SCSPTR] = sci_reg_invalid,
234 [SCLSR] = sci_reg_invalid,
f303b364 235 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 236 [SCPCR] = { 0x30, 16 },
237 [SCPDR] = { 0x34, 16 },
b8bbd6b2
GU		 238 [SCDL] = sci_reg_invalid,
239 [SCCKS] = sci_reg_invalid,
61a6976b
PM		 240 },
241
242 /*
243 * Common SCIFB definitions.
244 */
245 [SCIx_SCIFB_REGTYPE] = {
246 [SCSMR] = { 0x00, 16 },
247 [SCBRR] = { 0x04, 8 },
248 [SCSCR] = { 0x08, 16 },
249 [SCxTDR] = { 0x40, 8 },
250 [SCxSR] = { 0x14, 16 },
251 [SCxRDR] = { 0x60, 8 },
252 [SCFCR] = { 0x18, 16 },
8c66d6d2
TY		 253 [SCFDR] = sci_reg_invalid,
254 [SCTFDR] = { 0x38, 16 },
255 [SCRFDR] = { 0x3c, 16 },
61a6976b
PM		 256 [SCSPTR] = sci_reg_invalid,
257 [SCLSR] = sci_reg_invalid,
f303b364 258 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 259 [SCPCR] = { 0x30, 16 },
260 [SCPDR] = { 0x34, 16 },
b8bbd6b2
GU		 261 [SCDL] = sci_reg_invalid,
262 [SCCKS] = sci_reg_invalid,
61a6976b
PM		 263 },
264
3af1f8a4
PE		 265 /*
266 * Common SH-2(A) SCIF definitions for ports with FIFO data
267 * count registers.
268 */
269 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
270 [SCSMR] = { 0x00, 16 },
271 [SCBRR] = { 0x04, 8 },
272 [SCSCR] = { 0x08, 16 },
273 [SCxTDR] = { 0x0c, 8 },
274 [SCxSR] = { 0x10, 16 },
275 [SCxRDR] = { 0x14, 8 },
276 [SCFCR] = { 0x18, 16 },
277 [SCFDR] = { 0x1c, 16 },
278 [SCTFDR] = sci_reg_invalid,
279 [SCRFDR] = sci_reg_invalid,
280 [SCSPTR] = { 0x20, 16 },
281 [SCLSR] = { 0x24, 16 },
f303b364 282 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 283 [SCPCR] = sci_reg_invalid,
284 [SCPDR] = sci_reg_invalid,
b8bbd6b2
GU		 285 [SCDL] = sci_reg_invalid,
286 [SCCKS] = sci_reg_invalid,
3af1f8a4
PE		 287 },
288
61a6976b
PM		 289 /*
290 * Common SH-3 SCIF definitions.
291 */
292 [SCIx_SH3_SCIF_REGTYPE] = {
293 [SCSMR] = { 0x00, 8 },
294 [SCBRR] = { 0x02, 8 },
295 [SCSCR] = { 0x04, 8 },
296 [SCxTDR] = { 0x06, 8 },
297 [SCxSR] = { 0x08, 16 },
298 [SCxRDR] = { 0x0a, 8 },
299 [SCFCR] = { 0x0c, 8 },
300 [SCFDR] = { 0x0e, 16 },
301 [SCTFDR] = sci_reg_invalid,
302 [SCRFDR] = sci_reg_invalid,
303 [SCSPTR] = sci_reg_invalid,
304 [SCLSR] = sci_reg_invalid,
f303b364 305 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 306 [SCPCR] = sci_reg_invalid,
307 [SCPDR] = sci_reg_invalid,
b8bbd6b2
GU		 308 [SCDL] = sci_reg_invalid,
309 [SCCKS] = sci_reg_invalid,
61a6976b
PM		 310 },
311
312 /*
313 * Common SH-4(A) SCIF(B) definitions.
314 */
315 [SCIx_SH4_SCIF_REGTYPE] = {
316 [SCSMR] = { 0x00, 16 },
317 [SCBRR] = { 0x04, 8 },
318 [SCSCR] = { 0x08, 16 },
319 [SCxTDR] = { 0x0c, 8 },
320 [SCxSR] = { 0x10, 16 },
321 [SCxRDR] = { 0x14, 8 },
322 [SCFCR] = { 0x18, 16 },
323 [SCFDR] = { 0x1c, 16 },
324 [SCTFDR] = sci_reg_invalid,
325 [SCRFDR] = sci_reg_invalid,
326 [SCSPTR] = { 0x20, 16 },
327 [SCLSR] = { 0x24, 16 },
f303b364 328 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 329 [SCPCR] = sci_reg_invalid,
330 [SCPDR] = sci_reg_invalid,
b8bbd6b2
GU		 331 [SCDL] = sci_reg_invalid,
332 [SCCKS] = sci_reg_invalid,
333 },
334
335 /*
336 * Common SCIF definitions for ports with a Baud Rate Generator for
337 * External Clock (BRG).
338 */
339 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
340 [SCSMR] = { 0x00, 16 },
341 [SCBRR] = { 0x04, 8 },
342 [SCSCR] = { 0x08, 16 },
343 [SCxTDR] = { 0x0c, 8 },
344 [SCxSR] = { 0x10, 16 },
345 [SCxRDR] = { 0x14, 8 },
346 [SCFCR] = { 0x18, 16 },
347 [SCFDR] = { 0x1c, 16 },
348 [SCTFDR] = sci_reg_invalid,
349 [SCRFDR] = sci_reg_invalid,
350 [SCSPTR] = { 0x20, 16 },
351 [SCLSR] = { 0x24, 16 },
352 [HSSRR] = sci_reg_invalid,
353 [SCPCR] = sci_reg_invalid,
354 [SCPDR] = sci_reg_invalid,
355 [SCDL] = { 0x30, 16 },
356 [SCCKS] = { 0x34, 16 },
f303b364
UH		 357 },
358
359 /*
360 * Common HSCIF definitions.
361 */
362 [SCIx_HSCIF_REGTYPE] = {
363 [SCSMR] = { 0x00, 16 },
364 [SCBRR] = { 0x04, 8 },
365 [SCSCR] = { 0x08, 16 },
366 [SCxTDR] = { 0x0c, 8 },
367 [SCxSR] = { 0x10, 16 },
368 [SCxRDR] = { 0x14, 8 },
369 [SCFCR] = { 0x18, 16 },
370 [SCFDR] = { 0x1c, 16 },
371 [SCTFDR] = sci_reg_invalid,
372 [SCRFDR] = sci_reg_invalid,
373 [SCSPTR] = { 0x20, 16 },
374 [SCLSR] = { 0x24, 16 },
375 [HSSRR] = { 0x40, 16 },
c097abc3
GU		 376 [SCPCR] = sci_reg_invalid,
377 [SCPDR] = sci_reg_invalid,
b8bbd6b2
GU		 378 [SCDL] = { 0x30, 16 },
379 [SCCKS] = { 0x34, 16 },
61a6976b
PM		 380 },
381
382 /*
383 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
384 * register.
385 */
386 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
387 [SCSMR] = { 0x00, 16 },
388 [SCBRR] = { 0x04, 8 },
389 [SCSCR] = { 0x08, 16 },
390 [SCxTDR] = { 0x0c, 8 },
391 [SCxSR] = { 0x10, 16 },
392 [SCxRDR] = { 0x14, 8 },
393 [SCFCR] = { 0x18, 16 },
394 [SCFDR] = { 0x1c, 16 },
395 [SCTFDR] = sci_reg_invalid,
396 [SCRFDR] = sci_reg_invalid,
397 [SCSPTR] = sci_reg_invalid,
398 [SCLSR] = { 0x24, 16 },
f303b364 399 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 400 [SCPCR] = sci_reg_invalid,
401 [SCPDR] = sci_reg_invalid,
b8bbd6b2
GU		 402 [SCDL] = sci_reg_invalid,
403 [SCCKS] = sci_reg_invalid,
61a6976b
PM		 404 },
405
406 /*
407 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
408 * count registers.
409 */
410 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
411 [SCSMR] = { 0x00, 16 },
412 [SCBRR] = { 0x04, 8 },
413 [SCSCR] = { 0x08, 16 },
414 [SCxTDR] = { 0x0c, 8 },
415 [SCxSR] = { 0x10, 16 },
416 [SCxRDR] = { 0x14, 8 },
417 [SCFCR] = { 0x18, 16 },
418 [SCFDR] = { 0x1c, 16 },
419 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
420 [SCRFDR] = { 0x20, 16 },
421 [SCSPTR] = { 0x24, 16 },
422 [SCLSR] = { 0x28, 16 },
f303b364 423 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 424 [SCPCR] = sci_reg_invalid,
425 [SCPDR] = sci_reg_invalid,
b8bbd6b2
GU		 426 [SCDL] = sci_reg_invalid,
427 [SCCKS] = sci_reg_invalid,
61a6976b
PM		 428 },
429
430 /*
431 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
432 * registers.
433 */
434 [SCIx_SH7705_SCIF_REGTYPE] = {
435 [SCSMR] = { 0x00, 16 },
436 [SCBRR] = { 0x04, 8 },
437 [SCSCR] = { 0x08, 16 },
438 [SCxTDR] = { 0x20, 8 },
439 [SCxSR] = { 0x14, 16 },
440 [SCxRDR] = { 0x24, 8 },
441 [SCFCR] = { 0x18, 16 },
442 [SCFDR] = { 0x1c, 16 },
443 [SCTFDR] = sci_reg_invalid,
444 [SCRFDR] = sci_reg_invalid,
445 [SCSPTR] = sci_reg_invalid,
446 [SCLSR] = sci_reg_invalid,
f303b364 447 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 448 [SCPCR] = sci_reg_invalid,
449 [SCPDR] = sci_reg_invalid,
b8bbd6b2
GU		 450 [SCDL] = sci_reg_invalid,
451 [SCCKS] = sci_reg_invalid,
61a6976b
PM		 452 },
453};
454
72b294cf
PM		 455#define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
456
61a6976b
PM		 457/*
458 * The "offset" here is rather misleading, in that it refers to an enum
459 * value relative to the port mapping rather than the fixed offset
460 * itself, which needs to be manually retrieved from the platform's
461 * register map for the given port.
462 */
463static unsigned int sci_serial_in(struct uart_port *p, int offset)
464{
d3184e68 465 const struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 466
467 if (reg->size == 8)
468 return ioread8(p->membase + (reg->offset << p->regshift));
469 else if (reg->size == 16)
470 return ioread16(p->membase + (reg->offset << p->regshift));
471 else
472 WARN(1, "Invalid register access\n");
473
474 return 0;
475}
476
477static void sci_serial_out(struct uart_port *p, int offset, int value)
478{
d3184e68 479 const struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 480
481 if (reg->size == 8)
482 iowrite8(value, p->membase + (reg->offset << p->regshift));
483 else if (reg->size == 16)
484 iowrite16(value, p->membase + (reg->offset << p->regshift));
485 else
486 WARN(1, "Invalid register access\n");
487}
488
61a6976b
PM		 489static int sci_probe_regmap(struct plat_sci_port *cfg)
490{
491 switch (cfg->type) {
492 case PORT_SCI:
493 cfg->regtype = SCIx_SCI_REGTYPE;
494 break;
495 case PORT_IRDA:
496 cfg->regtype = SCIx_IRDA_REGTYPE;
497 break;
498 case PORT_SCIFA:
499 cfg->regtype = SCIx_SCIFA_REGTYPE;
500 break;
501 case PORT_SCIFB:
502 cfg->regtype = SCIx_SCIFB_REGTYPE;
503 break;
504 case PORT_SCIF:
505 /*
506 * The SH-4 is a bit of a misnomer here, although that's
507 * where this particular port layout originated. This
508 * configuration (or some slight variation thereof)
509 * remains the dominant model for all SCIFs.
510 */
511 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
512 break;
f303b364
UH		 513 case PORT_HSCIF:
514 cfg->regtype = SCIx_HSCIF_REGTYPE;
515 break;
61a6976b 516 default:
6c13d5d2 517 pr_err("Can't probe register map for given port\n");
61a6976b
PM		 518 return -EINVAL;
519 }
520
521 return 0;
522}
523
23241d43
PM		 524static void sci_port_enable(struct sci_port *sci_port)
525{
f4998e55
GU		 526 unsigned int i;
527
23241d43
PM		 528 if (!sci_port->port.dev)
529 return;
530
531 pm_runtime_get_sync(sci_port->port.dev);
532
f4998e55
GU		 533 for (i = 0; i < SCI_NUM_CLKS; i++) {
534 clk_prepare_enable(sci_port->clks[i]);
535 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
536 }
537 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
23241d43
PM		 538}
539
540static void sci_port_disable(struct sci_port *sci_port)
541{
f4998e55
GU		 542 unsigned int i;
543
23241d43
PM		 544 if (!sci_port->port.dev)
545 return;
546
caec7038
LP		 547 /* Cancel the break timer to ensure that the timer handler will not try
548 * to access the hardware with clocks and power disabled. Reset the
549 * break flag to make the break debouncing state machine ready for the
550 * next break.
551 */
552 del_timer_sync(&sci_port->break_timer);
553 sci_port->break_flag = 0;
554
f4998e55
GU		 555 for (i = SCI_NUM_CLKS; i-- > 0; )
556 clk_disable_unprepare(sci_port->clks[i]);
23241d43
PM		 557
558 pm_runtime_put_sync(sci_port->port.dev);
559}
560
e1910fcd
GU		 561static inline unsigned long port_rx_irq_mask(struct uart_port *port)
562{
563 /*
564 * Not all ports (such as SCIFA) will support REIE. Rather than
565 * special-casing the port type, we check the port initialization
566 * IRQ enable mask to see whether the IRQ is desired at all. If
567 * it's unset, it's logically inferred that there's no point in
568 * testing for it.
569 */
570 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
571}
572
573static void sci_start_tx(struct uart_port *port)
574{
575 struct sci_port *s = to_sci_port(port);
576 unsigned short ctrl;
577
578#ifdef CONFIG_SERIAL_SH_SCI_DMA
579 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
580 u16 new, scr = serial_port_in(port, SCSCR);
581 if (s->chan_tx)
582 new = scr | SCSCR_TDRQE;
583 else
584 new = scr & ~SCSCR_TDRQE;
585 if (new != scr)
586 serial_port_out(port, SCSCR, new);
587 }
588
589 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
590 dma_submit_error(s->cookie_tx)) {
591 s->cookie_tx = 0;
592 schedule_work(&s->work_tx);
593 }
594#endif
595
596 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
597 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
598 ctrl = serial_port_in(port, SCSCR);
599 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
600 }
601}
602
603static void sci_stop_tx(struct uart_port *port)
604{
605 unsigned short ctrl;
606
607 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
608 ctrl = serial_port_in(port, SCSCR);
609
610 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
611 ctrl &= ~SCSCR_TDRQE;
612
613 ctrl &= ~SCSCR_TIE;
614
615 serial_port_out(port, SCSCR, ctrl);
616}
617
618static void sci_start_rx(struct uart_port *port)
619{
620 unsigned short ctrl;
621
622 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
623
624 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
625 ctrl &= ~SCSCR_RDRQE;
626
627 serial_port_out(port, SCSCR, ctrl);
628}
629
630static void sci_stop_rx(struct uart_port *port)
631{
632 unsigned short ctrl;
633
634 ctrl = serial_port_in(port, SCSCR);
635
636 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
637 ctrl &= ~SCSCR_RDRQE;
638
639 ctrl &= ~port_rx_irq_mask(port);
640
641 serial_port_out(port, SCSCR, ctrl);
642}
643
a1b5b43f
GU		 644static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
645{
646 if (port->type == PORT_SCI) {
647 /* Just store the mask */
648 serial_port_out(port, SCxSR, mask);
649 } else if (to_sci_port(port)->overrun_mask == SCIFA_ORER) {
650 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
651 /* Only clear the status bits we want to clear */
652 serial_port_out(port, SCxSR,
653 serial_port_in(port, SCxSR) & mask);
654 } else {
655 /* Store the mask, clear parity/framing errors */
656 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
657 }
658}
659
0b0cced1
YS		 660#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
661 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
1f6fd5c9
PM		 662
663#ifdef CONFIG_CONSOLE_POLL
07d2a1a1 664static int sci_poll_get_char(struct uart_port *port)
1da177e4 665{
1da177e4
LT		 666 unsigned short status;
667 int c;
668
e108b2ca 669 do {
b12bb29f 670 status = serial_port_in(port, SCxSR);
1da177e4 671 if (status & SCxSR_ERRORS(port)) {
a1b5b43f 672 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 673 continue;
674 }
3f255eb3
JW		 675 break;
676 } while (1);
677
678 if (!(status & SCxSR_RDxF(port)))
679 return NO_POLL_CHAR;
07d2a1a1 680
b12bb29f 681 c = serial_port_in(port, SCxRDR);
07d2a1a1 682
e7c98dc7 683 /* Dummy read */
b12bb29f 684 serial_port_in(port, SCxSR);
a1b5b43f 685 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 686
687 return c;
688}
1f6fd5c9 689#endif
1da177e4 690
07d2a1a1 691static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 692{
1da177e4
LT		 693 unsigned short status;
694
1da177e4 695 do {
b12bb29f 696 status = serial_port_in(port, SCxSR);
1da177e4
LT		 697 } while (!(status & SCxSR_TDxE(port)));
698
b12bb29f 699 serial_port_out(port, SCxTDR, c);
a1b5b43f 700 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 701}
0b0cced1
YS		 702#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
703 CONFIG_SERIAL_SH_SCI_EARLYCON */
1da177e4 704
61a6976b 705static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 706{
61a6976b 707 struct sci_port *s = to_sci_port(port);
1da177e4 708
61a6976b
PM		 709 /*
710 * Use port-specific handler if provided.
711 */
712 if (s->cfg->ops && s->cfg->ops->init_pins) {
713 s->cfg->ops->init_pins(port, cflag);
714 return;
1da177e4 715 }
41504c39 716
e9d7a45a
GU		 717 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
718 u16 ctrl = serial_port_in(port, SCPCR);
719
720 /* Enable RXD and TXD pin functions */
721 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
722 if (to_sci_port(port)->cfg->capabilities & SCIx_HAVE_RTSCTS) {
723 /* RTS# is output, driven 1 */
724 ctrl |= SCPCR_RTSC;
725 serial_port_out(port, SCPDR,
726 serial_port_in(port, SCPDR) | SCPDR_RTSD);
727 /* Enable CTS# pin function */
728 ctrl &= ~SCPCR_CTSC;
729 }
730 serial_port_out(port, SCPCR, ctrl);
731 } else if (sci_getreg(port, SCSPTR)->size) {
d2b9775d
GU		 732 u16 status = serial_port_in(port, SCSPTR);
733
734 /* RTS# is output, driven 1 */
735 status |= SCSPTR_RTSIO | SCSPTR_RTSDT;
736 /* CTS# and SCK are inputs */
737 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
738 serial_port_out(port, SCSPTR, status);
faf02f8f 739 }
d5701647 740}
e108b2ca 741
72b294cf 742static int sci_txfill(struct uart_port *port)
e108b2ca 743{
d3184e68 744 const struct plat_sci_reg *reg;
e108b2ca 745
72b294cf
PM		 746 reg = sci_getreg(port, SCTFDR);
747 if (reg->size)
63f7ad11 748 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
c63847a3 749
72b294cf
PM		 750 reg = sci_getreg(port, SCFDR);
751 if (reg->size)
b12bb29f 752 return serial_port_in(port, SCFDR) >> 8;
d1d4b10c 753
b12bb29f 754 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 755}
756
73a19e4c
GL		 757static int sci_txroom(struct uart_port *port)
758{
72b294cf 759 return port->fifosize - sci_txfill(port);
73a19e4c
GL		 760}
761
762static int sci_rxfill(struct uart_port *port)
e108b2ca 763{
d3184e68 764 const struct plat_sci_reg *reg;
72b294cf
PM		 765
766 reg = sci_getreg(port, SCRFDR);
767 if (reg->size)
63f7ad11 768 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
72b294cf
PM		 769
770 reg = sci_getreg(port, SCFDR);
771 if (reg->size)
b12bb29f 772 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
72b294cf 773
b12bb29f 774 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 775}
776
514820eb
PM		 777/*
778 * SCI helper for checking the state of the muxed port/RXD pins.
779 */
780static inline int sci_rxd_in(struct uart_port *port)
781{
782 struct sci_port *s = to_sci_port(port);
783
784 if (s->cfg->port_reg <= 0)
785 return 1;
786
0dd4d5cb 787 /* Cast for ARM damage */
e2afca69 788 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
514820eb
PM		 789}
790
1da177e4
LT		 791/* ********************************************************************** *
792 * the interrupt related routines *
793 * ********************************************************************** */
794
795static void sci_transmit_chars(struct uart_port *port)
796{
ebd2c8f6 797 struct circ_buf *xmit = &port->state->xmit;
1da177e4 798 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 799 unsigned short status;
800 unsigned short ctrl;
e108b2ca 801 int count;
1da177e4 802
b12bb29f 803 status = serial_port_in(port, SCxSR);
1da177e4 804 if (!(status & SCxSR_TDxE(port))) {
b12bb29f 805 ctrl = serial_port_in(port, SCSCR);
e7c98dc7 806 if (uart_circ_empty(xmit))
8e698614 807 ctrl &= ~SCSCR_TIE;
e7c98dc7 808 else
8e698614 809 ctrl |= SCSCR_TIE;
b12bb29f 810 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 811 return;
812 }
813
72b294cf 814 count = sci_txroom(port);
1da177e4
LT		 815
816 do {
817 unsigned char c;
818
819 if (port->x_char) {
820 c = port->x_char;
821 port->x_char = 0;
822 } else if (!uart_circ_empty(xmit) && !stopped) {
823 c = xmit->buf[xmit->tail];
824 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
825 } else {
826 break;
827 }
828
b12bb29f 829 serial_port_out(port, SCxTDR, c);
1da177e4
LT		 830
831 port->icount.tx++;
832 } while (--count > 0);
833
a1b5b43f 834 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1da177e4
LT		 835
836 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
837 uart_write_wakeup(port);
838 if (uart_circ_empty(xmit)) {
b129a8cc 839 sci_stop_tx(port);
1da177e4 840 } else {
b12bb29f 841 ctrl = serial_port_in(port, SCSCR);
1da177e4 842
1a22f08d 843 if (port->type != PORT_SCI) {
b12bb29f 844 serial_port_in(port, SCxSR); /* Dummy read */
a1b5b43f 845 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1da177e4 846 }
1da177e4 847
8e698614 848 ctrl |= SCSCR_TIE;
b12bb29f 849 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 850 }
851}
852
853/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 854#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 855
94c8b6db 856static void sci_receive_chars(struct uart_port *port)
1da177e4 857{
e7c98dc7 858 struct sci_port *sci_port = to_sci_port(port);
227434f8 859 struct tty_port *tport = &port->state->port;
1da177e4
LT		 860 int i, count, copied = 0;
861 unsigned short status;
33f0f88f 862 unsigned char flag;
1da177e4 863
b12bb29f 864 status = serial_port_in(port, SCxSR);
1da177e4
LT		 865 if (!(status & SCxSR_RDxF(port)))
866 return;
867
868 while (1) {
1da177e4 869 /* Don't copy more bytes than there is room for in the buffer */
227434f8 870 count = tty_buffer_request_room(tport, sci_rxfill(port));
1da177e4
LT		 871
872 /* If for any reason we can't copy more data, we're done! */
873 if (count == 0)
874 break;
875
876 if (port->type == PORT_SCI) {
b12bb29f 877 char c = serial_port_in(port, SCxRDR);
e7c98dc7
MT		 878 if (uart_handle_sysrq_char(port, c) ||
879 sci_port->break_flag)
1da177e4 880 count = 0;
e7c98dc7 881 else
92a19f9c 882 tty_insert_flip_char(tport, c, TTY_NORMAL);
1da177e4 883 } else {
e7c98dc7 884 for (i = 0; i < count; i++) {
b12bb29f 885 char c = serial_port_in(port, SCxRDR);
d97fbbed 886
b12bb29f 887 status = serial_port_in(port, SCxSR);
1da177e4
LT		 888#if defined(CONFIG_CPU_SH3)
889 /* Skip "chars" during break */
e108b2ca 890 if (sci_port->break_flag) {
1da177e4
LT		 891 if ((c == 0) &&
892 (status & SCxSR_FER(port))) {
893 count--; i--;
894 continue;
895 }
e108b2ca 896
1da177e4 897 /* Nonzero => end-of-break */
762c69e3 898 dev_dbg(port->dev, "debounce<%02x>\n", c);
e108b2ca
PM		 899 sci_port->break_flag = 0;
900
1da177e4
LT		 901 if (STEPFN(c)) {
902 count--; i--;
903 continue;
904 }
905 }
906#endif /* CONFIG_CPU_SH3 */
7d12e780 907 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 908 count--; i--;
909 continue;
910 }
911
912 /* Store data and status */
73a19e4c 913 if (status & SCxSR_FER(port)) {
33f0f88f 914 flag = TTY_FRAME;
d97fbbed 915 port->icount.frame++;
762c69e3 916 dev_notice(port->dev, "frame error\n");
73a19e4c 917 } else if (status & SCxSR_PER(port)) {
33f0f88f 918 flag = TTY_PARITY;
d97fbbed 919 port->icount.parity++;
762c69e3 920 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 921 } else
922 flag = TTY_NORMAL;
762c69e3 923
92a19f9c 924 tty_insert_flip_char(tport, c, flag);
1da177e4
LT		 925 }
926 }
927
b12bb29f 928 serial_port_in(port, SCxSR); /* dummy read */
a1b5b43f 929 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4 930
1da177e4
LT		 931 copied += count;
932 port->icount.rx += count;
933 }
934
935 if (copied) {
936 /* Tell the rest of the system the news. New characters! */
2e124b4a 937 tty_flip_buffer_push(tport);
1da177e4 938 } else {
b12bb29f 939 serial_port_in(port, SCxSR); /* dummy read */
a1b5b43f 940 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 941 }
942}
943
944#define SCI_BREAK_JIFFIES (HZ/20)
94c8b6db
PM		 945
946/*
947 * The sci generates interrupts during the break,
1da177e4
LT		 948 * 1 per millisecond or so during the break period, for 9600 baud.
949 * So dont bother disabling interrupts.
950 * But dont want more than 1 break event.
951 * Use a kernel timer to periodically poll the rx line until
952 * the break is finished.
953 */
94c8b6db 954static inline void sci_schedule_break_timer(struct sci_port *port)
1da177e4 955{
bc9b3f5c 956 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
1da177e4 957}
94c8b6db 958
1da177e4
LT		 959/* Ensure that two consecutive samples find the break over. */
960static void sci_break_timer(unsigned long data)
961{
e108b2ca
PM		 962 struct sci_port *port = (struct sci_port *)data;
963
964 if (sci_rxd_in(&port->port) == 0) {
1da177e4 965 port->break_flag = 1;
e108b2ca
PM		 966 sci_schedule_break_timer(port);
967 } else if (port->break_flag == 1) {
1da177e4
LT		 968 /* break is over. */
969 port->break_flag = 2;
e108b2ca
PM		 970 sci_schedule_break_timer(port);
971 } else
972 port->break_flag = 0;
1da177e4
LT		 973}
974
94c8b6db 975static int sci_handle_errors(struct uart_port *port)
1da177e4
LT		 976{
977 int copied = 0;
b12bb29f 978 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 979 struct tty_port *tport = &port->state->port;
debf9507 980 struct sci_port *s = to_sci_port(port);
1da177e4 981
3ae988d9 982 /* Handle overruns */
75c249fd 983 if (status & s->overrun_mask) {
3ae988d9 984 port->icount.overrun++;
d97fbbed 985
3ae988d9
LP		 986 /* overrun error */
987 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
988 copied++;
762c69e3 989
9b971cd2 990 dev_notice(port->dev, "overrun error\n");
1da177e4
LT		 991 }
992
e108b2ca 993 if (status & SCxSR_FER(port)) {
1da177e4
LT		 994 if (sci_rxd_in(port) == 0) {
995 /* Notify of BREAK */
e7c98dc7 996 struct sci_port *sci_port = to_sci_port(port);
e108b2ca
PM		 997
998 if (!sci_port->break_flag) {
d97fbbed
PM		 999 port->icount.brk++;
1000
e108b2ca
PM		 1001 sci_port->break_flag = 1;
1002 sci_schedule_break_timer(sci_port);
1003
1da177e4 1004 /* Do sysrq handling. */
e108b2ca 1005 if (uart_handle_break(port))
1da177e4 1006 return 0;
762c69e3
PM		 1007
1008 dev_dbg(port->dev, "BREAK detected\n");
1009
92a19f9c 1010 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
e7c98dc7
MT		 1011 copied++;
1012 }
1013
e108b2ca 1014 } else {
1da177e4 1015 /* frame error */
d97fbbed
PM		 1016 port->icount.frame++;
1017
92a19f9c 1018 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
33f0f88f 1019 copied++;
762c69e3
PM		 1020
1021 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 1022 }
1023 }
1024
e108b2ca 1025 if (status & SCxSR_PER(port)) {
1da177e4 1026 /* parity error */
d97fbbed
PM		 1027 port->icount.parity++;
1028
92a19f9c 1029 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
e108b2ca 1030 copied++;
762c69e3 1031
9b971cd2 1032 dev_notice(port->dev, "parity error\n");
1da177e4
LT		 1033 }
1034
33f0f88f 1035 if (copied)
2e124b4a 1036 tty_flip_buffer_push(tport);
1da177e4
LT		 1037
1038 return copied;
1039}
1040
94c8b6db 1041static int sci_handle_fifo_overrun(struct uart_port *port)
d830fa45 1042{
92a19f9c 1043 struct tty_port *tport = &port->state->port;
debf9507 1044 struct sci_port *s = to_sci_port(port);
d3184e68 1045 const struct plat_sci_reg *reg;
2e0842a1 1046 int copied = 0;
75c249fd 1047 u16 status;
d830fa45 1048
2e0842a1 1049 reg = sci_getreg(port, s->overrun_reg);
4b8c59a3 1050 if (!reg->size)
d830fa45
PM		 1051 return 0;
1052
2e0842a1 1053 status = serial_port_in(port, s->overrun_reg);
75c249fd
GU		 1054 if (status & s->overrun_mask) {
1055 status &= ~s->overrun_mask;
2e0842a1 1056 serial_port_out(port, s->overrun_reg, status);
d830fa45 1057
d97fbbed
PM		 1058 port->icount.overrun++;
1059
92a19f9c 1060 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
2e124b4a 1061 tty_flip_buffer_push(tport);
d830fa45 1062
51b31f1c 1063 dev_dbg(port->dev, "overrun error\n");
d830fa45
PM		 1064 copied++;
1065 }
1066
1067 return copied;
1068}
1069
94c8b6db 1070static int sci_handle_breaks(struct uart_port *port)
1da177e4
LT		 1071{
1072 int copied = 0;
b12bb29f 1073 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 1074 struct tty_port *tport = &port->state->port;
a5660ada 1075 struct sci_port *s = to_sci_port(port);
1da177e4 1076
0b3d4ef6
PM		 1077 if (uart_handle_break(port))
1078 return 0;
1079
b7a76e4b 1080 if (!s->break_flag && status & SCxSR_BRK(port)) {
1da177e4
LT		 1081#if defined(CONFIG_CPU_SH3)
1082 /* Debounce break */
1083 s->break_flag = 1;
1084#endif
d97fbbed
PM		 1085
1086 port->icount.brk++;
1087
1da177e4 1088 /* Notify of BREAK */
92a19f9c 1089 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
33f0f88f 1090 copied++;
762c69e3
PM		 1091
1092 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 1093 }
1094
33f0f88f 1095 if (copied)
2e124b4a 1096 tty_flip_buffer_push(tport);
e108b2ca 1097
d830fa45
PM		 1098 copied += sci_handle_fifo_overrun(port);
1099
1da177e4
LT		 1100 return copied;
1101}
1102
73a19e4c 1103#ifdef CONFIG_SERIAL_SH_SCI_DMA
e1910fcd
GU		 1104static void sci_dma_tx_complete(void *arg)
1105{
1106 struct sci_port *s = arg;
1107 struct uart_port *port = &s->port;
1108 struct circ_buf *xmit = &port->state->xmit;
1109 unsigned long flags;
73a19e4c 1110
e1910fcd 1111 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
73a19e4c 1112
e1910fcd 1113 spin_lock_irqsave(&port->lock, flags);
73a19e4c 1114
e1910fcd
GU		 1115 xmit->tail += s->tx_dma_len;
1116 xmit->tail &= UART_XMIT_SIZE - 1;
73a19e4c 1117
e1910fcd 1118 port->icount.tx += s->tx_dma_len;
1da177e4 1119
e1910fcd
GU		 1120 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1121 uart_write_wakeup(port);
1da177e4 1122
e1910fcd
GU		 1123 if (!uart_circ_empty(xmit)) {
1124 s->cookie_tx = 0;
1125 schedule_work(&s->work_tx);
1126 } else {
1127 s->cookie_tx = -EINVAL;
1128 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1129 u16 ctrl = serial_port_in(port, SCSCR);
1130 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1131 }
1132 }
1da177e4 1133
fd78a76a 1134 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1135}
1136
e1910fcd
GU		 1137/* Locking: called with port lock held */
1138static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1da177e4 1139{
e1910fcd
GU		 1140 struct uart_port *port = &s->port;
1141 struct tty_port *tport = &port->state->port;
1142 int copied;
1da177e4 1143
e1910fcd
GU		 1144 copied = tty_insert_flip_string(tport, buf, count);
1145 if (copied < count) {
1146 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
1147 count - copied);
1148 port->icount.buf_overrun++;
1da177e4
LT		 1149 }
1150
e1910fcd 1151 port->icount.rx += copied;
1da177e4 1152
e1910fcd 1153 return copied;
1da177e4
LT		 1154}
1155
e1910fcd 1156static int sci_dma_rx_find_active(struct sci_port *s)
1da177e4 1157{
e1910fcd 1158 unsigned int i;
1da177e4 1159
e1910fcd
GU		 1160 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1161 if (s->active_rx == s->cookie_rx[i])
1162 return i;
1da177e4 1163
e1910fcd
GU		 1164 dev_err(s->port.dev, "%s: Rx cookie %d not found!\n", __func__,
1165 s->active_rx);
1166 return -1;
1da177e4
LT		 1167}
1168
e1910fcd 1169static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
f43dc23d 1170{
e1910fcd
GU		 1171 struct dma_chan *chan = s->chan_rx;
1172 struct uart_port *port = &s->port;
1173 unsigned long flags;
1174
1175 spin_lock_irqsave(&port->lock, flags);
1176 s->chan_rx = NULL;
1177 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1178 spin_unlock_irqrestore(&port->lock, flags);
1179 dmaengine_terminate_all(chan);
1180 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1181 sg_dma_address(&s->sg_rx[0]));
1182 dma_release_channel(chan);
1183 if (enable_pio)
1184 sci_start_rx(port);
f43dc23d
PM		 1185}
1186
e1910fcd 1187static void sci_dma_rx_complete(void *arg)
1da177e4 1188{
e1910fcd 1189 struct sci_port *s = arg;
1d3db608 1190 struct dma_chan *chan = s->chan_rx;
e1910fcd 1191 struct uart_port *port = &s->port;
67f462b0 1192 struct dma_async_tx_descriptor *desc;
e1910fcd
GU		 1193 unsigned long flags;
1194 int active, count = 0;
1da177e4 1195
e1910fcd
GU		 1196 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1197 s->active_rx);
cb772fe7 1198
e1910fcd 1199 spin_lock_irqsave(&port->lock, flags);
1da177e4 1200
e1910fcd
GU		 1201 active = sci_dma_rx_find_active(s);
1202 if (active >= 0)
1203 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
f43dc23d 1204
e1910fcd 1205 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
f43dc23d 1206
e1910fcd
GU		 1207 if (count)
1208 tty_flip_buffer_push(&port->state->port);
8b6ff84c 1209
67f462b0
GU		 1210 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1211 DMA_DEV_TO_MEM,
1212 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1213 if (!desc)
1214 goto fail;
1215
1216 desc->callback = sci_dma_rx_complete;
1217 desc->callback_param = s;
1218 s->cookie_rx[active] = dmaengine_submit(desc);
1219 if (dma_submit_error(s->cookie_rx[active]))
1220 goto fail;
1221
1222 s->active_rx = s->cookie_rx[!active];
1223
1d3db608
MHF		 1224 dma_async_issue_pending(chan);
1225
67f462b0
GU		 1226 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1227 __func__, s->cookie_rx[active], active, s->active_rx);
1228 spin_unlock_irqrestore(&port->lock, flags);
1229 return;
1230
1231fail:
1232 spin_unlock_irqrestore(&port->lock, flags);
1233 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1234 sci_rx_dma_release(s, true);
1da177e4
LT		 1235}
1236
e1910fcd 1237static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1da177e4 1238{
e1910fcd
GU		 1239 struct dma_chan *chan = s->chan_tx;
1240 struct uart_port *port = &s->port;
e552de24 1241 unsigned long flags;
1da177e4 1242
e1910fcd
GU		 1243 spin_lock_irqsave(&port->lock, flags);
1244 s->chan_tx = NULL;
1245 s->cookie_tx = -EINVAL;
1246 spin_unlock_irqrestore(&port->lock, flags);
1247 dmaengine_terminate_all(chan);
1248 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1249 DMA_TO_DEVICE);
1250 dma_release_channel(chan);
1251 if (enable_pio)
1252 sci_start_tx(port);
1253}
d535a230 1254
e1910fcd
GU		 1255static void sci_submit_rx(struct sci_port *s)
1256{
1257 struct dma_chan *chan = s->chan_rx;
1258 int i;
073e84c9 1259
e1910fcd
GU		 1260 for (i = 0; i < 2; i++) {
1261 struct scatterlist *sg = &s->sg_rx[i];
1262 struct dma_async_tx_descriptor *desc;
1da177e4 1263
e1910fcd
GU		 1264 desc = dmaengine_prep_slave_sg(chan,
1265 sg, 1, DMA_DEV_TO_MEM,
1266 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1267 if (!desc)
1268 goto fail;
501b825d 1269
e1910fcd
GU		 1270 desc->callback = sci_dma_rx_complete;
1271 desc->callback_param = s;
1272 s->cookie_rx[i] = dmaengine_submit(desc);
1273 if (dma_submit_error(s->cookie_rx[i]))
1274 goto fail;
9174fc8f 1275
e1910fcd
GU		 1276 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1277 s->cookie_rx[i], i);
1278 }
9174fc8f 1279
e1910fcd 1280 s->active_rx = s->cookie_rx[0];
9174fc8f 1281
e1910fcd
GU		 1282 dma_async_issue_pending(chan);
1283 return;
9174fc8f 1284
e1910fcd
GU		 1285fail:
1286 if (i)
1287 dmaengine_terminate_all(chan);
1288 for (i = 0; i < 2; i++)
1289 s->cookie_rx[i] = -EINVAL;
1290 s->active_rx = -EINVAL;
1291 dev_warn(s->port.dev, "Failed to re-start Rx DMA, using PIO\n");
1292 sci_rx_dma_release(s, true);
1293}
9174fc8f 1294
e1910fcd 1295static void work_fn_tx(struct work_struct *work)
1da177e4 1296{
e1910fcd
GU		 1297 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1298 struct dma_async_tx_descriptor *desc;
1299 struct dma_chan *chan = s->chan_tx;
1300 struct uart_port *port = &s->port;
1301 struct circ_buf *xmit = &port->state->xmit;
1302 dma_addr_t buf;
1da177e4 1303
9174fc8f 1304 /*
e1910fcd
GU		 1305 * DMA is idle now.
1306 * Port xmit buffer is already mapped, and it is one page... Just adjust
1307 * offsets and lengths. Since it is a circular buffer, we have to
1308 * transmit till the end, and then the rest. Take the port lock to get a
1309 * consistent xmit buffer state.
9174fc8f 1310 */
e1910fcd
GU		 1311 spin_lock_irq(&port->lock);
1312 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1313 s->tx_dma_len = min_t(unsigned int,
1314 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1315 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1316 spin_unlock_irq(&port->lock);
0e8963de 1317
e1910fcd
GU		 1318 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1319 DMA_MEM_TO_DEV,
1320 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1321 if (!desc) {
1322 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1323 /* switch to PIO */
1324 sci_tx_dma_release(s, true);
1325 return;
1326 }
0e8963de 1327
e1910fcd
GU		 1328 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1329 DMA_TO_DEVICE);
1da177e4 1330
e1910fcd
GU		 1331 spin_lock_irq(&port->lock);
1332 desc->callback = sci_dma_tx_complete;
1333 desc->callback_param = s;
1334 spin_unlock_irq(&port->lock);
1335 s->cookie_tx = dmaengine_submit(desc);
1336 if (dma_submit_error(s->cookie_tx)) {
1337 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1338 /* switch to PIO */
1339 sci_tx_dma_release(s, true);
1340 return;
1da177e4 1341 }
1da177e4 1342
e1910fcd
GU		 1343 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1344 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
73a19e4c 1345
e1910fcd 1346 dma_async_issue_pending(chan);
1da177e4
LT		 1347}
1348
e1910fcd 1349static void rx_timer_fn(unsigned long arg)
1da177e4 1350{
e1910fcd 1351 struct sci_port *s = (struct sci_port *)arg;
e7327c09 1352 struct dma_chan *chan = s->chan_rx;
e1910fcd 1353 struct uart_port *port = &s->port;
67f462b0
GU		 1354 struct dma_tx_state state;
1355 enum dma_status status;
1356 unsigned long flags;
1357 unsigned int read;
1358 int active, count;
1359 u16 scr;
1360
1361 spin_lock_irqsave(&port->lock, flags);
e1910fcd 1362
67f462b0 1363 dev_dbg(port->dev, "DMA Rx timed out\n");
67f462b0
GU		 1364
1365 active = sci_dma_rx_find_active(s);
1366 if (active < 0) {
1367 spin_unlock_irqrestore(&port->lock, flags);
1368 return;
1369 }
1370
1371 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
3b963042 1372 if (status == DMA_COMPLETE) {
67f462b0
GU		 1373 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1374 s->active_rx, active);
3b963042
MHF		 1375 spin_unlock_irqrestore(&port->lock, flags);
1376
1377 /* Let packet complete handler take care of the packet */
1378 return;
1379 }
67f462b0 1380
e7327c09
MHF		 1381 dmaengine_pause(chan);
1382
1383 /*
1384 * sometimes DMA transfer doesn't stop even if it is stopped and
1385 * data keeps on coming until transaction is complete so check
1386 * for DMA_COMPLETE again
1387 * Let packet complete handler take care of the packet
1388 */
1389 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1390 if (status == DMA_COMPLETE) {
1391 spin_unlock_irqrestore(&port->lock, flags);
1392 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1393 return;
1394 }
1395
67f462b0
GU		 1396 /* Handle incomplete DMA receive */
1397 dmaengine_terminate_all(s->chan_rx);
1398 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1399 dev_dbg(port->dev, "Read %u bytes with cookie %d\n", read,
1400 s->active_rx);
1401
1402 if (read) {
1403 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1404 if (count)
1405 tty_flip_buffer_push(&port->state->port);
1406 }
1407
756981be
GU		 1408 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1409 sci_submit_rx(s);
371cfed3
MHF		 1410
1411 /* Direct new serial port interrupts back to CPU */
1412 scr = serial_port_in(port, SCSCR);
1413 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1414 scr &= ~SCSCR_RDRQE;
1415 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1416 }
1417 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1418
1419 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1420}
1421
ff441129
GU		 1422static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1423 enum dma_transfer_direction dir,
1424 unsigned int id)
1425{
1426 dma_cap_mask_t mask;
1427 struct dma_chan *chan;
1428 struct dma_slave_config cfg;
1429 int ret;
1430
1431 dma_cap_zero(mask);
1432 dma_cap_set(DMA_SLAVE, mask);
1433
1434 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1435 (void *)(unsigned long)id, port->dev,
1436 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1437 if (!chan) {
1438 dev_warn(port->dev,
1439 "dma_request_slave_channel_compat failed\n");
1440 return NULL;
1441 }
1442
1443 memset(&cfg, 0, sizeof(cfg));
1444 cfg.direction = dir;
1445 if (dir == DMA_MEM_TO_DEV) {
1446 cfg.dst_addr = port->mapbase +
1447 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1448 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1449 } else {
1450 cfg.src_addr = port->mapbase +
1451 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1452 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1453 }
1454
1455 ret = dmaengine_slave_config(chan, &cfg);
1456 if (ret) {
1457 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1458 dma_release_channel(chan);
1459 return NULL;
1460 }
1461
1462 return chan;
1463}
1464
e1910fcd 1465static void sci_request_dma(struct uart_port *port)
73a19e4c 1466{
e1910fcd 1467 struct sci_port *s = to_sci_port(port);
e1910fcd 1468 struct dma_chan *chan;
73a19e4c 1469
e1910fcd 1470 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
73a19e4c 1471
ff441129
GU		 1472 if (!port->dev->of_node &&
1473 (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0))
e1910fcd 1474 return;
73a19e4c 1475
e1910fcd 1476 s->cookie_tx = -EINVAL;
ff441129 1477 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV, s->cfg->dma_slave_tx);
e1910fcd
GU		 1478 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1479 if (chan) {
1480 s->chan_tx = chan;
1481 /* UART circular tx buffer is an aligned page. */
1482 s->tx_dma_addr = dma_map_single(chan->device->dev,
1483 port->state->xmit.buf,
1484 UART_XMIT_SIZE,
1485 DMA_TO_DEVICE);
1486 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1487 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1488 dma_release_channel(chan);
1489 s->chan_tx = NULL;
1490 } else {
1491 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1492 __func__, UART_XMIT_SIZE,
1493 port->state->xmit.buf, &s->tx_dma_addr);
49d4bcad 1494 }
e1910fcd
GU		 1495
1496 INIT_WORK(&s->work_tx, work_fn_tx);
3089f381
GL		 1497 }
1498
ff441129 1499 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM, s->cfg->dma_slave_rx);
e1910fcd
GU		 1500 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1501 if (chan) {
1502 unsigned int i;
1503 dma_addr_t dma;
1504 void *buf;
73a19e4c 1505
e1910fcd 1506 s->chan_rx = chan;
73a19e4c 1507
e1910fcd
GU		 1508 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1509 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1510 &dma, GFP_KERNEL);
1511 if (!buf) {
1512 dev_warn(port->dev,
1513 "Failed to allocate Rx dma buffer, using PIO\n");
1514 dma_release_channel(chan);
1515 s->chan_rx = NULL;
e1910fcd
GU		 1516 return;
1517 }
73a19e4c 1518
e1910fcd
GU		 1519 for (i = 0; i < 2; i++) {
1520 struct scatterlist *sg = &s->sg_rx[i];
0533502d 1521
e1910fcd
GU		 1522 sg_init_table(sg, 1);
1523 s->rx_buf[i] = buf;
1524 sg_dma_address(sg) = dma;
d09959e7 1525 sg_dma_len(sg) = s->buf_len_rx;
0533502d 1526
e1910fcd
GU		 1527 buf += s->buf_len_rx;
1528 dma += s->buf_len_rx;
1529 }
1530
e1910fcd
GU		 1531 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1532
756981be
GU		 1533 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1534 sci_submit_rx(s);
e1910fcd 1535 }
0533502d
GU		 1536}
1537
e1910fcd 1538static void sci_free_dma(struct uart_port *port)
73a19e4c 1539{
e1910fcd 1540 struct sci_port *s = to_sci_port(port);
73a19e4c 1541
e1910fcd
GU		 1542 if (s->chan_tx)
1543 sci_tx_dma_release(s, false);
1544 if (s->chan_rx)
1545 sci_rx_dma_release(s, false);
1546}
1547#else
1548static inline void sci_request_dma(struct uart_port *port)
1549{
1550}
73a19e4c 1551
e1910fcd
GU		 1552static inline void sci_free_dma(struct uart_port *port)
1553{
1554}
1555#endif
73a19e4c 1556
e1910fcd
GU		 1557static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1558{
1559#ifdef CONFIG_SERIAL_SH_SCI_DMA
1560 struct uart_port *port = ptr;
1561 struct sci_port *s = to_sci_port(port);
73a19e4c 1562
e1910fcd
GU		 1563 if (s->chan_rx) {
1564 u16 scr = serial_port_in(port, SCSCR);
1565 u16 ssr = serial_port_in(port, SCxSR);
73a19e4c 1566
e1910fcd
GU		 1567 /* Disable future Rx interrupts */
1568 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1569 disable_irq_nosync(irq);
1570 scr |= SCSCR_RDRQE;
1571 } else {
1572 scr &= ~SCSCR_RIE;
756981be 1573 sci_submit_rx(s);
e1910fcd
GU		 1574 }
1575 serial_port_out(port, SCSCR, scr);
1576 /* Clear current interrupt */
1577 serial_port_out(port, SCxSR,
1578 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1579 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
1580 jiffies, s->rx_timeout);
1581 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c 1582
e1910fcd
GU		 1583 return IRQ_HANDLED;
1584 }
1585#endif
73a19e4c 1586
e1910fcd
GU		 1587 /* I think sci_receive_chars has to be called irrespective
1588 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1589 * to be disabled?
1590 */
1591 sci_receive_chars(ptr);
1592
1593 return IRQ_HANDLED;
73a19e4c
GL		 1594}
1595
e1910fcd 1596static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
73a19e4c 1597{
e1910fcd 1598 struct uart_port *port = ptr;
04928b79 1599 unsigned long flags;
73a19e4c 1600
04928b79 1601 spin_lock_irqsave(&port->lock, flags);
e1910fcd 1602 sci_transmit_chars(port);
04928b79 1603 spin_unlock_irqrestore(&port->lock, flags);
e1910fcd
GU		 1604
1605 return IRQ_HANDLED;
73a19e4c
GL		 1606}
1607
e1910fcd 1608static irqreturn_t sci_er_interrupt(int irq, void *ptr)
73a19e4c 1609{
e1910fcd
GU		 1610 struct uart_port *port = ptr;
1611 struct sci_port *s = to_sci_port(port);
73a19e4c 1612
e1910fcd
GU		 1613 /* Handle errors */
1614 if (port->type == PORT_SCI) {
1615 if (sci_handle_errors(port)) {
1616 /* discard character in rx buffer */
1617 serial_port_in(port, SCxSR);
1618 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1619 }
1620 } else {
1621 sci_handle_fifo_overrun(port);
1622 if (!s->chan_rx)
1623 sci_receive_chars(ptr);
1624 }
1625
1626 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1627
1628 /* Kick the transmission */
1629 if (!s->chan_tx)
1630 sci_tx_interrupt(irq, ptr);
1631
1632 return IRQ_HANDLED;
73a19e4c
GL		 1633}
1634
e1910fcd 1635static irqreturn_t sci_br_interrupt(int irq, void *ptr)
73a19e4c 1636{
e1910fcd 1637 struct uart_port *port = ptr;
73a19e4c 1638
e1910fcd
GU		 1639 /* Handle BREAKs */
1640 sci_handle_breaks(port);
1641 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
73a19e4c 1642
e1910fcd
GU		 1643 return IRQ_HANDLED;
1644}
73a19e4c 1645
e1910fcd
GU		 1646static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1647{
1648 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1649 struct uart_port *port = ptr;
1650 struct sci_port *s = to_sci_port(port);
1651 irqreturn_t ret = IRQ_NONE;
73a19e4c 1652
e1910fcd
GU		 1653 ssr_status = serial_port_in(port, SCxSR);
1654 scr_status = serial_port_in(port, SCSCR);
1655 if (s->overrun_reg == SCxSR)
1656 orer_status = ssr_status;
1657 else {
1658 if (sci_getreg(port, s->overrun_reg)->size)
1659 orer_status = serial_port_in(port, s->overrun_reg);
73a19e4c
GL		 1660 }
1661
e1910fcd 1662 err_enabled = scr_status & port_rx_irq_mask(port);
73a19e4c 1663
e1910fcd
GU		 1664 /* Tx Interrupt */
1665 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1666 !s->chan_tx)
1667 ret = sci_tx_interrupt(irq, ptr);
658daa95 1668
e1910fcd
GU		 1669 /*
1670 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1671 * DR flags
1672 */
1673 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1674 (scr_status & SCSCR_RIE))
1675 ret = sci_rx_interrupt(irq, ptr);
73a19e4c 1676
e1910fcd
GU		 1677 /* Error Interrupt */
1678 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1679 ret = sci_er_interrupt(irq, ptr);
73a19e4c 1680
e1910fcd
GU		 1681 /* Break Interrupt */
1682 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1683 ret = sci_br_interrupt(irq, ptr);
1684
1685 /* Overrun Interrupt */
1686 if (orer_status & s->overrun_mask) {
1687 sci_handle_fifo_overrun(port);
1688 ret = IRQ_HANDLED;
73a19e4c 1689 }
73a19e4c 1690
e1910fcd
GU		 1691 return ret;
1692}
73a19e4c 1693
e1910fcd
GU		 1694static const struct sci_irq_desc {
1695 const char *desc;
1696 irq_handler_t handler;
1697} sci_irq_desc[] = {
1698 /*
1699 * Split out handlers, the default case.
1700 */
1701 [SCIx_ERI_IRQ] = {
1702 .desc = "rx err",
1703 .handler = sci_er_interrupt,
1704 },
3089f381 1705
e1910fcd
GU		 1706 [SCIx_RXI_IRQ] = {
1707 .desc = "rx full",
1708 .handler = sci_rx_interrupt,
1709 },
47aceb92 1710
e1910fcd
GU		 1711 [SCIx_TXI_IRQ] = {
1712 .desc = "tx empty",
1713 .handler = sci_tx_interrupt,
1714 },
73a19e4c 1715
e1910fcd
GU		 1716 [SCIx_BRI_IRQ] = {
1717 .desc = "break",
1718 .handler = sci_br_interrupt,
1719 },
73a19e4c
GL		 1720
1721 /*
e1910fcd 1722 * Special muxed handler.
73a19e4c 1723 */
e1910fcd
GU		 1724 [SCIx_MUX_IRQ] = {
1725 .desc = "mux",
1726 .handler = sci_mpxed_interrupt,
1727 },
1728};
73a19e4c 1729
e1910fcd
GU		 1730static int sci_request_irq(struct sci_port *port)
1731{
1732 struct uart_port *up = &port->port;
1733 int i, j, ret = 0;
73a19e4c 1734
e1910fcd
GU		 1735 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1736 const struct sci_irq_desc *desc;
1737 int irq;
73a19e4c 1738
e1910fcd
GU		 1739 if (SCIx_IRQ_IS_MUXED(port)) {
1740 i = SCIx_MUX_IRQ;
1741 irq = up->irq;
1742 } else {
1743 irq = port->irqs[i];
1744
1745 /*
1746 * Certain port types won't support all of the
1747 * available interrupt sources.
1748 */
1749 if (unlikely(irq < 0))
1750 continue;
1751 }
1752
1753 desc = sci_irq_desc + i;
1754 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1755 dev_name(up->dev), desc->desc);
1756 if (!port->irqstr[j])
1757 goto out_nomem;
1758
1759 ret = request_irq(irq, desc->handler, up->irqflags,
1760 port->irqstr[j], port);
1761 if (unlikely(ret)) {
1762 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1763 goto out_noirq;
1764 }
73a19e4c
GL		 1765 }
1766
e1910fcd 1767 return 0;
1da177e4 1768
e1910fcd
GU		 1769out_noirq:
1770 while (--i >= 0)
1771 free_irq(port->irqs[i], port);
f43dc23d 1772
e1910fcd
GU		 1773out_nomem:
1774 while (--j >= 0)
1775 kfree(port->irqstr[j]);
f43dc23d 1776
e1910fcd 1777 return ret;
1da177e4
LT		 1778}
1779
e1910fcd 1780static void sci_free_irq(struct sci_port *port)
1da177e4 1781{
e1910fcd 1782 int i;
1da177e4 1783
e1910fcd
GU		 1784 /*
1785 * Intentionally in reverse order so we iterate over the muxed
1786 * IRQ first.
1787 */
1788 for (i = 0; i < SCIx_NR_IRQS; i++) {
1789 int irq = port->irqs[i];
f43dc23d 1790
e1910fcd
GU		 1791 /*
1792 * Certain port types won't support all of the available
1793 * interrupt sources.
1794 */
1795 if (unlikely(irq < 0))
1796 continue;
f43dc23d 1797
e1910fcd
GU		 1798 free_irq(port->irqs[i], port);
1799 kfree(port->irqstr[i]);
f43dc23d 1800
e1910fcd
GU		 1801 if (SCIx_IRQ_IS_MUXED(port)) {
1802 /* If there's only one IRQ, we're done. */
1803 return;
1804 }
1805 }
1da177e4
LT		 1806}
1807
e1910fcd 1808static unsigned int sci_tx_empty(struct uart_port *port)
1da177e4 1809{
e1910fcd
GU		 1810 unsigned short status = serial_port_in(port, SCxSR);
1811 unsigned short in_tx_fifo = sci_txfill(port);
f43dc23d 1812
e1910fcd 1813 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 1814}
1815
33f50ffc
GU		 1816static void sci_set_rts(struct uart_port *port, bool state)
1817{
1818 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1819 u16 data = serial_port_in(port, SCPDR);
1820
1821 /* Active low */
1822 if (state)
1823 data &= ~SCPDR_RTSD;
1824 else
1825 data |= SCPDR_RTSD;
1826 serial_port_out(port, SCPDR, data);
1827
1828 /* RTS# is output */
1829 serial_port_out(port, SCPCR,
1830 serial_port_in(port, SCPCR) | SCPCR_RTSC);
1831 } else if (sci_getreg(port, SCSPTR)->size) {
1832 u16 ctrl = serial_port_in(port, SCSPTR);
1833
1834 /* Active low */
1835 if (state)
1836 ctrl &= ~SCSPTR_RTSDT;
1837 else
1838 ctrl |= SCSPTR_RTSDT;
1839 serial_port_out(port, SCSPTR, ctrl);
1840 }
1841}
1842
1843static bool sci_get_cts(struct uart_port *port)
1844{
1845 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1846 /* Active low */
1847 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD);
1848 } else if (sci_getreg(port, SCSPTR)->size) {
1849 /* Active low */
1850 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT);
1851 }
1852
1853 return true;
1854}
1855
e1910fcd
GU		 1856/*
1857 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1858 * CTS/RTS is supported in hardware by at least one port and controlled
1859 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1860 * handled via the ->init_pins() op, which is a bit of a one-way street,
1861 * lacking any ability to defer pin control -- this will later be
1862 * converted over to the GPIO framework).
1863 *
1864 * Other modes (such as loopback) are supported generically on certain
1865 * port types, but not others. For these it's sufficient to test for the
1866 * existence of the support register and simply ignore the port type.
1867 */
1868static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1da177e4 1869{
f907c9ea
GU		 1870 struct sci_port *s = to_sci_port(port);
1871
e1910fcd
GU		 1872 if (mctrl & TIOCM_LOOP) {
1873 const struct plat_sci_reg *reg;
f43dc23d 1874
e1910fcd
GU		 1875 /*
1876 * Standard loopback mode for SCFCR ports.
1877 */
1878 reg = sci_getreg(port, SCFCR);
1879 if (reg->size)
1880 serial_port_out(port, SCFCR,
1881 serial_port_in(port, SCFCR) |
1882 SCFCR_LOOP);
1883 }
f907c9ea
GU		 1884
1885 mctrl_gpio_set(s->gpios, mctrl);
33f50ffc
GU		 1886
1887 if (!(s->cfg->capabilities & SCIx_HAVE_RTSCTS))
1888 return;
1889
1890 if (!(mctrl & TIOCM_RTS)) {
1891 /* Disable Auto RTS */
1892 serial_port_out(port, SCFCR,
1893 serial_port_in(port, SCFCR) & ~SCFCR_MCE);
1894
1895 /* Clear RTS */
1896 sci_set_rts(port, 0);
1897 } else if (s->autorts) {
1898 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1899 /* Enable RTS# pin function */
1900 serial_port_out(port, SCPCR,
1901 serial_port_in(port, SCPCR) & ~SCPCR_RTSC);
1902 }
1903
1904 /* Enable Auto RTS */
1905 serial_port_out(port, SCFCR,
1906 serial_port_in(port, SCFCR) | SCFCR_MCE);
1907 } else {
1908 /* Set RTS */
1909 sci_set_rts(port, 1);
1910 }
e1910fcd 1911}
f43dc23d 1912
e1910fcd
GU		 1913static unsigned int sci_get_mctrl(struct uart_port *port)
1914{
f907c9ea
GU		 1915 struct sci_port *s = to_sci_port(port);
1916 struct mctrl_gpios *gpios = s->gpios;
1917 unsigned int mctrl = 0;
1918
1919 mctrl_gpio_get(gpios, &mctrl);
1920
e1910fcd
GU		 1921 /*
1922 * CTS/RTS is handled in hardware when supported, while nothing
33f50ffc 1923 * else is wired up.
e1910fcd 1924 */
33f50ffc
GU		 1925 if (s->autorts) {
1926 if (sci_get_cts(port))
1927 mctrl |= TIOCM_CTS;
1928 } else if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS))) {
f907c9ea 1929 mctrl |= TIOCM_CTS;
33f50ffc 1930 }
f907c9ea
GU		 1931 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)))
1932 mctrl |= TIOCM_DSR;
1933 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)))
1934 mctrl |= TIOCM_CAR;
1935
1936 return mctrl;
1937}
1938
1939static void sci_enable_ms(struct uart_port *port)
1940{
1941 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
1da177e4
LT		 1942}
1943
1da177e4
LT		 1944static void sci_break_ctl(struct uart_port *port, int break_state)
1945{
bbb4ce50
SY		 1946 unsigned short scscr, scsptr;
1947
a4e02f6d 1948 /* check wheter the port has SCSPTR */
abbf121f 1949 if (!sci_getreg(port, SCSPTR)->size) {
bbb4ce50
SY		 1950 /*
1951 * Not supported by hardware. Most parts couple break and rx
1952 * interrupts together, with break detection always enabled.
1953 */
a4e02f6d 1954 return;
bbb4ce50 1955 }
a4e02f6d
SY		 1956
1957 scsptr = serial_port_in(port, SCSPTR);
1958 scscr = serial_port_in(port, SCSCR);
1959
1960 if (break_state == -1) {
1961 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1962 scscr &= ~SCSCR_TE;
1963 } else {
1964 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1965 scscr |= SCSCR_TE;
1966 }
1967
1968 serial_port_out(port, SCSPTR, scsptr);
1969 serial_port_out(port, SCSCR, scscr);
1da177e4
LT		 1970}
1971
1972static int sci_startup(struct uart_port *port)
1973{
a5660ada 1974 struct sci_port *s = to_sci_port(port);
073e84c9 1975 int ret;
1da177e4 1976
73a19e4c
GL		 1977 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1978
073e84c9
PM		 1979 ret = sci_request_irq(s);
1980 if (unlikely(ret < 0))
1981 return ret;
1982
73a19e4c 1983 sci_request_dma(port);
073e84c9 1984
1da177e4
LT		 1985 return 0;
1986}
1987
1988static void sci_shutdown(struct uart_port *port)
1989{
a5660ada 1990 struct sci_port *s = to_sci_port(port);
33b48e16 1991 unsigned long flags;
5fd2b6ee 1992 u16 scr;
1da177e4 1993
73a19e4c
GL		 1994 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1995
33f50ffc 1996 s->autorts = false;
f907c9ea
GU		 1997 mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
1998
33b48e16 1999 spin_lock_irqsave(&port->lock, flags);
1da177e4 2000 sci_stop_rx(port);
b129a8cc 2001 sci_stop_tx(port);
5fd2b6ee
GU		 2002 /* Stop RX and TX, disable related interrupts, keep clock source */
2003 scr = serial_port_in(port, SCSCR);
2004 serial_port_out(port, SCSCR, scr & (SCSCR_CKE1 | SCSCR_CKE0));
33b48e16 2005 spin_unlock_irqrestore(&port->lock, flags);
073e84c9 2006
9ab76556
AM		 2007#ifdef CONFIG_SERIAL_SH_SCI_DMA
2008 if (s->chan_rx) {
2009 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2010 port->line);
2011 del_timer_sync(&s->rx_timer);
2012 }
2013#endif
2014
73a19e4c 2015 sci_free_dma(port);
1da177e4 2016 sci_free_irq(s);
1da177e4
LT		 2017}
2018
6af27bf2
GU		 2019static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2020 unsigned int *srr)
26c92f37 2021{
6af27bf2 2022 unsigned long freq = s->clk_rates[SCI_SCK];
6af27bf2 2023 int err, min_err = INT_MAX;
69eee8e9 2024 unsigned int sr;
6af27bf2 2025
7b5c0c08
GU		 2026 if (s->port.type != PORT_HSCIF)
2027 freq *= 2;
6af27bf2 2028
69eee8e9 2029 for_each_sr(sr, s) {
6af27bf2
GU		 2030 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2031 if (abs(err) >= abs(min_err))
2032 continue;
2033
2034 min_err = err;
2035 *srr = sr - 1;
ec09c5eb 2036
6af27bf2
GU		 2037 if (!err)
2038 break;
2039 }
e8183a6c 2040
6af27bf2
GU		 2041 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2042 *srr + 1);
2043 return min_err;
26c92f37
PM		 2044}
2045
1270f865
GU		 2046static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2047 unsigned long freq, unsigned int *dlr,
2048 unsigned int *srr)
730c4e78 2049{
1270f865 2050 int err, min_err = INT_MAX;
69eee8e9 2051 unsigned int sr, dl;
730c4e78 2052
7b5c0c08
GU		 2053 if (s->port.type != PORT_HSCIF)
2054 freq *= 2;
730c4e78 2055
69eee8e9 2056 for_each_sr(sr, s) {
1270f865
GU		 2057 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2058 dl = clamp(dl, 1U, 65535U);
2059
2060 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2061 if (abs(err) >= abs(min_err))
2062 continue;
2063
2064 min_err = err;
2065 *dlr = dl;
2066 *srr = sr - 1;
2067
2068 if (!err)
2069 break;
2070 }
730c4e78 2071
1270f865
GU		 2072 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2073 min_err, *dlr, *srr + 1);
2074 return min_err;
2075}
730c4e78 2076
b4a5c459 2077/* calculate sample rate, BRR, and clock select */
f4998e55
GU		 2078static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2079 unsigned int *brr, unsigned int *srr,
2080 unsigned int *cks)
f303b364 2081{
f4998e55 2082 unsigned long freq = s->clk_rates[SCI_FCK];
69eee8e9 2083 unsigned int sr, br, prediv, scrate, c;
6c51332d 2084 int err, min_err = INT_MAX;
f303b364 2085
7b5c0c08
GU		 2086 if (s->port.type != PORT_HSCIF)
2087 freq *= 2;
b4a5c459 2088
6c51332d
GU		 2089 /*
2090 * Find the combination of sample rate and clock select with the
2091 * smallest deviation from the desired baud rate.
2092 * Prefer high sample rates to maximise the receive margin.
2093 *
2094 * M: Receive margin (%)
2095 * N: Ratio of bit rate to clock (N = sampling rate)
2096 * D: Clock duty (D = 0 to 1.0)
2097 * L: Frame length (L = 9 to 12)
2098 * F: Absolute value of clock frequency deviation
2099 *
2100 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2101 * (|D - 0.5| / N * (1 + F))|
2102 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2103 */
69eee8e9 2104 for_each_sr(sr, s) {
f303b364
UH		 2105 for (c = 0; c <= 3; c++) {
2106 /* integerized formulas from HSCIF documentation */
7b5c0c08 2107 prediv = sr * (1 << (2 * c + 1));
de01e6cd
GU		 2108
2109 /*
2110 * We need to calculate:
2111 *
2112 * br = freq / (prediv * bps) clamped to [1..256]
881a7489 2113 * err = freq / (br * prediv) - bps
730c4e78 2114 *
de01e6cd
GU		 2115 * Watch out for overflow when calculating the desired
2116 * sampling clock rate!
730c4e78 2117 */
de01e6cd
GU		 2118 if (bps > UINT_MAX / prediv)
2119 break;
2120
2121 scrate = prediv * bps;
2122 br = DIV_ROUND_CLOSEST(freq, scrate);
95a2703e 2123 br = clamp(br, 1U, 256U);
6c51332d 2124
881a7489 2125 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
6c51332d 2126 if (abs(err) >= abs(min_err))
730c4e78
NI		 2127 continue;
2128
6c51332d 2129 min_err = err;
95a2703e 2130 *brr = br - 1;
730c4e78
NI		 2131 *srr = sr - 1;
2132 *cks = c;
6c51332d
GU		 2133
2134 if (!err)
2135 goto found;
f303b364
UH		 2136 }
2137 }
2138
6c51332d 2139found:
881a7489
GU		 2140 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2141 min_err, *brr, *srr + 1, *cks);
f4998e55 2142 return min_err;
f303b364
UH		 2143}
2144
1ba76220
MD		 2145static void sci_reset(struct uart_port *port)
2146{
d3184e68 2147 const struct plat_sci_reg *reg;
1ba76220
MD		 2148 unsigned int status;
2149
2150 do {
b12bb29f 2151 status = serial_port_in(port, SCxSR);
1ba76220
MD		 2152 } while (!(status & SCxSR_TEND(port)));
2153
b12bb29f 2154 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1ba76220 2155
0979e0e6
PM		 2156 reg = sci_getreg(port, SCFCR);
2157 if (reg->size)
b12bb29f 2158 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2768cf42
GU		 2159
2160 sci_clear_SCxSR(port,
2161 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2162 SCxSR_BREAK_CLEAR(port));
fc2af334
GU		 2163 if (sci_getreg(port, SCLSR)->size) {
2164 status = serial_port_in(port, SCLSR);
2165 status &= ~(SCLSR_TO | SCLSR_ORER);
2166 serial_port_out(port, SCLSR, status);
2167 }
1ba76220
MD		 2168}
2169
606d099c
AC		 2170static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2171 struct ktermios *old)
1da177e4 2172{
95ee05c7 2173 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i;
1270f865
GU		 2174 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2175 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
00b9de9c 2176 struct sci_port *s = to_sci_port(port);
d3184e68 2177 const struct plat_sci_reg *reg;
f4998e55
GU		 2178 int min_err = INT_MAX, err;
2179 unsigned long max_freq = 0;
2180 int best_clk = -1;
1da177e4 2181
730c4e78
NI		 2182 if ((termios->c_cflag & CSIZE) == CS7)
2183 smr_val |= SCSMR_CHR;
2184 if (termios->c_cflag & PARENB)
2185 smr_val |= SCSMR_PE;
2186 if (termios->c_cflag & PARODD)
2187 smr_val |= SCSMR_PE | SCSMR_ODD;
2188 if (termios->c_cflag & CSTOPB)
2189 smr_val |= SCSMR_STOP;
2190
154280fd
MD		 2191 /*
2192 * earlyprintk comes here early on with port->uartclk set to zero.
2193 * the clock framework is not up and running at this point so here
2194 * we assume that 115200 is the maximum baud rate. please note that
2195 * the baud rate is not programmed during earlyprintk - it is assumed
2196 * that the previous boot loader has enabled required clocks and
2197 * setup the baud rate generator hardware for us already.
2198 */
f4998e55
GU		 2199 if (!port->uartclk) {
2200 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2201 goto done;
2202 }
1da177e4 2203
f4998e55
GU		 2204 for (i = 0; i < SCI_NUM_CLKS; i++)
2205 max_freq = max(max_freq, s->clk_rates[i]);
2206
69eee8e9 2207 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
f4998e55
GU		 2208 if (!baud)
2209 goto done;
2210
2211 /*
2212 * There can be multiple sources for the sampling clock. Find the one
2213 * that gives us the smallest deviation from the desired baud rate.
2214 */
2215
6af27bf2
GU		 2216 /* Optional Undivided External Clock */
2217 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2218 port->type != PORT_SCIFB) {
2219 err = sci_sck_calc(s, baud, &srr1);
2220 if (abs(err) < abs(min_err)) {
2221 best_clk = SCI_SCK;
2222 scr_val = SCSCR_CKE1;
2223 sccks = SCCKS_CKS;
2224 min_err = err;
2225 srr = srr1;
2226 if (!err)
2227 goto done;
2228 }
2229 }
2230
1270f865
GU		 2231 /* Optional BRG Frequency Divided External Clock */
2232 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2233 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2234 &srr1);
2235 if (abs(err) < abs(min_err)) {
2236 best_clk = SCI_SCIF_CLK;
2237 scr_val = SCSCR_CKE1;
2238 sccks = 0;
2239 min_err = err;
2240 dl = dl1;
2241 srr = srr1;
2242 if (!err)
2243 goto done;
2244 }
2245 }
2246
2247 /* Optional BRG Frequency Divided Internal Clock */
2248 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2249 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2250 &srr1);
2251 if (abs(err) < abs(min_err)) {
2252 best_clk = SCI_BRG_INT;
2253 scr_val = SCSCR_CKE1;
2254 sccks = SCCKS_XIN;
2255 min_err = err;
2256 dl = dl1;
2257 srr = srr1;
2258 if (!min_err)
2259 goto done;
f303b364
UH		 2260 }
2261 }
e108b2ca 2262
f4998e55
GU		 2263 /* Divided Functional Clock using standard Bit Rate Register */
2264 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2265 if (abs(err) < abs(min_err)) {
2266 best_clk = SCI_FCK;
6af27bf2 2267 scr_val = 0;
f4998e55
GU		 2268 min_err = err;
2269 brr = brr1;
2270 srr = srr1;
2271 cks = cks1;
2272 }
2273
2274done:
2275 if (best_clk >= 0)
2276 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2277 s->clks[best_clk], baud, min_err);
e108b2ca 2278
23241d43 2279 sci_port_enable(s);
36003386 2280
6af27bf2
GU		 2281 /*
2282 * Program the optional External Baud Rate Generator (BRG) first.
2283 * It controls the mux to select (H)SCK or frequency divided clock.
2284 */
1270f865
GU		 2285 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2286 serial_port_out(port, SCDL, dl);
6af27bf2 2287 serial_port_out(port, SCCKS, sccks);
1270f865 2288 }
1da177e4 2289
1ba76220 2290 sci_reset(port);
1da177e4
LT		 2291
2292 uart_update_timeout(port, termios->c_cflag, baud);
2293
f4998e55 2294 if (best_clk >= 0) {
92a05748
GU		 2295 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2296 switch (srr + 1) {
2297 case 5: smr_val |= SCSMR_SRC_5; break;
2298 case 7: smr_val |= SCSMR_SRC_7; break;
2299 case 11: smr_val |= SCSMR_SRC_11; break;
2300 case 13: smr_val |= SCSMR_SRC_13; break;
2301 case 16: smr_val |= SCSMR_SRC_16; break;
2302 case 17: smr_val |= SCSMR_SRC_17; break;
2303 case 19: smr_val |= SCSMR_SRC_19; break;
2304 case 27: smr_val |= SCSMR_SRC_27; break;
2305 }
f4998e55 2306 smr_val |= cks;
6af27bf2 2307 dev_dbg(port->dev,
1270f865
GU		 2308 "SCR 0x%x SMR 0x%x BRR %u CKS 0x%x DL %u SRR %u\n",
2309 scr_val, smr_val, brr, sccks, dl, srr);
6af27bf2 2310 serial_port_out(port, SCSCR, scr_val);
f4998e55
GU		 2311 serial_port_out(port, SCSMR, smr_val);
2312 serial_port_out(port, SCBRR, brr);
2313 if (sci_getreg(port, HSSRR)->size)
f303b364 2314 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
f4998e55
GU		 2315
2316 /* Wait one bit interval */
2317 udelay((1000000 + (baud - 1)) / baud);
2318 } else {
2319 /* Don't touch the bit rate configuration */
2320 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
3a964abe
GU		 2321 smr_val |= serial_port_in(port, SCSMR) &
2322 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
f4998e55
GU		 2323 dev_dbg(port->dev, "SCR 0x%x SMR 0x%x\n", scr_val, smr_val);
2324 serial_port_out(port, SCSCR, scr_val);
9d482cc3 2325 serial_port_out(port, SCSMR, smr_val);
f4998e55 2326 }
1da177e4 2327
d5701647 2328 sci_init_pins(port, termios->c_cflag);
0979e0e6 2329
33f50ffc
GU		 2330 port->status &= ~UPSTAT_AUTOCTS;
2331 s->autorts = false;
73c3d53f
PM		 2332 reg = sci_getreg(port, SCFCR);
2333 if (reg->size) {
b12bb29f 2334 unsigned short ctrl = serial_port_in(port, SCFCR);
0979e0e6 2335
33f50ffc
GU		 2336 if ((port->flags & UPF_HARD_FLOW) &&
2337 (termios->c_cflag & CRTSCTS)) {
2338 /* There is no CTS interrupt to restart the hardware */
2339 port->status |= UPSTAT_AUTOCTS;
2340 /* MCE is enabled when RTS is raised */
2341 s->autorts = true;
faf02f8f 2342 }
73c3d53f
PM		 2343
2344 /*
2345 * As we've done a sci_reset() above, ensure we don't
2346 * interfere with the FIFOs while toggling MCE. As the
2347 * reset values could still be set, simply mask them out.
2348 */
2349 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2350
b12bb29f 2351 serial_port_out(port, SCFCR, ctrl);
0979e0e6 2352 }
b7a76e4b 2353
f4998e55
GU		 2354 scr_val |= s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0);
2355 dev_dbg(port->dev, "SCSCR 0x%x\n", scr_val);
2356 serial_port_out(port, SCSCR, scr_val);
92a05748
GU		 2357 if ((srr + 1 == 5) &&
2358 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2359 /*
2360 * In asynchronous mode, when the sampling rate is 1/5, first
2361 * received data may become invalid on some SCIFA and SCIFB.
2362 * To avoid this problem wait more than 1 serial data time (1
2363 * bit time x serial data number) after setting SCSCR.RE = 1.
2364 */
2365 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2366 }
1da177e4 2367
3089f381
GL		 2368#ifdef CONFIG_SERIAL_SH_SCI_DMA
2369 /*
5f6d8515 2370 * Calculate delay for 2 DMA buffers (4 FIFO).
f5835c1d
GU		 2371 * See serial_core.c::uart_update_timeout().
2372 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2373 * function calculates 1 jiffie for the data plus 5 jiffies for the
2374 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2375 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2376 * value obtained by this formula is too small. Therefore, if the value
2377 * is smaller than 20ms, use 20ms as the timeout value for DMA.
3089f381
GL		 2378 */
2379 if (s->chan_rx) {
5f6d8515
NI		 2380 unsigned int bits;
2381
2382 /* byte size and parity */
2383 switch (termios->c_cflag & CSIZE) {
2384 case CS5:
2385 bits = 7;
2386 break;
2387 case CS6:
2388 bits = 8;
2389 break;
2390 case CS7:
2391 bits = 9;
2392 break;
2393 default:
2394 bits = 10;
2395 break;
2396 }
2397
2398 if (termios->c_cflag & CSTOPB)
2399 bits++;
2400 if (termios->c_cflag & PARENB)
2401 bits++;
2402 s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) /
2403 (baud / 10), 10);
9b971cd2 2404 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
3089f381
GL		 2405 s->rx_timeout * 1000 / HZ, port->timeout);
2406 if (s->rx_timeout < msecs_to_jiffies(20))
2407 s->rx_timeout = msecs_to_jiffies(20);
2408 }
2409#endif
2410
1da177e4 2411 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 2412 sci_start_rx(port);
36003386 2413
23241d43 2414 sci_port_disable(s);
f907c9ea
GU		 2415
2416 if (UART_ENABLE_MS(port, termios->c_cflag))
2417 sci_enable_ms(port);
1da177e4
LT		 2418}
2419
0174e5ca
TK		 2420static void sci_pm(struct uart_port *port, unsigned int state,
2421 unsigned int oldstate)
2422{
2423 struct sci_port *sci_port = to_sci_port(port);
2424
2425 switch (state) {
d3dfe5d9 2426 case UART_PM_STATE_OFF:
0174e5ca
TK		 2427 sci_port_disable(sci_port);
2428 break;
2429 default:
2430 sci_port_enable(sci_port);
2431 break;
2432 }
2433}
2434
1da177e4
LT		 2435static const char *sci_type(struct uart_port *port)
2436{
2437 switch (port->type) {
e7c98dc7
MT		 2438 case PORT_IRDA:
2439 return "irda";
2440 case PORT_SCI:
2441 return "sci";
2442 case PORT_SCIF:
2443 return "scif";
2444 case PORT_SCIFA:
2445 return "scifa";
d1d4b10c
GL		 2446 case PORT_SCIFB:
2447 return "scifb";
f303b364
UH		 2448 case PORT_HSCIF:
2449 return "hscif";
1da177e4
LT		 2450 }
2451
fa43972f 2452 return NULL;
1da177e4
LT		 2453}
2454
f6e9495d
PM		 2455static int sci_remap_port(struct uart_port *port)
2456{
e4d6f911 2457 struct sci_port *sport = to_sci_port(port);
f6e9495d
PM		 2458
2459 /*
2460 * Nothing to do if there's already an established membase.
2461 */
2462 if (port->membase)
2463 return 0;
2464
2465 if (port->flags & UPF_IOREMAP) {
e4d6f911 2466 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
f6e9495d
PM		 2467 if (unlikely(!port->membase)) {
2468 dev_err(port->dev, "can't remap port#%d\n", port->line);
2469 return -ENXIO;
2470 }
2471 } else {
2472 /*
2473 * For the simple (and majority of) cases where we don't
2474 * need to do any remapping, just cast the cookie
2475 * directly.
2476 */
3af4e960 2477 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
f6e9495d
PM		 2478 }
2479
2480 return 0;
2481}
2482
e2651647 2483static void sci_release_port(struct uart_port *port)
1da177e4 2484{
e4d6f911
YS		 2485 struct sci_port *sport = to_sci_port(port);
2486
e2651647
PM		 2487 if (port->flags & UPF_IOREMAP) {
2488 iounmap(port->membase);
2489 port->membase = NULL;
2490 }
2491
e4d6f911 2492 release_mem_region(port->mapbase, sport->reg_size);
1da177e4
LT		 2493}
2494
e2651647 2495static int sci_request_port(struct uart_port *port)
1da177e4 2496{
e2651647 2497 struct resource *res;
e4d6f911 2498 struct sci_port *sport = to_sci_port(port);
f6e9495d 2499 int ret;
1da177e4 2500
e4d6f911
YS		 2501 res = request_mem_region(port->mapbase, sport->reg_size,
2502 dev_name(port->dev));
2503 if (unlikely(res == NULL)) {
2504 dev_err(port->dev, "request_mem_region failed.");
e2651647 2505 return -EBUSY;
e4d6f911 2506 }
1da177e4 2507
f6e9495d
PM		 2508 ret = sci_remap_port(port);
2509 if (unlikely(ret != 0)) {
2510 release_resource(res);
2511 return ret;
7ff731ae 2512 }
e2651647
PM		 2513
2514 return 0;
2515}
2516
2517static void sci_config_port(struct uart_port *port, int flags)
2518{
2519 if (flags & UART_CONFIG_TYPE) {
2520 struct sci_port *sport = to_sci_port(port);
2521
2522 port->type = sport->cfg->type;
2523 sci_request_port(port);
2524 }
1da177e4
LT		 2525}
2526
2527static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2528{
1da177e4
LT		 2529 if (ser->baud_base < 2400)
2530 /* No paper tape reader for Mitch.. */
2531 return -EINVAL;
2532
2533 return 0;
2534}
2535
069a47e5 2536static const struct uart_ops sci_uart_ops = {
1da177e4
LT		 2537 .tx_empty = sci_tx_empty,
2538 .set_mctrl = sci_set_mctrl,
2539 .get_mctrl = sci_get_mctrl,
2540 .start_tx = sci_start_tx,
2541 .stop_tx = sci_stop_tx,
2542 .stop_rx = sci_stop_rx,
f907c9ea 2543 .enable_ms = sci_enable_ms,
1da177e4
LT		 2544 .break_ctl = sci_break_ctl,
2545 .startup = sci_startup,
2546 .shutdown = sci_shutdown,
2547 .set_termios = sci_set_termios,
0174e5ca 2548 .pm = sci_pm,
1da177e4
LT		 2549 .type = sci_type,
2550 .release_port = sci_release_port,
2551 .request_port = sci_request_port,
2552 .config_port = sci_config_port,
2553 .verify_port = sci_verify_port,
07d2a1a1
PM		 2554#ifdef CONFIG_CONSOLE_POLL
2555 .poll_get_char = sci_poll_get_char,
2556 .poll_put_char = sci_poll_put_char,
2557#endif
1da177e4
LT		 2558};
2559
a9ec81f4
LP		 2560static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2561{
f4998e55
GU		 2562 const char *clk_names[] = {
2563 [SCI_FCK] = "fck",
6af27bf2 2564 [SCI_SCK] = "sck",
1270f865
GU		 2565 [SCI_BRG_INT] = "brg_int",
2566 [SCI_SCIF_CLK] = "scif_clk",
f4998e55
GU		 2567 };
2568 struct clk *clk;
2569 unsigned int i;
a9ec81f4 2570
6af27bf2
GU		 2571 if (sci_port->cfg->type == PORT_HSCIF)
2572 clk_names[SCI_SCK] = "hsck";
2573
f4998e55
GU		 2574 for (i = 0; i < SCI_NUM_CLKS; i++) {
2575 clk = devm_clk_get(dev, clk_names[i]);
2576 if (PTR_ERR(clk) == -EPROBE_DEFER)
2577 return -EPROBE_DEFER;
a9ec81f4 2578
f4998e55
GU		 2579 if (IS_ERR(clk) && i == SCI_FCK) {
2580 /*
2581 * "fck" used to be called "sci_ick", and we need to
2582 * maintain DT backward compatibility.
2583 */
2584 clk = devm_clk_get(dev, "sci_ick");
2585 if (PTR_ERR(clk) == -EPROBE_DEFER)
2586 return -EPROBE_DEFER;
a9ec81f4 2587
f4998e55
GU		 2588 if (!IS_ERR(clk))
2589 goto found;
a9ec81f4 2590
f4998e55
GU		 2591 /*
2592 * Not all SH platforms declare a clock lookup entry
2593 * for SCI devices, in which case we need to get the
2594 * global "peripheral_clk" clock.
2595 */
2596 clk = devm_clk_get(dev, "peripheral_clk");
2597 if (!IS_ERR(clk))
2598 goto found;
2599
2600 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i],
2601 PTR_ERR(clk));
2602 return PTR_ERR(clk);
2603 }
2604
2605found:
2606 if (IS_ERR(clk))
2607 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i],
2608 PTR_ERR(clk));
2609 else
2610 dev_dbg(dev, "clk %s is %pC rate %pCr\n", clk_names[i],
2611 clk, clk);
2612 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
2613 }
2614 return 0;
a9ec81f4
LP		 2615}
2616
9671f099 2617static int sci_init_single(struct platform_device *dev,
1fcc91a6
LP		 2618 struct sci_port *sci_port, unsigned int index,
2619 struct plat_sci_port *p, bool early)
e108b2ca 2620{
73a19e4c 2621 struct uart_port *port = &sci_port->port;
1fcc91a6
LP		 2622 const struct resource *res;
2623 unsigned int i;
3127c6b2 2624 int ret;
e108b2ca 2625
50f0959a
PM		 2626 sci_port->cfg = p;
2627
73a19e4c
GL		 2628 port->ops = &sci_uart_ops;
2629 port->iotype = UPIO_MEM;
2630 port->line = index;
75136d48 2631
89b5c1ab
LP		 2632 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2633 if (res == NULL)
2634 return -ENOMEM;
1fcc91a6 2635
89b5c1ab 2636 port->mapbase = res->start;
e4d6f911 2637 sci_port->reg_size = resource_size(res);
1fcc91a6 2638
89b5c1ab
LP		 2639 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2640 sci_port->irqs[i] = platform_get_irq(dev, i);
1fcc91a6 2641
89b5c1ab
LP		 2642 /* The SCI generates several interrupts. They can be muxed together or
2643 * connected to different interrupt lines. In the muxed case only one
2644 * interrupt resource is specified. In the non-muxed case three or four
2645 * interrupt resources are specified, as the BRI interrupt is optional.
2646 */
2647 if (sci_port->irqs[0] < 0)
2648 return -ENXIO;
1fcc91a6 2649
89b5c1ab
LP		 2650 if (sci_port->irqs[1] < 0) {
2651 sci_port->irqs[1] = sci_port->irqs[0];
2652 sci_port->irqs[2] = sci_port->irqs[0];
2653 sci_port->irqs[3] = sci_port->irqs[0];
1fcc91a6
LP		 2654 }
2655
b545e4f4
LP		 2656 if (p->regtype == SCIx_PROBE_REGTYPE) {
2657 ret = sci_probe_regmap(p);
2658 if (unlikely(ret))
2659 return ret;
2660 }
2661
75136d48 2662 switch (p->type) {
d1d4b10c
GL		 2663 case PORT_SCIFB:
2664 port->fifosize = 256;
2e0842a1 2665 sci_port->overrun_reg = SCxSR;
75c249fd 2666 sci_port->overrun_mask = SCIFA_ORER;
92a05748 2667 sci_port->sampling_rate_mask = SCI_SR_SCIFAB;
d1d4b10c 2668 break;
f303b364
UH		 2669 case PORT_HSCIF:
2670 port->fifosize = 128;
2e0842a1 2671 sci_port->overrun_reg = SCLSR;
75c249fd 2672 sci_port->overrun_mask = SCLSR_ORER;
69eee8e9 2673 sci_port->sampling_rate_mask = SCI_SR_RANGE(8, 32);
f303b364 2674 break;
75136d48 2675 case PORT_SCIFA:
73a19e4c 2676 port->fifosize = 64;
2e0842a1 2677 sci_port->overrun_reg = SCxSR;
75c249fd 2678 sci_port->overrun_mask = SCIFA_ORER;
92a05748 2679 sci_port->sampling_rate_mask = SCI_SR_SCIFAB;
75136d48
MP		 2680 break;
2681 case PORT_SCIF:
73a19e4c 2682 port->fifosize = 16;
ec09c5eb 2683 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2e0842a1 2684 sci_port->overrun_reg = SCxSR;
75c249fd 2685 sci_port->overrun_mask = SCIFA_ORER;
69eee8e9 2686 sci_port->sampling_rate_mask = SCI_SR(16);
ec09c5eb 2687 } else {
2e0842a1 2688 sci_port->overrun_reg = SCLSR;
75c249fd 2689 sci_port->overrun_mask = SCLSR_ORER;
69eee8e9 2690 sci_port->sampling_rate_mask = SCI_SR(32);
ec09c5eb 2691 }
75136d48
MP		 2692 break;
2693 default:
73a19e4c 2694 port->fifosize = 1;
2e0842a1 2695 sci_port->overrun_reg = SCxSR;
75c249fd 2696 sci_port->overrun_mask = SCI_ORER;
69eee8e9 2697 sci_port->sampling_rate_mask = SCI_SR(32);
75136d48
MP		 2698 break;
2699 }
7b6fd3bf 2700
878fbb91
LP		 2701 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2702 * match the SoC datasheet, this should be investigated. Let platform
2703 * data override the sampling rate for now.
ec09c5eb 2704 */
f84b6bdc 2705 if (p->sampling_rate)
69eee8e9 2706 sci_port->sampling_rate_mask = SCI_SR(p->sampling_rate);
ec09c5eb 2707
1fcc91a6 2708 if (!early) {
a9ec81f4
LP		 2709 ret = sci_init_clocks(sci_port, &dev->dev);
2710 if (ret < 0)
2711 return ret;
c7ed1ab3 2712
73a19e4c 2713 port->dev = &dev->dev;
5e50d2d6
MD		 2714
2715 pm_runtime_enable(&dev->dev);
7b6fd3bf 2716 }
e108b2ca 2717
7ed7e071
MD		 2718 sci_port->break_timer.data = (unsigned long)sci_port;
2719 sci_port->break_timer.function = sci_break_timer;
2720 init_timer(&sci_port->break_timer);
2721
debf9507
PM		 2722 /*
2723 * Establish some sensible defaults for the error detection.
2724 */
5da0f468
GU		 2725 if (p->type == PORT_SCI) {
2726 sci_port->error_mask = SCI_DEFAULT_ERROR_MASK;
2727 sci_port->error_clear = SCI_ERROR_CLEAR;
2728 } else {
2729 sci_port->error_mask = SCIF_DEFAULT_ERROR_MASK;
2730 sci_port->error_clear = SCIF_ERROR_CLEAR;
2731 }
debf9507 2732
3ae988d9
LP		 2733 /*
2734 * Make the error mask inclusive of overrun detection, if
2735 * supported.
2736 */
5da0f468 2737 if (sci_port->overrun_reg == SCxSR) {
afd66db6 2738 sci_port->error_mask |= sci_port->overrun_mask;
5da0f468
GU		 2739 sci_port->error_clear &= ~sci_port->overrun_mask;
2740 }
debf9507 2741
ce6738b6 2742 port->type = p->type;
b6e4a3f1 2743 port->flags = UPF_FIXED_PORT | p->flags;
61a6976b 2744 port->regshift = p->regshift;
73a19e4c 2745
ce6738b6 2746 /*
61a6976b 2747 * The UART port needs an IRQ value, so we peg this to the RX IRQ
ce6738b6
PM		 2748 * for the multi-IRQ ports, which is where we are primarily
2749 * concerned with the shutdown path synchronization.
2750 *
2751 * For the muxed case there's nothing more to do.
2752 */
1fcc91a6 2753 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
9cfb5c05 2754 port->irqflags = 0;
73a19e4c 2755
61a6976b
PM		 2756 port->serial_in = sci_serial_in;
2757 port->serial_out = sci_serial_out;
2758
937bb6e4
GL		 2759 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2760 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2761 p->dma_slave_tx, p->dma_slave_rx);
7ed7e071 2762
c7ed1ab3 2763 return 0;
e108b2ca
PM		 2764}
2765
6dae1421
LP		 2766static void sci_cleanup_single(struct sci_port *port)
2767{
6dae1421
LP		 2768 pm_runtime_disable(port->port.dev);
2769}
2770
0b0cced1
YS		 2771#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
2772 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
dc8e6f5b
MD		 2773static void serial_console_putchar(struct uart_port *port, int ch)
2774{
2775 sci_poll_put_char(port, ch);
2776}
2777
1da177e4
LT		 2778/*
2779 * Print a string to the serial port trying not to disturb
2780 * any possible real use of the port...
2781 */
2782static void serial_console_write(struct console *co, const char *s,
2783 unsigned count)
2784{
906b17dc
PM		 2785 struct sci_port *sci_port = &sci_ports[co->index];
2786 struct uart_port *port = &sci_port->port;
a67969b5 2787 unsigned short bits, ctrl, ctrl_temp;
40f70c03
SK		 2788 unsigned long flags;
2789 int locked = 1;
2790
2791 local_irq_save(flags);
0b0cced1 2792#if defined(SUPPORT_SYSRQ)
40f70c03
SK		 2793 if (port->sysrq)
2794 locked = 0;
0b0cced1
YS		 2795 else
2796#endif
2797 if (oops_in_progress)
40f70c03
SK		 2798 locked = spin_trylock(&port->lock);
2799 else
2800 spin_lock(&port->lock);
2801
a67969b5 2802 /* first save SCSCR then disable interrupts, keep clock source */
40f70c03 2803 ctrl = serial_port_in(port, SCSCR);
a67969b5
GU		 2804 ctrl_temp = (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
2805 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
2806 serial_port_out(port, SCSCR, ctrl_temp);
07d2a1a1 2807
501b825d 2808 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 2809
2810 /* wait until fifo is empty and last bit has been transmitted */
2811 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
b12bb29f 2812 while ((serial_port_in(port, SCxSR) & bits) != bits)
973e5d52 2813 cpu_relax();
40f70c03
SK		 2814
2815 /* restore the SCSCR */
2816 serial_port_out(port, SCSCR, ctrl);
2817
2818 if (locked)
2819 spin_unlock(&port->lock);
2820 local_irq_restore(flags);
1da177e4
LT		 2821}
2822
9671f099 2823static int serial_console_setup(struct console *co, char *options)
1da177e4 2824{
dc8e6f5b 2825 struct sci_port *sci_port;
1da177e4
LT		 2826 struct uart_port *port;
2827 int baud = 115200;
2828 int bits = 8;
2829 int parity = 'n';
2830 int flow = 'n';
2831 int ret;
2832
e108b2ca 2833 /*
906b17dc 2834 * Refuse to handle any bogus ports.
1da177e4 2835 */
906b17dc 2836 if (co->index < 0 || co->index >= SCI_NPORTS)
e108b2ca 2837 return -ENODEV;
e108b2ca 2838
906b17dc
PM		 2839 sci_port = &sci_ports[co->index];
2840 port = &sci_port->port;
2841
b2267a6b
AC		 2842 /*
2843 * Refuse to handle uninitialized ports.
2844 */
2845 if (!port->ops)
2846 return -ENODEV;
2847
f6e9495d
PM		 2848 ret = sci_remap_port(port);
2849 if (unlikely(ret != 0))
2850 return ret;
e108b2ca 2851
1da177e4
LT		 2852 if (options)
2853 uart_parse_options(options, &baud, &parity, &bits, &flow);
2854
ab7cfb55 2855 return uart_set_options(port, co, baud, parity, bits, flow);
1da177e4
LT		 2856}
2857
2858static struct console serial_console = {
2859 .name = "ttySC",
906b17dc 2860 .device = uart_console_device,
1da177e4
LT		 2861 .write = serial_console_write,
2862 .setup = serial_console_setup,
fa5da2f7 2863 .flags = CON_PRINTBUFFER,
1da177e4 2864 .index = -1,
906b17dc 2865 .data = &sci_uart_driver,
1da177e4
LT		 2866};
2867
7b6fd3bf
MD		 2868static struct console early_serial_console = {
2869 .name = "early_ttySC",
2870 .write = serial_console_write,
2871 .flags = CON_PRINTBUFFER,
906b17dc 2872 .index = -1,
7b6fd3bf 2873};
ecdf8a46 2874
7b6fd3bf
MD		 2875static char early_serial_buf[32];
2876
9671f099 2877static int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46 2878{
574de559 2879 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
ecdf8a46
PM		 2880
2881 if (early_serial_console.data)
2882 return -EEXIST;
2883
2884 early_serial_console.index = pdev->id;
ecdf8a46 2885
1fcc91a6 2886 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
ecdf8a46
PM		 2887
2888 serial_console_setup(&early_serial_console, early_serial_buf);
2889
2890 if (!strstr(early_serial_buf, "keep"))
2891 early_serial_console.flags |= CON_BOOT;
2892
2893 register_console(&early_serial_console);
2894 return 0;
2895}
6a8c9799
NI		 2896
2897#define SCI_CONSOLE (&serial_console)
2898
ecdf8a46 2899#else
9671f099 2900static inline int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46
PM		 2901{
2902 return -EINVAL;
2903}
1da177e4 2904
6a8c9799
NI		 2905#define SCI_CONSOLE NULL
2906
0b0cced1 2907#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
1da177e4 2908
6c13d5d2 2909static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
1da177e4
LT		 2910
2911static struct uart_driver sci_uart_driver = {
2912 .owner = THIS_MODULE,
2913 .driver_name = "sci",
1da177e4
LT		 2914 .dev_name = "ttySC",
2915 .major = SCI_MAJOR,
2916 .minor = SCI_MINOR_START,
e108b2ca 2917 .nr = SCI_NPORTS,
1da177e4
LT		 2918 .cons = SCI_CONSOLE,
2919};
2920
54507f6e 2921static int sci_remove(struct platform_device *dev)
e552de24 2922{
d535a230 2923 struct sci_port *port = platform_get_drvdata(dev);
e552de24 2924
d535a230
PM		 2925 uart_remove_one_port(&sci_uart_driver, &port->port);
2926
6dae1421 2927 sci_cleanup_single(port);
e552de24 2928
e552de24
MD		 2929 return 0;
2930}
2931
bd2238fb
GU		 2932
2933#define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
2934#define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
2935#define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
20bdcab8
BH		 2936
2937static const struct of_device_id of_sci_match[] = {
f443ff80
GU		 2938 /* SoC-specific types */
2939 {
2940 .compatible = "renesas,scif-r7s72100",
2941 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
2942 },
9ed44bb2
GU		 2943 /* Family-specific types */
2944 {
2945 .compatible = "renesas,rcar-gen1-scif",
2946 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2947 }, {
2948 .compatible = "renesas,rcar-gen2-scif",
2949 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2950 }, {
2951 .compatible = "renesas,rcar-gen3-scif",
2952 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2953 },
f443ff80 2954 /* Generic types */
20bdcab8
BH		 2955 {
2956 .compatible = "renesas,scif",
bd2238fb 2957 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
20bdcab8
BH		 2958 }, {
2959 .compatible = "renesas,scifa",
bd2238fb 2960 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
20bdcab8
BH		 2961 }, {
2962 .compatible = "renesas,scifb",
bd2238fb 2963 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
20bdcab8
BH		 2964 }, {
2965 .compatible = "renesas,hscif",
bd2238fb 2966 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
e1d0be61
YS		 2967 }, {
2968 .compatible = "renesas,sci",
bd2238fb 2969 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
20bdcab8
BH		 2970 }, {
2971 /* Terminator */
2972 },
2973};
2974MODULE_DEVICE_TABLE(of, of_sci_match);
2975
2976static struct plat_sci_port *
2977sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2978{
2979 struct device_node *np = pdev->dev.of_node;
2980 const struct of_device_id *match;
20bdcab8
BH		 2981 struct plat_sci_port *p;
2982 int id;
2983
2984 if (!IS_ENABLED(CONFIG_OF) || !np)
2985 return NULL;
2986
495bb47c 2987 match = of_match_node(of_sci_match, np);
20bdcab8
BH		 2988 if (!match)
2989 return NULL;
2990
20bdcab8 2991 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
4205463c 2992 if (!p)
20bdcab8 2993 return NULL;
20bdcab8 2994
2095fc76 2995 /* Get the line number from the aliases node. */
20bdcab8
BH		 2996 id = of_alias_get_id(np, "serial");
2997 if (id < 0) {
2998 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2999 return NULL;
3000 }
3001
3002 *dev_id = id;
3003
3004 p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
bd2238fb
GU		 3005 p->type = SCI_OF_TYPE(match->data);
3006 p->regtype = SCI_OF_REGTYPE(match->data);
20bdcab8
BH		 3007 p->scscr = SCSCR_RE | SCSCR_TE;
3008
861a70ab
GU		 3009 if (of_find_property(np, "uart-has-rtscts", NULL))
3010 p->capabilities |= SCIx_HAVE_RTSCTS;
3011
20bdcab8
BH		 3012 return p;
3013}
3014
9671f099 3015static int sci_probe_single(struct platform_device *dev,
0ee70712
MD		 3016 unsigned int index,
3017 struct plat_sci_port *p,
3018 struct sci_port *sciport)
3019{
0ee70712
MD		 3020 int ret;
3021
3022 /* Sanity check */
3023 if (unlikely(index >= SCI_NPORTS)) {
9b971cd2 3024 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
0ee70712 3025 index+1, SCI_NPORTS);
9b971cd2 3026 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
b6c5ef6f 3027 return -EINVAL;
0ee70712
MD		 3028 }
3029
1fcc91a6 3030 ret = sci_init_single(dev, sciport, index, p, false);
c7ed1ab3
PM		 3031 if (ret)
3032 return ret;
0ee70712 3033
f907c9ea
GU		 3034 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3035 if (IS_ERR(sciport->gpios) && PTR_ERR(sciport->gpios) != -ENOSYS)
3036 return PTR_ERR(sciport->gpios);
3037
3038 if (p->capabilities & SCIx_HAVE_RTSCTS) {
3039 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3040 UART_GPIO_CTS)) ||
3041 !IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3042 UART_GPIO_RTS))) {
3043 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3044 return -EINVAL;
3045 }
33f50ffc 3046 sciport->port.flags |= UPF_HARD_FLOW;
f907c9ea
GU		 3047 }
3048
6dae1421
LP		 3049 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
3050 if (ret) {
3051 sci_cleanup_single(sciport);
3052 return ret;
3053 }
3054
3055 return 0;
0ee70712
MD		 3056}
3057
9671f099 3058static int sci_probe(struct platform_device *dev)
1da177e4 3059{
20bdcab8
BH		 3060 struct plat_sci_port *p;
3061 struct sci_port *sp;
3062 unsigned int dev_id;
ecdf8a46 3063 int ret;
d535a230 3064
ecdf8a46
PM		 3065 /*
3066 * If we've come here via earlyprintk initialization, head off to
3067 * the special early probe. We don't have sufficient device state
3068 * to make it beyond this yet.
3069 */
3070 if (is_early_platform_device(dev))
3071 return sci_probe_earlyprintk(dev);
7b6fd3bf 3072
20bdcab8
BH		 3073 if (dev->dev.of_node) {
3074 p = sci_parse_dt(dev, &dev_id);
3075 if (p == NULL)
3076 return -EINVAL;
3077 } else {
3078 p = dev->dev.platform_data;
3079 if (p == NULL) {
3080 dev_err(&dev->dev, "no platform data supplied\n");
3081 return -EINVAL;
3082 }
3083
3084 dev_id = dev->id;
3085 }
3086
3087 sp = &sci_ports[dev_id];
d535a230 3088 platform_set_drvdata(dev, sp);
e552de24 3089
20bdcab8 3090 ret = sci_probe_single(dev, dev_id, p, sp);
d535a230 3091 if (ret)
6dae1421 3092 return ret;
e552de24 3093
1da177e4
LT		 3094#ifdef CONFIG_SH_STANDARD_BIOS
3095 sh_bios_gdb_detach();
3096#endif
3097
e108b2ca 3098 return 0;
1da177e4
LT		 3099}
3100
cb876341 3101static __maybe_unused int sci_suspend(struct device *dev)
1da177e4 3102{
d535a230 3103 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 3104
d535a230
PM		 3105 if (sport)
3106 uart_suspend_port(&sci_uart_driver, &sport->port);
1da177e4 3107
e108b2ca
PM		 3108 return 0;
3109}
1da177e4 3110
cb876341 3111static __maybe_unused int sci_resume(struct device *dev)
e108b2ca 3112{
d535a230 3113 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 3114
d535a230
PM		 3115 if (sport)
3116 uart_resume_port(&sci_uart_driver, &sport->port);
e108b2ca
PM		 3117
3118 return 0;
3119}
3120
cb876341 3121static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
6daa79b3 3122
e108b2ca
PM		 3123static struct platform_driver sci_driver = {
3124 .probe = sci_probe,
b9e39c89 3125 .remove = sci_remove,
e108b2ca
PM		 3126 .driver = {
3127 .name = "sh-sci",
6daa79b3 3128 .pm = &sci_dev_pm_ops,
20bdcab8 3129 .of_match_table = of_match_ptr(of_sci_match),
e108b2ca
PM		 3130 },
3131};
3132
3133static int __init sci_init(void)
3134{
3135 int ret;
3136
6c13d5d2 3137 pr_info("%s\n", banner);
e108b2ca 3138
e108b2ca
PM		 3139 ret = uart_register_driver(&sci_uart_driver);
3140 if (likely(ret == 0)) {
3141 ret = platform_driver_register(&sci_driver);
3142 if (unlikely(ret))
3143 uart_unregister_driver(&sci_uart_driver);
3144 }
3145
3146 return ret;
3147}
3148
3149static void __exit sci_exit(void)
3150{
3151 platform_driver_unregister(&sci_driver);
1da177e4
LT		 3152 uart_unregister_driver(&sci_uart_driver);
3153}
3154
7b6fd3bf
MD		 3155#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
3156early_platform_init_buffer("earlyprintk", &sci_driver,
3157 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3158#endif
0b0cced1
YS		 3159#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
3160static struct __init plat_sci_port port_cfg;
3161
3162static int __init early_console_setup(struct earlycon_device *device,
3163 int type)
3164{
3165 if (!device->port.membase)
3166 return -ENODEV;
3167
3168 device->port.serial_in = sci_serial_in;
3169 device->port.serial_out = sci_serial_out;
3170 device->port.type = type;
3171 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
3172 sci_ports[0].cfg = &port_cfg;
3173 sci_ports[0].cfg->type = type;
3174 sci_probe_regmap(sci_ports[0].cfg);
3175 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR) |
3176 SCSCR_RE | SCSCR_TE;
3177 sci_serial_out(&sci_ports[0].port, SCSCR, port_cfg.scscr);
3178
3179 device->con->write = serial_console_write;
3180 return 0;
3181}
3182static int __init sci_early_console_setup(struct earlycon_device *device,
3183 const char *opt)
3184{
3185 return early_console_setup(device, PORT_SCI);
3186}
3187static int __init scif_early_console_setup(struct earlycon_device *device,
3188 const char *opt)
3189{
3190 return early_console_setup(device, PORT_SCIF);
3191}
3192static int __init scifa_early_console_setup(struct earlycon_device *device,
3193 const char *opt)
3194{
3195 return early_console_setup(device, PORT_SCIFA);
3196}
3197static int __init scifb_early_console_setup(struct earlycon_device *device,
3198 const char *opt)
3199{
3200 return early_console_setup(device, PORT_SCIFB);
3201}
3202static int __init hscif_early_console_setup(struct earlycon_device *device,
3203 const char *opt)
3204{
3205 return early_console_setup(device, PORT_HSCIF);
3206}
3207
0b0cced1 3208OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
0b0cced1 3209OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
0b0cced1 3210OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
0b0cced1 3211OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
0b0cced1
YS		 3212OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3213#endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3214
1da177e4
LT		 3215module_init(sci_init);
3216module_exit(sci_exit);
3217
e108b2ca 3218MODULE_LICENSE("GPL");
e169c139 3219MODULE_ALIAS("platform:sh-sci");
7f405f9c 3220MODULE_AUTHOR("Paul Mundt");
f303b364 3221MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git