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serial: sh-sci: Remove SCIx_RZ_SCIFA_REGTYPE
[thirdparty/kernel/stable.git] / drivers / tty / serial / sh-sci.c
CommitLineData
e3b3d0f5 1// SPDX-License-Identifier: GPL-2.0
1da177e4 2/*
1da177e4
LT		 3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 *
f43dc23d 5 * Copyright (C) 2002 - 2011 Paul Mundt
f4998e55 6 * Copyright (C) 2015 Glider bvba
3ea6bc3d 7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 16 * Removed SH7300 support (Jul 2007).
1da177e4 17 */
0b3d4ef6
PM		 18#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
19#define SUPPORT_SYSRQ
20#endif
1da177e4
LT		 21
22#undef DEBUG
23
8fb9631c
LP		 24#include <linux/clk.h>
25#include <linux/console.h>
26#include <linux/ctype.h>
27#include <linux/cpufreq.h>
28#include <linux/delay.h>
29#include <linux/dmaengine.h>
30#include <linux/dma-mapping.h>
31#include <linux/err.h>
1da177e4 32#include <linux/errno.h>
8fb9631c 33#include <linux/init.h>
1da177e4 34#include <linux/interrupt.h>
1da177e4 35#include <linux/ioport.h>
b96408b4 36#include <linux/ktime.h>
8fb9631c
LP		 37#include <linux/major.h>
38#include <linux/module.h>
1da177e4 39#include <linux/mm.h>
20bdcab8 40#include <linux/of.h>
6e605a01 41#include <linux/of_device.h>
8fb9631c 42#include <linux/platform_device.h>
5e50d2d6 43#include <linux/pm_runtime.h>
73a19e4c 44#include <linux/scatterlist.h>
8fb9631c
LP		 45#include <linux/serial.h>
46#include <linux/serial_sci.h>
47#include <linux/sh_dma.h>
5a0e3ad6 48#include <linux/slab.h>
8fb9631c
LP		 49#include <linux/string.h>
50#include <linux/sysrq.h>
51#include <linux/timer.h>
52#include <linux/tty.h>
53#include <linux/tty_flip.h>
85f094ec
PM		 54
55#ifdef CONFIG_SUPERH
1da177e4
LT		 56#include <asm/sh_bios.h>
57#endif
58
f907c9ea 59#include "serial_mctrl_gpio.h"
1da177e4
LT		 60#include "sh-sci.h"
61
89b5c1ab
LP		 62/* Offsets into the sci_port->irqs array */
63enum {
64 SCIx_ERI_IRQ,
65 SCIx_RXI_IRQ,
66 SCIx_TXI_IRQ,
67 SCIx_BRI_IRQ,
8b0bbd95 68 SCIx_TEIDRI_IRQ,
89b5c1ab
LP		 69 SCIx_NR_IRQS,
70
71 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
72};
73
74#define SCIx_IRQ_IS_MUXED(port) \
75 ((port)->irqs[SCIx_ERI_IRQ] == \
76 (port)->irqs[SCIx_RXI_IRQ]) || \
77 ((port)->irqs[SCIx_ERI_IRQ] && \
78 ((port)->irqs[SCIx_RXI_IRQ] < 0))
79
8b0bbd95
CB		 80#define SCIx_TEIDRI_IRQ_EXISTS(port) \
81 ((port)->irqs[SCIx_TEIDRI_IRQ] > 0)
82
f4998e55
GU		 83enum SCI_CLKS {
84 SCI_FCK, /* Functional Clock */
6af27bf2 85 SCI_SCK, /* Optional External Clock */
1270f865
GU		 86 SCI_BRG_INT, /* Optional BRG Internal Clock Source */
87 SCI_SCIF_CLK, /* Optional BRG External Clock Source */
f4998e55
GU		 88 SCI_NUM_CLKS
89};
90
69eee8e9
GU		 91/* Bit x set means sampling rate x + 1 is supported */
92#define SCI_SR(x) BIT((x) - 1)
93#define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
94
92a05748
GU		 95#define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
96 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
97 SCI_SR(19) | SCI_SR(27)
98
69eee8e9
GU		 99#define min_sr(_port) ffs((_port)->sampling_rate_mask)
100#define max_sr(_port) fls((_port)->sampling_rate_mask)
101
102/* Iterate over all supported sampling rates, from high to low */
103#define for_each_sr(_sr, _port) \
104 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
105 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
106
e095ee6b
LP		 107struct plat_sci_reg {
108 u8 offset, size;
109};
110
111struct sci_port_params {
112 const struct plat_sci_reg regs[SCIx_NR_REGS];
b2f20ed9
LP		 113 unsigned int fifosize;
114 unsigned int overrun_reg;
115 unsigned int overrun_mask;
116 unsigned int sampling_rate_mask;
117 unsigned int error_mask;
118 unsigned int error_clear;
e095ee6b
LP		 119};
120
e108b2ca
PM		 121struct sci_port {
122 struct uart_port port;
123
ce6738b6 124 /* Platform configuration */
e095ee6b 125 const struct sci_port_params *params;
daf5a895 126 const struct plat_sci_port *cfg;
69eee8e9 127 unsigned int sampling_rate_mask;
e4d6f911 128 resource_size_t reg_size;
f907c9ea 129 struct mctrl_gpios *gpios;
e108b2ca 130
f4998e55
GU		 131 /* Clocks */
132 struct clk *clks[SCI_NUM_CLKS];
133 unsigned long clk_rates[SCI_NUM_CLKS];
edad1f20 134
1fcc91a6 135 int irqs[SCIx_NR_IRQS];
9174fc8f
PM		 136 char *irqstr[SCIx_NR_IRQS];
137
73a19e4c
GL		 138 struct dma_chan *chan_tx;
139 struct dma_chan *chan_rx;
f43dc23d 140
73a19e4c 141#ifdef CONFIG_SERIAL_SH_SCI_DMA
2c4ee235
GU		 142 struct dma_chan *chan_tx_saved;
143 struct dma_chan *chan_rx_saved;
73a19e4c
GL		 144 dma_cookie_t cookie_tx;
145 dma_cookie_t cookie_rx[2];
146 dma_cookie_t active_rx;
79904420
GU		 147 dma_addr_t tx_dma_addr;
148 unsigned int tx_dma_len;
73a19e4c 149 struct scatterlist sg_rx[2];
7b39d901 150 void *rx_buf[2];
73a19e4c 151 size_t buf_len_rx;
73a19e4c 152 struct work_struct work_tx;
b96408b4
UH		 153 struct hrtimer rx_timer;
154 unsigned int rx_timeout; /* microseconds */
73a19e4c 155#endif
03940376 156 unsigned int rx_frame;
18e8cf15 157 int rx_trigger;
03940376
UH		 158 struct timer_list rx_fifo_timer;
159 int rx_fifo_timeout;
fa2abb03 160 u16 hscif_tot;
33f50ffc 161
97ed9790 162 bool has_rtscts;
33f50ffc 163 bool autorts;
e108b2ca
PM		 164};
165
e108b2ca 166#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 167
e108b2ca 168static struct sci_port sci_ports[SCI_NPORTS];
7678f4c2 169static unsigned long sci_ports_in_use;
e108b2ca 170static struct uart_driver sci_uart_driver;
1da177e4 171
e7c98dc7
MT		 172static inline struct sci_port *
173to_sci_port(struct uart_port *uart)
174{
175 return container_of(uart, struct sci_port, port);
176}
177
e095ee6b 178static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
61a6976b
PM		 179 /*
180 * Common SCI definitions, dependent on the port's regshift
181 * value.
182 */
183 [SCIx_SCI_REGTYPE] = {
e095ee6b
LP		 184 .regs = {
185 [SCSMR] = { 0x00, 8 },
186 [SCBRR] = { 0x01, 8 },
187 [SCSCR] = { 0x02, 8 },
188 [SCxTDR] = { 0x03, 8 },
189 [SCxSR] = { 0x04, 8 },
190 [SCxRDR] = { 0x05, 8 },
191 },
b2f20ed9
LP		 192 .fifosize = 1,
193 .overrun_reg = SCxSR,
194 .overrun_mask = SCI_ORER,
195 .sampling_rate_mask = SCI_SR(32),
196 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
197 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
61a6976b
PM		 198 },
199
200 /*
a752ba18 201 * Common definitions for legacy IrDA ports.
61a6976b
PM		 202 */
203 [SCIx_IRDA_REGTYPE] = {
e095ee6b
LP		 204 .regs = {
205 [SCSMR] = { 0x00, 8 },
206 [SCBRR] = { 0x02, 8 },
207 [SCSCR] = { 0x04, 8 },
208 [SCxTDR] = { 0x06, 8 },
209 [SCxSR] = { 0x08, 16 },
210 [SCxRDR] = { 0x0a, 8 },
211 [SCFCR] = { 0x0c, 8 },
212 [SCFDR] = { 0x0e, 16 },
213 },
b2f20ed9
LP		 214 .fifosize = 1,
215 .overrun_reg = SCxSR,
216 .overrun_mask = SCI_ORER,
217 .sampling_rate_mask = SCI_SR(32),
218 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
219 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
61a6976b
PM		 220 },
221
222 /*
223 * Common SCIFA definitions.
224 */
225 [SCIx_SCIFA_REGTYPE] = {
e095ee6b
LP		 226 .regs = {
227 [SCSMR] = { 0x00, 16 },
228 [SCBRR] = { 0x04, 8 },
229 [SCSCR] = { 0x08, 16 },
230 [SCxTDR] = { 0x20, 8 },
231 [SCxSR] = { 0x14, 16 },
232 [SCxRDR] = { 0x24, 8 },
233 [SCFCR] = { 0x18, 16 },
234 [SCFDR] = { 0x1c, 16 },
235 [SCPCR] = { 0x30, 16 },
236 [SCPDR] = { 0x34, 16 },
237 },
b2f20ed9
LP		 238 .fifosize = 64,
239 .overrun_reg = SCxSR,
240 .overrun_mask = SCIFA_ORER,
241 .sampling_rate_mask = SCI_SR_SCIFAB,
242 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
243 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
61a6976b
PM		 244 },
245
246 /*
247 * Common SCIFB definitions.
248 */
249 [SCIx_SCIFB_REGTYPE] = {
e095ee6b
LP		 250 .regs = {
251 [SCSMR] = { 0x00, 16 },
252 [SCBRR] = { 0x04, 8 },
253 [SCSCR] = { 0x08, 16 },
254 [SCxTDR] = { 0x40, 8 },
255 [SCxSR] = { 0x14, 16 },
256 [SCxRDR] = { 0x60, 8 },
257 [SCFCR] = { 0x18, 16 },
258 [SCTFDR] = { 0x38, 16 },
259 [SCRFDR] = { 0x3c, 16 },
260 [SCPCR] = { 0x30, 16 },
261 [SCPDR] = { 0x34, 16 },
262 },
b2f20ed9
LP		 263 .fifosize = 256,
264 .overrun_reg = SCxSR,
265 .overrun_mask = SCIFA_ORER,
266 .sampling_rate_mask = SCI_SR_SCIFAB,
267 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
268 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
61a6976b
PM		 269 },
270
3af1f8a4
PE		 271 /*
272 * Common SH-2(A) SCIF definitions for ports with FIFO data
273 * count registers.
274 */
275 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
e095ee6b
LP		 276 .regs = {
277 [SCSMR] = { 0x00, 16 },
278 [SCBRR] = { 0x04, 8 },
279 [SCSCR] = { 0x08, 16 },
280 [SCxTDR] = { 0x0c, 8 },
281 [SCxSR] = { 0x10, 16 },
282 [SCxRDR] = { 0x14, 8 },
283 [SCFCR] = { 0x18, 16 },
284 [SCFDR] = { 0x1c, 16 },
285 [SCSPTR] = { 0x20, 16 },
286 [SCLSR] = { 0x24, 16 },
287 },
b2f20ed9
LP		 288 .fifosize = 16,
289 .overrun_reg = SCLSR,
290 .overrun_mask = SCLSR_ORER,
291 .sampling_rate_mask = SCI_SR(32),
292 .error_mask = SCIF_DEFAULT_ERROR_MASK,
293 .error_clear = SCIF_ERROR_CLEAR,
3af1f8a4
PE		 294 },
295
61a6976b
PM		 296 /*
297 * Common SH-3 SCIF definitions.
298 */
299 [SCIx_SH3_SCIF_REGTYPE] = {
e095ee6b
LP		 300 .regs = {
301 [SCSMR] = { 0x00, 8 },
302 [SCBRR] = { 0x02, 8 },
303 [SCSCR] = { 0x04, 8 },
304 [SCxTDR] = { 0x06, 8 },
305 [SCxSR] = { 0x08, 16 },
306 [SCxRDR] = { 0x0a, 8 },
307 [SCFCR] = { 0x0c, 8 },
308 [SCFDR] = { 0x0e, 16 },
309 },
b2f20ed9
LP		 310 .fifosize = 16,
311 .overrun_reg = SCLSR,
312 .overrun_mask = SCLSR_ORER,
313 .sampling_rate_mask = SCI_SR(32),
314 .error_mask = SCIF_DEFAULT_ERROR_MASK,
315 .error_clear = SCIF_ERROR_CLEAR,
61a6976b
PM		 316 },
317
318 /*
319 * Common SH-4(A) SCIF(B) definitions.
320 */
321 [SCIx_SH4_SCIF_REGTYPE] = {
e095ee6b
LP		 322 .regs = {
323 [SCSMR] = { 0x00, 16 },
2d4dd0da
CB		 324 [SCBRR] = { 0x02, 8 },
325 [SCSCR] = { 0x04, 16 },
326 [SCxTDR] = { 0x06, 8 },
327 [SCxSR] = { 0x08, 16 },
328 [SCxRDR] = { 0x0a, 8 },
329 [SCFCR] = { 0x0c, 16 },
330 [SCFDR] = { 0x0e, 16 },
331 [SCSPTR] = { 0x10, 16 },
332 [SCLSR] = { 0x12, 16 },
e095ee6b 333 },
b2f20ed9
LP		 334 .fifosize = 16,
335 .overrun_reg = SCLSR,
336 .overrun_mask = SCLSR_ORER,
337 .sampling_rate_mask = SCI_SR(32),
338 .error_mask = SCIF_DEFAULT_ERROR_MASK,
339 .error_clear = SCIF_ERROR_CLEAR,
b8bbd6b2
GU		 340 },
341
342 /*
343 * Common SCIF definitions for ports with a Baud Rate Generator for
344 * External Clock (BRG).
345 */
346 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
e095ee6b
LP		 347 .regs = {
348 [SCSMR] = { 0x00, 16 },
349 [SCBRR] = { 0x04, 8 },
350 [SCSCR] = { 0x08, 16 },
351 [SCxTDR] = { 0x0c, 8 },
352 [SCxSR] = { 0x10, 16 },
353 [SCxRDR] = { 0x14, 8 },
354 [SCFCR] = { 0x18, 16 },
355 [SCFDR] = { 0x1c, 16 },
356 [SCSPTR] = { 0x20, 16 },
357 [SCLSR] = { 0x24, 16 },
358 [SCDL] = { 0x30, 16 },
359 [SCCKS] = { 0x34, 16 },
360 },
b2f20ed9
LP		 361 .fifosize = 16,
362 .overrun_reg = SCLSR,
363 .overrun_mask = SCLSR_ORER,
364 .sampling_rate_mask = SCI_SR(32),
365 .error_mask = SCIF_DEFAULT_ERROR_MASK,
366 .error_clear = SCIF_ERROR_CLEAR,
f303b364
UH		 367 },
368
369 /*
370 * Common HSCIF definitions.
371 */
372 [SCIx_HSCIF_REGTYPE] = {
e095ee6b
LP		 373 .regs = {
374 [SCSMR] = { 0x00, 16 },
375 [SCBRR] = { 0x04, 8 },
376 [SCSCR] = { 0x08, 16 },
377 [SCxTDR] = { 0x0c, 8 },
378 [SCxSR] = { 0x10, 16 },
379 [SCxRDR] = { 0x14, 8 },
380 [SCFCR] = { 0x18, 16 },
381 [SCFDR] = { 0x1c, 16 },
382 [SCSPTR] = { 0x20, 16 },
383 [SCLSR] = { 0x24, 16 },
384 [HSSRR] = { 0x40, 16 },
385 [SCDL] = { 0x30, 16 },
386 [SCCKS] = { 0x34, 16 },
54e14ae2
UH		 387 [HSRTRGR] = { 0x54, 16 },
388 [HSTTRGR] = { 0x58, 16 },
e095ee6b 389 },
b2f20ed9
LP		 390 .fifosize = 128,
391 .overrun_reg = SCLSR,
392 .overrun_mask = SCLSR_ORER,
393 .sampling_rate_mask = SCI_SR_RANGE(8, 32),
394 .error_mask = SCIF_DEFAULT_ERROR_MASK,
395 .error_clear = SCIF_ERROR_CLEAR,
61a6976b
PM		 396 },
397
398 /*
399 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
400 * register.
401 */
402 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
e095ee6b
LP		 403 .regs = {
404 [SCSMR] = { 0x00, 16 },
405 [SCBRR] = { 0x04, 8 },
406 [SCSCR] = { 0x08, 16 },
407 [SCxTDR] = { 0x0c, 8 },
408 [SCxSR] = { 0x10, 16 },
409 [SCxRDR] = { 0x14, 8 },
410 [SCFCR] = { 0x18, 16 },
411 [SCFDR] = { 0x1c, 16 },
412 [SCLSR] = { 0x24, 16 },
413 },
b2f20ed9
LP		 414 .fifosize = 16,
415 .overrun_reg = SCLSR,
416 .overrun_mask = SCLSR_ORER,
417 .sampling_rate_mask = SCI_SR(32),
418 .error_mask = SCIF_DEFAULT_ERROR_MASK,
419 .error_clear = SCIF_ERROR_CLEAR,
61a6976b
PM		 420 },
421
422 /*
423 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
424 * count registers.
425 */
426 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
e095ee6b
LP		 427 .regs = {
428 [SCSMR] = { 0x00, 16 },
429 [SCBRR] = { 0x04, 8 },
430 [SCSCR] = { 0x08, 16 },
431 [SCxTDR] = { 0x0c, 8 },
432 [SCxSR] = { 0x10, 16 },
433 [SCxRDR] = { 0x14, 8 },
434 [SCFCR] = { 0x18, 16 },
435 [SCFDR] = { 0x1c, 16 },
436 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
437 [SCRFDR] = { 0x20, 16 },
438 [SCSPTR] = { 0x24, 16 },
439 [SCLSR] = { 0x28, 16 },
440 },
b2f20ed9
LP		 441 .fifosize = 16,
442 .overrun_reg = SCLSR,
443 .overrun_mask = SCLSR_ORER,
444 .sampling_rate_mask = SCI_SR(32),
445 .error_mask = SCIF_DEFAULT_ERROR_MASK,
446 .error_clear = SCIF_ERROR_CLEAR,
61a6976b
PM		 447 },
448
449 /*
450 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
451 * registers.
452 */
453 [SCIx_SH7705_SCIF_REGTYPE] = {
e095ee6b
LP		 454 .regs = {
455 [SCSMR] = { 0x00, 16 },
456 [SCBRR] = { 0x04, 8 },
457 [SCSCR] = { 0x08, 16 },
458 [SCxTDR] = { 0x20, 8 },
459 [SCxSR] = { 0x14, 16 },
460 [SCxRDR] = { 0x24, 8 },
461 [SCFCR] = { 0x18, 16 },
462 [SCFDR] = { 0x1c, 16 },
463 },
18e8cf15 464 .fifosize = 64,
b2f20ed9
LP		 465 .overrun_reg = SCxSR,
466 .overrun_mask = SCIFA_ORER,
467 .sampling_rate_mask = SCI_SR(16),
468 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
469 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
61a6976b
PM		 470 },
471};
472
e095ee6b 473#define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
72b294cf 474
61a6976b
PM		 475/*
476 * The "offset" here is rather misleading, in that it refers to an enum
477 * value relative to the port mapping rather than the fixed offset
478 * itself, which needs to be manually retrieved from the platform's
479 * register map for the given port.
480 */
481static unsigned int sci_serial_in(struct uart_port *p, int offset)
482{
d3184e68 483 const struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 484
485 if (reg->size == 8)
486 return ioread8(p->membase + (reg->offset << p->regshift));
487 else if (reg->size == 16)
488 return ioread16(p->membase + (reg->offset << p->regshift));
489 else
490 WARN(1, "Invalid register access\n");
491
492 return 0;
493}
494
495static void sci_serial_out(struct uart_port *p, int offset, int value)
496{
d3184e68 497 const struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 498
499 if (reg->size == 8)
500 iowrite8(value, p->membase + (reg->offset << p->regshift));
501 else if (reg->size == 16)
502 iowrite16(value, p->membase + (reg->offset << p->regshift));
503 else
504 WARN(1, "Invalid register access\n");
505}
506
23241d43
PM		 507static void sci_port_enable(struct sci_port *sci_port)
508{
f4998e55
GU		 509 unsigned int i;
510
23241d43
PM		 511 if (!sci_port->port.dev)
512 return;
513
514 pm_runtime_get_sync(sci_port->port.dev);
515
f4998e55
GU		 516 for (i = 0; i < SCI_NUM_CLKS; i++) {
517 clk_prepare_enable(sci_port->clks[i]);
518 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
519 }
520 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
23241d43
PM		 521}
522
523static void sci_port_disable(struct sci_port *sci_port)
524{
f4998e55
GU		 525 unsigned int i;
526
23241d43
PM		 527 if (!sci_port->port.dev)
528 return;
529
f4998e55
GU		 530 for (i = SCI_NUM_CLKS; i-- > 0; )
531 clk_disable_unprepare(sci_port->clks[i]);
23241d43
PM		 532
533 pm_runtime_put_sync(sci_port->port.dev);
534}
535
e1910fcd
GU		 536static inline unsigned long port_rx_irq_mask(struct uart_port *port)
537{
538 /*
539 * Not all ports (such as SCIFA) will support REIE. Rather than
540 * special-casing the port type, we check the port initialization
541 * IRQ enable mask to see whether the IRQ is desired at all. If
542 * it's unset, it's logically inferred that there's no point in
543 * testing for it.
544 */
545 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
546}
547
548static void sci_start_tx(struct uart_port *port)
549{
550 struct sci_port *s = to_sci_port(port);
551 unsigned short ctrl;
552
553#ifdef CONFIG_SERIAL_SH_SCI_DMA
554 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
555 u16 new, scr = serial_port_in(port, SCSCR);
556 if (s->chan_tx)
557 new = scr | SCSCR_TDRQE;
558 else
559 new = scr & ~SCSCR_TDRQE;
560 if (new != scr)
561 serial_port_out(port, SCSCR, new);
562 }
563
564 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
565 dma_submit_error(s->cookie_tx)) {
566 s->cookie_tx = 0;
567 schedule_work(&s->work_tx);
568 }
569#endif
570
571 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
572 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
573 ctrl = serial_port_in(port, SCSCR);
574 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
575 }
576}
577
578static void sci_stop_tx(struct uart_port *port)
579{
580 unsigned short ctrl;
581
582 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
583 ctrl = serial_port_in(port, SCSCR);
584
585 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
586 ctrl &= ~SCSCR_TDRQE;
587
588 ctrl &= ~SCSCR_TIE;
589
590 serial_port_out(port, SCSCR, ctrl);
591}
592
593static void sci_start_rx(struct uart_port *port)
594{
595 unsigned short ctrl;
596
597 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
598
599 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
600 ctrl &= ~SCSCR_RDRQE;
601
602 serial_port_out(port, SCSCR, ctrl);
603}
604
605static void sci_stop_rx(struct uart_port *port)
606{
607 unsigned short ctrl;
608
609 ctrl = serial_port_in(port, SCSCR);
610
611 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
612 ctrl &= ~SCSCR_RDRQE;
613
614 ctrl &= ~port_rx_irq_mask(port);
615
616 serial_port_out(port, SCSCR, ctrl);
617}
618
a1b5b43f
GU		 619static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
620{
621 if (port->type == PORT_SCI) {
622 /* Just store the mask */
623 serial_port_out(port, SCxSR, mask);
b2f20ed9 624 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
a1b5b43f
GU		 625 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
626 /* Only clear the status bits we want to clear */
627 serial_port_out(port, SCxSR,
628 serial_port_in(port, SCxSR) & mask);
629 } else {
630 /* Store the mask, clear parity/framing errors */
631 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
632 }
633}
634
0b0cced1
YS		 635#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
636 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
1f6fd5c9
PM		 637
638#ifdef CONFIG_CONSOLE_POLL
07d2a1a1 639static int sci_poll_get_char(struct uart_port *port)
1da177e4 640{
1da177e4
LT		 641 unsigned short status;
642 int c;
643
e108b2ca 644 do {
b12bb29f 645 status = serial_port_in(port, SCxSR);
1da177e4 646 if (status & SCxSR_ERRORS(port)) {
a1b5b43f 647 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 648 continue;
649 }
3f255eb3
JW		 650 break;
651 } while (1);
652
653 if (!(status & SCxSR_RDxF(port)))
654 return NO_POLL_CHAR;
07d2a1a1 655
b12bb29f 656 c = serial_port_in(port, SCxRDR);
07d2a1a1 657
e7c98dc7 658 /* Dummy read */
b12bb29f 659 serial_port_in(port, SCxSR);
a1b5b43f 660 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 661
662 return c;
663}
1f6fd5c9 664#endif
1da177e4 665
07d2a1a1 666static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 667{
1da177e4
LT		 668 unsigned short status;
669
1da177e4 670 do {
b12bb29f 671 status = serial_port_in(port, SCxSR);
1da177e4
LT		 672 } while (!(status & SCxSR_TDxE(port)));
673
b12bb29f 674 serial_port_out(port, SCxTDR, c);
a1b5b43f 675 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 676}
0b0cced1
YS		 677#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
678 CONFIG_SERIAL_SH_SCI_EARLYCON */
1da177e4 679
61a6976b 680static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 681{
61a6976b 682 struct sci_port *s = to_sci_port(port);
1da177e4 683
61a6976b
PM		 684 /*
685 * Use port-specific handler if provided.
686 */
687 if (s->cfg->ops && s->cfg->ops->init_pins) {
688 s->cfg->ops->init_pins(port, cflag);
689 return;
1da177e4 690 }
41504c39 691
e9d7a45a 692 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
cfa6eb23 693 u16 data = serial_port_in(port, SCPDR);
e9d7a45a
GU		 694 u16 ctrl = serial_port_in(port, SCPCR);
695
696 /* Enable RXD and TXD pin functions */
697 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
97ed9790 698 if (to_sci_port(port)->has_rtscts) {
cfa6eb23
GU		 699 /* RTS# is output, active low, unless autorts */
700 if (!(port->mctrl & TIOCM_RTS)) {
701 ctrl |= SCPCR_RTSC;
702 data |= SCPDR_RTSD;
703 } else if (!s->autorts) {
704 ctrl |= SCPCR_RTSC;
705 data &= ~SCPDR_RTSD;
706 } else {
707 /* Enable RTS# pin function */
708 ctrl &= ~SCPCR_RTSC;
709 }
e9d7a45a
GU		 710 /* Enable CTS# pin function */
711 ctrl &= ~SCPCR_CTSC;
712 }
cfa6eb23 713 serial_port_out(port, SCPDR, data);
e9d7a45a
GU		 714 serial_port_out(port, SCPCR, ctrl);
715 } else if (sci_getreg(port, SCSPTR)->size) {
d2b9775d
GU		 716 u16 status = serial_port_in(port, SCSPTR);
717
cfa6eb23
GU		 718 /* RTS# is always output; and active low, unless autorts */
719 status |= SCSPTR_RTSIO;
720 if (!(port->mctrl & TIOCM_RTS))
721 status |= SCSPTR_RTSDT;
722 else if (!s->autorts)
723 status &= ~SCSPTR_RTSDT;
d2b9775d
GU		 724 /* CTS# and SCK are inputs */
725 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
726 serial_port_out(port, SCSPTR, status);
faf02f8f 727 }
d5701647 728}
e108b2ca 729
72b294cf 730static int sci_txfill(struct uart_port *port)
e108b2ca 731{
b2f20ed9
LP		 732 struct sci_port *s = to_sci_port(port);
733 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
d3184e68 734 const struct plat_sci_reg *reg;
e108b2ca 735
72b294cf
PM		 736 reg = sci_getreg(port, SCTFDR);
737 if (reg->size)
b2f20ed9 738 return serial_port_in(port, SCTFDR) & fifo_mask;
c63847a3 739
72b294cf
PM		 740 reg = sci_getreg(port, SCFDR);
741 if (reg->size)
b12bb29f 742 return serial_port_in(port, SCFDR) >> 8;
d1d4b10c 743
b12bb29f 744 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 745}
746
73a19e4c
GL		 747static int sci_txroom(struct uart_port *port)
748{
72b294cf 749 return port->fifosize - sci_txfill(port);
73a19e4c
GL		 750}
751
752static int sci_rxfill(struct uart_port *port)
e108b2ca 753{
b2f20ed9
LP		 754 struct sci_port *s = to_sci_port(port);
755 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
d3184e68 756 const struct plat_sci_reg *reg;
72b294cf
PM		 757
758 reg = sci_getreg(port, SCRFDR);
759 if (reg->size)
b2f20ed9 760 return serial_port_in(port, SCRFDR) & fifo_mask;
72b294cf
PM		 761
762 reg = sci_getreg(port, SCFDR);
763 if (reg->size)
b2f20ed9 764 return serial_port_in(port, SCFDR) & fifo_mask;
72b294cf 765
b12bb29f 766 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 767}
768
1da177e4
LT		 769/* ********************************************************************** *
770 * the interrupt related routines *
771 * ********************************************************************** */
772
773static void sci_transmit_chars(struct uart_port *port)
774{
ebd2c8f6 775 struct circ_buf *xmit = &port->state->xmit;
1da177e4 776 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 777 unsigned short status;
778 unsigned short ctrl;
e108b2ca 779 int count;
1da177e4 780
b12bb29f 781 status = serial_port_in(port, SCxSR);
1da177e4 782 if (!(status & SCxSR_TDxE(port))) {
b12bb29f 783 ctrl = serial_port_in(port, SCSCR);
e7c98dc7 784 if (uart_circ_empty(xmit))
8e698614 785 ctrl &= ~SCSCR_TIE;
e7c98dc7 786 else
8e698614 787 ctrl |= SCSCR_TIE;
b12bb29f 788 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 789 return;
790 }
791
72b294cf 792 count = sci_txroom(port);
1da177e4
LT		 793
794 do {
795 unsigned char c;
796
797 if (port->x_char) {
798 c = port->x_char;
799 port->x_char = 0;
800 } else if (!uart_circ_empty(xmit) && !stopped) {
801 c = xmit->buf[xmit->tail];
802 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
803 } else {
804 break;
805 }
806
b12bb29f 807 serial_port_out(port, SCxTDR, c);
1da177e4
LT		 808
809 port->icount.tx++;
810 } while (--count > 0);
811
a1b5b43f 812 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1da177e4
LT		 813
814 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
815 uart_write_wakeup(port);
816 if (uart_circ_empty(xmit)) {
b129a8cc 817 sci_stop_tx(port);
1da177e4 818 } else {
b12bb29f 819 ctrl = serial_port_in(port, SCSCR);
1da177e4 820
1a22f08d 821 if (port->type != PORT_SCI) {
b12bb29f 822 serial_port_in(port, SCxSR); /* Dummy read */
a1b5b43f 823 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1da177e4 824 }
1da177e4 825
8e698614 826 ctrl |= SCSCR_TIE;
b12bb29f 827 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 828 }
829}
830
831/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 832#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 833
94c8b6db 834static void sci_receive_chars(struct uart_port *port)
1da177e4 835{
227434f8 836 struct tty_port *tport = &port->state->port;
1da177e4
LT		 837 int i, count, copied = 0;
838 unsigned short status;
33f0f88f 839 unsigned char flag;
1da177e4 840
b12bb29f 841 status = serial_port_in(port, SCxSR);
1da177e4
LT		 842 if (!(status & SCxSR_RDxF(port)))
843 return;
844
845 while (1) {
1da177e4 846 /* Don't copy more bytes than there is room for in the buffer */
227434f8 847 count = tty_buffer_request_room(tport, sci_rxfill(port));
1da177e4
LT		 848
849 /* If for any reason we can't copy more data, we're done! */
850 if (count == 0)
851 break;
852
853 if (port->type == PORT_SCI) {
b12bb29f 854 char c = serial_port_in(port, SCxRDR);
d5cb1319 855 if (uart_handle_sysrq_char(port, c))
1da177e4 856 count = 0;
e7c98dc7 857 else
92a19f9c 858 tty_insert_flip_char(tport, c, TTY_NORMAL);
1da177e4 859 } else {
e7c98dc7 860 for (i = 0; i < count; i++) {
b12bb29f 861 char c = serial_port_in(port, SCxRDR);
d97fbbed 862
b12bb29f 863 status = serial_port_in(port, SCxSR);
7d12e780 864 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 865 count--; i--;
866 continue;
867 }
868
869 /* Store data and status */
73a19e4c 870 if (status & SCxSR_FER(port)) {
33f0f88f 871 flag = TTY_FRAME;
d97fbbed 872 port->icount.frame++;
762c69e3 873 dev_notice(port->dev, "frame error\n");
73a19e4c 874 } else if (status & SCxSR_PER(port)) {
33f0f88f 875 flag = TTY_PARITY;
d97fbbed 876 port->icount.parity++;
762c69e3 877 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 878 } else
879 flag = TTY_NORMAL;
762c69e3 880
92a19f9c 881 tty_insert_flip_char(tport, c, flag);
1da177e4
LT		 882 }
883 }
884
b12bb29f 885 serial_port_in(port, SCxSR); /* dummy read */
a1b5b43f 886 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4 887
1da177e4
LT		 888 copied += count;
889 port->icount.rx += count;
890 }
891
892 if (copied) {
893 /* Tell the rest of the system the news. New characters! */
2e124b4a 894 tty_flip_buffer_push(tport);
1da177e4 895 } else {
7842055b
UH		 896 /* TTY buffers full; read from RX reg to prevent lockup */
897 serial_port_in(port, SCxRDR);
b12bb29f 898 serial_port_in(port, SCxSR); /* dummy read */
a1b5b43f 899 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 900 }
901}
902
94c8b6db 903static int sci_handle_errors(struct uart_port *port)
1da177e4
LT		 904{
905 int copied = 0;
b12bb29f 906 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 907 struct tty_port *tport = &port->state->port;
debf9507 908 struct sci_port *s = to_sci_port(port);
1da177e4 909
3ae988d9 910 /* Handle overruns */
b2f20ed9 911 if (status & s->params->overrun_mask) {
3ae988d9 912 port->icount.overrun++;
d97fbbed 913
3ae988d9
LP		 914 /* overrun error */
915 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
916 copied++;
762c69e3 917
9b971cd2 918 dev_notice(port->dev, "overrun error\n");
1da177e4
LT		 919 }
920
e108b2ca 921 if (status & SCxSR_FER(port)) {
d5cb1319
LP		 922 /* frame error */
923 port->icount.frame++;
d97fbbed 924
d5cb1319
LP		 925 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
926 copied++;
762c69e3 927
d5cb1319 928 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 929 }
930
e108b2ca 931 if (status & SCxSR_PER(port)) {
1da177e4 932 /* parity error */
d97fbbed
PM		 933 port->icount.parity++;
934
92a19f9c 935 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
e108b2ca 936 copied++;
762c69e3 937
9b971cd2 938 dev_notice(port->dev, "parity error\n");
1da177e4
LT		 939 }
940
33f0f88f 941 if (copied)
2e124b4a 942 tty_flip_buffer_push(tport);
1da177e4
LT		 943
944 return copied;
945}
946
94c8b6db 947static int sci_handle_fifo_overrun(struct uart_port *port)
d830fa45 948{
92a19f9c 949 struct tty_port *tport = &port->state->port;
debf9507 950 struct sci_port *s = to_sci_port(port);
d3184e68 951 const struct plat_sci_reg *reg;
2e0842a1 952 int copied = 0;
75c249fd 953 u16 status;
d830fa45 954
b2f20ed9 955 reg = sci_getreg(port, s->params->overrun_reg);
4b8c59a3 956 if (!reg->size)
d830fa45
PM		 957 return 0;
958
b2f20ed9
LP		 959 status = serial_port_in(port, s->params->overrun_reg);
960 if (status & s->params->overrun_mask) {
961 status &= ~s->params->overrun_mask;
962 serial_port_out(port, s->params->overrun_reg, status);
d830fa45 963
d97fbbed
PM		 964 port->icount.overrun++;
965
92a19f9c 966 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
2e124b4a 967 tty_flip_buffer_push(tport);
d830fa45 968
51b31f1c 969 dev_dbg(port->dev, "overrun error\n");
d830fa45
PM		 970 copied++;
971 }
972
973 return copied;
974}
975
94c8b6db 976static int sci_handle_breaks(struct uart_port *port)
1da177e4
LT		 977{
978 int copied = 0;
b12bb29f 979 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 980 struct tty_port *tport = &port->state->port;
1da177e4 981
0b3d4ef6
PM		 982 if (uart_handle_break(port))
983 return 0;
984
d5cb1319 985 if (status & SCxSR_BRK(port)) {
d97fbbed
PM		 986 port->icount.brk++;
987
1da177e4 988 /* Notify of BREAK */
92a19f9c 989 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
33f0f88f 990 copied++;
762c69e3
PM		 991
992 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 993 }
994
33f0f88f 995 if (copied)
2e124b4a 996 tty_flip_buffer_push(tport);
e108b2ca 997
d830fa45
PM		 998 copied += sci_handle_fifo_overrun(port);
999
1da177e4
LT		 1000 return copied;
1001}
1002
a380ed46
UH		 1003static int scif_set_rtrg(struct uart_port *port, int rx_trig)
1004{
1005 unsigned int bits;
1006
1007 if (rx_trig < 1)
1008 rx_trig = 1;
1009 if (rx_trig >= port->fifosize)
1010 rx_trig = port->fifosize;
1011
1012 /* HSCIF can be set to an arbitrary level. */
1013 if (sci_getreg(port, HSRTRGR)->size) {
1014 serial_port_out(port, HSRTRGR, rx_trig);
1015 return rx_trig;
1016 }
1017
1018 switch (port->type) {
1019 case PORT_SCIF:
1020 if (rx_trig < 4) {
1021 bits = 0;
1022 rx_trig = 1;
1023 } else if (rx_trig < 8) {
1024 bits = SCFCR_RTRG0;
1025 rx_trig = 4;
1026 } else if (rx_trig < 14) {
1027 bits = SCFCR_RTRG1;
1028 rx_trig = 8;
1029 } else {
1030 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1031 rx_trig = 14;
1032 }
1033 break;
1034 case PORT_SCIFA:
1035 case PORT_SCIFB:
1036 if (rx_trig < 16) {
1037 bits = 0;
1038 rx_trig = 1;
1039 } else if (rx_trig < 32) {
1040 bits = SCFCR_RTRG0;
1041 rx_trig = 16;
1042 } else if (rx_trig < 48) {
1043 bits = SCFCR_RTRG1;
1044 rx_trig = 32;
1045 } else {
1046 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1047 rx_trig = 48;
1048 }
1049 break;
1050 default:
1051 WARN(1, "unknown FIFO configuration");
1052 return 1;
1053 }
1054
1055 serial_port_out(port, SCFCR,
1056 (serial_port_in(port, SCFCR) &
1057 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
1058
1059 return rx_trig;
1060}
1061
03940376
UH		 1062static int scif_rtrg_enabled(struct uart_port *port)
1063{
1064 if (sci_getreg(port, HSRTRGR)->size)
1065 return serial_port_in(port, HSRTRGR) != 0;
1066 else
1067 return (serial_port_in(port, SCFCR) &
1068 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
1069}
1070
e99e88a9 1071static void rx_fifo_timer_fn(struct timer_list *t)
03940376 1072{
e99e88a9 1073 struct sci_port *s = from_timer(s, t, rx_fifo_timer);
03940376
UH		 1074 struct uart_port *port = &s->port;
1075
1076 dev_dbg(port->dev, "Rx timed out\n");
1077 scif_set_rtrg(port, 1);
1078}
1079
5d23188a
UH		 1080static ssize_t rx_trigger_show(struct device *dev,
1081 struct device_attribute *attr,
1082 char *buf)
1083{
1084 struct uart_port *port = dev_get_drvdata(dev);
1085 struct sci_port *sci = to_sci_port(port);
1086
1087 return sprintf(buf, "%d\n", sci->rx_trigger);
1088}
1089
1090static ssize_t rx_trigger_store(struct device *dev,
1091 struct device_attribute *attr,
1092 const char *buf,
1093 size_t count)
1094{
1095 struct uart_port *port = dev_get_drvdata(dev);
1096 struct sci_port *sci = to_sci_port(port);
4ab3c51e 1097 int ret;
5d23188a
UH		 1098 long r;
1099
4ab3c51e
DC		 1100 ret = kstrtol(buf, 0, &r);
1101 if (ret)
1102 return ret;
90afa525 1103
5d23188a 1104 sci->rx_trigger = scif_set_rtrg(port, r);
90afa525
UH		 1105 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1106 scif_set_rtrg(port, 1);
1107
5d23188a
UH		 1108 return count;
1109}
1110
1111static DEVICE_ATTR(rx_fifo_trigger, 0644, rx_trigger_show, rx_trigger_store);
1112
1113static ssize_t rx_fifo_timeout_show(struct device *dev,
1114 struct device_attribute *attr,
1115 char *buf)
1116{
1117 struct uart_port *port = dev_get_drvdata(dev);
1118 struct sci_port *sci = to_sci_port(port);
fa2abb03 1119 int v;
5d23188a 1120
fa2abb03
UH		 1121 if (port->type == PORT_HSCIF)
1122 v = sci->hscif_tot >> HSSCR_TOT_SHIFT;
1123 else
1124 v = sci->rx_fifo_timeout;
1125
1126 return sprintf(buf, "%d\n", v);
5d23188a
UH		 1127}
1128
1129static ssize_t rx_fifo_timeout_store(struct device *dev,
1130 struct device_attribute *attr,
1131 const char *buf,
1132 size_t count)
1133{
1134 struct uart_port *port = dev_get_drvdata(dev);
1135 struct sci_port *sci = to_sci_port(port);
4ab3c51e 1136 int ret;
5d23188a
UH		 1137 long r;
1138
4ab3c51e
DC		 1139 ret = kstrtol(buf, 0, &r);
1140 if (ret)
1141 return ret;
fa2abb03
UH		 1142
1143 if (port->type == PORT_HSCIF) {
1144 if (r < 0 || r > 3)
1145 return -EINVAL;
1146 sci->hscif_tot = r << HSSCR_TOT_SHIFT;
1147 } else {
1148 sci->rx_fifo_timeout = r;
1149 scif_set_rtrg(port, 1);
1150 if (r > 0)
e99e88a9 1151 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0);
fa2abb03
UH		 1152 }
1153
5d23188a
UH		 1154 return count;
1155}
1156
b6b996b6 1157static DEVICE_ATTR_RW(rx_fifo_timeout);
5d23188a
UH		 1158
1159
73a19e4c 1160#ifdef CONFIG_SERIAL_SH_SCI_DMA
e1910fcd
GU		 1161static void sci_dma_tx_complete(void *arg)
1162{
1163 struct sci_port *s = arg;
1164 struct uart_port *port = &s->port;
1165 struct circ_buf *xmit = &port->state->xmit;
1166 unsigned long flags;
73a19e4c 1167
e1910fcd 1168 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
73a19e4c 1169
e1910fcd 1170 spin_lock_irqsave(&port->lock, flags);
73a19e4c 1171
e1910fcd
GU		 1172 xmit->tail += s->tx_dma_len;
1173 xmit->tail &= UART_XMIT_SIZE - 1;
73a19e4c 1174
e1910fcd 1175 port->icount.tx += s->tx_dma_len;
1da177e4 1176
e1910fcd
GU		 1177 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1178 uart_write_wakeup(port);
1da177e4 1179
e1910fcd
GU		 1180 if (!uart_circ_empty(xmit)) {
1181 s->cookie_tx = 0;
1182 schedule_work(&s->work_tx);
1183 } else {
1184 s->cookie_tx = -EINVAL;
1185 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1186 u16 ctrl = serial_port_in(port, SCSCR);
1187 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1188 }
1189 }
1da177e4 1190
fd78a76a 1191 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1192}
1193
e1910fcd
GU		 1194/* Locking: called with port lock held */
1195static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1da177e4 1196{
e1910fcd
GU		 1197 struct uart_port *port = &s->port;
1198 struct tty_port *tport = &port->state->port;
1199 int copied;
1da177e4 1200
e1910fcd 1201 copied = tty_insert_flip_string(tport, buf, count);
6fc5a520 1202 if (copied < count)
e1910fcd 1203 port->icount.buf_overrun++;
1da177e4 1204
e1910fcd 1205 port->icount.rx += copied;
1da177e4 1206
e1910fcd 1207 return copied;
1da177e4
LT		 1208}
1209
e1910fcd 1210static int sci_dma_rx_find_active(struct sci_port *s)
1da177e4 1211{
e1910fcd 1212 unsigned int i;
1da177e4 1213
e1910fcd
GU		 1214 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1215 if (s->active_rx == s->cookie_rx[i])
1216 return i;
1da177e4 1217
e1910fcd 1218 return -1;
1da177e4
LT		 1219}
1220
2c4ee235 1221static void sci_rx_dma_release(struct sci_port *s)
f43dc23d 1222{
2c4ee235 1223 struct dma_chan *chan = s->chan_rx_saved;
e1910fcd 1224
2c4ee235 1225 s->chan_rx_saved = s->chan_rx = NULL;
e1910fcd 1226 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
6eefc68d 1227 dmaengine_terminate_sync(chan);
e1910fcd
GU		 1228 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1229 sg_dma_address(&s->sg_rx[0]));
1230 dma_release_channel(chan);
f43dc23d
PM		 1231}
1232
b96408b4
UH		 1233static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec)
1234{
1235 long sec = usec / 1000000;
1236 long nsec = (usec % 1000000) * 1000;
1237 ktime_t t = ktime_set(sec, nsec);
1238
1239 hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1240}
1241
e1910fcd 1242static void sci_dma_rx_complete(void *arg)
1da177e4 1243{
e1910fcd 1244 struct sci_port *s = arg;
1d3db608 1245 struct dma_chan *chan = s->chan_rx;
e1910fcd 1246 struct uart_port *port = &s->port;
67f462b0 1247 struct dma_async_tx_descriptor *desc;
e1910fcd
GU		 1248 unsigned long flags;
1249 int active, count = 0;
1da177e4 1250
e1910fcd
GU		 1251 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1252 s->active_rx);
cb772fe7 1253
e1910fcd 1254 spin_lock_irqsave(&port->lock, flags);
1da177e4 1255
e1910fcd
GU		 1256 active = sci_dma_rx_find_active(s);
1257 if (active >= 0)
1258 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
f43dc23d 1259
b96408b4 1260 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
f43dc23d 1261
e1910fcd
GU		 1262 if (count)
1263 tty_flip_buffer_push(&port->state->port);
8b6ff84c 1264
67f462b0
GU		 1265 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1266 DMA_DEV_TO_MEM,
1267 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1268 if (!desc)
1269 goto fail;
1270
1271 desc->callback = sci_dma_rx_complete;
1272 desc->callback_param = s;
1273 s->cookie_rx[active] = dmaengine_submit(desc);
1274 if (dma_submit_error(s->cookie_rx[active]))
1275 goto fail;
1276
1277 s->active_rx = s->cookie_rx[!active];
1278
1d3db608
MHF		 1279 dma_async_issue_pending(chan);
1280
6fc5a520 1281 spin_unlock_irqrestore(&port->lock, flags);
67f462b0
GU		 1282 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1283 __func__, s->cookie_rx[active], active, s->active_rx);
67f462b0
GU		 1284 return;
1285
1286fail:
1287 spin_unlock_irqrestore(&port->lock, flags);
1288 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
2c4ee235
GU		 1289 /* Switch to PIO */
1290 spin_lock_irqsave(&port->lock, flags);
1291 s->chan_rx = NULL;
1292 sci_start_rx(port);
1293 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1294}
1295
2c4ee235 1296static void sci_tx_dma_release(struct sci_port *s)
1da177e4 1297{
2c4ee235 1298 struct dma_chan *chan = s->chan_tx_saved;
1da177e4 1299
f6611317 1300 cancel_work_sync(&s->work_tx);
2c4ee235 1301 s->chan_tx_saved = s->chan_tx = NULL;
e1910fcd 1302 s->cookie_tx = -EINVAL;
6eefc68d 1303 dmaengine_terminate_sync(chan);
e1910fcd
GU		 1304 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1305 DMA_TO_DEVICE);
1306 dma_release_channel(chan);
e1910fcd 1307}
d535a230 1308
e1910fcd
GU		 1309static void sci_submit_rx(struct sci_port *s)
1310{
1311 struct dma_chan *chan = s->chan_rx;
2c4ee235
GU		 1312 struct uart_port *port = &s->port;
1313 unsigned long flags;
e1910fcd 1314 int i;
073e84c9 1315
e1910fcd
GU		 1316 for (i = 0; i < 2; i++) {
1317 struct scatterlist *sg = &s->sg_rx[i];
1318 struct dma_async_tx_descriptor *desc;
1da177e4 1319
e1910fcd
GU		 1320 desc = dmaengine_prep_slave_sg(chan,
1321 sg, 1, DMA_DEV_TO_MEM,
1322 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1323 if (!desc)
1324 goto fail;
501b825d 1325
e1910fcd
GU		 1326 desc->callback = sci_dma_rx_complete;
1327 desc->callback_param = s;
1328 s->cookie_rx[i] = dmaengine_submit(desc);
1329 if (dma_submit_error(s->cookie_rx[i]))
1330 goto fail;
9174fc8f 1331
e1910fcd 1332 }
9174fc8f 1333
e1910fcd 1334 s->active_rx = s->cookie_rx[0];
9174fc8f 1335
e1910fcd
GU		 1336 dma_async_issue_pending(chan);
1337 return;
9174fc8f 1338
e1910fcd
GU		 1339fail:
1340 if (i)
6eefc68d 1341 dmaengine_terminate_async(chan);
e1910fcd
GU		 1342 for (i = 0; i < 2; i++)
1343 s->cookie_rx[i] = -EINVAL;
1344 s->active_rx = -EINVAL;
2c4ee235
GU		 1345 /* Switch to PIO */
1346 spin_lock_irqsave(&port->lock, flags);
1347 s->chan_rx = NULL;
1348 sci_start_rx(port);
1349 spin_unlock_irqrestore(&port->lock, flags);
e1910fcd 1350}
9174fc8f 1351
e1910fcd 1352static void work_fn_tx(struct work_struct *work)
1da177e4 1353{
e1910fcd
GU		 1354 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1355 struct dma_async_tx_descriptor *desc;
1356 struct dma_chan *chan = s->chan_tx;
1357 struct uart_port *port = &s->port;
1358 struct circ_buf *xmit = &port->state->xmit;
2c4ee235 1359 unsigned long flags;
e1910fcd 1360 dma_addr_t buf;
1da177e4 1361
9174fc8f 1362 /*
e1910fcd
GU		 1363 * DMA is idle now.
1364 * Port xmit buffer is already mapped, and it is one page... Just adjust
1365 * offsets and lengths. Since it is a circular buffer, we have to
1366 * transmit till the end, and then the rest. Take the port lock to get a
1367 * consistent xmit buffer state.
9174fc8f 1368 */
e1910fcd
GU		 1369 spin_lock_irq(&port->lock);
1370 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1371 s->tx_dma_len = min_t(unsigned int,
1372 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1373 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1374 spin_unlock_irq(&port->lock);
0e8963de 1375
e1910fcd
GU		 1376 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1377 DMA_MEM_TO_DEV,
1378 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1379 if (!desc) {
1380 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
2c4ee235 1381 goto switch_to_pio;
e1910fcd 1382 }
0e8963de 1383
e1910fcd
GU		 1384 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1385 DMA_TO_DEVICE);
1da177e4 1386
e1910fcd
GU		 1387 spin_lock_irq(&port->lock);
1388 desc->callback = sci_dma_tx_complete;
1389 desc->callback_param = s;
1390 spin_unlock_irq(&port->lock);
1391 s->cookie_tx = dmaengine_submit(desc);
1392 if (dma_submit_error(s->cookie_tx)) {
1393 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
2c4ee235 1394 goto switch_to_pio;
1da177e4 1395 }
1da177e4 1396
e1910fcd
GU		 1397 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1398 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
73a19e4c 1399
e1910fcd 1400 dma_async_issue_pending(chan);
2c4ee235
GU		 1401 return;
1402
1403switch_to_pio:
1404 spin_lock_irqsave(&port->lock, flags);
1405 s->chan_tx = NULL;
1406 sci_start_tx(port);
1407 spin_unlock_irqrestore(&port->lock, flags);
1408 return;
1da177e4
LT		 1409}
1410
b96408b4 1411static enum hrtimer_restart rx_timer_fn(struct hrtimer *t)
1da177e4 1412{
b96408b4 1413 struct sci_port *s = container_of(t, struct sci_port, rx_timer);
e7327c09 1414 struct dma_chan *chan = s->chan_rx;
e1910fcd 1415 struct uart_port *port = &s->port;
67f462b0
GU		 1416 struct dma_tx_state state;
1417 enum dma_status status;
1418 unsigned long flags;
1419 unsigned int read;
1420 int active, count;
1421 u16 scr;
1422
67f462b0 1423 dev_dbg(port->dev, "DMA Rx timed out\n");
67f462b0 1424
6fc5a520
TA		 1425 spin_lock_irqsave(&port->lock, flags);
1426
67f462b0
GU		 1427 active = sci_dma_rx_find_active(s);
1428 if (active < 0) {
1429 spin_unlock_irqrestore(&port->lock, flags);
b96408b4 1430 return HRTIMER_NORESTART;
67f462b0
GU		 1431 }
1432
1433 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
3b963042 1434 if (status == DMA_COMPLETE) {
6fc5a520 1435 spin_unlock_irqrestore(&port->lock, flags);
67f462b0
GU		 1436 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1437 s->active_rx, active);
3b963042
MHF		 1438
1439 /* Let packet complete handler take care of the packet */
b96408b4 1440 return HRTIMER_NORESTART;
3b963042 1441 }
67f462b0 1442
e7327c09
MHF		 1443 dmaengine_pause(chan);
1444
1445 /*
1446 * sometimes DMA transfer doesn't stop even if it is stopped and
1447 * data keeps on coming until transaction is complete so check
1448 * for DMA_COMPLETE again
1449 * Let packet complete handler take care of the packet
1450 */
1451 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1452 if (status == DMA_COMPLETE) {
1453 spin_unlock_irqrestore(&port->lock, flags);
1454 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
b96408b4 1455 return HRTIMER_NORESTART;
e7327c09
MHF		 1456 }
1457
67f462b0 1458 /* Handle incomplete DMA receive */
6eefc68d 1459 dmaengine_terminate_async(s->chan_rx);
67f462b0 1460 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
67f462b0
GU		 1461
1462 if (read) {
1463 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1464 if (count)
1465 tty_flip_buffer_push(&port->state->port);
1466 }
1467
756981be
GU		 1468 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1469 sci_submit_rx(s);
371cfed3
MHF		 1470
1471 /* Direct new serial port interrupts back to CPU */
1472 scr = serial_port_in(port, SCSCR);
1473 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1474 scr &= ~SCSCR_RDRQE;
1475 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1476 }
1477 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1478
1479 spin_unlock_irqrestore(&port->lock, flags);
b96408b4
UH		 1480
1481 return HRTIMER_NORESTART;
1da177e4
LT		 1482}
1483
ff441129 1484static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
219fb0c1 1485 enum dma_transfer_direction dir)
ff441129 1486{
ff441129
GU		 1487 struct dma_chan *chan;
1488 struct dma_slave_config cfg;
1489 int ret;
1490
219fb0c1
LP		 1491 chan = dma_request_slave_channel(port->dev,
1492 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
ff441129 1493 if (!chan) {
9b7becf1 1494 dev_warn(port->dev, "dma_request_slave_channel failed\n");
ff441129
GU		 1495 return NULL;
1496 }
1497
1498 memset(&cfg, 0, sizeof(cfg));
1499 cfg.direction = dir;
1500 if (dir == DMA_MEM_TO_DEV) {
1501 cfg.dst_addr = port->mapbase +
1502 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1503 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1504 } else {
1505 cfg.src_addr = port->mapbase +
1506 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1507 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1508 }
1509
1510 ret = dmaengine_slave_config(chan, &cfg);
1511 if (ret) {
1512 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1513 dma_release_channel(chan);
1514 return NULL;
1515 }
1516
1517 return chan;
1518}
1519
e1910fcd 1520static void sci_request_dma(struct uart_port *port)
73a19e4c 1521{
e1910fcd 1522 struct sci_port *s = to_sci_port(port);
e1910fcd 1523 struct dma_chan *chan;
73a19e4c 1524
e1910fcd 1525 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
73a19e4c 1526
219fb0c1 1527 if (!port->dev->of_node)
e1910fcd 1528 return;
73a19e4c 1529
e1910fcd 1530 s->cookie_tx = -EINVAL;
7464779f
AL		 1531
1532 /*
1533 * Don't request a dma channel if no channel was specified
1534 * in the device tree.
1535 */
1536 if (!of_find_property(port->dev->of_node, "dmas", NULL))
1537 return;
1538
219fb0c1 1539 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
e1910fcd
GU		 1540 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1541 if (chan) {
e1910fcd
GU		 1542 /* UART circular tx buffer is an aligned page. */
1543 s->tx_dma_addr = dma_map_single(chan->device->dev,
1544 port->state->xmit.buf,
1545 UART_XMIT_SIZE,
1546 DMA_TO_DEVICE);
1547 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1548 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1549 dma_release_channel(chan);
e1910fcd
GU		 1550 } else {
1551 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1552 __func__, UART_XMIT_SIZE,
1553 port->state->xmit.buf, &s->tx_dma_addr);
2c4ee235 1554
f6611317 1555 INIT_WORK(&s->work_tx, work_fn_tx);
2c4ee235 1556 s->chan_tx_saved = s->chan_tx = chan;
49d4bcad 1557 }
3089f381
GL		 1558 }
1559
219fb0c1 1560 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
e1910fcd
GU		 1561 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1562 if (chan) {
1563 unsigned int i;
1564 dma_addr_t dma;
1565 void *buf;
73a19e4c 1566
e1910fcd
GU		 1567 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1568 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1569 &dma, GFP_KERNEL);
1570 if (!buf) {
1571 dev_warn(port->dev,
1572 "Failed to allocate Rx dma buffer, using PIO\n");
1573 dma_release_channel(chan);
e1910fcd
GU		 1574 return;
1575 }
73a19e4c 1576
e1910fcd
GU		 1577 for (i = 0; i < 2; i++) {
1578 struct scatterlist *sg = &s->sg_rx[i];
0533502d 1579
e1910fcd
GU		 1580 sg_init_table(sg, 1);
1581 s->rx_buf[i] = buf;
1582 sg_dma_address(sg) = dma;
d09959e7 1583 sg_dma_len(sg) = s->buf_len_rx;
0533502d 1584
e1910fcd
GU		 1585 buf += s->buf_len_rx;
1586 dma += s->buf_len_rx;
1587 }
1588
b96408b4
UH		 1589 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1590 s->rx_timer.function = rx_timer_fn;
e1910fcd 1591
756981be
GU		 1592 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1593 sci_submit_rx(s);
2c4ee235
GU		 1594
1595 s->chan_rx_saved = s->chan_rx = chan;
e1910fcd 1596 }
0533502d
GU		 1597}
1598
e1910fcd 1599static void sci_free_dma(struct uart_port *port)
73a19e4c 1600{
e1910fcd 1601 struct sci_port *s = to_sci_port(port);
73a19e4c 1602
2c4ee235
GU		 1603 if (s->chan_tx_saved)
1604 sci_tx_dma_release(s);
1605 if (s->chan_rx_saved)
1606 sci_rx_dma_release(s);
e1910fcd 1607}
1cf4a7ef
GU		 1608
1609static void sci_flush_buffer(struct uart_port *port)
1610{
1611 /*
1612 * In uart_flush_buffer(), the xmit circular buffer has just been
1613 * cleared, so we have to reset tx_dma_len accordingly.
1614 */
1615 to_sci_port(port)->tx_dma_len = 0;
1616}
1617#else /* !CONFIG_SERIAL_SH_SCI_DMA */
e1910fcd
GU		 1618static inline void sci_request_dma(struct uart_port *port)
1619{
1620}
73a19e4c 1621
e1910fcd
GU		 1622static inline void sci_free_dma(struct uart_port *port)
1623{
1624}
1cf4a7ef
GU		 1625
1626#define sci_flush_buffer NULL
1627#endif /* !CONFIG_SERIAL_SH_SCI_DMA */
73a19e4c 1628
e1910fcd
GU		 1629static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1630{
e1910fcd
GU		 1631 struct uart_port *port = ptr;
1632 struct sci_port *s = to_sci_port(port);
73a19e4c 1633
03940376 1634#ifdef CONFIG_SERIAL_SH_SCI_DMA
e1910fcd
GU		 1635 if (s->chan_rx) {
1636 u16 scr = serial_port_in(port, SCSCR);
1637 u16 ssr = serial_port_in(port, SCxSR);
73a19e4c 1638
e1910fcd
GU		 1639 /* Disable future Rx interrupts */
1640 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1641 disable_irq_nosync(irq);
1642 scr |= SCSCR_RDRQE;
1643 } else {
1644 scr &= ~SCSCR_RIE;
756981be 1645 sci_submit_rx(s);
e1910fcd
GU		 1646 }
1647 serial_port_out(port, SCSCR, scr);
1648 /* Clear current interrupt */
1649 serial_port_out(port, SCxSR,
1650 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
b96408b4 1651 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n",
e1910fcd 1652 jiffies, s->rx_timeout);
b96408b4 1653 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
73a19e4c 1654
e1910fcd
GU		 1655 return IRQ_HANDLED;
1656 }
1657#endif
73a19e4c 1658
03940376
UH		 1659 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
1660 if (!scif_rtrg_enabled(port))
1661 scif_set_rtrg(port, s->rx_trigger);
1662
1663 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
b96408b4 1664 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000));
03940376
UH		 1665 }
1666
e1910fcd
GU		 1667 /* I think sci_receive_chars has to be called irrespective
1668 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1669 * to be disabled?
1670 */
1671 sci_receive_chars(ptr);
1672
1673 return IRQ_HANDLED;
73a19e4c
GL		 1674}
1675
e1910fcd 1676static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
73a19e4c 1677{
e1910fcd 1678 struct uart_port *port = ptr;
04928b79 1679 unsigned long flags;
73a19e4c 1680
04928b79 1681 spin_lock_irqsave(&port->lock, flags);
e1910fcd 1682 sci_transmit_chars(port);
04928b79 1683 spin_unlock_irqrestore(&port->lock, flags);
e1910fcd
GU		 1684
1685 return IRQ_HANDLED;
73a19e4c
GL		 1686}
1687
8b0bbd95
CB		 1688static irqreturn_t sci_br_interrupt(int irq, void *ptr);
1689
e1910fcd 1690static irqreturn_t sci_er_interrupt(int irq, void *ptr)
73a19e4c 1691{
e1910fcd
GU		 1692 struct uart_port *port = ptr;
1693 struct sci_port *s = to_sci_port(port);
73a19e4c 1694
8b0bbd95
CB		 1695 if (SCIx_TEIDRI_IRQ_EXISTS(s)) {
1696 /* Break and Error interrupts are muxed */
1697 unsigned short ssr_status = serial_port_in(port, SCxSR);
1698
1699 /* Break Interrupt */
1700 if (ssr_status & SCxSR_BRK(port))
1701 sci_br_interrupt(irq, ptr);
1702
1703 /* Break only? */
1704 if (!(ssr_status & SCxSR_ERRORS(port)))
1705 return IRQ_HANDLED;
1706 }
1707
e1910fcd
GU		 1708 /* Handle errors */
1709 if (port->type == PORT_SCI) {
1710 if (sci_handle_errors(port)) {
1711 /* discard character in rx buffer */
1712 serial_port_in(port, SCxSR);
1713 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1714 }
1715 } else {
1716 sci_handle_fifo_overrun(port);
1717 if (!s->chan_rx)
1718 sci_receive_chars(ptr);
1719 }
1720
1721 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1722
1723 /* Kick the transmission */
1724 if (!s->chan_tx)
1725 sci_tx_interrupt(irq, ptr);
1726
1727 return IRQ_HANDLED;
73a19e4c
GL		 1728}
1729
e1910fcd 1730static irqreturn_t sci_br_interrupt(int irq, void *ptr)
73a19e4c 1731{
e1910fcd 1732 struct uart_port *port = ptr;
73a19e4c 1733
e1910fcd
GU		 1734 /* Handle BREAKs */
1735 sci_handle_breaks(port);
1736 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
73a19e4c 1737
e1910fcd
GU		 1738 return IRQ_HANDLED;
1739}
73a19e4c 1740
e1910fcd
GU		 1741static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1742{
1743 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1744 struct uart_port *port = ptr;
1745 struct sci_port *s = to_sci_port(port);
1746 irqreturn_t ret = IRQ_NONE;
73a19e4c 1747
e1910fcd
GU		 1748 ssr_status = serial_port_in(port, SCxSR);
1749 scr_status = serial_port_in(port, SCSCR);
b2f20ed9 1750 if (s->params->overrun_reg == SCxSR)
e1910fcd 1751 orer_status = ssr_status;
b2f20ed9
LP		 1752 else if (sci_getreg(port, s->params->overrun_reg)->size)
1753 orer_status = serial_port_in(port, s->params->overrun_reg);
73a19e4c 1754
e1910fcd 1755 err_enabled = scr_status & port_rx_irq_mask(port);
73a19e4c 1756
e1910fcd
GU		 1757 /* Tx Interrupt */
1758 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1759 !s->chan_tx)
1760 ret = sci_tx_interrupt(irq, ptr);
658daa95 1761
e1910fcd
GU		 1762 /*
1763 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1764 * DR flags
1765 */
1766 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1767 (scr_status & SCSCR_RIE))
1768 ret = sci_rx_interrupt(irq, ptr);
73a19e4c 1769
e1910fcd
GU		 1770 /* Error Interrupt */
1771 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1772 ret = sci_er_interrupt(irq, ptr);
73a19e4c 1773
e1910fcd
GU		 1774 /* Break Interrupt */
1775 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1776 ret = sci_br_interrupt(irq, ptr);
1777
1778 /* Overrun Interrupt */
b2f20ed9 1779 if (orer_status & s->params->overrun_mask) {
e1910fcd
GU		 1780 sci_handle_fifo_overrun(port);
1781 ret = IRQ_HANDLED;
73a19e4c 1782 }
73a19e4c 1783
e1910fcd
GU		 1784 return ret;
1785}
73a19e4c 1786
e1910fcd
GU		 1787static const struct sci_irq_desc {
1788 const char *desc;
1789 irq_handler_t handler;
1790} sci_irq_desc[] = {
1791 /*
1792 * Split out handlers, the default case.
1793 */
1794 [SCIx_ERI_IRQ] = {
1795 .desc = "rx err",
1796 .handler = sci_er_interrupt,
1797 },
3089f381 1798
e1910fcd
GU		 1799 [SCIx_RXI_IRQ] = {
1800 .desc = "rx full",
1801 .handler = sci_rx_interrupt,
1802 },
47aceb92 1803
e1910fcd
GU		 1804 [SCIx_TXI_IRQ] = {
1805 .desc = "tx empty",
1806 .handler = sci_tx_interrupt,
1807 },
73a19e4c 1808
e1910fcd
GU		 1809 [SCIx_BRI_IRQ] = {
1810 .desc = "break",
1811 .handler = sci_br_interrupt,
1812 },
73a19e4c
GL		 1813
1814 /*
e1910fcd 1815 * Special muxed handler.
73a19e4c 1816 */
e1910fcd
GU		 1817 [SCIx_MUX_IRQ] = {
1818 .desc = "mux",
1819 .handler = sci_mpxed_interrupt,
1820 },
1821};
73a19e4c 1822
e1910fcd
GU		 1823static int sci_request_irq(struct sci_port *port)
1824{
1825 struct uart_port *up = &port->port;
1826 int i, j, ret = 0;
73a19e4c 1827
e1910fcd
GU		 1828 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1829 const struct sci_irq_desc *desc;
1830 int irq;
73a19e4c 1831
e1910fcd
GU		 1832 if (SCIx_IRQ_IS_MUXED(port)) {
1833 i = SCIx_MUX_IRQ;
1834 irq = up->irq;
1835 } else {
1836 irq = port->irqs[i];
1837
1838 /*
1839 * Certain port types won't support all of the
1840 * available interrupt sources.
1841 */
1842 if (unlikely(irq < 0))
1843 continue;
1844 }
1845
1846 desc = sci_irq_desc + i;
1481ecf1 1847 port->irqstr[j] = NULL;
8b0bbd95
CB		 1848 if (SCIx_TEIDRI_IRQ_EXISTS(port)) {
1849 /*
1850 * ERI and BRI are muxed, just register ERI and
1851 * ignore BRI.
1852 * TEI and DRI are muxed, but only DRI
1853 * is enabled, so use RXI handler
1854 */
1855 if (i == SCIx_ERI_IRQ)
1856 port->irqstr[j] = kasprintf(GFP_KERNEL,
1857 "%s:err + break",
1858 dev_name(up->dev));
1859 if (i == SCIx_BRI_IRQ)
1860 continue;
1861 if (i == SCIx_TEIDRI_IRQ) {
1862 port->irqstr[j] = kasprintf(GFP_KERNEL,
1863 "%s:tx end + rx ready",
1864 dev_name(up->dev));
1865 desc = sci_irq_desc + SCIx_RXI_IRQ;
1866 }
1867 }
1868
1869 if (!port->irqstr[j])
1870 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1871 dev_name(up->dev),
1872 desc->desc);
623ac1d4
PB		 1873 if (!port->irqstr[j]) {
1874 ret = -ENOMEM;
e1910fcd 1875 goto out_nomem;
623ac1d4 1876 }
e1910fcd
GU		 1877
1878 ret = request_irq(irq, desc->handler, up->irqflags,
1879 port->irqstr[j], port);
1880 if (unlikely(ret)) {
1881 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1882 goto out_noirq;
1883 }
73a19e4c
GL		 1884 }
1885
e1910fcd 1886 return 0;
1da177e4 1887
e1910fcd
GU		 1888out_noirq:
1889 while (--i >= 0)
1890 free_irq(port->irqs[i], port);
f43dc23d 1891
e1910fcd
GU		 1892out_nomem:
1893 while (--j >= 0)
1894 kfree(port->irqstr[j]);
f43dc23d 1895
e1910fcd 1896 return ret;
1da177e4
LT		 1897}
1898
e1910fcd 1899static void sci_free_irq(struct sci_port *port)
1da177e4 1900{
e1910fcd 1901 int i;
1da177e4 1902
e1910fcd
GU		 1903 /*
1904 * Intentionally in reverse order so we iterate over the muxed
1905 * IRQ first.
1906 */
1907 for (i = 0; i < SCIx_NR_IRQS; i++) {
1908 int irq = port->irqs[i];
f43dc23d 1909
e1910fcd
GU		 1910 /*
1911 * Certain port types won't support all of the available
1912 * interrupt sources.
1913 */
1914 if (unlikely(irq < 0))
1915 continue;
f43dc23d 1916
e1910fcd
GU		 1917 free_irq(port->irqs[i], port);
1918 kfree(port->irqstr[i]);
f43dc23d 1919
e1910fcd
GU		 1920 if (SCIx_IRQ_IS_MUXED(port)) {
1921 /* If there's only one IRQ, we're done. */
1922 return;
1923 }
1924 }
1da177e4
LT		 1925}
1926
e1910fcd 1927static unsigned int sci_tx_empty(struct uart_port *port)
1da177e4 1928{
e1910fcd
GU		 1929 unsigned short status = serial_port_in(port, SCxSR);
1930 unsigned short in_tx_fifo = sci_txfill(port);
f43dc23d 1931
e1910fcd 1932 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 1933}
1934
33f50ffc
GU		 1935static void sci_set_rts(struct uart_port *port, bool state)
1936{
1937 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1938 u16 data = serial_port_in(port, SCPDR);
1939
1940 /* Active low */
1941 if (state)
1942 data &= ~SCPDR_RTSD;
1943 else
1944 data |= SCPDR_RTSD;
1945 serial_port_out(port, SCPDR, data);
1946
1947 /* RTS# is output */
1948 serial_port_out(port, SCPCR,
1949 serial_port_in(port, SCPCR) | SCPCR_RTSC);
1950 } else if (sci_getreg(port, SCSPTR)->size) {
1951 u16 ctrl = serial_port_in(port, SCSPTR);
1952
1953 /* Active low */
1954 if (state)
1955 ctrl &= ~SCSPTR_RTSDT;
1956 else
1957 ctrl |= SCSPTR_RTSDT;
1958 serial_port_out(port, SCSPTR, ctrl);
1959 }
1960}
1961
1962static bool sci_get_cts(struct uart_port *port)
1963{
1964 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1965 /* Active low */
1966 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD);
1967 } else if (sci_getreg(port, SCSPTR)->size) {
1968 /* Active low */
1969 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT);
1970 }
1971
1972 return true;
1973}
1974
e1910fcd
GU		 1975/*
1976 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1977 * CTS/RTS is supported in hardware by at least one port and controlled
1978 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1979 * handled via the ->init_pins() op, which is a bit of a one-way street,
1980 * lacking any ability to defer pin control -- this will later be
1981 * converted over to the GPIO framework).
1982 *
1983 * Other modes (such as loopback) are supported generically on certain
1984 * port types, but not others. For these it's sufficient to test for the
1985 * existence of the support register and simply ignore the port type.
1986 */
1987static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1da177e4 1988{
f907c9ea
GU		 1989 struct sci_port *s = to_sci_port(port);
1990
e1910fcd
GU		 1991 if (mctrl & TIOCM_LOOP) {
1992 const struct plat_sci_reg *reg;
f43dc23d 1993
e1910fcd
GU		 1994 /*
1995 * Standard loopback mode for SCFCR ports.
1996 */
1997 reg = sci_getreg(port, SCFCR);
1998 if (reg->size)
1999 serial_port_out(port, SCFCR,
2000 serial_port_in(port, SCFCR) |
2001 SCFCR_LOOP);
2002 }
f907c9ea
GU		 2003
2004 mctrl_gpio_set(s->gpios, mctrl);
33f50ffc 2005
97ed9790 2006 if (!s->has_rtscts)
33f50ffc
GU		 2007 return;
2008
2009 if (!(mctrl & TIOCM_RTS)) {
2010 /* Disable Auto RTS */
2011 serial_port_out(port, SCFCR,
2012 serial_port_in(port, SCFCR) & ~SCFCR_MCE);
2013
2014 /* Clear RTS */
2015 sci_set_rts(port, 0);
2016 } else if (s->autorts) {
2017 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2018 /* Enable RTS# pin function */
2019 serial_port_out(port, SCPCR,
2020 serial_port_in(port, SCPCR) & ~SCPCR_RTSC);
2021 }
2022
2023 /* Enable Auto RTS */
2024 serial_port_out(port, SCFCR,
2025 serial_port_in(port, SCFCR) | SCFCR_MCE);
2026 } else {
2027 /* Set RTS */
2028 sci_set_rts(port, 1);
2029 }
e1910fcd 2030}
f43dc23d 2031
e1910fcd
GU		 2032static unsigned int sci_get_mctrl(struct uart_port *port)
2033{
f907c9ea
GU		 2034 struct sci_port *s = to_sci_port(port);
2035 struct mctrl_gpios *gpios = s->gpios;
2036 unsigned int mctrl = 0;
2037
2038 mctrl_gpio_get(gpios, &mctrl);
2039
e1910fcd
GU		 2040 /*
2041 * CTS/RTS is handled in hardware when supported, while nothing
33f50ffc 2042 * else is wired up.
e1910fcd 2043 */
33f50ffc
GU		 2044 if (s->autorts) {
2045 if (sci_get_cts(port))
2046 mctrl |= TIOCM_CTS;
2047 } else if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS))) {
f907c9ea 2048 mctrl |= TIOCM_CTS;
33f50ffc 2049 }
f907c9ea
GU		 2050 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)))
2051 mctrl |= TIOCM_DSR;
2052 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)))
2053 mctrl |= TIOCM_CAR;
2054
2055 return mctrl;
2056}
2057
2058static void sci_enable_ms(struct uart_port *port)
2059{
2060 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
1da177e4
LT		 2061}
2062
1da177e4
LT		 2063static void sci_break_ctl(struct uart_port *port, int break_state)
2064{
bbb4ce50 2065 unsigned short scscr, scsptr;
1be22663 2066 unsigned long flags;
bbb4ce50 2067
a4e02f6d 2068 /* check wheter the port has SCSPTR */
abbf121f 2069 if (!sci_getreg(port, SCSPTR)->size) {
bbb4ce50
SY		 2070 /*
2071 * Not supported by hardware. Most parts couple break and rx
2072 * interrupts together, with break detection always enabled.
2073 */
a4e02f6d 2074 return;
bbb4ce50 2075 }
a4e02f6d 2076
1be22663 2077 spin_lock_irqsave(&port->lock, flags);
a4e02f6d
SY		 2078 scsptr = serial_port_in(port, SCSPTR);
2079 scscr = serial_port_in(port, SCSCR);
2080
2081 if (break_state == -1) {
2082 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
2083 scscr &= ~SCSCR_TE;
2084 } else {
2085 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
2086 scscr |= SCSCR_TE;
2087 }
2088
2089 serial_port_out(port, SCSPTR, scsptr);
2090 serial_port_out(port, SCSCR, scscr);
1be22663 2091 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 2092}
2093
2094static int sci_startup(struct uart_port *port)
2095{
a5660ada 2096 struct sci_port *s = to_sci_port(port);
073e84c9 2097 int ret;
1da177e4 2098
73a19e4c
GL		 2099 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2100
3c910176
TA		 2101 sci_request_dma(port);
2102
073e84c9 2103 ret = sci_request_irq(s);
3c910176
TA		 2104 if (unlikely(ret < 0)) {
2105 sci_free_dma(port);
073e84c9 2106 return ret;
3c910176 2107 }
073e84c9 2108
1da177e4
LT		 2109 return 0;
2110}
2111
2112static void sci_shutdown(struct uart_port *port)
2113{
a5660ada 2114 struct sci_port *s = to_sci_port(port);
33b48e16 2115 unsigned long flags;
5fd2b6ee 2116 u16 scr;
1da177e4 2117
73a19e4c
GL		 2118 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2119
33f50ffc 2120 s->autorts = false;
f907c9ea
GU		 2121 mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
2122
33b48e16 2123 spin_lock_irqsave(&port->lock, flags);
1da177e4 2124 sci_stop_rx(port);
b129a8cc 2125 sci_stop_tx(port);
fa2abb03
UH		 2126 /*
2127 * Stop RX and TX, disable related interrupts, keep clock source
2128 * and HSCIF TOT bits
2129 */
5fd2b6ee 2130 scr = serial_port_in(port, SCSCR);
fa2abb03
UH		 2131 serial_port_out(port, SCSCR, scr &
2132 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
33b48e16 2133 spin_unlock_irqrestore(&port->lock, flags);
073e84c9 2134
9ab76556 2135#ifdef CONFIG_SERIAL_SH_SCI_DMA
2c4ee235 2136 if (s->chan_rx_saved) {
9ab76556
AM		 2137 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2138 port->line);
b96408b4 2139 hrtimer_cancel(&s->rx_timer);
9ab76556
AM		 2140 }
2141#endif
2142
c5a9262f
GU		 2143 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0)
2144 del_timer_sync(&s->rx_fifo_timer);
1da177e4 2145 sci_free_irq(s);
3c910176 2146 sci_free_dma(port);
1da177e4
LT		 2147}
2148
6af27bf2
GU		 2149static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2150 unsigned int *srr)
26c92f37 2151{
6af27bf2 2152 unsigned long freq = s->clk_rates[SCI_SCK];
6af27bf2 2153 int err, min_err = INT_MAX;
69eee8e9 2154 unsigned int sr;
6af27bf2 2155
7b5c0c08
GU		 2156 if (s->port.type != PORT_HSCIF)
2157 freq *= 2;
6af27bf2 2158
69eee8e9 2159 for_each_sr(sr, s) {
6af27bf2
GU		 2160 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2161 if (abs(err) >= abs(min_err))
2162 continue;
2163
2164 min_err = err;
2165 *srr = sr - 1;
ec09c5eb 2166
6af27bf2
GU		 2167 if (!err)
2168 break;
2169 }
e8183a6c 2170
6af27bf2
GU		 2171 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2172 *srr + 1);
2173 return min_err;
26c92f37
PM		 2174}
2175
1270f865
GU		 2176static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2177 unsigned long freq, unsigned int *dlr,
2178 unsigned int *srr)
730c4e78 2179{
1270f865 2180 int err, min_err = INT_MAX;
69eee8e9 2181 unsigned int sr, dl;
730c4e78 2182
7b5c0c08
GU		 2183 if (s->port.type != PORT_HSCIF)
2184 freq *= 2;
730c4e78 2185
69eee8e9 2186 for_each_sr(sr, s) {
1270f865
GU		 2187 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2188 dl = clamp(dl, 1U, 65535U);
2189
2190 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2191 if (abs(err) >= abs(min_err))
2192 continue;
2193
2194 min_err = err;
2195 *dlr = dl;
2196 *srr = sr - 1;
2197
2198 if (!err)
2199 break;
2200 }
730c4e78 2201
1270f865
GU		 2202 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2203 min_err, *dlr, *srr + 1);
2204 return min_err;
2205}
730c4e78 2206
b4a5c459 2207/* calculate sample rate, BRR, and clock select */
f4998e55
GU		 2208static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2209 unsigned int *brr, unsigned int *srr,
2210 unsigned int *cks)
f303b364 2211{
f4998e55 2212 unsigned long freq = s->clk_rates[SCI_FCK];
69eee8e9 2213 unsigned int sr, br, prediv, scrate, c;
6c51332d 2214 int err, min_err = INT_MAX;
f303b364 2215
7b5c0c08
GU		 2216 if (s->port.type != PORT_HSCIF)
2217 freq *= 2;
b4a5c459 2218
6c51332d
GU		 2219 /*
2220 * Find the combination of sample rate and clock select with the
2221 * smallest deviation from the desired baud rate.
2222 * Prefer high sample rates to maximise the receive margin.
2223 *
2224 * M: Receive margin (%)
2225 * N: Ratio of bit rate to clock (N = sampling rate)
2226 * D: Clock duty (D = 0 to 1.0)
2227 * L: Frame length (L = 9 to 12)
2228 * F: Absolute value of clock frequency deviation
2229 *
2230 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2231 * (|D - 0.5| / N * (1 + F))|
2232 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2233 */
69eee8e9 2234 for_each_sr(sr, s) {
f303b364
UH		 2235 for (c = 0; c <= 3; c++) {
2236 /* integerized formulas from HSCIF documentation */
7b5c0c08 2237 prediv = sr * (1 << (2 * c + 1));
de01e6cd
GU		 2238
2239 /*
2240 * We need to calculate:
2241 *
2242 * br = freq / (prediv * bps) clamped to [1..256]
881a7489 2243 * err = freq / (br * prediv) - bps
730c4e78 2244 *
de01e6cd
GU		 2245 * Watch out for overflow when calculating the desired
2246 * sampling clock rate!
730c4e78 2247 */
de01e6cd
GU		 2248 if (bps > UINT_MAX / prediv)
2249 break;
2250
2251 scrate = prediv * bps;
2252 br = DIV_ROUND_CLOSEST(freq, scrate);
95a2703e 2253 br = clamp(br, 1U, 256U);
6c51332d 2254
881a7489 2255 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
6c51332d 2256 if (abs(err) >= abs(min_err))
730c4e78
NI		 2257 continue;
2258
6c51332d 2259 min_err = err;
95a2703e 2260 *brr = br - 1;
730c4e78
NI		 2261 *srr = sr - 1;
2262 *cks = c;
6c51332d
GU		 2263
2264 if (!err)
2265 goto found;
f303b364
UH		 2266 }
2267 }
2268
6c51332d 2269found:
881a7489
GU		 2270 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2271 min_err, *brr, *srr + 1, *cks);
f4998e55 2272 return min_err;
f303b364
UH		 2273}
2274
1ba76220
MD		 2275static void sci_reset(struct uart_port *port)
2276{
d3184e68 2277 const struct plat_sci_reg *reg;
1ba76220 2278 unsigned int status;
18e8cf15 2279 struct sci_port *s = to_sci_port(port);
1ba76220 2280
fa2abb03 2281 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */
1ba76220 2282
0979e0e6
PM		 2283 reg = sci_getreg(port, SCFCR);
2284 if (reg->size)
b12bb29f 2285 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2768cf42
GU		 2286
2287 sci_clear_SCxSR(port,
2288 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2289 SCxSR_BREAK_CLEAR(port));
fc2af334
GU		 2290 if (sci_getreg(port, SCLSR)->size) {
2291 status = serial_port_in(port, SCLSR);
2292 status &= ~(SCLSR_TO | SCLSR_ORER);
2293 serial_port_out(port, SCLSR, status);
2294 }
18e8cf15 2295
03940376
UH		 2296 if (s->rx_trigger > 1) {
2297 if (s->rx_fifo_timeout) {
2298 scif_set_rtrg(port, 1);
e99e88a9 2299 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0);
03940376 2300 } else {
90afa525
UH		 2301 if (port->type == PORT_SCIFA ||
2302 port->type == PORT_SCIFB)
2303 scif_set_rtrg(port, 1);
2304 else
2305 scif_set_rtrg(port, s->rx_trigger);
03940376
UH		 2306 }
2307 }
1ba76220
MD		 2308}
2309
606d099c
AC		 2310static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2311 struct ktermios *old)
1da177e4 2312{
03940376 2313 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
1270f865
GU		 2314 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2315 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
00b9de9c 2316 struct sci_port *s = to_sci_port(port);
d3184e68 2317 const struct plat_sci_reg *reg;
f4998e55
GU		 2318 int min_err = INT_MAX, err;
2319 unsigned long max_freq = 0;
2320 int best_clk = -1;
1be22663 2321 unsigned long flags;
1da177e4 2322
730c4e78
NI		 2323 if ((termios->c_cflag & CSIZE) == CS7)
2324 smr_val |= SCSMR_CHR;
2325 if (termios->c_cflag & PARENB)
2326 smr_val |= SCSMR_PE;
2327 if (termios->c_cflag & PARODD)
2328 smr_val |= SCSMR_PE | SCSMR_ODD;
2329 if (termios->c_cflag & CSTOPB)
2330 smr_val |= SCSMR_STOP;
2331
154280fd
MD		 2332 /*
2333 * earlyprintk comes here early on with port->uartclk set to zero.
2334 * the clock framework is not up and running at this point so here
2335 * we assume that 115200 is the maximum baud rate. please note that
2336 * the baud rate is not programmed during earlyprintk - it is assumed
2337 * that the previous boot loader has enabled required clocks and
2338 * setup the baud rate generator hardware for us already.
2339 */
f4998e55
GU		 2340 if (!port->uartclk) {
2341 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2342 goto done;
2343 }
1da177e4 2344
f4998e55
GU		 2345 for (i = 0; i < SCI_NUM_CLKS; i++)
2346 max_freq = max(max_freq, s->clk_rates[i]);
2347
69eee8e9 2348 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
f4998e55
GU		 2349 if (!baud)
2350 goto done;
2351
2352 /*
2353 * There can be multiple sources for the sampling clock. Find the one
2354 * that gives us the smallest deviation from the desired baud rate.
2355 */
2356
6af27bf2
GU		 2357 /* Optional Undivided External Clock */
2358 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2359 port->type != PORT_SCIFB) {
2360 err = sci_sck_calc(s, baud, &srr1);
2361 if (abs(err) < abs(min_err)) {
2362 best_clk = SCI_SCK;
2363 scr_val = SCSCR_CKE1;
2364 sccks = SCCKS_CKS;
2365 min_err = err;
2366 srr = srr1;
2367 if (!err)
2368 goto done;
2369 }
2370 }
2371
1270f865
GU		 2372 /* Optional BRG Frequency Divided External Clock */
2373 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2374 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2375 &srr1);
2376 if (abs(err) < abs(min_err)) {
2377 best_clk = SCI_SCIF_CLK;
2378 scr_val = SCSCR_CKE1;
2379 sccks = 0;
2380 min_err = err;
2381 dl = dl1;
2382 srr = srr1;
2383 if (!err)
2384 goto done;
2385 }
2386 }
2387
2388 /* Optional BRG Frequency Divided Internal Clock */
2389 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2390 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2391 &srr1);
2392 if (abs(err) < abs(min_err)) {
2393 best_clk = SCI_BRG_INT;
2394 scr_val = SCSCR_CKE1;
2395 sccks = SCCKS_XIN;
2396 min_err = err;
2397 dl = dl1;
2398 srr = srr1;
2399 if (!min_err)
2400 goto done;
f303b364
UH		 2401 }
2402 }
e108b2ca 2403
f4998e55
GU		 2404 /* Divided Functional Clock using standard Bit Rate Register */
2405 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2406 if (abs(err) < abs(min_err)) {
2407 best_clk = SCI_FCK;
6af27bf2 2408 scr_val = 0;
f4998e55
GU		 2409 min_err = err;
2410 brr = brr1;
2411 srr = srr1;
2412 cks = cks1;
2413 }
2414
2415done:
2416 if (best_clk >= 0)
2417 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2418 s->clks[best_clk], baud, min_err);
e108b2ca 2419
23241d43 2420 sci_port_enable(s);
36003386 2421
6af27bf2
GU		 2422 /*
2423 * Program the optional External Baud Rate Generator (BRG) first.
2424 * It controls the mux to select (H)SCK or frequency divided clock.
2425 */
1270f865
GU		 2426 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2427 serial_port_out(port, SCDL, dl);
6af27bf2 2428 serial_port_out(port, SCCKS, sccks);
1270f865 2429 }
1da177e4 2430
1be22663
TA		 2431 spin_lock_irqsave(&port->lock, flags);
2432
1ba76220 2433 sci_reset(port);
1da177e4
LT		 2434
2435 uart_update_timeout(port, termios->c_cflag, baud);
2436
63ba1e00
UH		 2437 /* byte size and parity */
2438 switch (termios->c_cflag & CSIZE) {
2439 case CS5:
2440 bits = 7;
2441 break;
2442 case CS6:
2443 bits = 8;
2444 break;
2445 case CS7:
2446 bits = 9;
2447 break;
2448 default:
2449 bits = 10;
2450 break;
2451 }
2452
2453 if (termios->c_cflag & CSTOPB)
2454 bits++;
2455 if (termios->c_cflag & PARENB)
2456 bits++;
2457
f4998e55 2458 if (best_clk >= 0) {
92a05748
GU		 2459 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2460 switch (srr + 1) {
2461 case 5: smr_val |= SCSMR_SRC_5; break;
2462 case 7: smr_val |= SCSMR_SRC_7; break;
2463 case 11: smr_val |= SCSMR_SRC_11; break;
2464 case 13: smr_val |= SCSMR_SRC_13; break;
2465 case 16: smr_val |= SCSMR_SRC_16; break;
2466 case 17: smr_val |= SCSMR_SRC_17; break;
2467 case 19: smr_val |= SCSMR_SRC_19; break;
2468 case 27: smr_val |= SCSMR_SRC_27; break;
2469 }
f4998e55 2470 smr_val |= cks;
fa2abb03 2471 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
f4998e55
GU		 2472 serial_port_out(port, SCSMR, smr_val);
2473 serial_port_out(port, SCBRR, brr);
63ba1e00
UH		 2474 if (sci_getreg(port, HSSRR)->size) {
2475 unsigned int hssrr = srr | HSCIF_SRE;
2476 /* Calculate deviation from intended rate at the
2477 * center of the last stop bit in sampling clocks.
2478 */
2479 int last_stop = bits * 2 - 1;
2480 int deviation = min_err * srr * last_stop / 2 / baud;
2481
2482 if (abs(deviation) >= 2) {
2483 /* At least two sampling clocks off at the
2484 * last stop bit; we can increase the error
2485 * margin by shifting the sampling point.
2486 */
2487 int shift = min(-8, max(7, deviation / 2));
2488
2489 hssrr |= (shift << HSCIF_SRHP_SHIFT) &
2490 HSCIF_SRHP_MASK;
2491 hssrr |= HSCIF_SRDE;
2492 }
2493 serial_port_out(port, HSSRR, hssrr);
2494 }
f4998e55
GU		 2495
2496 /* Wait one bit interval */
2497 udelay((1000000 + (baud - 1)) / baud);
2498 } else {
2499 /* Don't touch the bit rate configuration */
2500 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
3a964abe
GU		 2501 smr_val |= serial_port_in(port, SCSMR) &
2502 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
fa2abb03 2503 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
9d482cc3 2504 serial_port_out(port, SCSMR, smr_val);
f4998e55 2505 }
1da177e4 2506
d5701647 2507 sci_init_pins(port, termios->c_cflag);
0979e0e6 2508
33f50ffc
GU		 2509 port->status &= ~UPSTAT_AUTOCTS;
2510 s->autorts = false;
73c3d53f
PM		 2511 reg = sci_getreg(port, SCFCR);
2512 if (reg->size) {
b12bb29f 2513 unsigned short ctrl = serial_port_in(port, SCFCR);
0979e0e6 2514
33f50ffc
GU		 2515 if ((port->flags & UPF_HARD_FLOW) &&
2516 (termios->c_cflag & CRTSCTS)) {
2517 /* There is no CTS interrupt to restart the hardware */
2518 port->status |= UPSTAT_AUTOCTS;
2519 /* MCE is enabled when RTS is raised */
2520 s->autorts = true;
faf02f8f 2521 }
73c3d53f
PM		 2522
2523 /*
2524 * As we've done a sci_reset() above, ensure we don't
2525 * interfere with the FIFOs while toggling MCE. As the
2526 * reset values could still be set, simply mask them out.
2527 */
2528 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2529
b12bb29f 2530 serial_port_out(port, SCFCR, ctrl);
0979e0e6 2531 }
5f76895e
GU		 2532 if (port->flags & UPF_HARD_FLOW) {
2533 /* Refresh (Auto) RTS */
2534 sci_set_mctrl(port, port->mctrl);
2535 }
b7a76e4b 2536
9f8325b3
LP		 2537 scr_val |= SCSCR_RE | SCSCR_TE |
2538 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
fa2abb03 2539 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
92a05748
GU		 2540 if ((srr + 1 == 5) &&
2541 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2542 /*
2543 * In asynchronous mode, when the sampling rate is 1/5, first
2544 * received data may become invalid on some SCIFA and SCIFB.
2545 * To avoid this problem wait more than 1 serial data time (1
2546 * bit time x serial data number) after setting SCSCR.RE = 1.
2547 */
2548 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2549 }
1da177e4 2550
3089f381 2551 /*
5f6d8515 2552 * Calculate delay for 2 DMA buffers (4 FIFO).
f5835c1d
GU		 2553 * See serial_core.c::uart_update_timeout().
2554 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2555 * function calculates 1 jiffie for the data plus 5 jiffies for the
2556 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2557 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2558 * value obtained by this formula is too small. Therefore, if the value
2559 * is smaller than 20ms, use 20ms as the timeout value for DMA.
3089f381 2560 */
b96408b4 2561 s->rx_frame = (10000 * bits) / (baud / 100);
03940376 2562#ifdef CONFIG_SERIAL_SH_SCI_DMA
b96408b4
UH		 2563 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame;
2564 if (s->rx_timeout < 20)
2565 s->rx_timeout = 20;
3089f381
GL		 2566#endif
2567
1da177e4 2568 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 2569 sci_start_rx(port);
36003386 2570
1be22663
TA		 2571 spin_unlock_irqrestore(&port->lock, flags);
2572
23241d43 2573 sci_port_disable(s);
f907c9ea
GU		 2574
2575 if (UART_ENABLE_MS(port, termios->c_cflag))
2576 sci_enable_ms(port);
1da177e4
LT		 2577}
2578
0174e5ca
TK		 2579static void sci_pm(struct uart_port *port, unsigned int state,
2580 unsigned int oldstate)
2581{
2582 struct sci_port *sci_port = to_sci_port(port);
2583
2584 switch (state) {
d3dfe5d9 2585 case UART_PM_STATE_OFF:
0174e5ca
TK		 2586 sci_port_disable(sci_port);
2587 break;
2588 default:
2589 sci_port_enable(sci_port);
2590 break;
2591 }
2592}
2593
1da177e4
LT		 2594static const char *sci_type(struct uart_port *port)
2595{
2596 switch (port->type) {
e7c98dc7
MT		 2597 case PORT_IRDA:
2598 return "irda";
2599 case PORT_SCI:
2600 return "sci";
2601 case PORT_SCIF:
2602 return "scif";
2603 case PORT_SCIFA:
2604 return "scifa";
d1d4b10c
GL		 2605 case PORT_SCIFB:
2606 return "scifb";
f303b364
UH		 2607 case PORT_HSCIF:
2608 return "hscif";
1da177e4
LT		 2609 }
2610
fa43972f 2611 return NULL;
1da177e4
LT		 2612}
2613
f6e9495d
PM		 2614static int sci_remap_port(struct uart_port *port)
2615{
e4d6f911 2616 struct sci_port *sport = to_sci_port(port);
f6e9495d
PM		 2617
2618 /*
2619 * Nothing to do if there's already an established membase.
2620 */
2621 if (port->membase)
2622 return 0;
2623
3d73f32b 2624 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
e4d6f911 2625 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
f6e9495d
PM		 2626 if (unlikely(!port->membase)) {
2627 dev_err(port->dev, "can't remap port#%d\n", port->line);
2628 return -ENXIO;
2629 }
2630 } else {
2631 /*
2632 * For the simple (and majority of) cases where we don't
2633 * need to do any remapping, just cast the cookie
2634 * directly.
2635 */
3af4e960 2636 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
f6e9495d
PM		 2637 }
2638
2639 return 0;
2640}
2641
e2651647 2642static void sci_release_port(struct uart_port *port)
1da177e4 2643{
e4d6f911
YS		 2644 struct sci_port *sport = to_sci_port(port);
2645
3d73f32b 2646 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
e2651647
PM		 2647 iounmap(port->membase);
2648 port->membase = NULL;
2649 }
2650
e4d6f911 2651 release_mem_region(port->mapbase, sport->reg_size);
1da177e4
LT		 2652}
2653
e2651647 2654static int sci_request_port(struct uart_port *port)
1da177e4 2655{
e2651647 2656 struct resource *res;
e4d6f911 2657 struct sci_port *sport = to_sci_port(port);
f6e9495d 2658 int ret;
1da177e4 2659
e4d6f911
YS		 2660 res = request_mem_region(port->mapbase, sport->reg_size,
2661 dev_name(port->dev));
2662 if (unlikely(res == NULL)) {
2663 dev_err(port->dev, "request_mem_region failed.");
e2651647 2664 return -EBUSY;
e4d6f911 2665 }
1da177e4 2666
f6e9495d
PM		 2667 ret = sci_remap_port(port);
2668 if (unlikely(ret != 0)) {
2669 release_resource(res);
2670 return ret;
7ff731ae 2671 }
e2651647
PM		 2672
2673 return 0;
2674}
2675
2676static void sci_config_port(struct uart_port *port, int flags)
2677{
2678 if (flags & UART_CONFIG_TYPE) {
2679 struct sci_port *sport = to_sci_port(port);
2680
2681 port->type = sport->cfg->type;
2682 sci_request_port(port);
2683 }
1da177e4
LT		 2684}
2685
2686static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2687{
1da177e4
LT		 2688 if (ser->baud_base < 2400)
2689 /* No paper tape reader for Mitch.. */
2690 return -EINVAL;
2691
2692 return 0;
2693}
2694
069a47e5 2695static const struct uart_ops sci_uart_ops = {
1da177e4
LT		 2696 .tx_empty = sci_tx_empty,
2697 .set_mctrl = sci_set_mctrl,
2698 .get_mctrl = sci_get_mctrl,
2699 .start_tx = sci_start_tx,
2700 .stop_tx = sci_stop_tx,
2701 .stop_rx = sci_stop_rx,
f907c9ea 2702 .enable_ms = sci_enable_ms,
1da177e4
LT		 2703 .break_ctl = sci_break_ctl,
2704 .startup = sci_startup,
2705 .shutdown = sci_shutdown,
1cf4a7ef 2706 .flush_buffer = sci_flush_buffer,
1da177e4 2707 .set_termios = sci_set_termios,
0174e5ca 2708 .pm = sci_pm,
1da177e4
LT		 2709 .type = sci_type,
2710 .release_port = sci_release_port,
2711 .request_port = sci_request_port,
2712 .config_port = sci_config_port,
2713 .verify_port = sci_verify_port,
07d2a1a1
PM		 2714#ifdef CONFIG_CONSOLE_POLL
2715 .poll_get_char = sci_poll_get_char,
2716 .poll_put_char = sci_poll_put_char,
2717#endif
1da177e4
LT		 2718};
2719
a9ec81f4
LP		 2720static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2721{
f4998e55
GU		 2722 const char *clk_names[] = {
2723 [SCI_FCK] = "fck",
6af27bf2 2724 [SCI_SCK] = "sck",
1270f865
GU		 2725 [SCI_BRG_INT] = "brg_int",
2726 [SCI_SCIF_CLK] = "scif_clk",
f4998e55
GU		 2727 };
2728 struct clk *clk;
2729 unsigned int i;
a9ec81f4 2730
6af27bf2
GU		 2731 if (sci_port->cfg->type == PORT_HSCIF)
2732 clk_names[SCI_SCK] = "hsck";
2733
f4998e55
GU		 2734 for (i = 0; i < SCI_NUM_CLKS; i++) {
2735 clk = devm_clk_get(dev, clk_names[i]);
2736 if (PTR_ERR(clk) == -EPROBE_DEFER)
2737 return -EPROBE_DEFER;
a9ec81f4 2738
f4998e55
GU		 2739 if (IS_ERR(clk) && i == SCI_FCK) {
2740 /*
2741 * "fck" used to be called "sci_ick", and we need to
2742 * maintain DT backward compatibility.
2743 */
2744 clk = devm_clk_get(dev, "sci_ick");
2745 if (PTR_ERR(clk) == -EPROBE_DEFER)
2746 return -EPROBE_DEFER;
a9ec81f4 2747
f4998e55
GU		 2748 if (!IS_ERR(clk))
2749 goto found;
a9ec81f4 2750
f4998e55
GU		 2751 /*
2752 * Not all SH platforms declare a clock lookup entry
2753 * for SCI devices, in which case we need to get the
2754 * global "peripheral_clk" clock.
2755 */
2756 clk = devm_clk_get(dev, "peripheral_clk");
2757 if (!IS_ERR(clk))
2758 goto found;
2759
2760 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i],
2761 PTR_ERR(clk));
2762 return PTR_ERR(clk);
2763 }
2764
2765found:
2766 if (IS_ERR(clk))
2767 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i],
2768 PTR_ERR(clk));
2769 else
d63c16f8
GU		 2770 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i],
2771 clk, clk_get_rate(clk));
f4998e55
GU		 2772 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
2773 }
2774 return 0;
a9ec81f4
LP		 2775}
2776
daf5a895
LP		 2777static const struct sci_port_params *
2778sci_probe_regmap(const struct plat_sci_port *cfg)
2779{
2780 unsigned int regtype;
2781
2782 if (cfg->regtype != SCIx_PROBE_REGTYPE)
2783 return &sci_port_params[cfg->regtype];
2784
2785 switch (cfg->type) {
2786 case PORT_SCI:
2787 regtype = SCIx_SCI_REGTYPE;
2788 break;
2789 case PORT_IRDA:
2790 regtype = SCIx_IRDA_REGTYPE;
2791 break;
2792 case PORT_SCIFA:
2793 regtype = SCIx_SCIFA_REGTYPE;
2794 break;
2795 case PORT_SCIFB:
2796 regtype = SCIx_SCIFB_REGTYPE;
2797 break;
2798 case PORT_SCIF:
2799 /*
2800 * The SH-4 is a bit of a misnomer here, although that's
2801 * where this particular port layout originated. This
2802 * configuration (or some slight variation thereof)
2803 * remains the dominant model for all SCIFs.
2804 */
2805 regtype = SCIx_SH4_SCIF_REGTYPE;
2806 break;
2807 case PORT_HSCIF:
2808 regtype = SCIx_HSCIF_REGTYPE;
2809 break;
2810 default:
2811 pr_err("Can't probe register map for given port\n");
2812 return NULL;
2813 }
2814
2815 return &sci_port_params[regtype];
2816}
2817
9671f099 2818static int sci_init_single(struct platform_device *dev,
1fcc91a6 2819 struct sci_port *sci_port, unsigned int index,
daf5a895 2820 const struct plat_sci_port *p, bool early)
e108b2ca 2821{
73a19e4c 2822 struct uart_port *port = &sci_port->port;
1fcc91a6 2823 const struct resource *res;
2d4dd0da 2824 unsigned int i, regtype;
3127c6b2 2825 int ret;
e108b2ca 2826
50f0959a
PM		 2827 sci_port->cfg = p;
2828
73a19e4c
GL		 2829 port->ops = &sci_uart_ops;
2830 port->iotype = UPIO_MEM;
2831 port->line = index;
75136d48 2832
89b5c1ab
LP		 2833 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2834 if (res == NULL)
2835 return -ENOMEM;
1fcc91a6 2836
89b5c1ab 2837 port->mapbase = res->start;
e4d6f911 2838 sci_port->reg_size = resource_size(res);
1fcc91a6 2839
89b5c1ab
LP		 2840 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2841 sci_port->irqs[i] = platform_get_irq(dev, i);
1fcc91a6 2842
89b5c1ab
LP		 2843 /* The SCI generates several interrupts. They can be muxed together or
2844 * connected to different interrupt lines. In the muxed case only one
2845 * interrupt resource is specified. In the non-muxed case three or four
2846 * interrupt resources are specified, as the BRI interrupt is optional.
2847 */
2848 if (sci_port->irqs[0] < 0)
2849 return -ENXIO;
1fcc91a6 2850
89b5c1ab
LP		 2851 if (sci_port->irqs[1] < 0) {
2852 sci_port->irqs[1] = sci_port->irqs[0];
2853 sci_port->irqs[2] = sci_port->irqs[0];
2854 sci_port->irqs[3] = sci_port->irqs[0];
1fcc91a6
LP		 2855 }
2856
daf5a895
LP		 2857 sci_port->params = sci_probe_regmap(p);
2858 if (unlikely(sci_port->params == NULL))
2859 return -EINVAL;
e095ee6b 2860
2d4dd0da 2861 regtype = sci_port->params - sci_port_params;
18e8cf15
UH		 2862 switch (p->type) {
2863 case PORT_SCIFB:
2864 sci_port->rx_trigger = 48;
2865 break;
2866 case PORT_HSCIF:
2867 sci_port->rx_trigger = 64;
2868 break;
2869 case PORT_SCIFA:
2870 sci_port->rx_trigger = 32;
2871 break;
2872 case PORT_SCIF:
2873 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
2874 /* RX triggering not implemented for this IP */
2875 sci_port->rx_trigger = 1;
2876 else
2877 sci_port->rx_trigger = 8;
2878 break;
2879 default:
2880 sci_port->rx_trigger = 1;
2881 break;
2882 }
2883
03940376 2884 sci_port->rx_fifo_timeout = 0;
fa2abb03 2885 sci_port->hscif_tot = 0;
03940376 2886
878fbb91
LP		 2887 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2888 * match the SoC datasheet, this should be investigated. Let platform
2889 * data override the sampling rate for now.
ec09c5eb 2890 */
b2f20ed9
LP		 2891 sci_port->sampling_rate_mask = p->sampling_rate
2892 ? SCI_SR(p->sampling_rate)
2893 : sci_port->params->sampling_rate_mask;
ec09c5eb 2894
1fcc91a6 2895 if (!early) {
a9ec81f4
LP		 2896 ret = sci_init_clocks(sci_port, &dev->dev);
2897 if (ret < 0)
2898 return ret;
c7ed1ab3 2899
73a19e4c 2900 port->dev = &dev->dev;
5e50d2d6
MD		 2901
2902 pm_runtime_enable(&dev->dev);
7b6fd3bf 2903 }
e108b2ca 2904
ce6738b6 2905 port->type = p->type;
3d73f32b 2906 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
b2f20ed9 2907 port->fifosize = sci_port->params->fifosize;
73a19e4c 2908
dfc80387
LP		 2909 if (port->type == PORT_SCI) {
2910 if (sci_port->reg_size >= 0x20)
2911 port->regshift = 2;
2912 else
2913 port->regshift = 1;
2914 }
2915
2d4dd0da
CB		 2916 if (regtype == SCIx_SH4_SCIF_REGTYPE)
2917 if (sci_port->reg_size >= 0x20)
2918 port->regshift = 1;
2919
ce6738b6 2920 /*
61a6976b 2921 * The UART port needs an IRQ value, so we peg this to the RX IRQ
ce6738b6
PM		 2922 * for the multi-IRQ ports, which is where we are primarily
2923 * concerned with the shutdown path synchronization.
2924 *
2925 * For the muxed case there's nothing more to do.
2926 */
1fcc91a6 2927 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
9cfb5c05 2928 port->irqflags = 0;
73a19e4c 2929
61a6976b
PM		 2930 port->serial_in = sci_serial_in;
2931 port->serial_out = sci_serial_out;
2932
c7ed1ab3 2933 return 0;
e108b2ca
PM		 2934}
2935
6dae1421
LP		 2936static void sci_cleanup_single(struct sci_port *port)
2937{
6dae1421
LP		 2938 pm_runtime_disable(port->port.dev);
2939}
2940
0b0cced1
YS		 2941#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
2942 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
dc8e6f5b
MD		 2943static void serial_console_putchar(struct uart_port *port, int ch)
2944{
2945 sci_poll_put_char(port, ch);
2946}
2947
1da177e4
LT		 2948/*
2949 * Print a string to the serial port trying not to disturb
2950 * any possible real use of the port...
2951 */
2952static void serial_console_write(struct console *co, const char *s,
2953 unsigned count)
2954{
906b17dc
PM		 2955 struct sci_port *sci_port = &sci_ports[co->index];
2956 struct uart_port *port = &sci_port->port;
a67969b5 2957 unsigned short bits, ctrl, ctrl_temp;
40f70c03
SK		 2958 unsigned long flags;
2959 int locked = 1;
2960
0b0cced1 2961#if defined(SUPPORT_SYSRQ)
40f70c03
SK		 2962 if (port->sysrq)
2963 locked = 0;
0b0cced1
YS		 2964 else
2965#endif
2966 if (oops_in_progress)
8afb1d2c 2967 locked = spin_trylock_irqsave(&port->lock, flags);
40f70c03 2968 else
8afb1d2c 2969 spin_lock_irqsave(&port->lock, flags);
40f70c03 2970
a67969b5 2971 /* first save SCSCR then disable interrupts, keep clock source */
40f70c03 2972 ctrl = serial_port_in(port, SCSCR);
9f8325b3
LP		 2973 ctrl_temp = SCSCR_RE | SCSCR_TE |
2974 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
a67969b5 2975 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
fa2abb03 2976 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot);
07d2a1a1 2977
501b825d 2978 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 2979
2980 /* wait until fifo is empty and last bit has been transmitted */
2981 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
b12bb29f 2982 while ((serial_port_in(port, SCxSR) & bits) != bits)
973e5d52 2983 cpu_relax();
40f70c03
SK		 2984
2985 /* restore the SCSCR */
2986 serial_port_out(port, SCSCR, ctrl);
2987
2988 if (locked)
8afb1d2c 2989 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 2990}
2991
9671f099 2992static int serial_console_setup(struct console *co, char *options)
1da177e4 2993{
dc8e6f5b 2994 struct sci_port *sci_port;
1da177e4
LT		 2995 struct uart_port *port;
2996 int baud = 115200;
2997 int bits = 8;
2998 int parity = 'n';
2999 int flow = 'n';
3000 int ret;
3001
e108b2ca 3002 /*
906b17dc 3003 * Refuse to handle any bogus ports.
1da177e4 3004 */
906b17dc 3005 if (co->index < 0 || co->index >= SCI_NPORTS)
e108b2ca 3006 return -ENODEV;
e108b2ca 3007
906b17dc
PM		 3008 sci_port = &sci_ports[co->index];
3009 port = &sci_port->port;
3010
b2267a6b
AC		 3011 /*
3012 * Refuse to handle uninitialized ports.
3013 */
3014 if (!port->ops)
3015 return -ENODEV;
3016
f6e9495d
PM		 3017 ret = sci_remap_port(port);
3018 if (unlikely(ret != 0))
3019 return ret;
e108b2ca 3020
1da177e4
LT		 3021 if (options)
3022 uart_parse_options(options, &baud, &parity, &bits, &flow);
3023
ab7cfb55 3024 return uart_set_options(port, co, baud, parity, bits, flow);
1da177e4
LT		 3025}
3026
3027static struct console serial_console = {
3028 .name = "ttySC",
906b17dc 3029 .device = uart_console_device,
1da177e4
LT		 3030 .write = serial_console_write,
3031 .setup = serial_console_setup,
fa5da2f7 3032 .flags = CON_PRINTBUFFER,
1da177e4 3033 .index = -1,
906b17dc 3034 .data = &sci_uart_driver,
1da177e4
LT		 3035};
3036
7b6fd3bf
MD		 3037static struct console early_serial_console = {
3038 .name = "early_ttySC",
3039 .write = serial_console_write,
3040 .flags = CON_PRINTBUFFER,
906b17dc 3041 .index = -1,
7b6fd3bf 3042};
ecdf8a46 3043
7b6fd3bf
MD		 3044static char early_serial_buf[32];
3045
9671f099 3046static int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46 3047{
daf5a895 3048 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
ecdf8a46
PM		 3049
3050 if (early_serial_console.data)
3051 return -EEXIST;
3052
3053 early_serial_console.index = pdev->id;
ecdf8a46 3054
1fcc91a6 3055 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
ecdf8a46
PM		 3056
3057 serial_console_setup(&early_serial_console, early_serial_buf);
3058
3059 if (!strstr(early_serial_buf, "keep"))
3060 early_serial_console.flags |= CON_BOOT;
3061
3062 register_console(&early_serial_console);
3063 return 0;
3064}
6a8c9799
NI		 3065
3066#define SCI_CONSOLE (&serial_console)
3067
ecdf8a46 3068#else
9671f099 3069static inline int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46
PM		 3070{
3071 return -EINVAL;
3072}
1da177e4 3073
6a8c9799
NI		 3074#define SCI_CONSOLE NULL
3075
0b0cced1 3076#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
1da177e4 3077
6c13d5d2 3078static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
1da177e4 3079
352b9266 3080static DEFINE_MUTEX(sci_uart_registration_lock);
1da177e4
LT		 3081static struct uart_driver sci_uart_driver = {
3082 .owner = THIS_MODULE,
3083 .driver_name = "sci",
1da177e4
LT		 3084 .dev_name = "ttySC",
3085 .major = SCI_MAJOR,
3086 .minor = SCI_MINOR_START,
e108b2ca 3087 .nr = SCI_NPORTS,
1da177e4
LT		 3088 .cons = SCI_CONSOLE,
3089};
3090
54507f6e 3091static int sci_remove(struct platform_device *dev)
e552de24 3092{
d535a230 3093 struct sci_port *port = platform_get_drvdata(dev);
e552de24 3094
7678f4c2 3095 sci_ports_in_use &= ~BIT(port->port.line);
d535a230
PM		 3096 uart_remove_one_port(&sci_uart_driver, &port->port);
3097
6dae1421 3098 sci_cleanup_single(port);
e552de24 3099
5d23188a
UH		 3100 if (port->port.fifosize > 1) {
3101 sysfs_remove_file(&dev->dev.kobj,
3102 &dev_attr_rx_fifo_trigger.attr);
3103 }
fa2abb03
UH		 3104 if (port->port.type == PORT_SCIFA || port->port.type == PORT_SCIFB ||
3105 port->port.type == PORT_HSCIF) {
5d23188a
UH		 3106 sysfs_remove_file(&dev->dev.kobj,
3107 &dev_attr_rx_fifo_timeout.attr);
3108 }
3109
e552de24
MD		 3110 return 0;
3111}
3112
bd2238fb
GU		 3113
3114#define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
3115#define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
3116#define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
20bdcab8
BH		 3117
3118static const struct of_device_id of_sci_match[] = {
f443ff80
GU		 3119 /* SoC-specific types */
3120 {
3121 .compatible = "renesas,scif-r7s72100",
3122 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
3123 },
9ed44bb2
GU		 3124 /* Family-specific types */
3125 {
3126 .compatible = "renesas,rcar-gen1-scif",
3127 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3128 }, {
3129 .compatible = "renesas,rcar-gen2-scif",
3130 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3131 }, {
3132 .compatible = "renesas,rcar-gen3-scif",
3133 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3134 },
f443ff80 3135 /* Generic types */
20bdcab8
BH		 3136 {
3137 .compatible = "renesas,scif",
bd2238fb 3138 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
20bdcab8
BH		 3139 }, {
3140 .compatible = "renesas,scifa",
bd2238fb 3141 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
20bdcab8
BH		 3142 }, {
3143 .compatible = "renesas,scifb",
bd2238fb 3144 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
20bdcab8
BH		 3145 }, {
3146 .compatible = "renesas,hscif",
bd2238fb 3147 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
e1d0be61
YS		 3148 }, {
3149 .compatible = "renesas,sci",
bd2238fb 3150 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
20bdcab8
BH		 3151 }, {
3152 /* Terminator */
3153 },
3154};
3155MODULE_DEVICE_TABLE(of, of_sci_match);
3156
54b12c48
GU		 3157static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
3158 unsigned int *dev_id)
20bdcab8
BH		 3159{
3160 struct device_node *np = pdev->dev.of_node;
20bdcab8 3161 struct plat_sci_port *p;
97ed9790 3162 struct sci_port *sp;
6e605a01 3163 const void *data;
20bdcab8
BH		 3164 int id;
3165
3166 if (!IS_ENABLED(CONFIG_OF) || !np)
3167 return NULL;
3168
6e605a01 3169 data = of_device_get_match_data(&pdev->dev);
20bdcab8 3170
20bdcab8 3171 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
4205463c 3172 if (!p)
20bdcab8 3173 return NULL;
20bdcab8 3174
2095fc76 3175 /* Get the line number from the aliases node. */
20bdcab8 3176 id = of_alias_get_id(np, "serial");
7678f4c2
GU		 3177 if (id < 0 && ~sci_ports_in_use)
3178 id = ffz(sci_ports_in_use);
20bdcab8
BH		 3179 if (id < 0) {
3180 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
3181 return NULL;
3182 }
090fa4b0
GU		 3183 if (id >= ARRAY_SIZE(sci_ports)) {
3184 dev_err(&pdev->dev, "serial%d out of range\n", id);
3185 return NULL;
3186 }
20bdcab8 3187
97ed9790 3188 sp = &sci_ports[id];
20bdcab8
BH		 3189 *dev_id = id;
3190
6e605a01
GU		 3191 p->type = SCI_OF_TYPE(data);
3192 p->regtype = SCI_OF_REGTYPE(data);
20bdcab8 3193
43c61286 3194 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
861a70ab 3195
20bdcab8
BH		 3196 return p;
3197}
3198
9671f099 3199static int sci_probe_single(struct platform_device *dev,
0ee70712
MD		 3200 unsigned int index,
3201 struct plat_sci_port *p,
3202 struct sci_port *sciport)
3203{
0ee70712
MD		 3204 int ret;
3205
3206 /* Sanity check */
3207 if (unlikely(index >= SCI_NPORTS)) {
9b971cd2 3208 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
0ee70712 3209 index+1, SCI_NPORTS);
9b971cd2 3210 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
b6c5ef6f 3211 return -EINVAL;
0ee70712 3212 }
7678f4c2
GU		 3213 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8);
3214 if (sci_ports_in_use & BIT(index))
3215 return -EBUSY;
0ee70712 3216
352b9266
SS		 3217 mutex_lock(&sci_uart_registration_lock);
3218 if (!sci_uart_driver.state) {
3219 ret = uart_register_driver(&sci_uart_driver);
3220 if (ret) {
3221 mutex_unlock(&sci_uart_registration_lock);
3222 return ret;
3223 }
3224 }
3225 mutex_unlock(&sci_uart_registration_lock);
3226
1fcc91a6 3227 ret = sci_init_single(dev, sciport, index, p, false);
c7ed1ab3
PM		 3228 if (ret)
3229 return ret;
0ee70712 3230
f907c9ea
GU		 3231 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3232 if (IS_ERR(sciport->gpios) && PTR_ERR(sciport->gpios) != -ENOSYS)
3233 return PTR_ERR(sciport->gpios);
3234
97ed9790 3235 if (sciport->has_rtscts) {
f907c9ea
GU		 3236 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3237 UART_GPIO_CTS)) ||
3238 !IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3239 UART_GPIO_RTS))) {
3240 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3241 return -EINVAL;
3242 }
33f50ffc 3243 sciport->port.flags |= UPF_HARD_FLOW;
f907c9ea
GU		 3244 }
3245
6dae1421
LP		 3246 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
3247 if (ret) {
3248 sci_cleanup_single(sciport);
3249 return ret;
3250 }
3251
3252 return 0;
0ee70712
MD		 3253}
3254
9671f099 3255static int sci_probe(struct platform_device *dev)
1da177e4 3256{
20bdcab8
BH		 3257 struct plat_sci_port *p;
3258 struct sci_port *sp;
3259 unsigned int dev_id;
ecdf8a46 3260 int ret;
d535a230 3261
ecdf8a46
PM		 3262 /*
3263 * If we've come here via earlyprintk initialization, head off to
3264 * the special early probe. We don't have sufficient device state
3265 * to make it beyond this yet.
3266 */
3267 if (is_early_platform_device(dev))
3268 return sci_probe_earlyprintk(dev);
7b6fd3bf 3269
20bdcab8
BH		 3270 if (dev->dev.of_node) {
3271 p = sci_parse_dt(dev, &dev_id);
3272 if (p == NULL)
3273 return -EINVAL;
3274 } else {
3275 p = dev->dev.platform_data;
3276 if (p == NULL) {
3277 dev_err(&dev->dev, "no platform data supplied\n");
3278 return -EINVAL;
3279 }
3280
3281 dev_id = dev->id;
3282 }
3283
3284 sp = &sci_ports[dev_id];
d535a230 3285 platform_set_drvdata(dev, sp);
e552de24 3286
20bdcab8 3287 ret = sci_probe_single(dev, dev_id, p, sp);
d535a230 3288 if (ret)
6dae1421 3289 return ret;
e552de24 3290
5d23188a
UH		 3291 if (sp->port.fifosize > 1) {
3292 ret = sysfs_create_file(&dev->dev.kobj,
3293 &dev_attr_rx_fifo_trigger.attr);
3294 if (ret)
3295 return ret;
3296 }
fa2abb03
UH		 3297 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB ||
3298 sp->port.type == PORT_HSCIF) {
5d23188a
UH		 3299 ret = sysfs_create_file(&dev->dev.kobj,
3300 &dev_attr_rx_fifo_timeout.attr);
3301 if (ret) {
3302 if (sp->port.fifosize > 1) {
3303 sysfs_remove_file(&dev->dev.kobj,
3304 &dev_attr_rx_fifo_trigger.attr);
3305 }
3306 return ret;
3307 }
3308 }
3309
1da177e4
LT		 3310#ifdef CONFIG_SH_STANDARD_BIOS
3311 sh_bios_gdb_detach();
3312#endif
3313
7678f4c2 3314 sci_ports_in_use |= BIT(dev_id);
e108b2ca 3315 return 0;
1da177e4
LT		 3316}
3317
cb876341 3318static __maybe_unused int sci_suspend(struct device *dev)
1da177e4 3319{
d535a230 3320 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 3321
d535a230
PM		 3322 if (sport)
3323 uart_suspend_port(&sci_uart_driver, &sport->port);
1da177e4 3324
e108b2ca
PM		 3325 return 0;
3326}
1da177e4 3327
cb876341 3328static __maybe_unused int sci_resume(struct device *dev)
e108b2ca 3329{
d535a230 3330 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 3331
d535a230
PM		 3332 if (sport)
3333 uart_resume_port(&sci_uart_driver, &sport->port);
e108b2ca
PM		 3334
3335 return 0;
3336}
3337
cb876341 3338static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
6daa79b3 3339
e108b2ca
PM		 3340static struct platform_driver sci_driver = {
3341 .probe = sci_probe,
b9e39c89 3342 .remove = sci_remove,
e108b2ca
PM		 3343 .driver = {
3344 .name = "sh-sci",
6daa79b3 3345 .pm = &sci_dev_pm_ops,
20bdcab8 3346 .of_match_table = of_match_ptr(of_sci_match),
e108b2ca
PM		 3347 },
3348};
3349
3350static int __init sci_init(void)
3351{
6c13d5d2 3352 pr_info("%s\n", banner);
e108b2ca 3353
352b9266 3354 return platform_driver_register(&sci_driver);
e108b2ca
PM		 3355}
3356
3357static void __exit sci_exit(void)
3358{
3359 platform_driver_unregister(&sci_driver);
352b9266
SS		 3360
3361 if (sci_uart_driver.state)
3362 uart_unregister_driver(&sci_uart_driver);
1da177e4
LT		 3363}
3364
7b6fd3bf
MD		 3365#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
3366early_platform_init_buffer("earlyprintk", &sci_driver,
3367 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3368#endif
0b0cced1 3369#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
dd076cff 3370static struct plat_sci_port port_cfg __initdata;
0b0cced1
YS		 3371
3372static int __init early_console_setup(struct earlycon_device *device,
3373 int type)
3374{
3375 if (!device->port.membase)
3376 return -ENODEV;
3377
3378 device->port.serial_in = sci_serial_in;
3379 device->port.serial_out = sci_serial_out;
3380 device->port.type = type;
3381 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
daf5a895 3382 port_cfg.type = type;
0b0cced1 3383 sci_ports[0].cfg = &port_cfg;
daf5a895 3384 sci_ports[0].params = sci_probe_regmap(&port_cfg);
9f8325b3
LP		 3385 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
3386 sci_serial_out(&sci_ports[0].port, SCSCR,
3387 SCSCR_RE | SCSCR_TE | port_cfg.scscr);
0b0cced1
YS		 3388
3389 device->con->write = serial_console_write;
3390 return 0;
3391}
3392static int __init sci_early_console_setup(struct earlycon_device *device,
3393 const char *opt)
3394{
3395 return early_console_setup(device, PORT_SCI);
3396}
3397static int __init scif_early_console_setup(struct earlycon_device *device,
3398 const char *opt)
3399{
3400 return early_console_setup(device, PORT_SCIF);
3401}
3402static int __init scifa_early_console_setup(struct earlycon_device *device,
3403 const char *opt)
3404{
3405 return early_console_setup(device, PORT_SCIFA);
3406}
3407static int __init scifb_early_console_setup(struct earlycon_device *device,
3408 const char *opt)
3409{
3410 return early_console_setup(device, PORT_SCIFB);
3411}
3412static int __init hscif_early_console_setup(struct earlycon_device *device,
3413 const char *opt)
3414{
3415 return early_console_setup(device, PORT_HSCIF);
3416}
3417
0b0cced1 3418OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
0b0cced1 3419OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
0b0cced1 3420OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
0b0cced1 3421OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
0b0cced1
YS		 3422OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3423#endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3424
1da177e4
LT		 3425module_init(sci_init);
3426module_exit(sci_exit);
3427
e108b2ca 3428MODULE_LICENSE("GPL");
e169c139 3429MODULE_ALIAS("platform:sh-sci");
7f405f9c 3430MODULE_AUTHOR("Paul Mundt");
f303b364 3431MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git