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85d5e707 KVA |
1 | /** |
2 | * core.c - DesignWare USB3 DRD Controller Core file | |
3 | * | |
30c31d58 | 4 | * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com |
85d5e707 KVA |
5 | * |
6 | * Authors: Felipe Balbi <balbi@ti.com>, | |
7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
8 | * | |
30c31d58 KVA |
9 | * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/core.c) and ported |
10 | * to uboot. | |
85d5e707 | 11 | * |
30c31d58 | 12 | * commit cd72f890d2 : usb: dwc3: core: enable phy suspend quirk on non-FPGA |
85d5e707 | 13 | * |
30c31d58 | 14 | * SPDX-License-Identifier: GPL-2.0 |
85d5e707 KVA |
15 | */ |
16 | ||
71744d0d KVA |
17 | #include <common.h> |
18 | #include <malloc.h> | |
19 | #include <asm/dma-mapping.h> | |
85d5e707 | 20 | #include <linux/ioport.h> |
85d5e707 KVA |
21 | |
22 | #include <linux/usb/ch9.h> | |
23 | #include <linux/usb/gadget.h> | |
85d5e707 | 24 | |
85d5e707 KVA |
25 | #include "core.h" |
26 | #include "gadget.h" | |
27 | #include "io.h" | |
28 | ||
71744d0d | 29 | #include "linux-compat.h" |
85d5e707 KVA |
30 | |
31 | /* -------------------------------------------------------------------------- */ | |
32 | ||
33 | void dwc3_set_mode(struct dwc3 *dwc, u32 mode) | |
34 | { | |
35 | u32 reg; | |
36 | ||
37 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
38 | reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); | |
39 | reg |= DWC3_GCTL_PRTCAPDIR(mode); | |
40 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
41 | } | |
42 | ||
43 | /** | |
44 | * dwc3_core_soft_reset - Issues core soft reset and PHY reset | |
45 | * @dwc: pointer to our context structure | |
46 | */ | |
47 | static int dwc3_core_soft_reset(struct dwc3 *dwc) | |
48 | { | |
49 | u32 reg; | |
85d5e707 KVA |
50 | |
51 | /* Before Resetting PHY, put Core in Reset */ | |
52 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
53 | reg |= DWC3_GCTL_CORESOFTRESET; | |
54 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
55 | ||
56 | /* Assert USB3 PHY reset */ | |
57 | reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); | |
58 | reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST; | |
59 | dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); | |
60 | ||
61 | /* Assert USB2 PHY reset */ | |
62 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
63 | reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST; | |
64 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
65 | ||
85d5e707 KVA |
66 | mdelay(100); |
67 | ||
68 | /* Clear USB3 PHY reset */ | |
69 | reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); | |
70 | reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST; | |
71 | dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); | |
72 | ||
73 | /* Clear USB2 PHY reset */ | |
74 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
75 | reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST; | |
76 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
77 | ||
78 | mdelay(100); | |
79 | ||
80 | /* After PHYs are stable we can take Core out of reset state */ | |
81 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
82 | reg &= ~DWC3_GCTL_CORESOFTRESET; | |
83 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
84 | ||
85 | return 0; | |
86 | } | |
87 | ||
88 | /** | |
89 | * dwc3_free_one_event_buffer - Frees one event buffer | |
90 | * @dwc: Pointer to our controller context structure | |
91 | * @evt: Pointer to event buffer to be freed | |
92 | */ | |
93 | static void dwc3_free_one_event_buffer(struct dwc3 *dwc, | |
94 | struct dwc3_event_buffer *evt) | |
95 | { | |
71744d0d | 96 | dma_free_coherent(evt->buf); |
85d5e707 KVA |
97 | } |
98 | ||
99 | /** | |
100 | * dwc3_alloc_one_event_buffer - Allocates one event buffer structure | |
101 | * @dwc: Pointer to our controller context structure | |
102 | * @length: size of the event buffer | |
103 | * | |
104 | * Returns a pointer to the allocated event buffer structure on success | |
105 | * otherwise ERR_PTR(errno). | |
106 | */ | |
107 | static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, | |
108 | unsigned length) | |
109 | { | |
110 | struct dwc3_event_buffer *evt; | |
111 | ||
112 | evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); | |
113 | if (!evt) | |
114 | return ERR_PTR(-ENOMEM); | |
115 | ||
116 | evt->dwc = dwc; | |
117 | evt->length = length; | |
71744d0d KVA |
118 | evt->buf = dma_alloc_coherent(length, |
119 | (unsigned long *)&evt->dma); | |
85d5e707 KVA |
120 | if (!evt->buf) |
121 | return ERR_PTR(-ENOMEM); | |
122 | ||
123 | return evt; | |
124 | } | |
125 | ||
126 | /** | |
127 | * dwc3_free_event_buffers - frees all allocated event buffers | |
128 | * @dwc: Pointer to our controller context structure | |
129 | */ | |
130 | static void dwc3_free_event_buffers(struct dwc3 *dwc) | |
131 | { | |
132 | struct dwc3_event_buffer *evt; | |
133 | int i; | |
134 | ||
135 | for (i = 0; i < dwc->num_event_buffers; i++) { | |
136 | evt = dwc->ev_buffs[i]; | |
137 | if (evt) | |
138 | dwc3_free_one_event_buffer(dwc, evt); | |
139 | } | |
140 | } | |
141 | ||
142 | /** | |
143 | * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length | |
144 | * @dwc: pointer to our controller context structure | |
145 | * @length: size of event buffer | |
146 | * | |
147 | * Returns 0 on success otherwise negative errno. In the error case, dwc | |
148 | * may contain some buffers allocated but not all which were requested. | |
149 | */ | |
150 | static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) | |
151 | { | |
152 | int num; | |
153 | int i; | |
154 | ||
155 | num = DWC3_NUM_INT(dwc->hwparams.hwparams1); | |
156 | dwc->num_event_buffers = num; | |
157 | ||
158 | dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num, | |
159 | GFP_KERNEL); | |
160 | if (!dwc->ev_buffs) | |
161 | return -ENOMEM; | |
162 | ||
163 | for (i = 0; i < num; i++) { | |
164 | struct dwc3_event_buffer *evt; | |
165 | ||
166 | evt = dwc3_alloc_one_event_buffer(dwc, length); | |
167 | if (IS_ERR(evt)) { | |
168 | dev_err(dwc->dev, "can't allocate event buffer\n"); | |
169 | return PTR_ERR(evt); | |
170 | } | |
171 | dwc->ev_buffs[i] = evt; | |
172 | } | |
173 | ||
174 | return 0; | |
175 | } | |
176 | ||
177 | /** | |
178 | * dwc3_event_buffers_setup - setup our allocated event buffers | |
179 | * @dwc: pointer to our controller context structure | |
180 | * | |
181 | * Returns 0 on success otherwise negative errno. | |
182 | */ | |
183 | static int dwc3_event_buffers_setup(struct dwc3 *dwc) | |
184 | { | |
185 | struct dwc3_event_buffer *evt; | |
186 | int n; | |
187 | ||
188 | for (n = 0; n < dwc->num_event_buffers; n++) { | |
189 | evt = dwc->ev_buffs[n]; | |
190 | dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n", | |
191 | evt->buf, (unsigned long long) evt->dma, | |
192 | evt->length); | |
193 | ||
194 | evt->lpos = 0; | |
195 | ||
196 | dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), | |
197 | lower_32_bits(evt->dma)); | |
198 | dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), | |
199 | upper_32_bits(evt->dma)); | |
200 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), | |
201 | DWC3_GEVNTSIZ_SIZE(evt->length)); | |
202 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); | |
203 | } | |
204 | ||
205 | return 0; | |
206 | } | |
207 | ||
208 | static void dwc3_event_buffers_cleanup(struct dwc3 *dwc) | |
209 | { | |
210 | struct dwc3_event_buffer *evt; | |
211 | int n; | |
212 | ||
213 | for (n = 0; n < dwc->num_event_buffers; n++) { | |
214 | evt = dwc->ev_buffs[n]; | |
215 | ||
216 | evt->lpos = 0; | |
217 | ||
218 | dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0); | |
219 | dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0); | |
220 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK | |
221 | | DWC3_GEVNTSIZ_SIZE(0)); | |
222 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); | |
223 | } | |
224 | } | |
225 | ||
226 | static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) | |
227 | { | |
228 | if (!dwc->has_hibernation) | |
229 | return 0; | |
230 | ||
231 | if (!dwc->nr_scratch) | |
232 | return 0; | |
233 | ||
234 | dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, | |
235 | DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); | |
236 | if (!dwc->scratchbuf) | |
237 | return -ENOMEM; | |
238 | ||
239 | return 0; | |
240 | } | |
241 | ||
242 | static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) | |
243 | { | |
244 | dma_addr_t scratch_addr; | |
245 | u32 param; | |
246 | int ret; | |
247 | ||
248 | if (!dwc->has_hibernation) | |
249 | return 0; | |
250 | ||
251 | if (!dwc->nr_scratch) | |
252 | return 0; | |
253 | ||
71744d0d KVA |
254 | scratch_addr = dma_map_single(dwc->scratchbuf, |
255 | dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, | |
256 | DMA_BIDIRECTIONAL); | |
85d5e707 KVA |
257 | if (dma_mapping_error(dwc->dev, scratch_addr)) { |
258 | dev_err(dwc->dev, "failed to map scratch buffer\n"); | |
259 | ret = -EFAULT; | |
260 | goto err0; | |
261 | } | |
262 | ||
263 | dwc->scratch_addr = scratch_addr; | |
264 | ||
265 | param = lower_32_bits(scratch_addr); | |
266 | ||
267 | ret = dwc3_send_gadget_generic_command(dwc, | |
268 | DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); | |
269 | if (ret < 0) | |
270 | goto err1; | |
271 | ||
272 | param = upper_32_bits(scratch_addr); | |
273 | ||
274 | ret = dwc3_send_gadget_generic_command(dwc, | |
275 | DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); | |
276 | if (ret < 0) | |
277 | goto err1; | |
278 | ||
279 | return 0; | |
280 | ||
281 | err1: | |
71744d0d KVA |
282 | dma_unmap_single((void *)dwc->scratch_addr, dwc->nr_scratch * |
283 | DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); | |
85d5e707 KVA |
284 | |
285 | err0: | |
286 | return ret; | |
287 | } | |
288 | ||
289 | static void dwc3_free_scratch_buffers(struct dwc3 *dwc) | |
290 | { | |
291 | if (!dwc->has_hibernation) | |
292 | return; | |
293 | ||
294 | if (!dwc->nr_scratch) | |
295 | return; | |
296 | ||
71744d0d KVA |
297 | dma_unmap_single((void *)dwc->scratch_addr, dwc->nr_scratch * |
298 | DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); | |
85d5e707 KVA |
299 | kfree(dwc->scratchbuf); |
300 | } | |
301 | ||
302 | static void dwc3_core_num_eps(struct dwc3 *dwc) | |
303 | { | |
304 | struct dwc3_hwparams *parms = &dwc->hwparams; | |
305 | ||
306 | dwc->num_in_eps = DWC3_NUM_IN_EPS(parms); | |
307 | dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps; | |
308 | ||
309 | dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n", | |
310 | dwc->num_in_eps, dwc->num_out_eps); | |
311 | } | |
312 | ||
313 | static void dwc3_cache_hwparams(struct dwc3 *dwc) | |
314 | { | |
315 | struct dwc3_hwparams *parms = &dwc->hwparams; | |
316 | ||
317 | parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); | |
318 | parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); | |
319 | parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); | |
320 | parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); | |
321 | parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); | |
322 | parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); | |
323 | parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); | |
324 | parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); | |
325 | parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); | |
326 | } | |
327 | ||
328 | /** | |
329 | * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core | |
330 | * @dwc: Pointer to our controller context structure | |
331 | */ | |
332 | static void dwc3_phy_setup(struct dwc3 *dwc) | |
333 | { | |
334 | u32 reg; | |
335 | ||
336 | reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); | |
337 | ||
338 | /* | |
339 | * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY | |
340 | * to '0' during coreConsultant configuration. So default value | |
341 | * will be '0' when the core is reset. Application needs to set it | |
342 | * to '1' after the core initialization is completed. | |
343 | */ | |
344 | if (dwc->revision > DWC3_REVISION_194A) | |
345 | reg |= DWC3_GUSB3PIPECTL_SUSPHY; | |
346 | ||
347 | if (dwc->u2ss_inp3_quirk) | |
348 | reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; | |
349 | ||
350 | if (dwc->req_p1p2p3_quirk) | |
351 | reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; | |
352 | ||
353 | if (dwc->del_p1p2p3_quirk) | |
354 | reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; | |
355 | ||
356 | if (dwc->del_phy_power_chg_quirk) | |
357 | reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; | |
358 | ||
359 | if (dwc->lfps_filter_quirk) | |
360 | reg |= DWC3_GUSB3PIPECTL_LFPSFILT; | |
361 | ||
362 | if (dwc->rx_detect_poll_quirk) | |
363 | reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; | |
364 | ||
365 | if (dwc->tx_de_emphasis_quirk) | |
366 | reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); | |
367 | ||
368 | if (dwc->dis_u3_susphy_quirk) | |
369 | reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; | |
370 | ||
371 | dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); | |
372 | ||
373 | mdelay(100); | |
374 | ||
375 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
376 | ||
377 | /* | |
378 | * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to | |
379 | * '0' during coreConsultant configuration. So default value will | |
380 | * be '0' when the core is reset. Application needs to set it to | |
381 | * '1' after the core initialization is completed. | |
382 | */ | |
383 | if (dwc->revision > DWC3_REVISION_194A) | |
384 | reg |= DWC3_GUSB2PHYCFG_SUSPHY; | |
385 | ||
386 | if (dwc->dis_u2_susphy_quirk) | |
387 | reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; | |
388 | ||
389 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
390 | ||
391 | mdelay(100); | |
392 | } | |
393 | ||
394 | /** | |
395 | * dwc3_core_init - Low-level initialization of DWC3 Core | |
396 | * @dwc: Pointer to our controller context structure | |
397 | * | |
398 | * Returns 0 on success otherwise negative errno. | |
399 | */ | |
400 | static int dwc3_core_init(struct dwc3 *dwc) | |
401 | { | |
402 | unsigned long timeout; | |
403 | u32 hwparams4 = dwc->hwparams.hwparams4; | |
404 | u32 reg; | |
405 | int ret; | |
406 | ||
407 | reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); | |
408 | /* This should read as U3 followed by revision number */ | |
409 | if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) { | |
410 | dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); | |
411 | ret = -ENODEV; | |
412 | goto err0; | |
413 | } | |
414 | dwc->revision = reg; | |
415 | ||
85d5e707 KVA |
416 | /* Handle USB2.0-only core configuration */ |
417 | if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == | |
418 | DWC3_GHWPARAMS3_SSPHY_IFC_DIS) { | |
419 | if (dwc->maximum_speed == USB_SPEED_SUPER) | |
420 | dwc->maximum_speed = USB_SPEED_HIGH; | |
421 | } | |
422 | ||
423 | /* issue device SoftReset too */ | |
71744d0d | 424 | timeout = 5000; |
85d5e707 | 425 | dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST); |
71744d0d | 426 | while (timeout--) { |
85d5e707 KVA |
427 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
428 | if (!(reg & DWC3_DCTL_CSFTRST)) | |
429 | break; | |
71744d0d | 430 | }; |
85d5e707 | 431 | |
71744d0d KVA |
432 | if (!timeout) { |
433 | dev_err(dwc->dev, "Reset Timed Out\n"); | |
434 | ret = -ETIMEDOUT; | |
435 | goto err0; | |
436 | } | |
85d5e707 KVA |
437 | |
438 | ret = dwc3_core_soft_reset(dwc); | |
439 | if (ret) | |
440 | goto err0; | |
441 | ||
442 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
443 | reg &= ~DWC3_GCTL_SCALEDOWN_MASK; | |
444 | ||
445 | switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { | |
446 | case DWC3_GHWPARAMS1_EN_PWROPT_CLK: | |
447 | /** | |
448 | * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an | |
449 | * issue which would cause xHCI compliance tests to fail. | |
450 | * | |
451 | * Because of that we cannot enable clock gating on such | |
452 | * configurations. | |
453 | * | |
454 | * Refers to: | |
455 | * | |
456 | * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based | |
457 | * SOF/ITP Mode Used | |
458 | */ | |
459 | if ((dwc->dr_mode == USB_DR_MODE_HOST || | |
460 | dwc->dr_mode == USB_DR_MODE_OTG) && | |
461 | (dwc->revision >= DWC3_REVISION_210A && | |
462 | dwc->revision <= DWC3_REVISION_250A)) | |
463 | reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; | |
464 | else | |
465 | reg &= ~DWC3_GCTL_DSBLCLKGTNG; | |
466 | break; | |
467 | case DWC3_GHWPARAMS1_EN_PWROPT_HIB: | |
468 | /* enable hibernation here */ | |
469 | dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); | |
470 | ||
471 | /* | |
472 | * REVISIT Enabling this bit so that host-mode hibernation | |
473 | * will work. Device-mode hibernation is not yet implemented. | |
474 | */ | |
475 | reg |= DWC3_GCTL_GBLHIBERNATIONEN; | |
476 | break; | |
477 | default: | |
478 | dev_dbg(dwc->dev, "No power optimization available\n"); | |
479 | } | |
480 | ||
481 | /* check if current dwc3 is on simulation board */ | |
482 | if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { | |
483 | dev_dbg(dwc->dev, "it is on FPGA board\n"); | |
484 | dwc->is_fpga = true; | |
485 | } | |
486 | ||
71744d0d KVA |
487 | if(dwc->disable_scramble_quirk && !dwc->is_fpga) |
488 | WARN(true, | |
489 | "disable_scramble cannot be used on non-FPGA builds\n"); | |
85d5e707 KVA |
490 | |
491 | if (dwc->disable_scramble_quirk && dwc->is_fpga) | |
492 | reg |= DWC3_GCTL_DISSCRAMBLE; | |
493 | else | |
494 | reg &= ~DWC3_GCTL_DISSCRAMBLE; | |
495 | ||
496 | if (dwc->u2exit_lfps_quirk) | |
497 | reg |= DWC3_GCTL_U2EXIT_LFPS; | |
498 | ||
499 | /* | |
500 | * WORKAROUND: DWC3 revisions <1.90a have a bug | |
501 | * where the device can fail to connect at SuperSpeed | |
502 | * and falls back to high-speed mode which causes | |
503 | * the device to enter a Connect/Disconnect loop | |
504 | */ | |
505 | if (dwc->revision < DWC3_REVISION_190A) | |
506 | reg |= DWC3_GCTL_U2RSTECN; | |
507 | ||
508 | dwc3_core_num_eps(dwc); | |
509 | ||
510 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
511 | ||
512 | dwc3_phy_setup(dwc); | |
513 | ||
514 | ret = dwc3_alloc_scratch_buffers(dwc); | |
515 | if (ret) | |
71744d0d | 516 | goto err0; |
85d5e707 KVA |
517 | |
518 | ret = dwc3_setup_scratch_buffers(dwc); | |
519 | if (ret) | |
71744d0d | 520 | goto err1; |
85d5e707 KVA |
521 | |
522 | return 0; | |
523 | ||
85d5e707 | 524 | err1: |
71744d0d | 525 | dwc3_free_scratch_buffers(dwc); |
85d5e707 KVA |
526 | |
527 | err0: | |
528 | return ret; | |
529 | } | |
530 | ||
531 | static void dwc3_core_exit(struct dwc3 *dwc) | |
532 | { | |
533 | dwc3_free_scratch_buffers(dwc); | |
85d5e707 KVA |
534 | } |
535 | ||
536 | static int dwc3_core_init_mode(struct dwc3 *dwc) | |
537 | { | |
85d5e707 KVA |
538 | int ret; |
539 | ||
540 | switch (dwc->dr_mode) { | |
541 | case USB_DR_MODE_PERIPHERAL: | |
542 | dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); | |
543 | ret = dwc3_gadget_init(dwc); | |
544 | if (ret) { | |
545 | dev_err(dev, "failed to initialize gadget\n"); | |
546 | return ret; | |
547 | } | |
548 | break; | |
549 | case USB_DR_MODE_HOST: | |
550 | dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST); | |
551 | ret = dwc3_host_init(dwc); | |
552 | if (ret) { | |
553 | dev_err(dev, "failed to initialize host\n"); | |
554 | return ret; | |
555 | } | |
556 | break; | |
557 | case USB_DR_MODE_OTG: | |
558 | dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG); | |
559 | ret = dwc3_host_init(dwc); | |
560 | if (ret) { | |
561 | dev_err(dev, "failed to initialize host\n"); | |
562 | return ret; | |
563 | } | |
564 | ||
565 | ret = dwc3_gadget_init(dwc); | |
566 | if (ret) { | |
567 | dev_err(dev, "failed to initialize gadget\n"); | |
568 | return ret; | |
569 | } | |
570 | break; | |
571 | default: | |
572 | dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); | |
573 | return -EINVAL; | |
574 | } | |
575 | ||
576 | return 0; | |
577 | } | |
578 | ||
579 | static void dwc3_core_exit_mode(struct dwc3 *dwc) | |
580 | { | |
581 | switch (dwc->dr_mode) { | |
582 | case USB_DR_MODE_PERIPHERAL: | |
583 | dwc3_gadget_exit(dwc); | |
584 | break; | |
585 | case USB_DR_MODE_HOST: | |
586 | dwc3_host_exit(dwc); | |
587 | break; | |
588 | case USB_DR_MODE_OTG: | |
589 | dwc3_host_exit(dwc); | |
590 | dwc3_gadget_exit(dwc); | |
591 | break; | |
592 | default: | |
593 | /* do nothing */ | |
594 | break; | |
595 | } | |
596 | } | |
597 | ||
598 | #define DWC3_ALIGN_MASK (16 - 1) | |
599 | ||
600 | static int dwc3_probe(struct platform_device *pdev) | |
601 | { | |
602 | struct device *dev = &pdev->dev; | |
603 | struct dwc3_platform_data *pdata = dev_get_platdata(dev); | |
604 | struct device_node *node = dev->of_node; | |
605 | struct resource *res; | |
606 | struct dwc3 *dwc; | |
607 | u8 lpm_nyet_threshold; | |
608 | u8 tx_de_emphasis; | |
609 | u8 hird_threshold; | |
610 | ||
611 | int ret; | |
612 | ||
613 | void __iomem *regs; | |
614 | void *mem; | |
615 | ||
616 | mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL); | |
617 | if (!mem) | |
618 | return -ENOMEM; | |
619 | ||
620 | dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1); | |
621 | dwc->mem = mem; | |
622 | dwc->dev = dev; | |
623 | ||
624 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
625 | if (!res) { | |
626 | dev_err(dev, "missing IRQ\n"); | |
627 | return -ENODEV; | |
628 | } | |
629 | dwc->xhci_resources[1].start = res->start; | |
630 | dwc->xhci_resources[1].end = res->end; | |
631 | dwc->xhci_resources[1].flags = res->flags; | |
632 | dwc->xhci_resources[1].name = res->name; | |
633 | ||
634 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
635 | if (!res) { | |
636 | dev_err(dev, "missing memory resource\n"); | |
637 | return -ENODEV; | |
638 | } | |
639 | ||
640 | dwc->xhci_resources[0].start = res->start; | |
641 | dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + | |
642 | DWC3_XHCI_REGS_END; | |
643 | dwc->xhci_resources[0].flags = res->flags; | |
644 | dwc->xhci_resources[0].name = res->name; | |
645 | ||
646 | res->start += DWC3_GLOBALS_REGS_START; | |
647 | ||
648 | /* | |
649 | * Request memory region but exclude xHCI regs, | |
650 | * since it will be requested by the xhci-plat driver. | |
651 | */ | |
652 | regs = devm_ioremap_resource(dev, res); | |
653 | if (IS_ERR(regs)) | |
654 | return PTR_ERR(regs); | |
655 | ||
656 | dwc->regs = regs; | |
657 | dwc->regs_size = resource_size(res); | |
658 | /* | |
659 | * restore res->start back to its original value so that, | |
660 | * in case the probe is deferred, we don't end up getting error in | |
661 | * request the memory region the next time probe is called. | |
662 | */ | |
663 | res->start -= DWC3_GLOBALS_REGS_START; | |
664 | ||
665 | /* default to highest possible threshold */ | |
666 | lpm_nyet_threshold = 0xff; | |
667 | ||
668 | /* default to -3.5dB de-emphasis */ | |
669 | tx_de_emphasis = 1; | |
670 | ||
671 | /* | |
672 | * default to assert utmi_sleep_n and use maximum allowed HIRD | |
673 | * threshold value of 0b1100 | |
674 | */ | |
675 | hird_threshold = 12; | |
676 | ||
677 | if (node) { | |
678 | dwc->maximum_speed = of_usb_get_maximum_speed(node); | |
679 | dwc->has_lpm_erratum = of_property_read_bool(node, | |
680 | "snps,has-lpm-erratum"); | |
681 | of_property_read_u8(node, "snps,lpm-nyet-threshold", | |
682 | &lpm_nyet_threshold); | |
683 | dwc->is_utmi_l1_suspend = of_property_read_bool(node, | |
684 | "snps,is-utmi-l1-suspend"); | |
685 | of_property_read_u8(node, "snps,hird-threshold", | |
686 | &hird_threshold); | |
687 | ||
688 | dwc->needs_fifo_resize = of_property_read_bool(node, | |
689 | "tx-fifo-resize"); | |
690 | dwc->dr_mode = of_usb_get_dr_mode(node); | |
691 | ||
692 | dwc->disable_scramble_quirk = of_property_read_bool(node, | |
693 | "snps,disable_scramble_quirk"); | |
694 | dwc->u2exit_lfps_quirk = of_property_read_bool(node, | |
695 | "snps,u2exit_lfps_quirk"); | |
696 | dwc->u2ss_inp3_quirk = of_property_read_bool(node, | |
697 | "snps,u2ss_inp3_quirk"); | |
698 | dwc->req_p1p2p3_quirk = of_property_read_bool(node, | |
699 | "snps,req_p1p2p3_quirk"); | |
700 | dwc->del_p1p2p3_quirk = of_property_read_bool(node, | |
701 | "snps,del_p1p2p3_quirk"); | |
702 | dwc->del_phy_power_chg_quirk = of_property_read_bool(node, | |
703 | "snps,del_phy_power_chg_quirk"); | |
704 | dwc->lfps_filter_quirk = of_property_read_bool(node, | |
705 | "snps,lfps_filter_quirk"); | |
706 | dwc->rx_detect_poll_quirk = of_property_read_bool(node, | |
707 | "snps,rx_detect_poll_quirk"); | |
708 | dwc->dis_u3_susphy_quirk = of_property_read_bool(node, | |
709 | "snps,dis_u3_susphy_quirk"); | |
710 | dwc->dis_u2_susphy_quirk = of_property_read_bool(node, | |
711 | "snps,dis_u2_susphy_quirk"); | |
712 | ||
713 | dwc->tx_de_emphasis_quirk = of_property_read_bool(node, | |
714 | "snps,tx_de_emphasis_quirk"); | |
715 | of_property_read_u8(node, "snps,tx_de_emphasis", | |
716 | &tx_de_emphasis); | |
717 | } else if (pdata) { | |
718 | dwc->maximum_speed = pdata->maximum_speed; | |
719 | dwc->has_lpm_erratum = pdata->has_lpm_erratum; | |
720 | if (pdata->lpm_nyet_threshold) | |
721 | lpm_nyet_threshold = pdata->lpm_nyet_threshold; | |
722 | dwc->is_utmi_l1_suspend = pdata->is_utmi_l1_suspend; | |
723 | if (pdata->hird_threshold) | |
724 | hird_threshold = pdata->hird_threshold; | |
725 | ||
726 | dwc->needs_fifo_resize = pdata->tx_fifo_resize; | |
727 | dwc->dr_mode = pdata->dr_mode; | |
728 | ||
729 | dwc->disable_scramble_quirk = pdata->disable_scramble_quirk; | |
730 | dwc->u2exit_lfps_quirk = pdata->u2exit_lfps_quirk; | |
731 | dwc->u2ss_inp3_quirk = pdata->u2ss_inp3_quirk; | |
732 | dwc->req_p1p2p3_quirk = pdata->req_p1p2p3_quirk; | |
733 | dwc->del_p1p2p3_quirk = pdata->del_p1p2p3_quirk; | |
734 | dwc->del_phy_power_chg_quirk = pdata->del_phy_power_chg_quirk; | |
735 | dwc->lfps_filter_quirk = pdata->lfps_filter_quirk; | |
736 | dwc->rx_detect_poll_quirk = pdata->rx_detect_poll_quirk; | |
737 | dwc->dis_u3_susphy_quirk = pdata->dis_u3_susphy_quirk; | |
738 | dwc->dis_u2_susphy_quirk = pdata->dis_u2_susphy_quirk; | |
739 | ||
740 | dwc->tx_de_emphasis_quirk = pdata->tx_de_emphasis_quirk; | |
741 | if (pdata->tx_de_emphasis) | |
742 | tx_de_emphasis = pdata->tx_de_emphasis; | |
743 | } | |
744 | ||
745 | /* default to superspeed if no maximum_speed passed */ | |
746 | if (dwc->maximum_speed == USB_SPEED_UNKNOWN) | |
747 | dwc->maximum_speed = USB_SPEED_SUPER; | |
748 | ||
749 | dwc->lpm_nyet_threshold = lpm_nyet_threshold; | |
750 | dwc->tx_de_emphasis = tx_de_emphasis; | |
751 | ||
752 | dwc->hird_threshold = hird_threshold | |
753 | | (dwc->is_utmi_l1_suspend << 4); | |
754 | ||
85d5e707 KVA |
755 | spin_lock_init(&dwc->lock); |
756 | platform_set_drvdata(pdev, dwc); | |
757 | ||
758 | if (!dev->dma_mask) { | |
759 | dev->dma_mask = dev->parent->dma_mask; | |
760 | dev->dma_parms = dev->parent->dma_parms; | |
761 | dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask); | |
762 | } | |
763 | ||
85d5e707 KVA |
764 | dwc3_cache_hwparams(dwc); |
765 | ||
766 | ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); | |
767 | if (ret) { | |
768 | dev_err(dwc->dev, "failed to allocate event buffers\n"); | |
71744d0d | 769 | return -ENOMEM; |
85d5e707 KVA |
770 | } |
771 | ||
772 | if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) | |
773 | dwc->dr_mode = USB_DR_MODE_HOST; | |
774 | else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) | |
775 | dwc->dr_mode = USB_DR_MODE_PERIPHERAL; | |
776 | ||
777 | if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) | |
778 | dwc->dr_mode = USB_DR_MODE_OTG; | |
779 | ||
780 | ret = dwc3_core_init(dwc); | |
781 | if (ret) { | |
782 | dev_err(dev, "failed to initialize core\n"); | |
783 | goto err0; | |
784 | } | |
785 | ||
85d5e707 KVA |
786 | ret = dwc3_event_buffers_setup(dwc); |
787 | if (ret) { | |
788 | dev_err(dwc->dev, "failed to setup event buffers\n"); | |
71744d0d | 789 | goto err1; |
85d5e707 KVA |
790 | } |
791 | ||
792 | ret = dwc3_core_init_mode(dwc); | |
793 | if (ret) | |
794 | goto err2; | |
795 | ||
85d5e707 KVA |
796 | return 0; |
797 | ||
85d5e707 KVA |
798 | err2: |
799 | dwc3_event_buffers_cleanup(dwc); | |
800 | ||
85d5e707 | 801 | err1: |
85d5e707 KVA |
802 | dwc3_core_exit(dwc); |
803 | ||
804 | err0: | |
805 | dwc3_free_event_buffers(dwc); | |
806 | ||
807 | return ret; | |
808 | } | |
809 | ||
810 | static int dwc3_remove(struct platform_device *pdev) | |
811 | { | |
812 | struct dwc3 *dwc = platform_get_drvdata(pdev); | |
813 | ||
85d5e707 KVA |
814 | dwc3_core_exit_mode(dwc); |
815 | dwc3_event_buffers_cleanup(dwc); | |
816 | dwc3_free_event_buffers(dwc); | |
817 | ||
85d5e707 KVA |
818 | dwc3_core_exit(dwc); |
819 | ||
85d5e707 KVA |
820 | return 0; |
821 | } | |
822 | ||
85d5e707 KVA |
823 | #ifdef CONFIG_OF |
824 | static const struct of_device_id of_dwc3_match[] = { | |
825 | { | |
826 | .compatible = "snps,dwc3" | |
827 | }, | |
828 | { | |
829 | .compatible = "synopsys,dwc3" | |
830 | }, | |
831 | { }, | |
832 | }; | |
833 | MODULE_DEVICE_TABLE(of, of_dwc3_match); | |
834 | #endif | |
835 | ||
836 | #ifdef CONFIG_ACPI | |
837 | ||
838 | #define ACPI_ID_INTEL_BSW "808622B7" | |
839 | ||
840 | static const struct acpi_device_id dwc3_acpi_match[] = { | |
841 | { ACPI_ID_INTEL_BSW, 0 }, | |
842 | { }, | |
843 | }; | |
844 | MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); | |
845 | #endif | |
846 | ||
847 | static struct platform_driver dwc3_driver = { | |
848 | .probe = dwc3_probe, | |
849 | .remove = dwc3_remove, | |
850 | .driver = { | |
851 | .name = "dwc3", | |
852 | .of_match_table = of_match_ptr(of_dwc3_match), | |
853 | .acpi_match_table = ACPI_PTR(dwc3_acpi_match), | |
85d5e707 KVA |
854 | }, |
855 | }; | |
856 | ||
857 | module_platform_driver(dwc3_driver); | |
858 | ||
859 | MODULE_ALIAS("platform:dwc3"); | |
860 | MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); | |
861 | MODULE_LICENSE("GPL v2"); | |
862 | MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); |