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5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0 |
bfad65ee | 2 | /* |
72246da4 FB |
3 | * core.h - DesignWare USB3 DRD Core Header |
4 | * | |
5 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
6 | * |
7 | * Authors: Felipe Balbi <balbi@ti.com>, | |
8 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
72246da4 FB |
9 | */ |
10 | ||
11 | #ifndef __DRIVERS_USB_DWC3_CORE_H | |
12 | #define __DRIVERS_USB_DWC3_CORE_H | |
13 | ||
14 | #include <linux/device.h> | |
15 | #include <linux/spinlock.h> | |
d07e8819 | 16 | #include <linux/ioport.h> |
72246da4 | 17 | #include <linux/list.h> |
ff3f0789 | 18 | #include <linux/bitops.h> |
72246da4 FB |
19 | #include <linux/dma-mapping.h> |
20 | #include <linux/mm.h> | |
21 | #include <linux/debugfs.h> | |
76a638f8 | 22 | #include <linux/wait.h> |
41ce1456 | 23 | #include <linux/workqueue.h> |
72246da4 FB |
24 | |
25 | #include <linux/usb/ch9.h> | |
26 | #include <linux/usb/gadget.h> | |
a45c82b8 | 27 | #include <linux/usb/otg.h> |
8a0a1379 | 28 | #include <linux/usb/role.h> |
88bc9d19 | 29 | #include <linux/ulpi/interface.h> |
72246da4 | 30 | |
57303488 KVA |
31 | #include <linux/phy/phy.h> |
32 | ||
2c4cbe6e FB |
33 | #define DWC3_MSG_MAX 500 |
34 | ||
72246da4 | 35 | /* Global constants */ |
bb014736 | 36 | #define DWC3_PULL_UP_TIMEOUT 500 /* ms */ |
905dc04e | 37 | #define DWC3_BOUNCE_SIZE 1024 /* size of a superspeed bulk */ |
4199c5f8 | 38 | #define DWC3_EP0_SETUP_SIZE 512 |
72246da4 | 39 | #define DWC3_ENDPOINTS_NUM 32 |
51249dca | 40 | #define DWC3_XHCI_RESOURCES_NUM 2 |
d5370106 | 41 | #define DWC3_ISOC_MAX_RETRIES 5 |
72246da4 | 42 | |
0ffcaf37 | 43 | #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */ |
e71d363d | 44 | #define DWC3_EVENT_BUFFERS_SIZE 4096 |
72246da4 FB |
45 | #define DWC3_EVENT_TYPE_MASK 0xfe |
46 | ||
47 | #define DWC3_EVENT_TYPE_DEV 0 | |
48 | #define DWC3_EVENT_TYPE_CARKIT 3 | |
49 | #define DWC3_EVENT_TYPE_I2C 4 | |
50 | ||
51 | #define DWC3_DEVICE_EVENT_DISCONNECT 0 | |
52 | #define DWC3_DEVICE_EVENT_RESET 1 | |
53 | #define DWC3_DEVICE_EVENT_CONNECT_DONE 2 | |
54 | #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 | |
55 | #define DWC3_DEVICE_EVENT_WAKEUP 4 | |
2c61a8ef | 56 | #define DWC3_DEVICE_EVENT_HIBER_REQ 5 |
72246da4 FB |
57 | #define DWC3_DEVICE_EVENT_EOPF 6 |
58 | #define DWC3_DEVICE_EVENT_SOF 7 | |
59 | #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 | |
60 | #define DWC3_DEVICE_EVENT_CMD_CMPL 10 | |
61 | #define DWC3_DEVICE_EVENT_OVERFLOW 11 | |
62 | ||
f09cc79b RQ |
63 | /* Controller's role while using the OTG block */ |
64 | #define DWC3_OTG_ROLE_IDLE 0 | |
65 | #define DWC3_OTG_ROLE_HOST 1 | |
66 | #define DWC3_OTG_ROLE_DEVICE 2 | |
67 | ||
72246da4 | 68 | #define DWC3_GEVNTCOUNT_MASK 0xfffc |
ff3f0789 | 69 | #define DWC3_GEVNTCOUNT_EHB BIT(31) |
72246da4 FB |
70 | #define DWC3_GSNPSID_MASK 0xffff0000 |
71 | #define DWC3_GSNPSREV_MASK 0xffff | |
72 | ||
51249dca IS |
73 | /* DWC3 registers memory space boundries */ |
74 | #define DWC3_XHCI_REGS_START 0x0 | |
75 | #define DWC3_XHCI_REGS_END 0x7fff | |
76 | #define DWC3_GLOBALS_REGS_START 0xc100 | |
77 | #define DWC3_GLOBALS_REGS_END 0xc6ff | |
78 | #define DWC3_DEVICE_REGS_START 0xc700 | |
79 | #define DWC3_DEVICE_REGS_END 0xcbff | |
80 | #define DWC3_OTG_REGS_START 0xcc00 | |
81 | #define DWC3_OTG_REGS_END 0xccff | |
82 | ||
72246da4 FB |
83 | /* Global Registers */ |
84 | #define DWC3_GSBUSCFG0 0xc100 | |
85 | #define DWC3_GSBUSCFG1 0xc104 | |
86 | #define DWC3_GTXTHRCFG 0xc108 | |
87 | #define DWC3_GRXTHRCFG 0xc10c | |
88 | #define DWC3_GCTL 0xc110 | |
89 | #define DWC3_GEVTEN 0xc114 | |
90 | #define DWC3_GSTS 0xc118 | |
475c8beb | 91 | #define DWC3_GUCTL1 0xc11c |
72246da4 FB |
92 | #define DWC3_GSNPSID 0xc120 |
93 | #define DWC3_GGPIO 0xc124 | |
94 | #define DWC3_GUID 0xc128 | |
95 | #define DWC3_GUCTL 0xc12c | |
96 | #define DWC3_GBUSERRADDR0 0xc130 | |
97 | #define DWC3_GBUSERRADDR1 0xc134 | |
98 | #define DWC3_GPRTBIMAP0 0xc138 | |
99 | #define DWC3_GPRTBIMAP1 0xc13c | |
100 | #define DWC3_GHWPARAMS0 0xc140 | |
101 | #define DWC3_GHWPARAMS1 0xc144 | |
102 | #define DWC3_GHWPARAMS2 0xc148 | |
103 | #define DWC3_GHWPARAMS3 0xc14c | |
104 | #define DWC3_GHWPARAMS4 0xc150 | |
105 | #define DWC3_GHWPARAMS5 0xc154 | |
106 | #define DWC3_GHWPARAMS6 0xc158 | |
107 | #define DWC3_GHWPARAMS7 0xc15c | |
108 | #define DWC3_GDBGFIFOSPACE 0xc160 | |
109 | #define DWC3_GDBGLTSSM 0xc164 | |
80b77634 TN |
110 | #define DWC3_GDBGBMU 0xc16c |
111 | #define DWC3_GDBGLSPMUX 0xc170 | |
112 | #define DWC3_GDBGLSP 0xc174 | |
113 | #define DWC3_GDBGEPINFO0 0xc178 | |
114 | #define DWC3_GDBGEPINFO1 0xc17c | |
72246da4 FB |
115 | #define DWC3_GPRTBIMAP_HS0 0xc180 |
116 | #define DWC3_GPRTBIMAP_HS1 0xc184 | |
117 | #define DWC3_GPRTBIMAP_FS0 0xc188 | |
118 | #define DWC3_GPRTBIMAP_FS1 0xc18c | |
06281d46 | 119 | #define DWC3_GUCTL2 0xc19c |
72246da4 | 120 | |
690fb371 JY |
121 | #define DWC3_VER_NUMBER 0xc1a0 |
122 | #define DWC3_VER_TYPE 0xc1a4 | |
123 | ||
8261bd4e RQ |
124 | #define DWC3_GUSB2PHYCFG(n) (0xc200 + ((n) * 0x04)) |
125 | #define DWC3_GUSB2I2CCTL(n) (0xc240 + ((n) * 0x04)) | |
72246da4 | 126 | |
8261bd4e | 127 | #define DWC3_GUSB2PHYACC(n) (0xc280 + ((n) * 0x04)) |
72246da4 | 128 | |
8261bd4e | 129 | #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + ((n) * 0x04)) |
72246da4 | 130 | |
8261bd4e RQ |
131 | #define DWC3_GTXFIFOSIZ(n) (0xc300 + ((n) * 0x04)) |
132 | #define DWC3_GRXFIFOSIZ(n) (0xc380 + ((n) * 0x04)) | |
72246da4 | 133 | |
8261bd4e RQ |
134 | #define DWC3_GEVNTADRLO(n) (0xc400 + ((n) * 0x10)) |
135 | #define DWC3_GEVNTADRHI(n) (0xc404 + ((n) * 0x10)) | |
136 | #define DWC3_GEVNTSIZ(n) (0xc408 + ((n) * 0x10)) | |
137 | #define DWC3_GEVNTCOUNT(n) (0xc40c + ((n) * 0x10)) | |
72246da4 FB |
138 | |
139 | #define DWC3_GHWPARAMS8 0xc600 | |
db2be4e9 | 140 | #define DWC3_GFLADJ 0xc630 |
72246da4 FB |
141 | |
142 | /* Device Registers */ | |
143 | #define DWC3_DCFG 0xc700 | |
144 | #define DWC3_DCTL 0xc704 | |
145 | #define DWC3_DEVTEN 0xc708 | |
146 | #define DWC3_DSTS 0xc70c | |
147 | #define DWC3_DGCMDPAR 0xc710 | |
148 | #define DWC3_DGCMD 0xc714 | |
149 | #define DWC3_DALEPENA 0xc720 | |
2eb88016 | 150 | |
8261bd4e | 151 | #define DWC3_DEP_BASE(n) (0xc800 + ((n) * 0x10)) |
2eb88016 FB |
152 | #define DWC3_DEPCMDPAR2 0x00 |
153 | #define DWC3_DEPCMDPAR1 0x04 | |
154 | #define DWC3_DEPCMDPAR0 0x08 | |
155 | #define DWC3_DEPCMD 0x0c | |
72246da4 | 156 | |
8261bd4e | 157 | #define DWC3_DEV_IMOD(n) (0xca00 + ((n) * 0x4)) |
cf40b86b | 158 | |
72246da4 FB |
159 | /* OTG Registers */ |
160 | #define DWC3_OCFG 0xcc00 | |
161 | #define DWC3_OCTL 0xcc04 | |
d4436c3a GC |
162 | #define DWC3_OEVT 0xcc08 |
163 | #define DWC3_OEVTEN 0xcc0C | |
164 | #define DWC3_OSTS 0xcc10 | |
72246da4 FB |
165 | |
166 | /* Bit fields */ | |
167 | ||
d635db55 PM |
168 | /* Global SoC Bus Configuration INCRx Register 0 */ |
169 | #define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7) /* INCR256 burst */ | |
170 | #define DWC3_GSBUSCFG0_INCR128BRSTENA (1 << 6) /* INCR128 burst */ | |
171 | #define DWC3_GSBUSCFG0_INCR64BRSTENA (1 << 5) /* INCR64 burst */ | |
172 | #define DWC3_GSBUSCFG0_INCR32BRSTENA (1 << 4) /* INCR32 burst */ | |
173 | #define DWC3_GSBUSCFG0_INCR16BRSTENA (1 << 3) /* INCR16 burst */ | |
174 | #define DWC3_GSBUSCFG0_INCR8BRSTENA (1 << 2) /* INCR8 burst */ | |
175 | #define DWC3_GSBUSCFG0_INCR4BRSTENA (1 << 1) /* INCR4 burst */ | |
176 | #define DWC3_GSBUSCFG0_INCRBRSTENA (1 << 0) /* undefined length enable */ | |
177 | #define DWC3_GSBUSCFG0_INCRBRST_MASK 0xff | |
178 | ||
62ba09d6 TN |
179 | /* Global Debug LSP MUX Select */ |
180 | #define DWC3_GDBGLSPMUX_ENDBC BIT(15) /* Host only */ | |
181 | #define DWC3_GDBGLSPMUX_HOSTSELECT(n) ((n) & 0x3fff) | |
182 | #define DWC3_GDBGLSPMUX_DEVSELECT(n) (((n) & 0xf) << 4) | |
183 | #define DWC3_GDBGLSPMUX_EPSELECT(n) ((n) & 0xf) | |
184 | ||
cf6d867d FB |
185 | /* Global Debug Queue/FIFO Space Available Register */ |
186 | #define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f) | |
187 | #define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0) | |
188 | #define DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(n) (((n) >> 16) & 0xffff) | |
189 | ||
2c85a181 TN |
190 | #define DWC3_TXFIFO 0 |
191 | #define DWC3_RXFIFO 1 | |
b16ea8b9 TN |
192 | #define DWC3_TXREQQ 2 |
193 | #define DWC3_RXREQQ 3 | |
194 | #define DWC3_RXINFOQ 4 | |
195 | #define DWC3_PSTATQ 5 | |
196 | #define DWC3_DESCFETCHQ 6 | |
197 | #define DWC3_EVENTQ 7 | |
198 | #define DWC3_AUXEVENTQ 8 | |
cf6d867d | 199 | |
2a58f9c1 FB |
200 | /* Global RX Threshold Configuration Register */ |
201 | #define DWC3_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 19) | |
202 | #define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24) | |
ff3f0789 | 203 | #define DWC3_GRXTHRCFG_PKTCNTSEL BIT(29) |
2a58f9c1 | 204 | |
2fbc5bdc TN |
205 | /* Global RX Threshold Configuration Register for DWC_usb31 only */ |
206 | #define DWC31_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 16) | |
207 | #define DWC31_GRXTHRCFG_RXPKTCNT(n) (((n) & 0x1f) << 21) | |
208 | #define DWC31_GRXTHRCFG_PKTCNTSEL BIT(26) | |
209 | #define DWC31_RXTHRNUMPKTSEL_HS_PRD BIT(15) | |
210 | #define DWC31_RXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13) | |
211 | #define DWC31_RXTHRNUMPKTSEL_PRD BIT(10) | |
212 | #define DWC31_RXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5) | |
213 | #define DWC31_MAXRXBURSTSIZE_PRD(n) ((n) & 0x1f) | |
214 | ||
6743e817 TN |
215 | /* Global TX Threshold Configuration Register for DWC_usb31 only */ |
216 | #define DWC31_GTXTHRCFG_MAXTXBURSTSIZE(n) (((n) & 0x1f) << 16) | |
217 | #define DWC31_GTXTHRCFG_TXPKTCNT(n) (((n) & 0x1f) << 21) | |
218 | #define DWC31_GTXTHRCFG_PKTCNTSEL BIT(26) | |
219 | #define DWC31_TXTHRNUMPKTSEL_HS_PRD BIT(15) | |
220 | #define DWC31_TXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13) | |
221 | #define DWC31_TXTHRNUMPKTSEL_PRD BIT(10) | |
222 | #define DWC31_TXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5) | |
223 | #define DWC31_MAXTXBURSTSIZE_PRD(n) ((n) & 0x1f) | |
224 | ||
72246da4 | 225 | /* Global Configuration Register */ |
1d046793 | 226 | #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) |
ff3f0789 | 227 | #define DWC3_GCTL_U2RSTECN BIT(16) |
1d046793 | 228 | #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6) |
72246da4 FB |
229 | #define DWC3_GCTL_CLK_BUS (0) |
230 | #define DWC3_GCTL_CLK_PIPE (1) | |
231 | #define DWC3_GCTL_CLK_PIPEHALF (2) | |
232 | #define DWC3_GCTL_CLK_MASK (3) | |
233 | ||
0b9fe32d | 234 | #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) |
1d046793 | 235 | #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) |
72246da4 FB |
236 | #define DWC3_GCTL_PRTCAP_HOST 1 |
237 | #define DWC3_GCTL_PRTCAP_DEVICE 2 | |
238 | #define DWC3_GCTL_PRTCAP_OTG 3 | |
239 | ||
ff3f0789 RQ |
240 | #define DWC3_GCTL_CORESOFTRESET BIT(11) |
241 | #define DWC3_GCTL_SOFITPSYNC BIT(10) | |
2c61a8ef PZ |
242 | #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) |
243 | #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) | |
ff3f0789 RQ |
244 | #define DWC3_GCTL_DISSCRAMBLE BIT(3) |
245 | #define DWC3_GCTL_U2EXIT_LFPS BIT(2) | |
246 | #define DWC3_GCTL_GBLHIBERNATIONEN BIT(1) | |
247 | #define DWC3_GCTL_DSBLCLKGTNG BIT(0) | |
72246da4 | 248 | |
b138e23d AKV |
249 | /* Global User Control Register */ |
250 | #define DWC3_GUCTL_HSTINAUTORETRY BIT(14) | |
251 | ||
0bb39ca1 | 252 | /* Global User Control 1 Register */ |
7ba6b09f | 253 | #define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17) |
65db7a0c | 254 | #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28) |
ff3f0789 | 255 | #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24) |
0bb39ca1 | 256 | |
4cff75c7 RQ |
257 | /* Global Status Register */ |
258 | #define DWC3_GSTS_OTG_IP BIT(10) | |
259 | #define DWC3_GSTS_BC_IP BIT(9) | |
260 | #define DWC3_GSTS_ADP_IP BIT(8) | |
261 | #define DWC3_GSTS_HOST_IP BIT(7) | |
262 | #define DWC3_GSTS_DEVICE_IP BIT(6) | |
263 | #define DWC3_GSTS_CSR_TIMEOUT BIT(5) | |
264 | #define DWC3_GSTS_BUS_ERR_ADDR_VLD BIT(4) | |
62ba09d6 TN |
265 | #define DWC3_GSTS_CURMOD(n) ((n) & 0x3) |
266 | #define DWC3_GSTS_CURMOD_DEVICE 0 | |
267 | #define DWC3_GSTS_CURMOD_HOST 1 | |
4cff75c7 | 268 | |
72246da4 | 269 | /* Global USB2 PHY Configuration Register */ |
ff3f0789 RQ |
270 | #define DWC3_GUSB2PHYCFG_PHYSOFTRST BIT(31) |
271 | #define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS BIT(30) | |
272 | #define DWC3_GUSB2PHYCFG_SUSPHY BIT(6) | |
273 | #define DWC3_GUSB2PHYCFG_ULPI_UTMI BIT(4) | |
274 | #define DWC3_GUSB2PHYCFG_ENBLSLPM BIT(8) | |
32f2ed86 WW |
275 | #define DWC3_GUSB2PHYCFG_PHYIF(n) (n << 3) |
276 | #define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1) | |
277 | #define DWC3_GUSB2PHYCFG_USBTRDTIM(n) (n << 10) | |
278 | #define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf) | |
279 | #define USBTRDTIM_UTMI_8_BIT 9 | |
280 | #define USBTRDTIM_UTMI_16_BIT 5 | |
281 | #define UTMI_PHYIF_16_BIT 1 | |
282 | #define UTMI_PHYIF_8_BIT 0 | |
72246da4 | 283 | |
b5699eee | 284 | /* Global USB2 PHY Vendor Control Register */ |
ff3f0789 RQ |
285 | #define DWC3_GUSB2PHYACC_NEWREGREQ BIT(25) |
286 | #define DWC3_GUSB2PHYACC_BUSY BIT(23) | |
287 | #define DWC3_GUSB2PHYACC_WRITE BIT(22) | |
b5699eee HK |
288 | #define DWC3_GUSB2PHYACC_ADDR(n) (n << 16) |
289 | #define DWC3_GUSB2PHYACC_EXTEND_ADDR(n) (n << 8) | |
290 | #define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff) | |
291 | ||
72246da4 | 292 | /* Global USB3 PIPE Control Register */ |
ff3f0789 RQ |
293 | #define DWC3_GUSB3PIPECTL_PHYSOFTRST BIT(31) |
294 | #define DWC3_GUSB3PIPECTL_U2SSINP3OK BIT(29) | |
295 | #define DWC3_GUSB3PIPECTL_DISRXDETINP3 BIT(28) | |
296 | #define DWC3_GUSB3PIPECTL_UX_EXIT_PX BIT(27) | |
297 | #define DWC3_GUSB3PIPECTL_REQP1P2P3 BIT(24) | |
a2a1d0f5 HR |
298 | #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19) |
299 | #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7) | |
300 | #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1) | |
ff3f0789 RQ |
301 | #define DWC3_GUSB3PIPECTL_DEPOCHANGE BIT(18) |
302 | #define DWC3_GUSB3PIPECTL_SUSPHY BIT(17) | |
303 | #define DWC3_GUSB3PIPECTL_LFPSFILT BIT(9) | |
304 | #define DWC3_GUSB3PIPECTL_RX_DETOPOLL BIT(8) | |
6b6a0c9a HR |
305 | #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3) |
306 | #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1) | |
72246da4 | 307 | |
457e84b6 | 308 | /* Global TX Fifo Size Register */ |
0cab8d26 | 309 | #define DWC31_GTXFIFOSIZ_TXFRAMNUM BIT(15) /* DWC_usb31 only */ |
586f4335 TN |
310 | #define DWC31_GTXFIFOSIZ_TXFDEP(n) ((n) & 0x7fff) /* DWC_usb31 only */ |
311 | #define DWC3_GTXFIFOSIZ_TXFDEP(n) ((n) & 0xffff) | |
2c61a8ef | 312 | #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) |
457e84b6 | 313 | |
d94ea531 TN |
314 | /* Global RX Fifo Size Register */ |
315 | #define DWC31_GRXFIFOSIZ_RXFDEP(n) ((n) & 0x7fff) /* DWC_usb31 only */ | |
316 | #define DWC3_GRXFIFOSIZ_RXFDEP(n) ((n) & 0xffff) | |
317 | ||
68d6a01b | 318 | /* Global Event Size Registers */ |
ff3f0789 | 319 | #define DWC3_GEVNTSIZ_INTMASK BIT(31) |
68d6a01b FB |
320 | #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff) |
321 | ||
4e99472b | 322 | /* Global HWPARAMS0 Register */ |
9d6173e1 TN |
323 | #define DWC3_GHWPARAMS0_MODE(n) ((n) & 0x3) |
324 | #define DWC3_GHWPARAMS0_MODE_GADGET 0 | |
325 | #define DWC3_GHWPARAMS0_MODE_HOST 1 | |
326 | #define DWC3_GHWPARAMS0_MODE_DRD 2 | |
4e99472b FB |
327 | #define DWC3_GHWPARAMS0_MBUS_TYPE(n) (((n) >> 3) & 0x7) |
328 | #define DWC3_GHWPARAMS0_SBUS_TYPE(n) (((n) >> 6) & 0x3) | |
329 | #define DWC3_GHWPARAMS0_MDWIDTH(n) (((n) >> 8) & 0xff) | |
330 | #define DWC3_GHWPARAMS0_SDWIDTH(n) (((n) >> 16) & 0xff) | |
331 | #define DWC3_GHWPARAMS0_AWIDTH(n) (((n) >> 24) & 0xff) | |
332 | ||
aabb7075 | 333 | /* Global HWPARAMS1 Register */ |
1d046793 | 334 | #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) |
aabb7075 FB |
335 | #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 |
336 | #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 | |
2c61a8ef PZ |
337 | #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2 |
338 | #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24) | |
339 | #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3) | |
62ba09d6 | 340 | #define DWC3_GHWPARAMS1_ENDBC BIT(31) |
2c61a8ef | 341 | |
0e1e5c47 PZ |
342 | /* Global HWPARAMS3 Register */ |
343 | #define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3) | |
344 | #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0 | |
1f38f88a JY |
345 | #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN1 1 |
346 | #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN2 2 /* DWC_usb31 only */ | |
0e1e5c47 PZ |
347 | #define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2) |
348 | #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0 | |
349 | #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1 | |
350 | #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2 | |
351 | #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3 | |
352 | #define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4) | |
353 | #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0 | |
354 | #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1 | |
355 | ||
2c61a8ef PZ |
356 | /* Global HWPARAMS4 Register */ |
357 | #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13) | |
358 | #define DWC3_MAX_HIBER_SCRATCHBUFS 15 | |
aabb7075 | 359 | |
946bd579 | 360 | /* Global HWPARAMS6 Register */ |
4cff75c7 RQ |
361 | #define DWC3_GHWPARAMS6_BCSUPPORT BIT(14) |
362 | #define DWC3_GHWPARAMS6_OTG3SUPPORT BIT(13) | |
363 | #define DWC3_GHWPARAMS6_ADPSUPPORT BIT(12) | |
364 | #define DWC3_GHWPARAMS6_HNPSUPPORT BIT(11) | |
365 | #define DWC3_GHWPARAMS6_SRPSUPPORT BIT(10) | |
ff3f0789 | 366 | #define DWC3_GHWPARAMS6_EN_FPGA BIT(7) |
946bd579 | 367 | |
4e99472b FB |
368 | /* Global HWPARAMS7 Register */ |
369 | #define DWC3_GHWPARAMS7_RAM1_DEPTH(n) ((n) & 0xffff) | |
370 | #define DWC3_GHWPARAMS7_RAM2_DEPTH(n) (((n) >> 16) & 0xffff) | |
371 | ||
db2be4e9 | 372 | /* Global Frame Length Adjustment Register */ |
ff3f0789 | 373 | #define DWC3_GFLADJ_30MHZ_SDBND_SEL BIT(7) |
db2be4e9 NB |
374 | #define DWC3_GFLADJ_30MHZ_MASK 0x3f |
375 | ||
06281d46 | 376 | /* Global User Control Register 2 */ |
ff3f0789 | 377 | #define DWC3_GUCTL2_RST_ACTBITLATER BIT(14) |
06281d46 | 378 | |
72246da4 FB |
379 | /* Device Configuration Register */ |
380 | #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) | |
381 | #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) | |
382 | ||
383 | #define DWC3_DCFG_SPEED_MASK (7 << 0) | |
1f38f88a | 384 | #define DWC3_DCFG_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */ |
72246da4 FB |
385 | #define DWC3_DCFG_SUPERSPEED (4 << 0) |
386 | #define DWC3_DCFG_HIGHSPEED (0 << 0) | |
ff3f0789 | 387 | #define DWC3_DCFG_FULLSPEED BIT(0) |
72246da4 | 388 | #define DWC3_DCFG_LOWSPEED (2 << 0) |
72246da4 | 389 | |
676e3497 | 390 | #define DWC3_DCFG_NUMP_SHIFT 17 |
97398612 | 391 | #define DWC3_DCFG_NUMP(n) (((n) >> DWC3_DCFG_NUMP_SHIFT) & 0x1f) |
676e3497 | 392 | #define DWC3_DCFG_NUMP_MASK (0x1f << DWC3_DCFG_NUMP_SHIFT) |
ff3f0789 | 393 | #define DWC3_DCFG_LPM_CAP BIT(22) |
2c61a8ef | 394 | |
72246da4 | 395 | /* Device Control Register */ |
ff3f0789 RQ |
396 | #define DWC3_DCTL_RUN_STOP BIT(31) |
397 | #define DWC3_DCTL_CSFTRST BIT(30) | |
398 | #define DWC3_DCTL_LSFTRST BIT(29) | |
72246da4 FB |
399 | |
400 | #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24) | |
7e39b817 | 401 | #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24) |
72246da4 | 402 | |
ff3f0789 | 403 | #define DWC3_DCTL_APPL1RES BIT(23) |
72246da4 | 404 | |
2c61a8ef PZ |
405 | /* These apply for core versions 1.87a and earlier */ |
406 | #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17) | |
407 | #define DWC3_DCTL_TRGTULST(n) ((n) << 17) | |
408 | #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2)) | |
409 | #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3)) | |
410 | #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4)) | |
411 | #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5)) | |
412 | #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6)) | |
413 | ||
414 | /* These apply for core versions 1.94a and later */ | |
2e487d28 | 415 | #define DWC3_DCTL_NYET_THRES(n) (((n) & 0xf) << 20) |
8db7ed15 | 416 | |
ff3f0789 RQ |
417 | #define DWC3_DCTL_KEEP_CONNECT BIT(19) |
418 | #define DWC3_DCTL_L1_HIBER_EN BIT(18) | |
419 | #define DWC3_DCTL_CRS BIT(17) | |
420 | #define DWC3_DCTL_CSS BIT(16) | |
80caf7d2 | 421 | |
ff3f0789 RQ |
422 | #define DWC3_DCTL_INITU2ENA BIT(12) |
423 | #define DWC3_DCTL_ACCEPTU2ENA BIT(11) | |
424 | #define DWC3_DCTL_INITU1ENA BIT(10) | |
425 | #define DWC3_DCTL_ACCEPTU1ENA BIT(9) | |
80caf7d2 | 426 | #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) |
72246da4 FB |
427 | |
428 | #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) | |
429 | #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) | |
430 | ||
431 | #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0)) | |
432 | #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4)) | |
433 | #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5)) | |
434 | #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6)) | |
435 | #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8)) | |
436 | #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10)) | |
437 | #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11)) | |
438 | ||
439 | /* Device Event Enable Register */ | |
ff3f0789 RQ |
440 | #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN BIT(12) |
441 | #define DWC3_DEVTEN_EVNTOVERFLOWEN BIT(11) | |
442 | #define DWC3_DEVTEN_CMDCMPLTEN BIT(10) | |
443 | #define DWC3_DEVTEN_ERRTICERREN BIT(9) | |
444 | #define DWC3_DEVTEN_SOFEN BIT(7) | |
445 | #define DWC3_DEVTEN_EOPFEN BIT(6) | |
446 | #define DWC3_DEVTEN_HIBERNATIONREQEVTEN BIT(5) | |
447 | #define DWC3_DEVTEN_WKUPEVTEN BIT(4) | |
448 | #define DWC3_DEVTEN_ULSTCNGEN BIT(3) | |
449 | #define DWC3_DEVTEN_CONNECTDONEEN BIT(2) | |
450 | #define DWC3_DEVTEN_USBRSTEN BIT(1) | |
451 | #define DWC3_DEVTEN_DISCONNEVTEN BIT(0) | |
72246da4 FB |
452 | |
453 | /* Device Status Register */ | |
ff3f0789 | 454 | #define DWC3_DSTS_DCNRD BIT(29) |
2c61a8ef PZ |
455 | |
456 | /* This applies for core versions 1.87a and earlier */ | |
ff3f0789 | 457 | #define DWC3_DSTS_PWRUPREQ BIT(24) |
2c61a8ef PZ |
458 | |
459 | /* These apply for core versions 1.94a and later */ | |
ff3f0789 RQ |
460 | #define DWC3_DSTS_RSS BIT(25) |
461 | #define DWC3_DSTS_SSS BIT(24) | |
2c61a8ef | 462 | |
ff3f0789 RQ |
463 | #define DWC3_DSTS_COREIDLE BIT(23) |
464 | #define DWC3_DSTS_DEVCTRLHLT BIT(22) | |
72246da4 FB |
465 | |
466 | #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18) | |
467 | #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) | |
468 | ||
ff3f0789 | 469 | #define DWC3_DSTS_RXFIFOEMPTY BIT(17) |
72246da4 | 470 | |
d05b8182 | 471 | #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3) |
72246da4 FB |
472 | #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) |
473 | ||
474 | #define DWC3_DSTS_CONNECTSPD (7 << 0) | |
475 | ||
1f38f88a | 476 | #define DWC3_DSTS_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */ |
72246da4 FB |
477 | #define DWC3_DSTS_SUPERSPEED (4 << 0) |
478 | #define DWC3_DSTS_HIGHSPEED (0 << 0) | |
ff3f0789 | 479 | #define DWC3_DSTS_FULLSPEED BIT(0) |
72246da4 | 480 | #define DWC3_DSTS_LOWSPEED (2 << 0) |
72246da4 FB |
481 | |
482 | /* Device Generic Command Register */ | |
483 | #define DWC3_DGCMD_SET_LMP 0x01 | |
484 | #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02 | |
485 | #define DWC3_DGCMD_XMIT_FUNCTION 0x03 | |
2c61a8ef PZ |
486 | |
487 | /* These apply for core versions 1.94a and later */ | |
488 | #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04 | |
489 | #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05 | |
490 | ||
72246da4 FB |
491 | #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09 |
492 | #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a | |
493 | #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c | |
494 | #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 | |
495 | ||
459e210c | 496 | #define DWC3_DGCMD_STATUS(n) (((n) >> 12) & 0x0F) |
ff3f0789 RQ |
497 | #define DWC3_DGCMD_CMDACT BIT(10) |
498 | #define DWC3_DGCMD_CMDIOC BIT(8) | |
2c61a8ef PZ |
499 | |
500 | /* Device Generic Command Parameter Register */ | |
ff3f0789 | 501 | #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT BIT(0) |
2c61a8ef PZ |
502 | #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0) |
503 | #define DWC3_DGCMDPAR_RX_FIFO (0 << 5) | |
ff3f0789 | 504 | #define DWC3_DGCMDPAR_TX_FIFO BIT(5) |
2c61a8ef | 505 | #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0) |
ff3f0789 | 506 | #define DWC3_DGCMDPAR_LOOPBACK_ENA BIT(0) |
b09bb642 | 507 | |
72246da4 FB |
508 | /* Device Endpoint Command Register */ |
509 | #define DWC3_DEPCMD_PARAM_SHIFT 16 | |
1d046793 | 510 | #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT) |
835fadb4 | 511 | #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) |
459e210c | 512 | #define DWC3_DEPCMD_STATUS(x) (((x) >> 12) & 0x0F) |
ff3f0789 RQ |
513 | #define DWC3_DEPCMD_HIPRI_FORCERM BIT(11) |
514 | #define DWC3_DEPCMD_CLEARPENDIN BIT(11) | |
515 | #define DWC3_DEPCMD_CMDACT BIT(10) | |
516 | #define DWC3_DEPCMD_CMDIOC BIT(8) | |
72246da4 FB |
517 | |
518 | #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0) | |
519 | #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0) | |
520 | #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0) | |
521 | #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0) | |
522 | #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0) | |
523 | #define DWC3_DEPCMD_SETSTALL (0x04 << 0) | |
2c61a8ef | 524 | /* This applies for core versions 1.90a and earlier */ |
72246da4 | 525 | #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0) |
2c61a8ef PZ |
526 | /* This applies for core versions 1.94a and later */ |
527 | #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0) | |
72246da4 FB |
528 | #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) |
529 | #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) | |
530 | ||
5999914f FB |
531 | #define DWC3_DEPCMD_CMD(x) ((x) & 0xf) |
532 | ||
72246da4 | 533 | /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ |
ff3f0789 | 534 | #define DWC3_DALEPENA_EP(n) BIT(n) |
72246da4 FB |
535 | |
536 | #define DWC3_DEPCMD_TYPE_CONTROL 0 | |
537 | #define DWC3_DEPCMD_TYPE_ISOC 1 | |
538 | #define DWC3_DEPCMD_TYPE_BULK 2 | |
539 | #define DWC3_DEPCMD_TYPE_INTR 3 | |
540 | ||
cf40b86b JY |
541 | #define DWC3_DEV_IMOD_COUNT_SHIFT 16 |
542 | #define DWC3_DEV_IMOD_COUNT_MASK (0xffff << 16) | |
543 | #define DWC3_DEV_IMOD_INTERVAL_SHIFT 0 | |
544 | #define DWC3_DEV_IMOD_INTERVAL_MASK (0xffff << 0) | |
545 | ||
4cff75c7 RQ |
546 | /* OTG Configuration Register */ |
547 | #define DWC3_OCFG_DISPWRCUTTOFF BIT(5) | |
548 | #define DWC3_OCFG_HIBDISMASK BIT(4) | |
549 | #define DWC3_OCFG_SFTRSTMASK BIT(3) | |
550 | #define DWC3_OCFG_OTGVERSION BIT(2) | |
551 | #define DWC3_OCFG_HNPCAP BIT(1) | |
552 | #define DWC3_OCFG_SRPCAP BIT(0) | |
553 | ||
554 | /* OTG CTL Register */ | |
555 | #define DWC3_OCTL_OTG3GOERR BIT(7) | |
556 | #define DWC3_OCTL_PERIMODE BIT(6) | |
557 | #define DWC3_OCTL_PRTPWRCTL BIT(5) | |
558 | #define DWC3_OCTL_HNPREQ BIT(4) | |
559 | #define DWC3_OCTL_SESREQ BIT(3) | |
560 | #define DWC3_OCTL_TERMSELIDPULSE BIT(2) | |
561 | #define DWC3_OCTL_DEVSETHNPEN BIT(1) | |
562 | #define DWC3_OCTL_HSTSETHNPEN BIT(0) | |
563 | ||
564 | /* OTG Event Register */ | |
565 | #define DWC3_OEVT_DEVICEMODE BIT(31) | |
566 | #define DWC3_OEVT_XHCIRUNSTPSET BIT(27) | |
567 | #define DWC3_OEVT_DEVRUNSTPSET BIT(26) | |
568 | #define DWC3_OEVT_HIBENTRY BIT(25) | |
569 | #define DWC3_OEVT_CONIDSTSCHNG BIT(24) | |
570 | #define DWC3_OEVT_HRRCONFNOTIF BIT(23) | |
571 | #define DWC3_OEVT_HRRINITNOTIF BIT(22) | |
572 | #define DWC3_OEVT_ADEVIDLE BIT(21) | |
573 | #define DWC3_OEVT_ADEVBHOSTEND BIT(20) | |
574 | #define DWC3_OEVT_ADEVHOST BIT(19) | |
575 | #define DWC3_OEVT_ADEVHNPCHNG BIT(18) | |
576 | #define DWC3_OEVT_ADEVSRPDET BIT(17) | |
577 | #define DWC3_OEVT_ADEVSESSENDDET BIT(16) | |
578 | #define DWC3_OEVT_BDEVBHOSTEND BIT(11) | |
579 | #define DWC3_OEVT_BDEVHNPCHNG BIT(10) | |
580 | #define DWC3_OEVT_BDEVSESSVLDDET BIT(9) | |
581 | #define DWC3_OEVT_BDEVVBUSCHNG BIT(8) | |
582 | #define DWC3_OEVT_BSESSVLD BIT(3) | |
583 | #define DWC3_OEVT_HSTNEGSTS BIT(2) | |
584 | #define DWC3_OEVT_SESREQSTS BIT(1) | |
585 | #define DWC3_OEVT_ERROR BIT(0) | |
586 | ||
587 | /* OTG Event Enable Register */ | |
588 | #define DWC3_OEVTEN_XHCIRUNSTPSETEN BIT(27) | |
589 | #define DWC3_OEVTEN_DEVRUNSTPSETEN BIT(26) | |
590 | #define DWC3_OEVTEN_HIBENTRYEN BIT(25) | |
591 | #define DWC3_OEVTEN_CONIDSTSCHNGEN BIT(24) | |
592 | #define DWC3_OEVTEN_HRRCONFNOTIFEN BIT(23) | |
593 | #define DWC3_OEVTEN_HRRINITNOTIFEN BIT(22) | |
594 | #define DWC3_OEVTEN_ADEVIDLEEN BIT(21) | |
595 | #define DWC3_OEVTEN_ADEVBHOSTENDEN BIT(20) | |
596 | #define DWC3_OEVTEN_ADEVHOSTEN BIT(19) | |
597 | #define DWC3_OEVTEN_ADEVHNPCHNGEN BIT(18) | |
598 | #define DWC3_OEVTEN_ADEVSRPDETEN BIT(17) | |
599 | #define DWC3_OEVTEN_ADEVSESSENDDETEN BIT(16) | |
600 | #define DWC3_OEVTEN_BDEVBHOSTENDEN BIT(11) | |
601 | #define DWC3_OEVTEN_BDEVHNPCHNGEN BIT(10) | |
602 | #define DWC3_OEVTEN_BDEVSESSVLDDETEN BIT(9) | |
603 | #define DWC3_OEVTEN_BDEVVBUSCHNGEN BIT(8) | |
604 | ||
605 | /* OTG Status Register */ | |
606 | #define DWC3_OSTS_DEVRUNSTP BIT(13) | |
607 | #define DWC3_OSTS_XHCIRUNSTP BIT(12) | |
608 | #define DWC3_OSTS_PERIPHERALSTATE BIT(4) | |
609 | #define DWC3_OSTS_XHCIPRTPOWER BIT(3) | |
610 | #define DWC3_OSTS_BSESVLD BIT(2) | |
611 | #define DWC3_OSTS_VBUSVLD BIT(1) | |
612 | #define DWC3_OSTS_CONIDSTS BIT(0) | |
613 | ||
72246da4 FB |
614 | /* Structures */ |
615 | ||
f6bafc6a | 616 | struct dwc3_trb; |
72246da4 FB |
617 | |
618 | /** | |
619 | * struct dwc3_event_buffer - Software event buffer representation | |
72246da4 | 620 | * @buf: _THE_ buffer |
d9fa4c63 | 621 | * @cache: The buffer cache used in the threaded interrupt |
72246da4 | 622 | * @length: size of this buffer |
abed4118 | 623 | * @lpos: event offset |
60d04bbe | 624 | * @count: cache of last read event count register |
abed4118 | 625 | * @flags: flags related to this event buffer |
72246da4 FB |
626 | * @dma: dma_addr_t |
627 | * @dwc: pointer to DWC controller | |
628 | */ | |
629 | struct dwc3_event_buffer { | |
630 | void *buf; | |
d9fa4c63 | 631 | void *cache; |
72246da4 FB |
632 | unsigned length; |
633 | unsigned int lpos; | |
60d04bbe | 634 | unsigned int count; |
abed4118 FB |
635 | unsigned int flags; |
636 | ||
637 | #define DWC3_EVENT_PENDING BIT(0) | |
72246da4 FB |
638 | |
639 | dma_addr_t dma; | |
640 | ||
641 | struct dwc3 *dwc; | |
642 | }; | |
643 | ||
ff3f0789 RQ |
644 | #define DWC3_EP_FLAG_STALLED BIT(0) |
645 | #define DWC3_EP_FLAG_WEDGED BIT(1) | |
72246da4 FB |
646 | |
647 | #define DWC3_EP_DIRECTION_TX true | |
648 | #define DWC3_EP_DIRECTION_RX false | |
649 | ||
8495036e | 650 | #define DWC3_TRB_NUM 256 |
72246da4 FB |
651 | |
652 | /** | |
653 | * struct dwc3_ep - device side endpoint representation | |
654 | * @endpoint: usb endpoint | |
d5443bbf | 655 | * @cancelled_list: list of cancelled requests for this endpoint |
aa3342c8 FB |
656 | * @pending_list: list of pending requests for this endpoint |
657 | * @started_list: list of started requests on this endpoint | |
2eb88016 | 658 | * @regs: pointer to first endpoint register |
72246da4 FB |
659 | * @trb_pool: array of transaction buffers |
660 | * @trb_pool_dma: dma address of @trb_pool | |
53fd8818 FB |
661 | * @trb_enqueue: enqueue 'pointer' into TRB array |
662 | * @trb_dequeue: dequeue 'pointer' into TRB array | |
72246da4 | 663 | * @dwc: pointer to DWC controller |
4cfcf876 | 664 | * @saved_state: ep state saved during hibernation |
72246da4 | 665 | * @flags: endpoint flags (wedged, stalled, ...) |
72246da4 FB |
666 | * @number: endpoint number (1 - 15) |
667 | * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK | |
b4996a86 | 668 | * @resource_index: Resource transfer index |
502a37b9 | 669 | * @frame_number: set to the frame number we want this transfer to start (ISOC) |
c75f52fb | 670 | * @interval: the interval on which the ISOC transfer is started |
72246da4 FB |
671 | * @name: a human readable name e.g. ep1out-bulk |
672 | * @direction: true for TX, false for RX | |
879631aa | 673 | * @stream_capable: true when streams are enabled |
d92021f6 TN |
674 | * @combo_num: the test combination BIT[15:14] of the frame number to test |
675 | * isochronous START TRANSFER command failure workaround | |
676 | * @start_cmd_status: the status of testing START TRANSFER command with | |
677 | * combo_num = 'b00 | |
72246da4 FB |
678 | */ |
679 | struct dwc3_ep { | |
680 | struct usb_ep endpoint; | |
d5443bbf | 681 | struct list_head cancelled_list; |
aa3342c8 FB |
682 | struct list_head pending_list; |
683 | struct list_head started_list; | |
72246da4 | 684 | |
2eb88016 FB |
685 | void __iomem *regs; |
686 | ||
f6bafc6a | 687 | struct dwc3_trb *trb_pool; |
72246da4 | 688 | dma_addr_t trb_pool_dma; |
72246da4 FB |
689 | struct dwc3 *dwc; |
690 | ||
4cfcf876 | 691 | u32 saved_state; |
72246da4 | 692 | unsigned flags; |
ff3f0789 RQ |
693 | #define DWC3_EP_ENABLED BIT(0) |
694 | #define DWC3_EP_STALL BIT(1) | |
695 | #define DWC3_EP_WEDGE BIT(2) | |
5f2e7975 | 696 | #define DWC3_EP_TRANSFER_STARTED BIT(3) |
c58d8bfc | 697 | #define DWC3_EP_END_TRANSFER_PENDING BIT(4) |
ff3f0789 | 698 | #define DWC3_EP_PENDING_REQUEST BIT(5) |
da10bcdd | 699 | #define DWC3_EP_DELAY_START BIT(6) |
72246da4 | 700 | |
984f66a6 | 701 | /* This last one is specific to EP0 */ |
ff3f0789 | 702 | #define DWC3_EP0_DIR_IN BIT(31) |
984f66a6 | 703 | |
c28f8259 FB |
704 | /* |
705 | * IMPORTANT: we *know* we have 256 TRBs in our @trb_pool, so we will | |
706 | * use a u8 type here. If anybody decides to increase number of TRBs to | |
707 | * anything larger than 256 - I can't see why people would want to do | |
708 | * this though - then this type needs to be changed. | |
709 | * | |
710 | * By using u8 types we ensure that our % operator when incrementing | |
711 | * enqueue and dequeue get optimized away by the compiler. | |
712 | */ | |
713 | u8 trb_enqueue; | |
714 | u8 trb_dequeue; | |
715 | ||
72246da4 FB |
716 | u8 number; |
717 | u8 type; | |
b4996a86 | 718 | u8 resource_index; |
502a37b9 | 719 | u32 frame_number; |
72246da4 FB |
720 | u32 interval; |
721 | ||
722 | char name[20]; | |
723 | ||
724 | unsigned direction:1; | |
879631aa | 725 | unsigned stream_capable:1; |
d92021f6 TN |
726 | |
727 | /* For isochronous START TRANSFER workaround only */ | |
728 | u8 combo_num; | |
729 | int start_cmd_status; | |
72246da4 FB |
730 | }; |
731 | ||
732 | enum dwc3_phy { | |
733 | DWC3_PHY_UNKNOWN = 0, | |
734 | DWC3_PHY_USB3, | |
735 | DWC3_PHY_USB2, | |
736 | }; | |
737 | ||
b53c772d FB |
738 | enum dwc3_ep0_next { |
739 | DWC3_EP0_UNKNOWN = 0, | |
740 | DWC3_EP0_COMPLETE, | |
b53c772d FB |
741 | DWC3_EP0_NRDY_DATA, |
742 | DWC3_EP0_NRDY_STATUS, | |
743 | }; | |
744 | ||
72246da4 FB |
745 | enum dwc3_ep0_state { |
746 | EP0_UNCONNECTED = 0, | |
c7fcdeb2 FB |
747 | EP0_SETUP_PHASE, |
748 | EP0_DATA_PHASE, | |
749 | EP0_STATUS_PHASE, | |
72246da4 FB |
750 | }; |
751 | ||
752 | enum dwc3_link_state { | |
753 | /* In SuperSpeed */ | |
754 | DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */ | |
755 | DWC3_LINK_STATE_U1 = 0x01, | |
756 | DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */ | |
757 | DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */ | |
758 | DWC3_LINK_STATE_SS_DIS = 0x04, | |
759 | DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */ | |
760 | DWC3_LINK_STATE_SS_INACT = 0x06, | |
761 | DWC3_LINK_STATE_POLL = 0x07, | |
762 | DWC3_LINK_STATE_RECOV = 0x08, | |
763 | DWC3_LINK_STATE_HRESET = 0x09, | |
764 | DWC3_LINK_STATE_CMPLY = 0x0a, | |
765 | DWC3_LINK_STATE_LPBK = 0x0b, | |
2c61a8ef PZ |
766 | DWC3_LINK_STATE_RESET = 0x0e, |
767 | DWC3_LINK_STATE_RESUME = 0x0f, | |
72246da4 FB |
768 | DWC3_LINK_STATE_MASK = 0x0f, |
769 | }; | |
770 | ||
f6bafc6a FB |
771 | /* TRB Length, PCM and Status */ |
772 | #define DWC3_TRB_SIZE_MASK (0x00ffffff) | |
773 | #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK) | |
774 | #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24) | |
389f2828 | 775 | #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28) |
f6bafc6a FB |
776 | |
777 | #define DWC3_TRBSTS_OK 0 | |
778 | #define DWC3_TRBSTS_MISSED_ISOC 1 | |
779 | #define DWC3_TRBSTS_SETUP_PENDING 2 | |
2c61a8ef | 780 | #define DWC3_TRB_STS_XFER_IN_PROG 4 |
f6bafc6a FB |
781 | |
782 | /* TRB Control */ | |
ff3f0789 RQ |
783 | #define DWC3_TRB_CTRL_HWO BIT(0) |
784 | #define DWC3_TRB_CTRL_LST BIT(1) | |
785 | #define DWC3_TRB_CTRL_CHN BIT(2) | |
786 | #define DWC3_TRB_CTRL_CSP BIT(3) | |
f6bafc6a | 787 | #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4) |
ff3f0789 RQ |
788 | #define DWC3_TRB_CTRL_ISP_IMI BIT(10) |
789 | #define DWC3_TRB_CTRL_IOC BIT(11) | |
f6bafc6a | 790 | #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14) |
6abfa0f5 | 791 | #define DWC3_TRB_CTRL_GET_SID_SOFN(n) (((n) & (0xffff << 14)) >> 14) |
f6bafc6a | 792 | |
b058f3e8 | 793 | #define DWC3_TRBCTL_TYPE(n) ((n) & (0x3f << 4)) |
f6bafc6a FB |
794 | #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1) |
795 | #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2) | |
796 | #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3) | |
797 | #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4) | |
798 | #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5) | |
799 | #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6) | |
800 | #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7) | |
801 | #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8) | |
72246da4 FB |
802 | |
803 | /** | |
f6bafc6a | 804 | * struct dwc3_trb - transfer request block (hw format) |
72246da4 FB |
805 | * @bpl: DW0-3 |
806 | * @bph: DW4-7 | |
807 | * @size: DW8-B | |
bfad65ee | 808 | * @ctrl: DWC-F |
72246da4 | 809 | */ |
f6bafc6a FB |
810 | struct dwc3_trb { |
811 | u32 bpl; | |
812 | u32 bph; | |
813 | u32 size; | |
814 | u32 ctrl; | |
72246da4 FB |
815 | } __packed; |
816 | ||
a3299499 | 817 | /** |
bfad65ee FB |
818 | * struct dwc3_hwparams - copy of HWPARAMS registers |
819 | * @hwparams0: GHWPARAMS0 | |
820 | * @hwparams1: GHWPARAMS1 | |
821 | * @hwparams2: GHWPARAMS2 | |
822 | * @hwparams3: GHWPARAMS3 | |
823 | * @hwparams4: GHWPARAMS4 | |
824 | * @hwparams5: GHWPARAMS5 | |
825 | * @hwparams6: GHWPARAMS6 | |
826 | * @hwparams7: GHWPARAMS7 | |
827 | * @hwparams8: GHWPARAMS8 | |
a3299499 FB |
828 | */ |
829 | struct dwc3_hwparams { | |
830 | u32 hwparams0; | |
831 | u32 hwparams1; | |
832 | u32 hwparams2; | |
833 | u32 hwparams3; | |
834 | u32 hwparams4; | |
835 | u32 hwparams5; | |
836 | u32 hwparams6; | |
837 | u32 hwparams7; | |
838 | u32 hwparams8; | |
839 | }; | |
840 | ||
0949e99b FB |
841 | /* HWPARAMS0 */ |
842 | #define DWC3_MODE(n) ((n) & 0x7) | |
843 | ||
457e84b6 FB |
844 | #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8) |
845 | ||
0949e99b | 846 | /* HWPARAMS1 */ |
457e84b6 FB |
847 | #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15) |
848 | ||
789451f6 FB |
849 | /* HWPARAMS3 */ |
850 | #define DWC3_NUM_IN_EPS_MASK (0x1f << 18) | |
851 | #define DWC3_NUM_EPS_MASK (0x3f << 12) | |
852 | #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \ | |
853 | (DWC3_NUM_EPS_MASK)) >> 12) | |
854 | #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \ | |
855 | (DWC3_NUM_IN_EPS_MASK)) >> 18) | |
856 | ||
457e84b6 FB |
857 | /* HWPARAMS7 */ |
858 | #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff) | |
9f622b2a | 859 | |
5ef68c56 FB |
860 | /** |
861 | * struct dwc3_request - representation of a transfer request | |
862 | * @request: struct usb_request to be transferred | |
863 | * @list: a list_head used for request queueing | |
864 | * @dep: struct dwc3_ep owning this request | |
0b3e4af3 | 865 | * @sg: pointer to first incomplete sg |
a31e63b6 | 866 | * @start_sg: pointer to the sg which should be queued next |
0b3e4af3 | 867 | * @num_pending_sgs: counter to pending sgs |
c96e6725 | 868 | * @num_queued_sgs: counter to the number of sgs which already got queued |
e62c5bc5 | 869 | * @remaining: amount of data remaining |
a3af5e3a | 870 | * @status: internal dwc3 request status tracking |
5ef68c56 FB |
871 | * @epnum: endpoint number to which this request refers |
872 | * @trb: pointer to struct dwc3_trb | |
873 | * @trb_dma: DMA address of @trb | |
09fe1f8d | 874 | * @num_trbs: number of TRBs used by this request |
1a22ec64 FB |
875 | * @needs_extra_trb: true when request needs one extra TRB (either due to ZLP |
876 | * or unaligned OUT) | |
5ef68c56 FB |
877 | * @direction: IN or OUT direction flag |
878 | * @mapped: true when request has been dma-mapped | |
5ef68c56 | 879 | */ |
e0ce0b0a SAS |
880 | struct dwc3_request { |
881 | struct usb_request request; | |
882 | struct list_head list; | |
883 | struct dwc3_ep *dep; | |
0b3e4af3 | 884 | struct scatterlist *sg; |
a31e63b6 | 885 | struct scatterlist *start_sg; |
e0ce0b0a | 886 | |
0b3e4af3 | 887 | unsigned num_pending_sgs; |
c96e6725 | 888 | unsigned int num_queued_sgs; |
e62c5bc5 | 889 | unsigned remaining; |
a3af5e3a FB |
890 | |
891 | unsigned int status; | |
892 | #define DWC3_REQUEST_STATUS_QUEUED 0 | |
893 | #define DWC3_REQUEST_STATUS_STARTED 1 | |
894 | #define DWC3_REQUEST_STATUS_CANCELLED 2 | |
895 | #define DWC3_REQUEST_STATUS_COMPLETED 3 | |
896 | #define DWC3_REQUEST_STATUS_UNKNOWN -1 | |
897 | ||
e0ce0b0a | 898 | u8 epnum; |
f6bafc6a | 899 | struct dwc3_trb *trb; |
e0ce0b0a SAS |
900 | dma_addr_t trb_dma; |
901 | ||
09fe1f8d FB |
902 | unsigned num_trbs; |
903 | ||
1a22ec64 | 904 | unsigned needs_extra_trb:1; |
e0ce0b0a SAS |
905 | unsigned direction:1; |
906 | unsigned mapped:1; | |
e0ce0b0a SAS |
907 | }; |
908 | ||
2c61a8ef PZ |
909 | /* |
910 | * struct dwc3_scratchpad_array - hibernation scratchpad array | |
911 | * (format defined by hw) | |
912 | */ | |
913 | struct dwc3_scratchpad_array { | |
914 | __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS]; | |
915 | }; | |
916 | ||
72246da4 FB |
917 | /** |
918 | * struct dwc3 - representation of our controller | |
bfad65ee | 919 | * @drd_work: workqueue used for role swapping |
91db07dc | 920 | * @ep0_trb: trb which is used for the ctrl_req |
bfad65ee FB |
921 | * @bounce: address of bounce buffer |
922 | * @scratchbuf: address of scratch buffer | |
91db07dc | 923 | * @setup_buf: used while precessing STD USB requests |
bfad65ee FB |
924 | * @ep0_trb_addr: dma address of @ep0_trb |
925 | * @bounce_addr: dma address of @bounce | |
91db07dc | 926 | * @ep0_usb_req: dummy req used while handling STD USB requests |
0ffcaf37 | 927 | * @scratch_addr: dma address of scratchbuf |
bb014736 | 928 | * @ep0_in_setup: one control transfer is completed and enter setup phase |
72246da4 FB |
929 | * @lock: for synchronizing |
930 | * @dev: pointer to our struct device | |
bfad65ee | 931 | * @sysdev: pointer to the DMA-capable device |
d07e8819 | 932 | * @xhci: pointer to our xHCI child |
bfad65ee FB |
933 | * @xhci_resources: struct resources for our @xhci child |
934 | * @ev_buf: struct dwc3_event_buffer pointer | |
935 | * @eps: endpoint array | |
72246da4 FB |
936 | * @gadget: device side representation of the peripheral controller |
937 | * @gadget_driver: pointer to the gadget driver | |
fe8abf33 MY |
938 | * @clks: array of clocks |
939 | * @num_clks: number of clocks | |
940 | * @reset: reset control | |
72246da4 FB |
941 | * @regs: base address for our registers |
942 | * @regs_size: address space size | |
bcdb3272 | 943 | * @fladj: frame length adjustment |
3f308d17 | 944 | * @irq_gadget: peripheral controller's IRQ number |
f09cc79b RQ |
945 | * @otg_irq: IRQ number for OTG IRQs |
946 | * @current_otg_role: current role of operation while using the OTG block | |
947 | * @desired_otg_role: desired role of operation while using the OTG block | |
948 | * @otg_restart_host: flag that OTG controller needs to restart host | |
0ffcaf37 | 949 | * @nr_scratch: number of scratch buffers |
fae2b904 | 950 | * @u1u2: only used on revisions <1.83a for workaround |
6c167fc9 | 951 | * @maximum_speed: maximum speed requested (mainly for testing purposes) |
72246da4 | 952 | * @revision: revision register contents |
475d8e01 | 953 | * @version_type: VERSIONTYPE register contents, a sub release of a revision |
a45c82b8 | 954 | * @dr_mode: requested mode of operation |
6b3261a2 | 955 | * @current_dr_role: current role of operation when in dual-role mode |
41ce1456 | 956 | * @desired_dr_role: desired role of operation when in dual-role mode |
9840354f RQ |
957 | * @edev: extcon handle |
958 | * @edev_nb: extcon notifier | |
32f2ed86 WW |
959 | * @hsphy_mode: UTMI phy mode, one of following: |
960 | * - USBPHY_INTERFACE_MODE_UTMI | |
961 | * - USBPHY_INTERFACE_MODE_UTMIW | |
8a0a1379 | 962 | * @role_sw: usb_role_switch handle |
98ed256a JS |
963 | * @role_switch_default_mode: default operation mode of controller while |
964 | * usb role is USB_ROLE_NONE. | |
51e1e7bc FB |
965 | * @usb2_phy: pointer to USB2 PHY |
966 | * @usb3_phy: pointer to USB3 PHY | |
57303488 KVA |
967 | * @usb2_generic_phy: pointer to USB2 PHY |
968 | * @usb3_generic_phy: pointer to USB3 PHY | |
98112041 | 969 | * @phys_ready: flag to indicate that PHYs are ready |
88bc9d19 | 970 | * @ulpi: pointer to ulpi interface |
98112041 | 971 | * @ulpi_ready: flag to indicate that ULPI is initialized |
865e09e7 FB |
972 | * @u2sel: parameter from Set SEL request. |
973 | * @u2pel: parameter from Set SEL request. | |
974 | * @u1sel: parameter from Set SEL request. | |
975 | * @u1pel: parameter from Set SEL request. | |
47d3946e | 976 | * @num_eps: number of endpoints |
b53c772d | 977 | * @ep0_next_event: hold the next expected event |
72246da4 FB |
978 | * @ep0state: state of endpoint zero |
979 | * @link_state: link state | |
980 | * @speed: device speed (super, high, full, low) | |
a3299499 | 981 | * @hwparams: copy of hwparams registers |
72246da4 | 982 | * @root: debugfs root folder pointer |
f2b685d5 | 983 | * @regset: debugfs pointer to regdump file |
62ba09d6 | 984 | * @dbg_lsp_select: current debug lsp mux register selection |
f2b685d5 FB |
985 | * @test_mode: true when we're entering a USB test mode |
986 | * @test_mode_nr: test feature selector | |
80caf7d2 | 987 | * @lpm_nyet_threshold: LPM NYET response threshold |
460d098c | 988 | * @hird_threshold: HIRD threshold |
938a5ad1 TN |
989 | * @rx_thr_num_pkt_prd: periodic ESS receive packet count |
990 | * @rx_max_burst_prd: max periodic ESS receive burst size | |
991 | * @tx_thr_num_pkt_prd: periodic ESS transmit packet count | |
992 | * @tx_max_burst_prd: max periodic ESS transmit burst size | |
3e10a2ce | 993 | * @hsphy_interface: "utmi" or "ulpi" |
fc8bb91b | 994 | * @connected: true when we're connected to a host, false otherwise |
f2b685d5 FB |
995 | * @delayed_status: true when gadget driver asks for delayed status |
996 | * @ep0_bounced: true when we used bounce buffer | |
997 | * @ep0_expect_in: true when we expect a DATA IN transfer | |
81bc5599 | 998 | * @has_hibernation: true when dwc3 was configured with Hibernation |
d64ff406 | 999 | * @sysdev_is_parent: true when dwc3 device has a parent driver |
80caf7d2 HR |
1000 | * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that |
1001 | * there's now way for software to detect this in runtime. | |
460d098c HR |
1002 | * @is_utmi_l1_suspend: the core asserts output signal |
1003 | * 0 - utmi_sleep_n | |
1004 | * 1 - utmi_l1_suspend_n | |
946bd579 | 1005 | * @is_fpga: true when we are using the FPGA board |
fc8bb91b | 1006 | * @pending_events: true when we have pending IRQs to be handled |
f2b685d5 | 1007 | * @pullups_connected: true when Run/Stop bit is set |
f2b685d5 | 1008 | * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround |
f2b685d5 | 1009 | * @three_stage_setup: set if we perform a three phase setup |
d92021f6 TN |
1010 | * @dis_start_transfer_quirk: set if start_transfer failure SW workaround is |
1011 | * not needed for DWC_usb31 version 1.70a-ea06 and below | |
eac68e8f | 1012 | * @usb3_lpm_capable: set if hadrware supports Link Power Management |
022a0208 | 1013 | * @usb2_lpm_disable: set to disable usb2 lpm |
3b81221a | 1014 | * @disable_scramble_quirk: set if we enable the disable scramble quirk |
9a5b2f31 | 1015 | * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk |
b5a65c40 | 1016 | * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk |
df31f5b3 | 1017 | * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk |
a2a1d0f5 | 1018 | * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk |
41c06ffd | 1019 | * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk |
fb67afca | 1020 | * @lfps_filter_quirk: set if we enable LFPS filter quirk |
14f4ac53 | 1021 | * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk |
59acfa20 | 1022 | * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy |
0effe0a3 | 1023 | * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy |
ec791d14 JY |
1024 | * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG, |
1025 | * disabling the suspend signal to the PHY. | |
729dcffd AKV |
1026 | * @dis_u1_entry_quirk: set if link entering into U1 state needs to be disabled. |
1027 | * @dis_u2_entry_quirk: set if link entering into U2 state needs to be disabled. | |
bfad65ee | 1028 | * @dis_rxdet_inp3_quirk: set if we disable Rx.Detect in P3 |
16199f33 WW |
1029 | * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists |
1030 | * in GUSB2PHYCFG, specify that USB2 PHY doesn't | |
1031 | * provide a free-running PHY clock. | |
00fe081d WW |
1032 | * @dis_del_phy_power_chg_quirk: set if we disable delay phy power |
1033 | * change quirk. | |
65db7a0c WW |
1034 | * @dis_tx_ipgap_linecheck_quirk: set if we disable u2mac linestate |
1035 | * check during HS transmit. | |
7ba6b09f NA |
1036 | * @parkmode_disable_ss_quirk: set if we need to disable all SuperSpeed |
1037 | * instances in park mode. | |
6b6a0c9a HR |
1038 | * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk |
1039 | * @tx_de_emphasis: Tx de-emphasis value | |
1040 | * 0 - -6dB de-emphasis | |
1041 | * 1 - -3.5dB de-emphasis | |
1042 | * 2 - No de-emphasis | |
1043 | * 3 - Reserved | |
42bf02ec | 1044 | * @dis_metastability_quirk: set to disable metastability quirk. |
cf40b86b JY |
1045 | * @imod_interval: set the interrupt moderation interval in 250ns |
1046 | * increments or 0 to disable. | |
72246da4 FB |
1047 | */ |
1048 | struct dwc3 { | |
41ce1456 | 1049 | struct work_struct drd_work; |
f6bafc6a | 1050 | struct dwc3_trb *ep0_trb; |
905dc04e | 1051 | void *bounce; |
0ffcaf37 | 1052 | void *scratchbuf; |
72246da4 | 1053 | u8 *setup_buf; |
72246da4 | 1054 | dma_addr_t ep0_trb_addr; |
905dc04e | 1055 | dma_addr_t bounce_addr; |
0ffcaf37 | 1056 | dma_addr_t scratch_addr; |
e0ce0b0a | 1057 | struct dwc3_request ep0_usb_req; |
bb014736 | 1058 | struct completion ep0_in_setup; |
789451f6 | 1059 | |
72246da4 FB |
1060 | /* device lock */ |
1061 | spinlock_t lock; | |
789451f6 | 1062 | |
72246da4 | 1063 | struct device *dev; |
d64ff406 | 1064 | struct device *sysdev; |
72246da4 | 1065 | |
d07e8819 | 1066 | struct platform_device *xhci; |
51249dca | 1067 | struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM]; |
d07e8819 | 1068 | |
696c8b12 | 1069 | struct dwc3_event_buffer *ev_buf; |
72246da4 FB |
1070 | struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; |
1071 | ||
1072 | struct usb_gadget gadget; | |
1073 | struct usb_gadget_driver *gadget_driver; | |
1074 | ||
fe8abf33 MY |
1075 | struct clk_bulk_data *clks; |
1076 | int num_clks; | |
1077 | ||
1078 | struct reset_control *reset; | |
1079 | ||
51e1e7bc FB |
1080 | struct usb_phy *usb2_phy; |
1081 | struct usb_phy *usb3_phy; | |
1082 | ||
57303488 KVA |
1083 | struct phy *usb2_generic_phy; |
1084 | struct phy *usb3_generic_phy; | |
1085 | ||
98112041 RQ |
1086 | bool phys_ready; |
1087 | ||
88bc9d19 | 1088 | struct ulpi *ulpi; |
98112041 | 1089 | bool ulpi_ready; |
88bc9d19 | 1090 | |
72246da4 FB |
1091 | void __iomem *regs; |
1092 | size_t regs_size; | |
1093 | ||
a45c82b8 | 1094 | enum usb_dr_mode dr_mode; |
6b3261a2 | 1095 | u32 current_dr_role; |
41ce1456 | 1096 | u32 desired_dr_role; |
9840354f RQ |
1097 | struct extcon_dev *edev; |
1098 | struct notifier_block edev_nb; | |
32f2ed86 | 1099 | enum usb_phy_interface hsphy_mode; |
8a0a1379 | 1100 | struct usb_role_switch *role_sw; |
98ed256a | 1101 | enum usb_dr_mode role_switch_default_mode; |
a45c82b8 | 1102 | |
bcdb3272 | 1103 | u32 fladj; |
3f308d17 | 1104 | u32 irq_gadget; |
f09cc79b RQ |
1105 | u32 otg_irq; |
1106 | u32 current_otg_role; | |
1107 | u32 desired_otg_role; | |
1108 | bool otg_restart_host; | |
0ffcaf37 | 1109 | u32 nr_scratch; |
fae2b904 | 1110 | u32 u1u2; |
6c167fc9 | 1111 | u32 maximum_speed; |
690fb371 JY |
1112 | |
1113 | /* | |
1114 | * All 3.1 IP version constants are greater than the 3.0 IP | |
1115 | * version constants. This works for most version checks in | |
1116 | * dwc3. However, in the future, this may not apply as | |
1117 | * features may be developed on newer versions of the 3.0 IP | |
1118 | * that are not in the 3.1 IP. | |
1119 | */ | |
72246da4 FB |
1120 | u32 revision; |
1121 | ||
1122 | #define DWC3_REVISION_173A 0x5533173a | |
1123 | #define DWC3_REVISION_175A 0x5533175a | |
1124 | #define DWC3_REVISION_180A 0x5533180a | |
1125 | #define DWC3_REVISION_183A 0x5533183a | |
1126 | #define DWC3_REVISION_185A 0x5533185a | |
2c61a8ef | 1127 | #define DWC3_REVISION_187A 0x5533187a |
72246da4 FB |
1128 | #define DWC3_REVISION_188A 0x5533188a |
1129 | #define DWC3_REVISION_190A 0x5533190a | |
2c61a8ef | 1130 | #define DWC3_REVISION_194A 0x5533194a |
1522d703 FB |
1131 | #define DWC3_REVISION_200A 0x5533200a |
1132 | #define DWC3_REVISION_202A 0x5533202a | |
1133 | #define DWC3_REVISION_210A 0x5533210a | |
1134 | #define DWC3_REVISION_220A 0x5533220a | |
7ac6a593 FB |
1135 | #define DWC3_REVISION_230A 0x5533230a |
1136 | #define DWC3_REVISION_240A 0x5533240a | |
1137 | #define DWC3_REVISION_250A 0x5533250a | |
dbf5aaf7 FB |
1138 | #define DWC3_REVISION_260A 0x5533260a |
1139 | #define DWC3_REVISION_270A 0x5533270a | |
1140 | #define DWC3_REVISION_280A 0x5533280a | |
0bb39ca1 | 1141 | #define DWC3_REVISION_290A 0x5533290a |
512e4757 JY |
1142 | #define DWC3_REVISION_300A 0x5533300a |
1143 | #define DWC3_REVISION_310A 0x5533310a | |
89a9cc47 | 1144 | #define DWC3_REVISION_330A 0x5533330a |
72246da4 | 1145 | |
690fb371 JY |
1146 | /* |
1147 | * NOTICE: we're using bit 31 as a "is usb 3.1" flag. This is really | |
1148 | * just so dwc31 revisions are always larger than dwc3. | |
1149 | */ | |
1150 | #define DWC3_REVISION_IS_DWC31 0x80000000 | |
e77c5614 | 1151 | #define DWC3_USB31_REVISION_110A (0x3131302a | DWC3_REVISION_IS_DWC31) |
cf40b86b | 1152 | #define DWC3_USB31_REVISION_120A (0x3132302a | DWC3_REVISION_IS_DWC31) |
d92021f6 TN |
1153 | #define DWC3_USB31_REVISION_160A (0x3136302a | DWC3_REVISION_IS_DWC31) |
1154 | #define DWC3_USB31_REVISION_170A (0x3137302a | DWC3_REVISION_IS_DWC31) | |
4749e0e6 TN |
1155 | #define DWC3_USB31_REVISION_180A (0x3138302a | DWC3_REVISION_IS_DWC31) |
1156 | #define DWC3_USB31_REVISION_190A (0x3139302a | DWC3_REVISION_IS_DWC31) | |
690fb371 | 1157 | |
475d8e01 TN |
1158 | u32 version_type; |
1159 | ||
1160 | #define DWC31_VERSIONTYPE_EA01 0x65613031 | |
1161 | #define DWC31_VERSIONTYPE_EA02 0x65613032 | |
1162 | #define DWC31_VERSIONTYPE_EA03 0x65613033 | |
1163 | #define DWC31_VERSIONTYPE_EA04 0x65613034 | |
1164 | #define DWC31_VERSIONTYPE_EA05 0x65613035 | |
1165 | #define DWC31_VERSIONTYPE_EA06 0x65613036 | |
1166 | ||
b53c772d | 1167 | enum dwc3_ep0_next ep0_next_event; |
72246da4 FB |
1168 | enum dwc3_ep0_state ep0state; |
1169 | enum dwc3_link_state link_state; | |
72246da4 | 1170 | |
865e09e7 FB |
1171 | u16 u2sel; |
1172 | u16 u2pel; | |
1173 | u8 u1sel; | |
1174 | u8 u1pel; | |
1175 | ||
72246da4 | 1176 | u8 speed; |
865e09e7 | 1177 | |
47d3946e | 1178 | u8 num_eps; |
789451f6 | 1179 | |
a3299499 | 1180 | struct dwc3_hwparams hwparams; |
72246da4 | 1181 | struct dentry *root; |
d7668024 | 1182 | struct debugfs_regset32 *regset; |
3b637367 | 1183 | |
62ba09d6 TN |
1184 | u32 dbg_lsp_select; |
1185 | ||
3b637367 GC |
1186 | u8 test_mode; |
1187 | u8 test_mode_nr; | |
80caf7d2 | 1188 | u8 lpm_nyet_threshold; |
460d098c | 1189 | u8 hird_threshold; |
938a5ad1 TN |
1190 | u8 rx_thr_num_pkt_prd; |
1191 | u8 rx_max_burst_prd; | |
1192 | u8 tx_thr_num_pkt_prd; | |
1193 | u8 tx_max_burst_prd; | |
f2b685d5 | 1194 | |
3e10a2ce HK |
1195 | const char *hsphy_interface; |
1196 | ||
fc8bb91b | 1197 | unsigned connected:1; |
f2b685d5 FB |
1198 | unsigned delayed_status:1; |
1199 | unsigned ep0_bounced:1; | |
1200 | unsigned ep0_expect_in:1; | |
81bc5599 | 1201 | unsigned has_hibernation:1; |
d64ff406 | 1202 | unsigned sysdev_is_parent:1; |
80caf7d2 | 1203 | unsigned has_lpm_erratum:1; |
460d098c | 1204 | unsigned is_utmi_l1_suspend:1; |
946bd579 | 1205 | unsigned is_fpga:1; |
fc8bb91b | 1206 | unsigned pending_events:1; |
f2b685d5 | 1207 | unsigned pullups_connected:1; |
f2b685d5 | 1208 | unsigned setup_packet_pending:1; |
f2b685d5 | 1209 | unsigned three_stage_setup:1; |
d92021f6 | 1210 | unsigned dis_start_transfer_quirk:1; |
eac68e8f | 1211 | unsigned usb3_lpm_capable:1; |
022a0208 | 1212 | unsigned usb2_lpm_disable:1; |
3b81221a HR |
1213 | |
1214 | unsigned disable_scramble_quirk:1; | |
9a5b2f31 | 1215 | unsigned u2exit_lfps_quirk:1; |
b5a65c40 | 1216 | unsigned u2ss_inp3_quirk:1; |
df31f5b3 | 1217 | unsigned req_p1p2p3_quirk:1; |
a2a1d0f5 | 1218 | unsigned del_p1p2p3_quirk:1; |
41c06ffd | 1219 | unsigned del_phy_power_chg_quirk:1; |
fb67afca | 1220 | unsigned lfps_filter_quirk:1; |
14f4ac53 | 1221 | unsigned rx_detect_poll_quirk:1; |
59acfa20 | 1222 | unsigned dis_u3_susphy_quirk:1; |
0effe0a3 | 1223 | unsigned dis_u2_susphy_quirk:1; |
ec791d14 | 1224 | unsigned dis_enblslpm_quirk:1; |
729dcffd AKV |
1225 | unsigned dis_u1_entry_quirk:1; |
1226 | unsigned dis_u2_entry_quirk:1; | |
e58dd357 | 1227 | unsigned dis_rxdet_inp3_quirk:1; |
16199f33 | 1228 | unsigned dis_u2_freeclk_exists_quirk:1; |
00fe081d | 1229 | unsigned dis_del_phy_power_chg_quirk:1; |
65db7a0c | 1230 | unsigned dis_tx_ipgap_linecheck_quirk:1; |
7ba6b09f | 1231 | unsigned parkmode_disable_ss_quirk:1; |
6b6a0c9a HR |
1232 | |
1233 | unsigned tx_de_emphasis_quirk:1; | |
1234 | unsigned tx_de_emphasis:2; | |
cf40b86b | 1235 | |
42bf02ec RQ |
1236 | unsigned dis_metastability_quirk:1; |
1237 | ||
cf40b86b | 1238 | u16 imod_interval; |
72246da4 FB |
1239 | }; |
1240 | ||
d9612c2f PM |
1241 | #define INCRX_BURST_MODE 0 |
1242 | #define INCRX_UNDEF_LENGTH_BURST_MODE 1 | |
1243 | ||
41ce1456 | 1244 | #define work_to_dwc(w) (container_of((w), struct dwc3, drd_work)) |
72246da4 | 1245 | |
72246da4 FB |
1246 | /* -------------------------------------------------------------------------- */ |
1247 | ||
1248 | struct dwc3_event_type { | |
1249 | u32 is_devspec:1; | |
1974d494 HR |
1250 | u32 type:7; |
1251 | u32 reserved8_31:24; | |
72246da4 FB |
1252 | } __packed; |
1253 | ||
1254 | #define DWC3_DEPEVT_XFERCOMPLETE 0x01 | |
1255 | #define DWC3_DEPEVT_XFERINPROGRESS 0x02 | |
1256 | #define DWC3_DEPEVT_XFERNOTREADY 0x03 | |
1257 | #define DWC3_DEPEVT_RXTXFIFOEVT 0x04 | |
1258 | #define DWC3_DEPEVT_STREAMEVT 0x06 | |
1259 | #define DWC3_DEPEVT_EPCMDCMPLT 0x07 | |
1260 | ||
1261 | /** | |
1262 | * struct dwc3_event_depvt - Device Endpoint Events | |
1263 | * @one_bit: indicates this is an endpoint event (not used) | |
1264 | * @endpoint_number: number of the endpoint | |
1265 | * @endpoint_event: The event we have: | |
1266 | * 0x00 - Reserved | |
1267 | * 0x01 - XferComplete | |
1268 | * 0x02 - XferInProgress | |
1269 | * 0x03 - XferNotReady | |
1270 | * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun) | |
1271 | * 0x05 - Reserved | |
1272 | * 0x06 - StreamEvt | |
1273 | * 0x07 - EPCmdCmplt | |
1274 | * @reserved11_10: Reserved, don't use. | |
1275 | * @status: Indicates the status of the event. Refer to databook for | |
1276 | * more information. | |
1277 | * @parameters: Parameters of the current event. Refer to databook for | |
1278 | * more information. | |
1279 | */ | |
1280 | struct dwc3_event_depevt { | |
1281 | u32 one_bit:1; | |
1282 | u32 endpoint_number:5; | |
1283 | u32 endpoint_event:4; | |
1284 | u32 reserved11_10:2; | |
1285 | u32 status:4; | |
40aa41fb FB |
1286 | |
1287 | /* Within XferNotReady */ | |
ff3f0789 | 1288 | #define DEPEVT_STATUS_TRANSFER_ACTIVE BIT(3) |
40aa41fb | 1289 | |
6d8a0196 | 1290 | /* Within XferComplete or XferInProgress */ |
ff3f0789 RQ |
1291 | #define DEPEVT_STATUS_BUSERR BIT(0) |
1292 | #define DEPEVT_STATUS_SHORT BIT(1) | |
1293 | #define DEPEVT_STATUS_IOC BIT(2) | |
6d8a0196 FB |
1294 | #define DEPEVT_STATUS_LST BIT(3) /* XferComplete */ |
1295 | #define DEPEVT_STATUS_MISSED_ISOC BIT(3) /* XferInProgress */ | |
dc137f01 | 1296 | |
879631aa FB |
1297 | /* Stream event only */ |
1298 | #define DEPEVT_STREAMEVT_FOUND 1 | |
1299 | #define DEPEVT_STREAMEVT_NOTFOUND 2 | |
1300 | ||
dc137f01 | 1301 | /* Control-only Status */ |
dc137f01 FB |
1302 | #define DEPEVT_STATUS_CONTROL_DATA 1 |
1303 | #define DEPEVT_STATUS_CONTROL_STATUS 2 | |
45a2af2f | 1304 | #define DEPEVT_STATUS_CONTROL_PHASE(n) ((n) & 3) |
dc137f01 | 1305 | |
7b9cc7a2 KL |
1306 | /* In response to Start Transfer */ |
1307 | #define DEPEVT_TRANSFER_NO_RESOURCE 1 | |
1308 | #define DEPEVT_TRANSFER_BUS_EXPIRY 2 | |
1309 | ||
72246da4 | 1310 | u32 parameters:16; |
76a638f8 BW |
1311 | |
1312 | /* For Command Complete Events */ | |
1313 | #define DEPEVT_PARAMETER_CMD(n) (((n) & (0xf << 8)) >> 8) | |
72246da4 FB |
1314 | } __packed; |
1315 | ||
1316 | /** | |
1317 | * struct dwc3_event_devt - Device Events | |
1318 | * @one_bit: indicates this is a non-endpoint event (not used) | |
1319 | * @device_event: indicates it's a device event. Should read as 0x00 | |
1320 | * @type: indicates the type of device event. | |
1321 | * 0 - DisconnEvt | |
1322 | * 1 - USBRst | |
1323 | * 2 - ConnectDone | |
1324 | * 3 - ULStChng | |
1325 | * 4 - WkUpEvt | |
1326 | * 5 - Reserved | |
1327 | * 6 - EOPF | |
1328 | * 7 - SOF | |
1329 | * 8 - Reserved | |
1330 | * 9 - ErrticErr | |
1331 | * 10 - CmdCmplt | |
1332 | * 11 - EvntOverflow | |
1333 | * 12 - VndrDevTstRcved | |
1334 | * @reserved15_12: Reserved, not used | |
1335 | * @event_info: Information about this event | |
06f9b6e5 | 1336 | * @reserved31_25: Reserved, not used |
72246da4 FB |
1337 | */ |
1338 | struct dwc3_event_devt { | |
1339 | u32 one_bit:1; | |
1340 | u32 device_event:7; | |
1341 | u32 type:4; | |
1342 | u32 reserved15_12:4; | |
06f9b6e5 HR |
1343 | u32 event_info:9; |
1344 | u32 reserved31_25:7; | |
72246da4 FB |
1345 | } __packed; |
1346 | ||
1347 | /** | |
1348 | * struct dwc3_event_gevt - Other Core Events | |
1349 | * @one_bit: indicates this is a non-endpoint event (not used) | |
1350 | * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. | |
1351 | * @phy_port_number: self-explanatory | |
1352 | * @reserved31_12: Reserved, not used. | |
1353 | */ | |
1354 | struct dwc3_event_gevt { | |
1355 | u32 one_bit:1; | |
1356 | u32 device_event:7; | |
1357 | u32 phy_port_number:4; | |
1358 | u32 reserved31_12:20; | |
1359 | } __packed; | |
1360 | ||
1361 | /** | |
1362 | * union dwc3_event - representation of Event Buffer contents | |
1363 | * @raw: raw 32-bit event | |
1364 | * @type: the type of the event | |
1365 | * @depevt: Device Endpoint Event | |
1366 | * @devt: Device Event | |
1367 | * @gevt: Global Event | |
1368 | */ | |
1369 | union dwc3_event { | |
1370 | u32 raw; | |
1371 | struct dwc3_event_type type; | |
1372 | struct dwc3_event_depevt depevt; | |
1373 | struct dwc3_event_devt devt; | |
1374 | struct dwc3_event_gevt gevt; | |
1375 | }; | |
1376 | ||
61018305 FB |
1377 | /** |
1378 | * struct dwc3_gadget_ep_cmd_params - representation of endpoint command | |
1379 | * parameters | |
1380 | * @param2: third parameter | |
1381 | * @param1: second parameter | |
1382 | * @param0: first parameter | |
1383 | */ | |
1384 | struct dwc3_gadget_ep_cmd_params { | |
1385 | u32 param2; | |
1386 | u32 param1; | |
1387 | u32 param0; | |
1388 | }; | |
1389 | ||
72246da4 FB |
1390 | /* |
1391 | * DWC3 Features to be used as Driver Data | |
1392 | */ | |
1393 | ||
1394 | #define DWC3_HAS_PERIPHERAL BIT(0) | |
1395 | #define DWC3_HAS_XHCI BIT(1) | |
1396 | #define DWC3_HAS_OTG BIT(3) | |
1397 | ||
d07e8819 | 1398 | /* prototypes */ |
f09cc79b | 1399 | void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode); |
3140e8cb | 1400 | void dwc3_set_mode(struct dwc3 *dwc, u32 mode); |
cf6d867d | 1401 | u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type); |
3140e8cb | 1402 | |
a987a906 JY |
1403 | /* check whether we are on the DWC_usb3 core */ |
1404 | static inline bool dwc3_is_usb3(struct dwc3 *dwc) | |
1405 | { | |
1406 | return !(dwc->revision & DWC3_REVISION_IS_DWC31); | |
1407 | } | |
1408 | ||
c4137a9c JY |
1409 | /* check whether we are on the DWC_usb31 core */ |
1410 | static inline bool dwc3_is_usb31(struct dwc3 *dwc) | |
1411 | { | |
1412 | return !!(dwc->revision & DWC3_REVISION_IS_DWC31); | |
1413 | } | |
1414 | ||
cf40b86b JY |
1415 | bool dwc3_has_imod(struct dwc3 *dwc); |
1416 | ||
f09cc79b RQ |
1417 | int dwc3_event_buffers_setup(struct dwc3 *dwc); |
1418 | void dwc3_event_buffers_cleanup(struct dwc3 *dwc); | |
1419 | ||
388e5c51 | 1420 | #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) |
d07e8819 FB |
1421 | int dwc3_host_init(struct dwc3 *dwc); |
1422 | void dwc3_host_exit(struct dwc3 *dwc); | |
388e5c51 VG |
1423 | #else |
1424 | static inline int dwc3_host_init(struct dwc3 *dwc) | |
1425 | { return 0; } | |
1426 | static inline void dwc3_host_exit(struct dwc3 *dwc) | |
1427 | { } | |
1428 | #endif | |
1429 | ||
1430 | #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) | |
f80b45e7 FB |
1431 | int dwc3_gadget_init(struct dwc3 *dwc); |
1432 | void dwc3_gadget_exit(struct dwc3 *dwc); | |
61018305 FB |
1433 | int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode); |
1434 | int dwc3_gadget_get_link_state(struct dwc3 *dwc); | |
1435 | int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state); | |
2cd4718d FB |
1436 | int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd, |
1437 | struct dwc3_gadget_ep_cmd_params *params); | |
3ece0ec4 | 1438 | int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param); |
388e5c51 VG |
1439 | #else |
1440 | static inline int dwc3_gadget_init(struct dwc3 *dwc) | |
1441 | { return 0; } | |
1442 | static inline void dwc3_gadget_exit(struct dwc3 *dwc) | |
1443 | { } | |
61018305 FB |
1444 | static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) |
1445 | { return 0; } | |
1446 | static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc) | |
1447 | { return 0; } | |
1448 | static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc, | |
1449 | enum dwc3_link_state state) | |
1450 | { return 0; } | |
1451 | ||
2cd4718d FB |
1452 | static inline int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd, |
1453 | struct dwc3_gadget_ep_cmd_params *params) | |
61018305 FB |
1454 | { return 0; } |
1455 | static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc, | |
1456 | int cmd, u32 param) | |
1457 | { return 0; } | |
388e5c51 | 1458 | #endif |
f80b45e7 | 1459 | |
9840354f RQ |
1460 | #if IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) |
1461 | int dwc3_drd_init(struct dwc3 *dwc); | |
1462 | void dwc3_drd_exit(struct dwc3 *dwc); | |
f09cc79b RQ |
1463 | void dwc3_otg_init(struct dwc3 *dwc); |
1464 | void dwc3_otg_exit(struct dwc3 *dwc); | |
1465 | void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus); | |
1466 | void dwc3_otg_host_init(struct dwc3 *dwc); | |
9840354f RQ |
1467 | #else |
1468 | static inline int dwc3_drd_init(struct dwc3 *dwc) | |
1469 | { return 0; } | |
1470 | static inline void dwc3_drd_exit(struct dwc3 *dwc) | |
1471 | { } | |
f09cc79b RQ |
1472 | static inline void dwc3_otg_init(struct dwc3 *dwc) |
1473 | { } | |
1474 | static inline void dwc3_otg_exit(struct dwc3 *dwc) | |
1475 | { } | |
1476 | static inline void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus) | |
1477 | { } | |
1478 | static inline void dwc3_otg_host_init(struct dwc3 *dwc) | |
1479 | { } | |
9840354f RQ |
1480 | #endif |
1481 | ||
7415f17c FB |
1482 | /* power management interface */ |
1483 | #if !IS_ENABLED(CONFIG_USB_DWC3_HOST) | |
7415f17c FB |
1484 | int dwc3_gadget_suspend(struct dwc3 *dwc); |
1485 | int dwc3_gadget_resume(struct dwc3 *dwc); | |
fc8bb91b | 1486 | void dwc3_gadget_process_pending_events(struct dwc3 *dwc); |
7415f17c | 1487 | #else |
7415f17c FB |
1488 | static inline int dwc3_gadget_suspend(struct dwc3 *dwc) |
1489 | { | |
1490 | return 0; | |
1491 | } | |
1492 | ||
1493 | static inline int dwc3_gadget_resume(struct dwc3 *dwc) | |
1494 | { | |
1495 | return 0; | |
1496 | } | |
fc8bb91b FB |
1497 | |
1498 | static inline void dwc3_gadget_process_pending_events(struct dwc3 *dwc) | |
1499 | { | |
1500 | } | |
7415f17c FB |
1501 | #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */ |
1502 | ||
88bc9d19 HK |
1503 | #if IS_ENABLED(CONFIG_USB_DWC3_ULPI) |
1504 | int dwc3_ulpi_init(struct dwc3 *dwc); | |
1505 | void dwc3_ulpi_exit(struct dwc3 *dwc); | |
1506 | #else | |
1507 | static inline int dwc3_ulpi_init(struct dwc3 *dwc) | |
1508 | { return 0; } | |
1509 | static inline void dwc3_ulpi_exit(struct dwc3 *dwc) | |
1510 | { } | |
1511 | #endif | |
1512 | ||
72246da4 | 1513 | #endif /* __DRIVERS_USB_DWC3_CORE_H */ |