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5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0 |
72246da4 FB |
2 | /** |
3 | * dwc3-pci.c - PCI Specific glue layer | |
4 | * | |
5 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
6 | * |
7 | * Authors: Felipe Balbi <balbi@ti.com>, | |
8 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
72246da4 FB |
9 | */ |
10 | ||
11 | #include <linux/kernel.h> | |
46a57283 | 12 | #include <linux/module.h> |
72246da4 FB |
13 | #include <linux/slab.h> |
14 | #include <linux/pci.h> | |
8eed00b2 | 15 | #include <linux/workqueue.h> |
e9af9229 | 16 | #include <linux/pm_runtime.h> |
72246da4 | 17 | #include <linux/platform_device.h> |
a89d977c | 18 | #include <linux/gpio/consumer.h> |
5741022c | 19 | #include <linux/gpio/machine.h> |
a89d977c | 20 | #include <linux/acpi.h> |
cf48305d | 21 | #include <linux/delay.h> |
8f317b47 | 22 | |
9a5a0783 JY |
23 | #define PCI_DEVICE_ID_INTEL_BYT 0x0f37 |
24 | #define PCI_DEVICE_ID_INTEL_MRFLD 0x119e | |
25 | #define PCI_DEVICE_ID_INTEL_BSW 0x22b7 | |
26 | #define PCI_DEVICE_ID_INTEL_SPTLP 0x9d30 | |
27 | #define PCI_DEVICE_ID_INTEL_SPTH 0xa130 | |
b4c580a4 | 28 | #define PCI_DEVICE_ID_INTEL_BXT 0x0aaa |
1ffb4d5c | 29 | #define PCI_DEVICE_ID_INTEL_BXT_M 0x1aaa |
b4c580a4 | 30 | #define PCI_DEVICE_ID_INTEL_APL 0x5aaa |
4491ed50 | 31 | #define PCI_DEVICE_ID_INTEL_KBP 0xa2b0 |
3c3caae4 HK |
32 | #define PCI_DEVICE_ID_INTEL_CMLLP 0x02ee |
33 | #define PCI_DEVICE_ID_INTEL_CMLH 0x06ee | |
8f8983a5 | 34 | #define PCI_DEVICE_ID_INTEL_GLK 0x31aa |
68217959 HK |
35 | #define PCI_DEVICE_ID_INTEL_CNPLP 0x9dee |
36 | #define PCI_DEVICE_ID_INTEL_CNPH 0xa36e | |
f5ae8869 | 37 | #define PCI_DEVICE_ID_INTEL_CNPV 0xa3b0 |
00908693 | 38 | #define PCI_DEVICE_ID_INTEL_ICLLP 0x34ee |
dbb0569d | 39 | #define PCI_DEVICE_ID_INTEL_EHLLP 0x4b7e |
b3649dee | 40 | #define PCI_DEVICE_ID_INTEL_TGPLP 0xa0ee |
72246da4 | 41 | |
94116f81 | 42 | #define PCI_INTEL_BXT_DSM_GUID "732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511" |
9cecca75 FB |
43 | #define PCI_INTEL_BXT_FUNC_PMU_PWR 4 |
44 | #define PCI_INTEL_BXT_STATE_D0 0 | |
45 | #define PCI_INTEL_BXT_STATE_D3 3 | |
46 | ||
7740d04d HG |
47 | #define GP_RWBAR 1 |
48 | #define GP_RWREG1 0xa0 | |
49 | #define GP_RWREG1_ULPI_REFCLK_DISABLE (1 << 17) | |
50 | ||
0f817ae6 FB |
51 | /** |
52 | * struct dwc3_pci - Driver private structure | |
53 | * @dwc3: child dwc3 platform_device | |
54 | * @pci: our link to PCI bus | |
94116f81 | 55 | * @guid: _DSM GUID |
9cecca75 | 56 | * @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM |
87d852de | 57 | * @wakeup_work: work for asynchronous resume |
0f817ae6 FB |
58 | */ |
59 | struct dwc3_pci { | |
60 | struct platform_device *dwc3; | |
61 | struct pci_dev *pci; | |
9cecca75 | 62 | |
94116f81 | 63 | guid_t guid; |
9cecca75 FB |
64 | |
65 | unsigned int has_dsm_for_pm:1; | |
8eed00b2 | 66 | struct work_struct wakeup_work; |
0f817ae6 FB |
67 | }; |
68 | ||
a89d977c HK |
69 | static const struct acpi_gpio_params reset_gpios = { 0, 0, false }; |
70 | static const struct acpi_gpio_params cs_gpios = { 1, 0, false }; | |
71 | ||
72 | static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = { | |
73 | { "reset-gpios", &reset_gpios, 1 }, | |
74 | { "cs-gpios", &cs_gpios, 1 }, | |
75 | { }, | |
76 | }; | |
77 | ||
5741022c HG |
78 | static struct gpiod_lookup_table platform_bytcr_gpios = { |
79 | .dev_id = "0000:00:16.0", | |
80 | .table = { | |
81 | GPIO_LOOKUP("INT33FC:00", 54, "reset", GPIO_ACTIVE_HIGH), | |
82 | GPIO_LOOKUP("INT33FC:02", 14, "cs", GPIO_ACTIVE_HIGH), | |
83 | {} | |
84 | }, | |
85 | }; | |
86 | ||
7740d04d HG |
87 | static int dwc3_byt_enable_ulpi_refclock(struct pci_dev *pci) |
88 | { | |
89 | void __iomem *reg; | |
90 | u32 value; | |
91 | ||
92 | reg = pcim_iomap(pci, GP_RWBAR, 0); | |
b497fff6 WY |
93 | if (!reg) |
94 | return -ENOMEM; | |
7740d04d HG |
95 | |
96 | value = readl(reg + GP_RWREG1); | |
97 | if (!(value & GP_RWREG1_ULPI_REFCLK_DISABLE)) | |
98 | goto unmap; /* ULPI refclk already enabled */ | |
99 | ||
100 | value &= ~GP_RWREG1_ULPI_REFCLK_DISABLE; | |
101 | writel(value, reg + GP_RWREG1); | |
102 | /* This comes from the Intel Android x86 tree w/o any explanation */ | |
103 | msleep(100); | |
104 | unmap: | |
105 | pcim_iounmap(pci, reg); | |
106 | return 0; | |
107 | } | |
108 | ||
1a7b12f6 AS |
109 | static const struct property_entry dwc3_pci_intel_properties[] = { |
110 | PROPERTY_ENTRY_STRING("dr_mode", "peripheral"), | |
111 | PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), | |
112 | {} | |
113 | }; | |
114 | ||
c31d983b AS |
115 | static const struct property_entry dwc3_pci_mrfld_properties[] = { |
116 | PROPERTY_ENTRY_STRING("dr_mode", "otg"), | |
066c0959 | 117 | PROPERTY_ENTRY_STRING("linux,extcon-name", "mrfld_bcove_pwrsrc"), |
c31d983b AS |
118 | PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), |
119 | {} | |
120 | }; | |
121 | ||
1a7b12f6 AS |
122 | static const struct property_entry dwc3_pci_amd_properties[] = { |
123 | PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"), | |
124 | PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf), | |
125 | PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"), | |
126 | PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"), | |
127 | PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"), | |
128 | PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"), | |
129 | PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"), | |
130 | PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"), | |
131 | PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"), | |
132 | PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"), | |
133 | PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1), | |
134 | /* FIXME these quirks should be removed when AMD NL tapes out */ | |
135 | PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"), | |
136 | PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"), | |
137 | PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"), | |
138 | PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), | |
139 | {} | |
140 | }; | |
141 | ||
0f817ae6 | 142 | static int dwc3_pci_quirks(struct dwc3_pci *dwc) |
2cd9ddf7 | 143 | { |
0f817ae6 FB |
144 | struct pci_dev *pdev = dwc->pci; |
145 | ||
e6fe66fe | 146 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) { |
9cecca75 FB |
147 | if (pdev->device == PCI_DEVICE_ID_INTEL_BXT || |
148 | pdev->device == PCI_DEVICE_ID_INTEL_BXT_M) { | |
94116f81 | 149 | guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid); |
9cecca75 FB |
150 | dwc->has_dsm_for_pm = true; |
151 | } | |
152 | ||
e6fe66fe FB |
153 | if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) { |
154 | struct gpio_desc *gpio; | |
1a7b12f6 | 155 | int ret; |
e6fe66fe | 156 | |
7740d04d HG |
157 | /* On BYT the FW does not always enable the refclock */ |
158 | ret = dwc3_byt_enable_ulpi_refclock(pdev); | |
159 | if (ret) | |
160 | return ret; | |
161 | ||
4a56e413 | 162 | ret = devm_acpi_dev_add_driver_gpios(&pdev->dev, |
e6fe66fe | 163 | acpi_dwc3_byt_gpios); |
4a56e413 AS |
164 | if (ret) |
165 | dev_dbg(&pdev->dev, "failed to add mapping table\n"); | |
e6fe66fe | 166 | |
5741022c HG |
167 | /* |
168 | * A lot of BYT devices lack ACPI resource entries for | |
169 | * the GPIOs, add a fallback mapping to the reference | |
170 | * design GPIOs which all boards seem to use. | |
171 | */ | |
172 | gpiod_add_lookup_table(&platform_bytcr_gpios); | |
173 | ||
e6fe66fe FB |
174 | /* |
175 | * These GPIOs will turn on the USB2 PHY. Note that we have to | |
176 | * put the gpio descriptors again here because the phy driver | |
177 | * might want to grab them, too. | |
178 | */ | |
3004cfd6 | 179 | gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW); |
e6fe66fe FB |
180 | if (IS_ERR(gpio)) |
181 | return PTR_ERR(gpio); | |
182 | ||
a89d977c | 183 | gpiod_set_value_cansleep(gpio, 1); |
3004cfd6 | 184 | gpiod_put(gpio); |
e6fe66fe | 185 | |
3004cfd6 | 186 | gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW); |
e6fe66fe FB |
187 | if (IS_ERR(gpio)) |
188 | return PTR_ERR(gpio); | |
189 | ||
190 | if (gpio) { | |
191 | gpiod_set_value_cansleep(gpio, 1); | |
3004cfd6 | 192 | gpiod_put(gpio); |
e6fe66fe FB |
193 | usleep_range(10000, 11000); |
194 | } | |
a89d977c HK |
195 | } |
196 | } | |
197 | ||
2cd9ddf7 HK |
198 | return 0; |
199 | } | |
72246da4 | 200 | |
8eed00b2 MG |
201 | #ifdef CONFIG_PM |
202 | static void dwc3_pci_resume_work(struct work_struct *work) | |
203 | { | |
204 | struct dwc3_pci *dwc = container_of(work, struct dwc3_pci, wakeup_work); | |
205 | struct platform_device *dwc3 = dwc->dwc3; | |
206 | int ret; | |
207 | ||
208 | ret = pm_runtime_get_sync(&dwc3->dev); | |
209 | if (ret) | |
210 | return; | |
211 | ||
212 | pm_runtime_mark_last_busy(&dwc3->dev); | |
213 | pm_runtime_put_sync_autosuspend(&dwc3->dev); | |
214 | } | |
215 | #endif | |
216 | ||
1a7b12f6 | 217 | static int dwc3_pci_probe(struct pci_dev *pci, const struct pci_device_id *id) |
72246da4 | 218 | { |
1a7b12f6 | 219 | struct property_entry *p = (struct property_entry *)id->driver_data; |
0f817ae6 | 220 | struct dwc3_pci *dwc; |
72246da4 | 221 | struct resource res[2]; |
b09e99ee | 222 | int ret; |
802ca850 | 223 | struct device *dev = &pci->dev; |
72246da4 | 224 | |
f1c7e710 | 225 | ret = pcim_enable_device(pci); |
72246da4 | 226 | if (ret) { |
802ca850 CP |
227 | dev_err(dev, "failed to enable pci device\n"); |
228 | return -ENODEV; | |
72246da4 FB |
229 | } |
230 | ||
72246da4 FB |
231 | pci_set_master(pci); |
232 | ||
0f817ae6 FB |
233 | dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); |
234 | if (!dwc) | |
235 | return -ENOMEM; | |
236 | ||
237 | dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); | |
238 | if (!dwc->dwc3) | |
f1c7e710 | 239 | return -ENOMEM; |
72246da4 FB |
240 | |
241 | memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res)); | |
242 | ||
243 | res[0].start = pci_resource_start(pci, 0); | |
244 | res[0].end = pci_resource_end(pci, 0); | |
245 | res[0].name = "dwc_usb3"; | |
246 | res[0].flags = IORESOURCE_MEM; | |
247 | ||
248 | res[1].start = pci->irq; | |
249 | res[1].name = "dwc_usb3"; | |
250 | res[1].flags = IORESOURCE_IRQ; | |
251 | ||
0f817ae6 | 252 | ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res)); |
72246da4 | 253 | if (ret) { |
802ca850 | 254 | dev_err(dev, "couldn't add resources to dwc3 device\n"); |
cabdf83d | 255 | goto err; |
72246da4 FB |
256 | } |
257 | ||
0f817ae6 FB |
258 | dwc->pci = pci; |
259 | dwc->dwc3->dev.parent = dev; | |
260 | ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev)); | |
72246da4 | 261 | |
1a7b12f6 AS |
262 | ret = platform_device_add_properties(dwc->dwc3, p); |
263 | if (ret < 0) | |
9bbfceea | 264 | goto err; |
1a7b12f6 | 265 | |
0f817ae6 | 266 | ret = dwc3_pci_quirks(dwc); |
474799f0 HK |
267 | if (ret) |
268 | goto err; | |
269 | ||
0f817ae6 | 270 | ret = platform_device_add(dwc->dwc3); |
72246da4 | 271 | if (ret) { |
802ca850 | 272 | dev_err(dev, "failed to register dwc3 device\n"); |
2cd9ddf7 | 273 | goto err; |
72246da4 FB |
274 | } |
275 | ||
e9af9229 | 276 | device_init_wakeup(dev, true); |
0f817ae6 | 277 | pci_set_drvdata(pci, dwc); |
e9af9229 | 278 | pm_runtime_put(dev); |
8eed00b2 MG |
279 | #ifdef CONFIG_PM |
280 | INIT_WORK(&dwc->wakeup_work, dwc3_pci_resume_work); | |
281 | #endif | |
e9af9229 | 282 | |
72246da4 | 283 | return 0; |
2cd9ddf7 | 284 | err: |
0f817ae6 | 285 | platform_device_put(dwc->dwc3); |
72246da4 FB |
286 | return ret; |
287 | } | |
288 | ||
fb4e98ab | 289 | static void dwc3_pci_remove(struct pci_dev *pci) |
72246da4 | 290 | { |
0f817ae6 | 291 | struct dwc3_pci *dwc = pci_get_drvdata(pci); |
7b412b04 | 292 | struct pci_dev *pdev = dwc->pci; |
0f817ae6 | 293 | |
7b412b04 KS |
294 | if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) |
295 | gpiod_remove_lookup_table(&platform_bytcr_gpios); | |
8eed00b2 MG |
296 | #ifdef CONFIG_PM |
297 | cancel_work_sync(&dwc->wakeup_work); | |
298 | #endif | |
e9af9229 FB |
299 | device_init_wakeup(&pci->dev, false); |
300 | pm_runtime_get(&pci->dev); | |
0f817ae6 | 301 | platform_device_unregister(dwc->dwc3); |
72246da4 FB |
302 | } |
303 | ||
782df20c | 304 | static const struct pci_device_id dwc3_pci_id_table[] = { |
1a7b12f6 AS |
305 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BSW), |
306 | (kernel_ulong_t) &dwc3_pci_intel_properties }, | |
307 | ||
308 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BYT), | |
309 | (kernel_ulong_t) &dwc3_pci_intel_properties, }, | |
310 | ||
311 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MRFLD), | |
c31d983b | 312 | (kernel_ulong_t) &dwc3_pci_mrfld_properties, }, |
1a7b12f6 | 313 | |
3c3caae4 HK |
314 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLLP), |
315 | (kernel_ulong_t) &dwc3_pci_intel_properties, }, | |
316 | ||
7ae622c9 FB |
317 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLH), |
318 | (kernel_ulong_t) &dwc3_pci_intel_properties, }, | |
319 | ||
1a7b12f6 AS |
320 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTLP), |
321 | (kernel_ulong_t) &dwc3_pci_intel_properties, }, | |
322 | ||
323 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTH), | |
324 | (kernel_ulong_t) &dwc3_pci_intel_properties, }, | |
325 | ||
326 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT), | |
327 | (kernel_ulong_t) &dwc3_pci_intel_properties, }, | |
328 | ||
329 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT_M), | |
330 | (kernel_ulong_t) &dwc3_pci_intel_properties, }, | |
331 | ||
332 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_APL), | |
333 | (kernel_ulong_t) &dwc3_pci_intel_properties, }, | |
334 | ||
335 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_KBP), | |
336 | (kernel_ulong_t) &dwc3_pci_intel_properties, }, | |
337 | ||
338 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_GLK), | |
339 | (kernel_ulong_t) &dwc3_pci_intel_properties, }, | |
340 | ||
341 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPLP), | |
342 | (kernel_ulong_t) &dwc3_pci_intel_properties, }, | |
343 | ||
344 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPH), | |
345 | (kernel_ulong_t) &dwc3_pci_intel_properties, }, | |
346 | ||
f5ae8869 HK |
347 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPV), |
348 | (kernel_ulong_t) &dwc3_pci_intel_properties, }, | |
349 | ||
1a7b12f6 AS |
350 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICLLP), |
351 | (kernel_ulong_t) &dwc3_pci_intel_properties, }, | |
352 | ||
dbb0569d FB |
353 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_EHLLP), |
354 | (kernel_ulong_t) &dwc3_pci_intel_properties, }, | |
355 | ||
b3649dee FB |
356 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPLP), |
357 | (kernel_ulong_t) &dwc3_pci_intel_properties, }, | |
358 | ||
1a7b12f6 AS |
359 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_NL_USB), |
360 | (kernel_ulong_t) &dwc3_pci_amd_properties, }, | |
72246da4 FB |
361 | { } /* Terminating Entry */ |
362 | }; | |
363 | MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table); | |
364 | ||
36daf3aa FB |
365 | #if defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP) |
366 | static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param) | |
367 | { | |
368 | union acpi_object *obj; | |
369 | union acpi_object tmp; | |
370 | union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp); | |
371 | ||
372 | if (!dwc->has_dsm_for_pm) | |
373 | return 0; | |
374 | ||
375 | tmp.type = ACPI_TYPE_INTEGER; | |
376 | tmp.integer.value = param; | |
377 | ||
94116f81 | 378 | obj = acpi_evaluate_dsm(ACPI_HANDLE(&dwc->pci->dev), &dwc->guid, |
36daf3aa FB |
379 | 1, PCI_INTEL_BXT_FUNC_PMU_PWR, &argv4); |
380 | if (!obj) { | |
381 | dev_err(&dwc->pci->dev, "failed to evaluate _DSM\n"); | |
382 | return -EIO; | |
383 | } | |
384 | ||
385 | ACPI_FREE(obj); | |
386 | ||
387 | return 0; | |
388 | } | |
389 | #endif /* CONFIG_PM || CONFIG_PM_SLEEP */ | |
390 | ||
e9af9229 FB |
391 | #ifdef CONFIG_PM |
392 | static int dwc3_pci_runtime_suspend(struct device *dev) | |
393 | { | |
9cecca75 FB |
394 | struct dwc3_pci *dwc = dev_get_drvdata(dev); |
395 | ||
de3ef1eb | 396 | if (device_can_wakeup(dev)) |
9cecca75 | 397 | return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3); |
e9af9229 FB |
398 | |
399 | return -EBUSY; | |
400 | } | |
401 | ||
f6c274e1 FB |
402 | static int dwc3_pci_runtime_resume(struct device *dev) |
403 | { | |
0f817ae6 | 404 | struct dwc3_pci *dwc = dev_get_drvdata(dev); |
9cecca75 FB |
405 | int ret; |
406 | ||
407 | ret = dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0); | |
408 | if (ret) | |
409 | return ret; | |
f6c274e1 | 410 | |
8eed00b2 MG |
411 | queue_work(pm_wq, &dwc->wakeup_work); |
412 | ||
413 | return 0; | |
f6c274e1 | 414 | } |
696118c0 | 415 | #endif /* CONFIG_PM */ |
f6c274e1 | 416 | |
696118c0 | 417 | #ifdef CONFIG_PM_SLEEP |
9cecca75 | 418 | static int dwc3_pci_suspend(struct device *dev) |
e9af9229 | 419 | { |
9cecca75 FB |
420 | struct dwc3_pci *dwc = dev_get_drvdata(dev); |
421 | ||
422 | return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3); | |
423 | } | |
424 | ||
425 | static int dwc3_pci_resume(struct device *dev) | |
426 | { | |
427 | struct dwc3_pci *dwc = dev_get_drvdata(dev); | |
428 | ||
429 | return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0); | |
e9af9229 | 430 | } |
696118c0 | 431 | #endif /* CONFIG_PM_SLEEP */ |
e9af9229 | 432 | |
95aa932c | 433 | static const struct dev_pm_ops dwc3_pci_dev_pm_ops = { |
9cecca75 | 434 | SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_suspend, dwc3_pci_resume) |
f6c274e1 | 435 | SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume, |
e9af9229 FB |
436 | NULL) |
437 | }; | |
438 | ||
72246da4 | 439 | static struct pci_driver dwc3_pci_driver = { |
0949e99b | 440 | .name = "dwc3-pci", |
72246da4 FB |
441 | .id_table = dwc3_pci_id_table, |
442 | .probe = dwc3_pci_probe, | |
7690417d | 443 | .remove = dwc3_pci_remove, |
e9af9229 FB |
444 | .driver = { |
445 | .pm = &dwc3_pci_dev_pm_ops, | |
446 | } | |
72246da4 FB |
447 | }; |
448 | ||
449 | MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); | |
5945f789 | 450 | MODULE_LICENSE("GPL v2"); |
72246da4 FB |
451 | MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer"); |
452 | ||
95656336 | 453 | module_pci_driver(dwc3_pci_driver); |