]> git.ipfire.org Git - people/ms/u-boot.git/blame - drivers/usb/eth/smsc95xx.c
smsc95xx: Use zero length packets when RX fifo is empty
[people/ms/u-boot.git] / drivers / usb / eth / smsc95xx.c
CommitLineData
291391be 1/*
0990fcb7 2 * Copyright (c) 2015 Google, Inc
291391be
SG
3 * Copyright (c) 2011 The Chromium OS Authors.
4 * Copyright (C) 2009 NVIDIA, Corporation
ad6e48e5 5 * Copyright (C) 2007-2008 SMSC (Steve Glendinning)
291391be 6 *
1a459660 7 * SPDX-License-Identifier: GPL-2.0+
291391be
SG
8 */
9
10#include <common.h>
0990fcb7 11#include <dm.h>
a2692591
SG
12#include <errno.h>
13#include <malloc.h>
cf92e05c 14#include <memalign.h>
291391be 15#include <usb.h>
a2692591 16#include <asm/unaligned.h>
291391be
SG
17#include <linux/mii.h>
18#include "usb_ether.h"
19
20/* SMSC LAN95xx based USB 2.0 Ethernet Devices */
21
98f686c2
SR
22/* LED defines */
23#define LED_GPIO_CFG (0x24)
24#define LED_GPIO_CFG_SPD_LED (0x01000000)
25#define LED_GPIO_CFG_LNK_LED (0x00100000)
26#define LED_GPIO_CFG_FDX_LED (0x00010000)
27
291391be
SG
28/* Tx command words */
29#define TX_CMD_A_FIRST_SEG_ 0x00002000
30#define TX_CMD_A_LAST_SEG_ 0x00001000
31
32/* Rx status word */
33#define RX_STS_FL_ 0x3FFF0000 /* Frame Length */
34#define RX_STS_ES_ 0x00008000 /* Error Summary */
35
36/* SCSRs */
37#define ID_REV 0x00
38
39#define INT_STS 0x08
40
41#define TX_CFG 0x10
42#define TX_CFG_ON_ 0x00000004
43
44#define HW_CFG 0x14
45#define HW_CFG_BIR_ 0x00001000
46#define HW_CFG_RXDOFF_ 0x00000600
47#define HW_CFG_MEF_ 0x00000020
48#define HW_CFG_BCE_ 0x00000002
49#define HW_CFG_LRST_ 0x00000008
50
51#define PM_CTRL 0x20
52#define PM_CTL_PHY_RST_ 0x00000010
53
54#define AFC_CFG 0x2C
55
56/*
57 * Hi watermark = 15.5Kb (~10 mtu pkts)
58 * low watermark = 3k (~2 mtu pkts)
59 * backpressure duration = ~ 350us
60 * Apply FC on any frame.
61 */
62#define AFC_CFG_DEFAULT 0x00F830A1
63
64#define E2P_CMD 0x30
65#define E2P_CMD_BUSY_ 0x80000000
66#define E2P_CMD_READ_ 0x00000000
67#define E2P_CMD_TIMEOUT_ 0x00000400
68#define E2P_CMD_LOADED_ 0x00000200
69#define E2P_CMD_ADDR_ 0x000001FF
70
71#define E2P_DATA 0x34
72
73#define BURST_CAP 0x38
74
75#define INT_EP_CTL 0x68
76#define INT_EP_CTL_PHY_INT_ 0x00008000
77
78#define BULK_IN_DLY 0x6C
79
80/* MAC CSRs */
81#define MAC_CR 0x100
82#define MAC_CR_MCPAS_ 0x00080000
83#define MAC_CR_PRMS_ 0x00040000
84#define MAC_CR_HPFILT_ 0x00002000
85#define MAC_CR_TXEN_ 0x00000008
86#define MAC_CR_RXEN_ 0x00000004
87
88#define ADDRH 0x104
89
90#define ADDRL 0x108
91
92#define MII_ADDR 0x114
93#define MII_WRITE_ 0x02
94#define MII_BUSY_ 0x01
95#define MII_READ_ 0x00 /* ~of MII Write bit */
96
97#define MII_DATA 0x118
98
99#define FLOW 0x11C
100
101#define VLAN1 0x120
102
103#define COE_CR 0x130
104#define Tx_COE_EN_ 0x00010000
105#define Rx_COE_EN_ 0x00000001
106
107/* Vendor-specific PHY Definitions */
108#define PHY_INT_SRC 29
109
110#define PHY_INT_MASK 30
111#define PHY_INT_MASK_ANEG_COMP_ ((u16)0x0040)
112#define PHY_INT_MASK_LINK_DOWN_ ((u16)0x0010)
113#define PHY_INT_MASK_DEFAULT_ (PHY_INT_MASK_ANEG_COMP_ | \
114 PHY_INT_MASK_LINK_DOWN_)
115
116/* USB Vendor Requests */
117#define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0
118#define USB_VENDOR_REQUEST_READ_REGISTER 0xA1
119
120/* Some extra defines */
121#define HS_USB_PKT_SIZE 512
122#define FS_USB_PKT_SIZE 64
0d2837cc
SB
123/* 5/33 is lower limit for BURST_CAP to work */
124#define DEFAULT_HS_BURST_CAP_SIZE (5 * HS_USB_PKT_SIZE)
125#define DEFAULT_FS_BURST_CAP_SIZE (33 * FS_USB_PKT_SIZE)
291391be
SG
126#define DEFAULT_BULK_IN_DELAY 0x00002000
127#define MAX_SINGLE_PACKET_SIZE 2048
128#define EEPROM_MAC_OFFSET 0x01
129#define SMSC95XX_INTERNAL_PHY_ID 1
130#define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */
131
132/* local defines */
133#define SMSC95XX_BASE_NAME "sms"
134#define USB_CTRL_SET_TIMEOUT 5000
135#define USB_CTRL_GET_TIMEOUT 5000
136#define USB_BULK_SEND_TIMEOUT 5000
137#define USB_BULK_RECV_TIMEOUT 5000
138
0d2837cc 139#define RX_URB_SIZE DEFAULT_HS_BURST_CAP_SIZE
291391be
SG
140#define PHY_CONNECT_TIMEOUT 5000
141
142#define TURBO_MODE
143
0990fcb7 144#ifndef CONFIG_DM_ETH
291391be
SG
145/* local vars */
146static int curr_eth_dev; /* index for name of next device detected */
0990fcb7 147#endif
291391be 148
e1dbdf91
LS
149/* driver private */
150struct smsc95xx_private {
0990fcb7
SG
151#ifdef CONFIG_DM_ETH
152 struct ueth_data ueth;
153#endif
e1dbdf91
LS
154 size_t rx_urb_size; /* maximum USB URB size */
155 u32 mac_cr; /* MAC control register value */
156 int have_hwaddr; /* 1 if we have a hardware MAC address */
157};
291391be
SG
158
159/*
160 * Smsc95xx infrastructure commands
161 */
527298c4 162static int smsc95xx_write_reg(struct usb_device *udev, u32 index, u32 data)
291391be
SG
163{
164 int len;
e3b31c8d 165 ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1);
291391be
SG
166
167 cpu_to_le32s(&data);
e3b31c8d 168 tmpbuf[0] = data;
291391be 169
527298c4
SG
170 len = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
171 USB_VENDOR_REQUEST_WRITE_REGISTER,
172 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
173 0, index, tmpbuf, sizeof(data),
174 USB_CTRL_SET_TIMEOUT);
291391be
SG
175 if (len != sizeof(data)) {
176 debug("smsc95xx_write_reg failed: index=%d, data=%d, len=%d",
177 index, data, len);
25a9e980 178 return -EIO;
291391be
SG
179 }
180 return 0;
181}
182
527298c4 183static int smsc95xx_read_reg(struct usb_device *udev, u32 index, u32 *data)
291391be
SG
184{
185 int len;
e3b31c8d 186 ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1);
291391be 187
527298c4
SG
188 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
189 USB_VENDOR_REQUEST_READ_REGISTER,
190 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
191 0, index, tmpbuf, sizeof(data),
192 USB_CTRL_GET_TIMEOUT);
e3b31c8d 193 *data = tmpbuf[0];
291391be
SG
194 if (len != sizeof(data)) {
195 debug("smsc95xx_read_reg failed: index=%d, len=%d",
196 index, len);
25a9e980 197 return -EIO;
291391be
SG
198 }
199
200 le32_to_cpus(data);
201 return 0;
202}
203
204/* Loop until the read is completed with timeout */
527298c4 205static int smsc95xx_phy_wait_not_busy(struct usb_device *udev)
291391be
SG
206{
207 unsigned long start_time = get_timer(0);
208 u32 val;
209
210 do {
527298c4 211 smsc95xx_read_reg(udev, MII_ADDR, &val);
291391be
SG
212 if (!(val & MII_BUSY_))
213 return 0;
527298c4 214 } while (get_timer(start_time) < 1000);
291391be 215
25a9e980 216 return -ETIMEDOUT;
291391be
SG
217}
218
527298c4 219static int smsc95xx_mdio_read(struct usb_device *udev, int phy_id, int idx)
291391be
SG
220{
221 u32 val, addr;
222
223 /* confirm MII not busy */
527298c4 224 if (smsc95xx_phy_wait_not_busy(udev)) {
291391be 225 debug("MII is busy in smsc95xx_mdio_read\n");
25a9e980 226 return -ETIMEDOUT;
291391be
SG
227 }
228
229 /* set the address, index & direction (read from PHY) */
230 addr = (phy_id << 11) | (idx << 6) | MII_READ_;
527298c4 231 smsc95xx_write_reg(udev, MII_ADDR, addr);
291391be 232
527298c4 233 if (smsc95xx_phy_wait_not_busy(udev)) {
291391be 234 debug("Timed out reading MII reg %02X\n", idx);
25a9e980 235 return -ETIMEDOUT;
291391be
SG
236 }
237
527298c4 238 smsc95xx_read_reg(udev, MII_DATA, &val);
291391be
SG
239
240 return (u16)(val & 0xFFFF);
241}
242
527298c4 243static void smsc95xx_mdio_write(struct usb_device *udev, int phy_id, int idx,
291391be
SG
244 int regval)
245{
246 u32 val, addr;
247
248 /* confirm MII not busy */
527298c4 249 if (smsc95xx_phy_wait_not_busy(udev)) {
291391be
SG
250 debug("MII is busy in smsc95xx_mdio_write\n");
251 return;
252 }
253
254 val = regval;
527298c4 255 smsc95xx_write_reg(udev, MII_DATA, val);
291391be
SG
256
257 /* set the address, index & direction (write to PHY) */
258 addr = (phy_id << 11) | (idx << 6) | MII_WRITE_;
527298c4 259 smsc95xx_write_reg(udev, MII_ADDR, addr);
291391be 260
527298c4 261 if (smsc95xx_phy_wait_not_busy(udev))
291391be
SG
262 debug("Timed out writing MII reg %02X\n", idx);
263}
264
527298c4 265static int smsc95xx_eeprom_confirm_not_busy(struct usb_device *udev)
291391be
SG
266{
267 unsigned long start_time = get_timer(0);
268 u32 val;
269
270 do {
527298c4 271 smsc95xx_read_reg(udev, E2P_CMD, &val);
291391be
SG
272 if (!(val & E2P_CMD_BUSY_))
273 return 0;
274 udelay(40);
275 } while (get_timer(start_time) < 1 * 1000 * 1000);
276
277 debug("EEPROM is busy\n");
25a9e980 278 return -ETIMEDOUT;
291391be
SG
279}
280
527298c4 281static int smsc95xx_wait_eeprom(struct usb_device *udev)
291391be
SG
282{
283 unsigned long start_time = get_timer(0);
284 u32 val;
285
286 do {
527298c4 287 smsc95xx_read_reg(udev, E2P_CMD, &val);
291391be
SG
288 if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_))
289 break;
290 udelay(40);
291 } while (get_timer(start_time) < 1 * 1000 * 1000);
292
293 if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) {
294 debug("EEPROM read operation timeout\n");
25a9e980 295 return -ETIMEDOUT;
291391be
SG
296 }
297 return 0;
298}
299
527298c4 300static int smsc95xx_read_eeprom(struct usb_device *udev, u32 offset, u32 length,
291391be
SG
301 u8 *data)
302{
303 u32 val;
304 int i, ret;
305
527298c4 306 ret = smsc95xx_eeprom_confirm_not_busy(udev);
291391be
SG
307 if (ret)
308 return ret;
309
310 for (i = 0; i < length; i++) {
311 val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_);
527298c4 312 smsc95xx_write_reg(udev, E2P_CMD, val);
291391be 313
527298c4 314 ret = smsc95xx_wait_eeprom(udev);
291391be
SG
315 if (ret < 0)
316 return ret;
317
527298c4 318 smsc95xx_read_reg(udev, E2P_DATA, &val);
291391be
SG
319 data[i] = val & 0xFF;
320 offset++;
321 }
322 return 0;
323}
324
325/*
326 * mii_nway_restart - restart NWay (autonegotiation) for this interface
327 *
328 * Returns 0 on success, negative on error.
329 */
527298c4 330static int mii_nway_restart(struct usb_device *udev, struct ueth_data *dev)
291391be
SG
331{
332 int bmcr;
333 int r = -1;
334
335 /* if autoneg is off, it's an error */
527298c4 336 bmcr = smsc95xx_mdio_read(udev, dev->phy_id, MII_BMCR);
291391be
SG
337
338 if (bmcr & BMCR_ANENABLE) {
339 bmcr |= BMCR_ANRESTART;
527298c4 340 smsc95xx_mdio_write(udev, dev->phy_id, MII_BMCR, bmcr);
291391be
SG
341 r = 0;
342 }
343 return r;
344}
345
527298c4
SG
346static int smsc95xx_phy_initialize(struct usb_device *udev,
347 struct ueth_data *dev)
291391be 348{
527298c4
SG
349 smsc95xx_mdio_write(udev, dev->phy_id, MII_BMCR, BMCR_RESET);
350 smsc95xx_mdio_write(udev, dev->phy_id, MII_ADVERTISE,
351 ADVERTISE_ALL | ADVERTISE_CSMA |
352 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
291391be
SG
353
354 /* read to clear */
527298c4 355 smsc95xx_mdio_read(udev, dev->phy_id, PHY_INT_SRC);
291391be 356
527298c4
SG
357 smsc95xx_mdio_write(udev, dev->phy_id, PHY_INT_MASK,
358 PHY_INT_MASK_DEFAULT_);
359 mii_nway_restart(udev, dev);
291391be
SG
360
361 debug("phy initialised succesfully\n");
362 return 0;
363}
364
527298c4
SG
365static int smsc95xx_init_mac_address(unsigned char *enetaddr,
366 struct usb_device *udev)
291391be 367{
527298c4
SG
368 int ret;
369
291391be 370 /* try reading mac address from EEPROM */
527298c4
SG
371 ret = smsc95xx_read_eeprom(udev, EEPROM_MAC_OFFSET, ETH_ALEN, enetaddr);
372 if (ret)
373 return ret;
374
375 if (is_valid_ethaddr(enetaddr)) {
376 /* eeprom values are valid so use them */
377 debug("MAC address read from EEPROM\n");
378 return 0;
291391be
SG
379 }
380
381 /*
382 * No eeprom, or eeprom values are invalid. Generating a random MAC
383 * address is not safe. Just return an error.
384 */
25a9e980
SG
385 debug("Invalid MAC address read from EEPROM\n");
386
387 return -ENXIO;
291391be
SG
388}
389
527298c4
SG
390static int smsc95xx_write_hwaddr_common(struct usb_device *udev,
391 struct smsc95xx_private *priv,
392 unsigned char *enetaddr)
291391be 393{
527298c4
SG
394 u32 addr_lo = __get_unaligned_le32(&enetaddr[0]);
395 u32 addr_hi = __get_unaligned_le16(&enetaddr[4]);
291391be
SG
396 int ret;
397
398 /* set hardware address */
399 debug("** %s()\n", __func__);
527298c4 400 ret = smsc95xx_write_reg(udev, ADDRL, addr_lo);
0d9679e6 401 if (ret < 0)
291391be 402 return ret;
291391be 403
527298c4 404 ret = smsc95xx_write_reg(udev, ADDRH, addr_hi);
291391be
SG
405 if (ret < 0)
406 return ret;
0d9679e6 407
527298c4 408 debug("MAC %pM\n", enetaddr);
e1dbdf91 409 priv->have_hwaddr = 1;
527298c4 410
291391be
SG
411 return 0;
412}
413
414/* Enable or disable Tx & Rx checksum offload engines */
527298c4
SG
415static int smsc95xx_set_csums(struct usb_device *udev, int use_tx_csum,
416 int use_rx_csum)
291391be
SG
417{
418 u32 read_buf;
527298c4 419 int ret = smsc95xx_read_reg(udev, COE_CR, &read_buf);
291391be
SG
420 if (ret < 0)
421 return ret;
422
423 if (use_tx_csum)
424 read_buf |= Tx_COE_EN_;
425 else
426 read_buf &= ~Tx_COE_EN_;
427
428 if (use_rx_csum)
429 read_buf |= Rx_COE_EN_;
430 else
431 read_buf &= ~Rx_COE_EN_;
432
527298c4 433 ret = smsc95xx_write_reg(udev, COE_CR, read_buf);
291391be
SG
434 if (ret < 0)
435 return ret;
436
437 debug("COE_CR = 0x%08x\n", read_buf);
438 return 0;
439}
440
527298c4 441static void smsc95xx_set_multicast(struct smsc95xx_private *priv)
291391be
SG
442{
443 /* No multicast in u-boot */
e1dbdf91 444 priv->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
291391be
SG
445}
446
447/* starts the TX path */
527298c4
SG
448static void smsc95xx_start_tx_path(struct usb_device *udev,
449 struct smsc95xx_private *priv)
291391be
SG
450{
451 u32 reg_val;
452
453 /* Enable Tx at MAC */
e1dbdf91 454 priv->mac_cr |= MAC_CR_TXEN_;
291391be 455
527298c4 456 smsc95xx_write_reg(udev, MAC_CR, priv->mac_cr);
291391be
SG
457
458 /* Enable Tx at SCSRs */
459 reg_val = TX_CFG_ON_;
527298c4 460 smsc95xx_write_reg(udev, TX_CFG, reg_val);
291391be
SG
461}
462
463/* Starts the Receive path */
527298c4
SG
464static void smsc95xx_start_rx_path(struct usb_device *udev,
465 struct smsc95xx_private *priv)
291391be 466{
e1dbdf91 467 priv->mac_cr |= MAC_CR_RXEN_;
527298c4 468 smsc95xx_write_reg(udev, MAC_CR, priv->mac_cr);
291391be
SG
469}
470
527298c4
SG
471static int smsc95xx_init_common(struct usb_device *udev, struct ueth_data *dev,
472 struct smsc95xx_private *priv,
473 unsigned char *enetaddr)
291391be
SG
474{
475 int ret;
476 u32 write_buf;
477 u32 read_buf;
478 u32 burst_cap;
479 int timeout;
291391be
SG
480#define TIMEOUT_RESOLUTION 50 /* ms */
481 int link_detected;
482
483 debug("** %s()\n", __func__);
484 dev->phy_id = SMSC95XX_INTERNAL_PHY_ID; /* fixed phy id */
485
486 write_buf = HW_CFG_LRST_;
527298c4 487 ret = smsc95xx_write_reg(udev, HW_CFG, write_buf);
291391be
SG
488 if (ret < 0)
489 return ret;
490
491 timeout = 0;
492 do {
527298c4 493 ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
291391be
SG
494 if (ret < 0)
495 return ret;
496 udelay(10 * 1000);
497 timeout++;
498 } while ((read_buf & HW_CFG_LRST_) && (timeout < 100));
499
500 if (timeout >= 100) {
501 debug("timeout waiting for completion of Lite Reset\n");
25a9e980 502 return -ETIMEDOUT;
291391be
SG
503 }
504
505 write_buf = PM_CTL_PHY_RST_;
527298c4 506 ret = smsc95xx_write_reg(udev, PM_CTRL, write_buf);
291391be
SG
507 if (ret < 0)
508 return ret;
509
510 timeout = 0;
511 do {
527298c4 512 ret = smsc95xx_read_reg(udev, PM_CTRL, &read_buf);
291391be
SG
513 if (ret < 0)
514 return ret;
515 udelay(10 * 1000);
516 timeout++;
517 } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100));
518 if (timeout >= 100) {
519 debug("timeout waiting for PHY Reset\n");
25a9e980 520 return -ETIMEDOUT;
291391be 521 }
527298c4
SG
522 if (!priv->have_hwaddr && smsc95xx_init_mac_address(enetaddr, udev) ==
523 0)
e1dbdf91
LS
524 priv->have_hwaddr = 1;
525 if (!priv->have_hwaddr) {
291391be 526 puts("Error: SMSC95xx: No MAC address set - set usbethaddr\n");
25a9e980 527 return -EADDRNOTAVAIL;
291391be 528 }
527298c4 529 ret = smsc95xx_write_hwaddr_common(udev, priv, enetaddr);
25a9e980
SG
530 if (ret < 0)
531 return ret;
291391be 532
291391be
SG
533#ifdef TURBO_MODE
534 if (dev->pusb_dev->speed == USB_SPEED_HIGH) {
535 burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
e1dbdf91 536 priv->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
291391be
SG
537 } else {
538 burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
e1dbdf91 539 priv->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
291391be
SG
540 }
541#else
542 burst_cap = 0;
e1dbdf91 543 priv->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
291391be 544#endif
e1dbdf91 545 debug("rx_urb_size=%ld\n", (ulong)priv->rx_urb_size);
291391be 546
527298c4 547 ret = smsc95xx_write_reg(udev, BURST_CAP, burst_cap);
291391be
SG
548 if (ret < 0)
549 return ret;
550
527298c4 551 ret = smsc95xx_read_reg(udev, BURST_CAP, &read_buf);
291391be
SG
552 if (ret < 0)
553 return ret;
554 debug("Read Value from BURST_CAP after writing: 0x%08x\n", read_buf);
555
556 read_buf = DEFAULT_BULK_IN_DELAY;
527298c4 557 ret = smsc95xx_write_reg(udev, BULK_IN_DLY, read_buf);
291391be
SG
558 if (ret < 0)
559 return ret;
560
527298c4 561 ret = smsc95xx_read_reg(udev, BULK_IN_DLY, &read_buf);
291391be
SG
562 if (ret < 0)
563 return ret;
564 debug("Read Value from BULK_IN_DLY after writing: "
565 "0x%08x\n", read_buf);
566
527298c4 567 ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
291391be
SG
568 if (ret < 0)
569 return ret;
570 debug("Read Value from HW_CFG: 0x%08x\n", read_buf);
571
572#ifdef TURBO_MODE
573 read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_);
574#endif
575 read_buf &= ~HW_CFG_RXDOFF_;
576
577#define NET_IP_ALIGN 0
578 read_buf |= NET_IP_ALIGN << 9;
579
527298c4 580 ret = smsc95xx_write_reg(udev, HW_CFG, read_buf);
291391be
SG
581 if (ret < 0)
582 return ret;
583
527298c4 584 ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
291391be
SG
585 if (ret < 0)
586 return ret;
587 debug("Read Value from HW_CFG after writing: 0x%08x\n", read_buf);
588
589 write_buf = 0xFFFFFFFF;
527298c4 590 ret = smsc95xx_write_reg(udev, INT_STS, write_buf);
291391be
SG
591 if (ret < 0)
592 return ret;
593
527298c4 594 ret = smsc95xx_read_reg(udev, ID_REV, &read_buf);
291391be
SG
595 if (ret < 0)
596 return ret;
597 debug("ID_REV = 0x%08x\n", read_buf);
598
98f686c2
SR
599 /* Configure GPIO pins as LED outputs */
600 write_buf = LED_GPIO_CFG_SPD_LED | LED_GPIO_CFG_LNK_LED |
601 LED_GPIO_CFG_FDX_LED;
527298c4 602 ret = smsc95xx_write_reg(udev, LED_GPIO_CFG, write_buf);
98f686c2
SR
603 if (ret < 0)
604 return ret;
605 debug("LED_GPIO_CFG set\n");
606
291391be
SG
607 /* Init Tx */
608 write_buf = 0;
527298c4 609 ret = smsc95xx_write_reg(udev, FLOW, write_buf);
291391be
SG
610 if (ret < 0)
611 return ret;
612
613 read_buf = AFC_CFG_DEFAULT;
527298c4 614 ret = smsc95xx_write_reg(udev, AFC_CFG, read_buf);
291391be
SG
615 if (ret < 0)
616 return ret;
617
527298c4 618 ret = smsc95xx_read_reg(udev, MAC_CR, &priv->mac_cr);
291391be
SG
619 if (ret < 0)
620 return ret;
621
622 /* Init Rx. Set Vlan */
623 write_buf = (u32)ETH_P_8021Q;
527298c4 624 ret = smsc95xx_write_reg(udev, VLAN1, write_buf);
291391be
SG
625 if (ret < 0)
626 return ret;
627
628 /* Disable checksum offload engines */
527298c4 629 ret = smsc95xx_set_csums(udev, 0, 0);
291391be
SG
630 if (ret < 0) {
631 debug("Failed to set csum offload: %d\n", ret);
632 return ret;
633 }
527298c4 634 smsc95xx_set_multicast(priv);
291391be 635
527298c4 636 ret = smsc95xx_phy_initialize(udev, dev);
25a9e980
SG
637 if (ret < 0)
638 return ret;
527298c4 639 ret = smsc95xx_read_reg(udev, INT_EP_CTL, &read_buf);
291391be
SG
640 if (ret < 0)
641 return ret;
642
643 /* enable PHY interrupts */
644 read_buf |= INT_EP_CTL_PHY_INT_;
645
527298c4 646 ret = smsc95xx_write_reg(udev, INT_EP_CTL, read_buf);
291391be
SG
647 if (ret < 0)
648 return ret;
649
527298c4
SG
650 smsc95xx_start_tx_path(udev, priv);
651 smsc95xx_start_rx_path(udev, priv);
291391be
SG
652
653 timeout = 0;
654 do {
527298c4 655 link_detected = smsc95xx_mdio_read(udev, dev->phy_id, MII_BMSR)
291391be
SG
656 & BMSR_LSTATUS;
657 if (!link_detected) {
658 if (timeout == 0)
659 printf("Waiting for Ethernet connection... ");
660 udelay(TIMEOUT_RESOLUTION * 1000);
661 timeout += TIMEOUT_RESOLUTION;
662 }
663 } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
664 if (link_detected) {
665 if (timeout != 0)
666 printf("done.\n");
667 } else {
668 printf("unable to connect.\n");
25a9e980 669 return -EIO;
291391be
SG
670 }
671 return 0;
672}
673
527298c4 674static int smsc95xx_send_common(struct ueth_data *dev, void *packet, int length)
291391be 675{
291391be
SG
676 int err;
677 int actual_len;
678 u32 tx_cmd_a;
679 u32 tx_cmd_b;
e3b31c8d
IY
680 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg,
681 PKTSIZE + sizeof(tx_cmd_a) + sizeof(tx_cmd_b));
291391be
SG
682
683 debug("** %s(), len %d, buf %#x\n", __func__, length, (int)msg);
684 if (length > PKTSIZE)
25a9e980 685 return -ENOSPC;
291391be
SG
686
687 tx_cmd_a = (u32)length | TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
688 tx_cmd_b = (u32)length;
689 cpu_to_le32s(&tx_cmd_a);
690 cpu_to_le32s(&tx_cmd_b);
691
692 /* prepend cmd_a and cmd_b */
693 memcpy(msg, &tx_cmd_a, sizeof(tx_cmd_a));
694 memcpy(msg + sizeof(tx_cmd_a), &tx_cmd_b, sizeof(tx_cmd_b));
695 memcpy(msg + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), (void *)packet,
696 length);
697 err = usb_bulk_msg(dev->pusb_dev,
698 usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
699 (void *)msg,
700 length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b),
701 &actual_len,
702 USB_BULK_SEND_TIMEOUT);
703 debug("Tx: len = %u, actual = %u, err = %d\n",
704 length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b),
705 actual_len, err);
527298c4 706
291391be
SG
707 return err;
708}
709
0990fcb7 710#ifndef CONFIG_DM_ETH
527298c4
SG
711/*
712 * Smsc95xx callbacks
713 */
714static int smsc95xx_init(struct eth_device *eth, bd_t *bd)
715{
716 struct ueth_data *dev = (struct ueth_data *)eth->priv;
717 struct usb_device *udev = dev->pusb_dev;
718 struct smsc95xx_private *priv =
719 (struct smsc95xx_private *)dev->dev_priv;
720
721 return smsc95xx_init_common(udev, dev, priv, eth->enetaddr);
722}
723
724static int smsc95xx_send(struct eth_device *eth, void *packet, int length)
725{
726 struct ueth_data *dev = (struct ueth_data *)eth->priv;
727
728 return smsc95xx_send_common(dev, packet, length);
729}
730
291391be
SG
731static int smsc95xx_recv(struct eth_device *eth)
732{
733 struct ueth_data *dev = (struct ueth_data *)eth->priv;
d62a1dc6 734 DEFINE_CACHE_ALIGN_BUFFER(unsigned char, recv_buf, RX_URB_SIZE);
291391be
SG
735 unsigned char *buf_ptr;
736 int err;
737 int actual_len;
738 u32 packet_len;
739 int cur_buf_align;
740
741 debug("** %s()\n", __func__);
742 err = usb_bulk_msg(dev->pusb_dev,
527298c4
SG
743 usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
744 (void *)recv_buf, RX_URB_SIZE, &actual_len,
745 USB_BULK_RECV_TIMEOUT);
d62a1dc6 746 debug("Rx: len = %u, actual = %u, err = %d\n", RX_URB_SIZE,
291391be
SG
747 actual_len, err);
748 if (err != 0) {
749 debug("Rx: failed to receive\n");
527298c4 750 return -err;
291391be 751 }
d62a1dc6 752 if (actual_len > RX_URB_SIZE) {
291391be 753 debug("Rx: received too many bytes %d\n", actual_len);
25a9e980 754 return -ENOSPC;
291391be
SG
755 }
756
757 buf_ptr = recv_buf;
758 while (actual_len > 0) {
759 /*
760 * 1st 4 bytes contain the length of the actual data plus error
761 * info. Extract data length.
762 */
763 if (actual_len < sizeof(packet_len)) {
764 debug("Rx: incomplete packet length\n");
25a9e980 765 return -EIO;
291391be
SG
766 }
767 memcpy(&packet_len, buf_ptr, sizeof(packet_len));
768 le32_to_cpus(&packet_len);
769 if (packet_len & RX_STS_ES_) {
770 debug("Rx: Error header=%#x", packet_len);
25a9e980 771 return -EIO;
291391be
SG
772 }
773 packet_len = ((packet_len & RX_STS_FL_) >> 16);
774
775 if (packet_len > actual_len - sizeof(packet_len)) {
776 debug("Rx: too large packet: %d\n", packet_len);
25a9e980 777 return -EIO;
291391be
SG
778 }
779
780 /* Notify net stack */
1fd92db8
JH
781 net_process_received_packet(buf_ptr + sizeof(packet_len),
782 packet_len - 4);
291391be
SG
783
784 /* Adjust for next iteration */
785 actual_len -= sizeof(packet_len) + packet_len;
786 buf_ptr += sizeof(packet_len) + packet_len;
787 cur_buf_align = (int)buf_ptr - (int)recv_buf;
788
789 if (cur_buf_align & 0x03) {
790 int align = 4 - (cur_buf_align & 0x03);
791
792 actual_len -= align;
793 buf_ptr += align;
794 }
795 }
796 return err;
797}
798
799static void smsc95xx_halt(struct eth_device *eth)
800{
801 debug("** %s()\n", __func__);
802}
803
527298c4
SG
804static int smsc95xx_write_hwaddr(struct eth_device *eth)
805{
806 struct ueth_data *dev = eth->priv;
807 struct usb_device *udev = dev->pusb_dev;
808 struct smsc95xx_private *priv = dev->dev_priv;
809
810 return smsc95xx_write_hwaddr_common(udev, priv, eth->enetaddr);
811}
812
291391be
SG
813/*
814 * SMSC probing functions
815 */
816void smsc95xx_eth_before_probe(void)
817{
818 curr_eth_dev = 0;
819}
820
821struct smsc95xx_dongle {
822 unsigned short vendor;
823 unsigned short product;
824};
825
826static const struct smsc95xx_dongle smsc95xx_dongles[] = {
827 { 0x0424, 0xec00 }, /* LAN9512/LAN9514 Ethernet */
828 { 0x0424, 0x9500 }, /* LAN9500 Ethernet */
e7dcecea 829 { 0x0424, 0x9730 }, /* LAN9730 Ethernet (HSIC) */
2eb60902 830 { 0x0424, 0x9900 }, /* SMSC9500 USB Ethernet Device (SAL10) */
08ebd467 831 { 0x0424, 0x9e00 }, /* LAN9500A Ethernet */
291391be
SG
832 { 0x0000, 0x0000 } /* END - Do not remove */
833};
834
835/* Probe to see if a new device is actually an SMSC device */
836int smsc95xx_eth_probe(struct usb_device *dev, unsigned int ifnum,
837 struct ueth_data *ss)
838{
839 struct usb_interface *iface;
840 struct usb_interface_descriptor *iface_desc;
841 int i;
842
843 /* let's examine the device now */
844 iface = &dev->config.if_desc[ifnum];
845 iface_desc = &dev->config.if_desc[ifnum].desc;
846
847 for (i = 0; smsc95xx_dongles[i].vendor != 0; i++) {
848 if (dev->descriptor.idVendor == smsc95xx_dongles[i].vendor &&
849 dev->descriptor.idProduct == smsc95xx_dongles[i].product)
850 /* Found a supported dongle */
851 break;
852 }
853 if (smsc95xx_dongles[i].vendor == 0)
854 return 0;
855
856 /* At this point, we know we've got a live one */
857 debug("\n\nUSB Ethernet device detected\n");
858 memset(ss, '\0', sizeof(struct ueth_data));
859
860 /* Initialize the ueth_data structure with some useful info */
861 ss->ifnum = ifnum;
862 ss->pusb_dev = dev;
863 ss->subclass = iface_desc->bInterfaceSubClass;
864 ss->protocol = iface_desc->bInterfaceProtocol;
865
866 /*
867 * We are expecting a minimum of 3 endpoints - in, out (bulk), and int.
868 * We will ignore any others.
869 */
870 for (i = 0; i < iface_desc->bNumEndpoints; i++) {
871 /* is it an BULK endpoint? */
872 if ((iface->ep_desc[i].bmAttributes &
873 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
874 if (iface->ep_desc[i].bEndpointAddress & USB_DIR_IN)
875 ss->ep_in =
876 iface->ep_desc[i].bEndpointAddress &
877 USB_ENDPOINT_NUMBER_MASK;
878 else
879 ss->ep_out =
880 iface->ep_desc[i].bEndpointAddress &
881 USB_ENDPOINT_NUMBER_MASK;
882 }
883
884 /* is it an interrupt endpoint? */
885 if ((iface->ep_desc[i].bmAttributes &
886 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
887 ss->ep_int = iface->ep_desc[i].bEndpointAddress &
888 USB_ENDPOINT_NUMBER_MASK;
889 ss->irqinterval = iface->ep_desc[i].bInterval;
890 }
891 }
892 debug("Endpoints In %d Out %d Int %d\n",
893 ss->ep_in, ss->ep_out, ss->ep_int);
894
895 /* Do some basic sanity checks, and bail if we find a problem */
896 if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
897 !ss->ep_in || !ss->ep_out || !ss->ep_int) {
898 debug("Problems with device\n");
899 return 0;
900 }
901 dev->privptr = (void *)ss;
e1dbdf91
LS
902
903 /* alloc driver private */
904 ss->dev_priv = calloc(1, sizeof(struct smsc95xx_private));
905 if (!ss->dev_priv)
906 return 0;
907
291391be
SG
908 return 1;
909}
910
911int smsc95xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
912 struct eth_device *eth)
913{
914 debug("** %s()\n", __func__);
915 if (!eth) {
916 debug("%s: missing parameter.\n", __func__);
917 return 0;
918 }
919 sprintf(eth->name, "%s%d", SMSC95XX_BASE_NAME, curr_eth_dev++);
920 eth->init = smsc95xx_init;
921 eth->send = smsc95xx_send;
922 eth->recv = smsc95xx_recv;
923 eth->halt = smsc95xx_halt;
924 eth->write_hwaddr = smsc95xx_write_hwaddr;
925 eth->priv = ss;
926 return 1;
927}
0990fcb7
SG
928#endif /* !CONFIG_DM_ETH */
929
930#ifdef CONFIG_DM_ETH
931static int smsc95xx_eth_start(struct udevice *dev)
932{
933 struct usb_device *udev = dev_get_parentdata(dev);
934 struct smsc95xx_private *priv = dev_get_priv(dev);
935 struct eth_pdata *pdata = dev_get_platdata(dev);
936
937 /* Driver-model Ethernet ensures we have this */
938 priv->have_hwaddr = 1;
939
940 return smsc95xx_init_common(udev, &priv->ueth, priv, pdata->enetaddr);
941}
942
943void smsc95xx_eth_stop(struct udevice *dev)
944{
945 debug("** %s()\n", __func__);
946}
947
948int smsc95xx_eth_send(struct udevice *dev, void *packet, int length)
949{
950 struct smsc95xx_private *priv = dev_get_priv(dev);
951
952 return smsc95xx_send_common(&priv->ueth, packet, length);
953}
954
955int smsc95xx_eth_recv(struct udevice *dev, int flags, uchar **packetp)
956{
957 struct smsc95xx_private *priv = dev_get_priv(dev);
958 struct ueth_data *ueth = &priv->ueth;
959 uint8_t *ptr;
960 int ret, len;
961 u32 packet_len;
962
963 len = usb_ether_get_rx_bytes(ueth, &ptr);
964 debug("%s: first try, len=%d\n", __func__, len);
965 if (!len) {
966 if (!(flags & ETH_RECV_CHECK_DEVICE))
967 return -EAGAIN;
968 ret = usb_ether_receive(ueth, RX_URB_SIZE);
969 if (ret == -EAGAIN)
970 return ret;
971
972 len = usb_ether_get_rx_bytes(ueth, &ptr);
973 debug("%s: second try, len=%d\n", __func__, len);
974 }
975
976 /*
977 * 1st 4 bytes contain the length of the actual data plus error info.
978 * Extract data length.
979 */
980 if (len < sizeof(packet_len)) {
981 debug("Rx: incomplete packet length\n");
982 goto err;
983 }
984 memcpy(&packet_len, ptr, sizeof(packet_len));
985 le32_to_cpus(&packet_len);
986 if (packet_len & RX_STS_ES_) {
987 debug("Rx: Error header=%#x", packet_len);
988 goto err;
989 }
990 packet_len = ((packet_len & RX_STS_FL_) >> 16);
991
992 if (packet_len > len - sizeof(packet_len)) {
993 debug("Rx: too large packet: %d\n", packet_len);
994 goto err;
995 }
996
997 *packetp = ptr + sizeof(packet_len);
998 return packet_len;
999
1000err:
1001 usb_ether_advance_rxbuf(ueth, -1);
1002 return -EINVAL;
1003}
1004
1005static int smsc95xx_free_pkt(struct udevice *dev, uchar *packet, int packet_len)
1006{
1007 struct smsc95xx_private *priv = dev_get_priv(dev);
1008
1009 packet_len = ALIGN(packet_len, 4);
1010 usb_ether_advance_rxbuf(&priv->ueth, sizeof(u32) + packet_len);
1011
1012 return 0;
1013}
1014
1015int smsc95xx_write_hwaddr(struct udevice *dev)
1016{
1017 struct usb_device *udev = dev_get_parentdata(dev);
1018 struct eth_pdata *pdata = dev_get_platdata(dev);
1019 struct smsc95xx_private *priv = dev_get_priv(dev);
1020
1021 return smsc95xx_write_hwaddr_common(udev, priv, pdata->enetaddr);
1022}
1023
1024static int smsc95xx_eth_probe(struct udevice *dev)
1025{
1026 struct smsc95xx_private *priv = dev_get_priv(dev);
1027 struct ueth_data *ueth = &priv->ueth;
1028
1029 return usb_ether_register(dev, ueth, RX_URB_SIZE);
1030}
1031
1032static const struct eth_ops smsc95xx_eth_ops = {
1033 .start = smsc95xx_eth_start,
1034 .send = smsc95xx_eth_send,
1035 .recv = smsc95xx_eth_recv,
1036 .free_pkt = smsc95xx_free_pkt,
1037 .stop = smsc95xx_eth_stop,
1038 .write_hwaddr = smsc95xx_write_hwaddr,
1039};
1040
1041U_BOOT_DRIVER(smsc95xx_eth) = {
1042 .name = "smsc95xx_eth",
1043 .id = UCLASS_ETH,
1044 .probe = smsc95xx_eth_probe,
1045 .ops = &smsc95xx_eth_ops,
1046 .priv_auto_alloc_size = sizeof(struct smsc95xx_private),
1047 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1048};
1049
1050static const struct usb_device_id smsc95xx_eth_id_table[] = {
1051 { USB_DEVICE(0x05ac, 0x1402) },
1052 { USB_DEVICE(0x0424, 0xec00) }, /* LAN9512/LAN9514 Ethernet */
1053 { USB_DEVICE(0x0424, 0x9500) }, /* LAN9500 Ethernet */
1054 { USB_DEVICE(0x0424, 0x9730) }, /* LAN9730 Ethernet (HSIC) */
1055 { USB_DEVICE(0x0424, 0x9900) }, /* SMSC9500 USB Ethernet (SAL10) */
1056 { USB_DEVICE(0x0424, 0x9e00) }, /* LAN9500A Ethernet */
1057 { } /* Terminating entry */
1058};
1059
1060U_BOOT_USB_DEVICE(smsc95xx_eth, smsc95xx_eth_id_table);
1061#endif