[thirdparty/u-boot.git] / drivers / usb / gadget / dwc2_udc_otg_phy.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * drivers/usb/gadget/dwc2_udc_otg.c
 * Designware DWC2 on-chip full/high speed USB OTG 2.0 device controllers
 *
 * Copyright (C) 2008 for Samsung Electronics
 *
 * BSP Support for Samsung's UDC driver
 * available at:
 * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git
 *
 * State machine bugfixes:
 * Marek Szyprowski <m.szyprowski@samsung.com>
 *
 * Ported to u-boot:
 * Marek Szyprowski <m.szyprowski@samsung.com>
 * Lukasz Majewski <l.majewski@samsumg.com>
 */

#include <common.h>
#include <linux/errno.h>
#include <linux/list.h>
#include <malloc.h>

#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>

#include <asm/byteorder.h>
#include <asm/unaligned.h>
#include <asm/io.h>

#include <asm/mach-types.h>

#include "dwc2_udc_otg_regs.h"
#include "dwc2_udc_otg_priv.h"
#include <usb/lin_gadget_compat.h>

#include <usb/dwc2_udc.h>

void otg_phy_init(struct dwc2_udc *dev)
{
	unsigned int usb_phy_ctrl = dev->pdata->usb_phy_ctrl;
	struct dwc2_usbotg_phy *phy =
		(struct dwc2_usbotg_phy *)dev->pdata->regs_phy;

	dev->pdata->phy_control(1);

	/* USB PHY0 Enable */
	printf("USB PHY0 Enable\n");

	/* Enable PHY */
	writel(readl(usb_phy_ctrl) | USB_PHY_CTRL_EN0, usb_phy_ctrl);

	if (dev->pdata->usb_flags == PHY0_SLEEP) /* C210 Universal */
		writel((readl(&phy->phypwr)
			&~(PHY_0_SLEEP | OTG_DISABLE_0 | ANALOG_PWRDOWN)
			&~FORCE_SUSPEND_0), &phy->phypwr);
	else /* C110 GONI */
		writel((readl(&phy->phypwr) &~(OTG_DISABLE_0 | ANALOG_PWRDOWN)
			&~FORCE_SUSPEND_0), &phy->phypwr);

	if (s5p_cpu_id == 0x4412)
		writel((readl(&phy->phyclk) & ~(EXYNOS4X12_ID_PULLUP0 |
			EXYNOS4X12_COMMON_ON_N0)) | EXYNOS4X12_CLK_SEL_24MHZ,
		       &phy->phyclk); /* PLL 24Mhz */
	else
		writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)) |
		       CLK_SEL_24MHZ, &phy->phyclk); /* PLL 24Mhz */

	writel((readl(&phy->rstcon) &~(LINK_SW_RST | PHYLNK_SW_RST))
	       | PHY_SW_RST0, &phy->rstcon);
	udelay(10);
	writel(readl(&phy->rstcon)
	       &~(PHY_SW_RST0 | LINK_SW_RST | PHYLNK_SW_RST), &phy->rstcon);
	udelay(10);
}

void otg_phy_off(struct dwc2_udc *dev)
{
	unsigned int usb_phy_ctrl = dev->pdata->usb_phy_ctrl;
	struct dwc2_usbotg_phy *phy =
		(struct dwc2_usbotg_phy *)dev->pdata->regs_phy;

	/* reset controller just in case */
	writel(PHY_SW_RST0, &phy->rstcon);
	udelay(20);
	writel(readl(&phy->phypwr) &~PHY_SW_RST0, &phy->rstcon);
	udelay(20);

	writel(readl(&phy->phypwr) | OTG_DISABLE_0 | ANALOG_PWRDOWN
	       | FORCE_SUSPEND_0, &phy->phypwr);

	writel(readl(usb_phy_ctrl) &~USB_PHY_CTRL_EN0, usb_phy_ctrl);

	writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)),
	      &phy->phyclk);

	udelay(10000);

	dev->pdata->phy_control(0);
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
d1b6c77e	2	/*
be5e4bdc	3	* drivers/usb/gadget/dwc2_udc_otg.c
e179cedd	4	* Designware DWC2 on-chip full/high speed USB OTG 2.0 device controllers
d1b6c77e MV	5	*
	6	* Copyright (C) 2008 for Samsung Electronics
	7	*
	8	* BSP Support for Samsung's UDC driver
	9	* available at:
	10	* git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git
	11	*
	12	* State machine bugfixes:
	13	* Marek Szyprowski <m.szyprowski@samsung.com>
	14	*
	15	* Ported to u-boot:
	16	* Marek Szyprowski <m.szyprowski@samsung.com>
	17	* Lukasz Majewski <l.majewski@samsumg.com>
d1b6c77e MV	18	*/
	19
	20	#include <common.h>
1221ce45	21	#include <linux/errno.h>
d1b6c77e MV	22	#include <linux/list.h>
	23	#include <malloc.h>
	24
	25	#include <linux/usb/ch9.h>
	26	#include <linux/usb/gadget.h>
	27
	28	#include <asm/byteorder.h>
	29	#include <asm/unaligned.h>
	30	#include <asm/io.h>
	31
	32	#include <asm/mach-types.h>
	33
f4d9bd06 MV	34	#include "dwc2_udc_otg_regs.h"
f4d9bd06 MV	35	#include "dwc2_udc_otg_priv.h"
d1b6c77e MV	36	#include <usb/lin_gadget_compat.h>
d1b6c77e MV	37
5d5716ee	38	#include <usb/dwc2_udc.h>
d1b6c77e	39
b4d5cf0b	40	void otg_phy_init(struct dwc2_udc *dev)
d1b6c77e MV	41	{
d1b6c77e MV	42	unsigned int usb_phy_ctrl = dev->pdata->usb_phy_ctrl;
1f99ab5c MV	43	struct dwc2_usbotg_phy *phy =
1f99ab5c MV	44	(struct dwc2_usbotg_phy *)dev->pdata->regs_phy;
d1b6c77e MV	45
	46	dev->pdata->phy_control(1);
	47
	48	/* USB PHY0 Enable */
	49	printf("USB PHY0 Enable\n");
	50
	51	/* Enable PHY */
	52	writel(readl(usb_phy_ctrl) \| USB_PHY_CTRL_EN0, usb_phy_ctrl);
	53
	54	if (dev->pdata->usb_flags == PHY0_SLEEP) /* C210 Universal */
	55	writel((readl(&phy->phypwr)
	56	&~(PHY_0_SLEEP \| OTG_DISABLE_0 \| ANALOG_PWRDOWN)
	57	&~FORCE_SUSPEND_0), &phy->phypwr);
	58	else /* C110 GONI */
	59	writel((readl(&phy->phypwr) &~(OTG_DISABLE_0 \| ANALOG_PWRDOWN)
	60	&~FORCE_SUSPEND_0), &phy->phypwr);
	61
	62	if (s5p_cpu_id == 0x4412)
	63	writel((readl(&phy->phyclk) & ~(EXYNOS4X12_ID_PULLUP0 \|
	64	EXYNOS4X12_COMMON_ON_N0)) \| EXYNOS4X12_CLK_SEL_24MHZ,
	65	&phy->phyclk); /* PLL 24Mhz */
	66	else
	67	writel((readl(&phy->phyclk) & ~(ID_PULLUP0 \| COMMON_ON_N0)) \|
	68	CLK_SEL_24MHZ, &phy->phyclk); /* PLL 24Mhz */
	69
	70	writel((readl(&phy->rstcon) &~(LINK_SW_RST \| PHYLNK_SW_RST))
	71	\| PHY_SW_RST0, &phy->rstcon);
	72	udelay(10);
	73	writel(readl(&phy->rstcon)
	74	&~(PHY_SW_RST0 \| LINK_SW_RST \| PHYLNK_SW_RST), &phy->rstcon);
	75	udelay(10);
	76	}
	77
b4d5cf0b	78	void otg_phy_off(struct dwc2_udc *dev)
d1b6c77e MV	79	{
d1b6c77e MV	80	unsigned int usb_phy_ctrl = dev->pdata->usb_phy_ctrl;
1f99ab5c MV	81	struct dwc2_usbotg_phy *phy =
1f99ab5c MV	82	(struct dwc2_usbotg_phy *)dev->pdata->regs_phy;
d1b6c77e MV	83
	84	/* reset controller just in case */
	85	writel(PHY_SW_RST0, &phy->rstcon);
	86	udelay(20);
	87	writel(readl(&phy->phypwr) &~PHY_SW_RST0, &phy->rstcon);
	88	udelay(20);
	89
	90	writel(readl(&phy->phypwr) \| OTG_DISABLE_0 \| ANALOG_PWRDOWN
	91	\| FORCE_SUSPEND_0, &phy->phypwr);
	92
	93	writel(readl(usb_phy_ctrl) &~USB_PHY_CTRL_EN0, usb_phy_ctrl);
	94
	95	writel((readl(&phy->phyclk) & ~(ID_PULLUP0 \| COMMON_ON_N0)),
	96	&phy->phyclk);
	97
	98	udelay(10000);
	99
	100	dev->pdata->phy_control(0);
	101	}