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Commit | Line | Data |
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5be19a9d XS |
1 | /* |
2 | * Intel Langwell USB Device Controller driver | |
3 | * Copyright (C) 2008-2009, Intel Corporation. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
17 | * | |
18 | */ | |
19 | ||
20 | ||
21 | /* #undef DEBUG */ | |
5f81f4b0 | 22 | /* #undef VERBOSE_DEBUG */ |
5be19a9d XS |
23 | |
24 | #if defined(CONFIG_USB_LANGWELL_OTG) | |
25 | #define OTG_TRANSCEIVER | |
26 | #endif | |
27 | ||
28 | ||
29 | #include <linux/module.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/dma-mapping.h> | |
32 | #include <linux/kernel.h> | |
33 | #include <linux/delay.h> | |
34 | #include <linux/ioport.h> | |
35 | #include <linux/sched.h> | |
36 | #include <linux/slab.h> | |
5be19a9d XS |
37 | #include <linux/errno.h> |
38 | #include <linux/init.h> | |
39 | #include <linux/timer.h> | |
40 | #include <linux/list.h> | |
41 | #include <linux/interrupt.h> | |
42 | #include <linux/moduleparam.h> | |
43 | #include <linux/device.h> | |
44 | #include <linux/usb/ch9.h> | |
45 | #include <linux/usb/gadget.h> | |
46 | #include <linux/usb/otg.h> | |
47 | #include <linux/pm.h> | |
48 | #include <linux/io.h> | |
49 | #include <linux/irq.h> | |
50 | #include <asm/system.h> | |
51 | #include <asm/unaligned.h> | |
52 | ||
53 | #include "langwell_udc.h" | |
54 | ||
55 | ||
56 | #define DRIVER_DESC "Intel Langwell USB Device Controller driver" | |
57 | #define DRIVER_VERSION "16 May 2009" | |
58 | ||
59 | static const char driver_name[] = "langwell_udc"; | |
60 | static const char driver_desc[] = DRIVER_DESC; | |
61 | ||
62 | ||
63 | /* controller device global variable */ | |
64 | static struct langwell_udc *the_controller; | |
65 | ||
66 | /* for endpoint 0 operations */ | |
67 | static const struct usb_endpoint_descriptor | |
68 | langwell_ep0_desc = { | |
69 | .bLength = USB_DT_ENDPOINT_SIZE, | |
70 | .bDescriptorType = USB_DT_ENDPOINT, | |
71 | .bEndpointAddress = 0, | |
72 | .bmAttributes = USB_ENDPOINT_XFER_CONTROL, | |
73 | .wMaxPacketSize = EP0_MAX_PKT_SIZE, | |
74 | }; | |
75 | ||
76 | ||
77 | /*-------------------------------------------------------------------------*/ | |
78 | /* debugging */ | |
79 | ||
5f81f4b0 | 80 | #ifdef VERBOSE_DEBUG |
5be19a9d XS |
81 | static inline void print_all_registers(struct langwell_udc *dev) |
82 | { | |
83 | int i; | |
84 | ||
85 | /* Capability Registers */ | |
5f81f4b0 J |
86 | dev_dbg(&dev->pdev->dev, |
87 | "Capability Registers (offset: 0x%04x, length: 0x%08x)\n", | |
88 | CAP_REG_OFFSET, (u32)sizeof(struct langwell_cap_regs)); | |
89 | dev_dbg(&dev->pdev->dev, "caplength=0x%02x\n", | |
5be19a9d | 90 | readb(&dev->cap_regs->caplength)); |
5f81f4b0 | 91 | dev_dbg(&dev->pdev->dev, "hciversion=0x%04x\n", |
5be19a9d | 92 | readw(&dev->cap_regs->hciversion)); |
5f81f4b0 | 93 | dev_dbg(&dev->pdev->dev, "hcsparams=0x%08x\n", |
5be19a9d | 94 | readl(&dev->cap_regs->hcsparams)); |
5f81f4b0 | 95 | dev_dbg(&dev->pdev->dev, "hccparams=0x%08x\n", |
5be19a9d | 96 | readl(&dev->cap_regs->hccparams)); |
5f81f4b0 | 97 | dev_dbg(&dev->pdev->dev, "dciversion=0x%04x\n", |
5be19a9d | 98 | readw(&dev->cap_regs->dciversion)); |
5f81f4b0 | 99 | dev_dbg(&dev->pdev->dev, "dccparams=0x%08x\n", |
5be19a9d XS |
100 | readl(&dev->cap_regs->dccparams)); |
101 | ||
102 | /* Operational Registers */ | |
5f81f4b0 J |
103 | dev_dbg(&dev->pdev->dev, |
104 | "Operational Registers (offset: 0x%04x, length: 0x%08x)\n", | |
105 | OP_REG_OFFSET, (u32)sizeof(struct langwell_op_regs)); | |
106 | dev_dbg(&dev->pdev->dev, "extsts=0x%08x\n", | |
5be19a9d | 107 | readl(&dev->op_regs->extsts)); |
5f81f4b0 | 108 | dev_dbg(&dev->pdev->dev, "extintr=0x%08x\n", |
5be19a9d | 109 | readl(&dev->op_regs->extintr)); |
5f81f4b0 | 110 | dev_dbg(&dev->pdev->dev, "usbcmd=0x%08x\n", |
5be19a9d | 111 | readl(&dev->op_regs->usbcmd)); |
5f81f4b0 | 112 | dev_dbg(&dev->pdev->dev, "usbsts=0x%08x\n", |
5be19a9d | 113 | readl(&dev->op_regs->usbsts)); |
5f81f4b0 | 114 | dev_dbg(&dev->pdev->dev, "usbintr=0x%08x\n", |
5be19a9d | 115 | readl(&dev->op_regs->usbintr)); |
5f81f4b0 | 116 | dev_dbg(&dev->pdev->dev, "frindex=0x%08x\n", |
5be19a9d | 117 | readl(&dev->op_regs->frindex)); |
5f81f4b0 | 118 | dev_dbg(&dev->pdev->dev, "ctrldssegment=0x%08x\n", |
5be19a9d | 119 | readl(&dev->op_regs->ctrldssegment)); |
5f81f4b0 | 120 | dev_dbg(&dev->pdev->dev, "deviceaddr=0x%08x\n", |
5be19a9d | 121 | readl(&dev->op_regs->deviceaddr)); |
5f81f4b0 | 122 | dev_dbg(&dev->pdev->dev, "endpointlistaddr=0x%08x\n", |
5be19a9d | 123 | readl(&dev->op_regs->endpointlistaddr)); |
5f81f4b0 | 124 | dev_dbg(&dev->pdev->dev, "ttctrl=0x%08x\n", |
5be19a9d | 125 | readl(&dev->op_regs->ttctrl)); |
5f81f4b0 | 126 | dev_dbg(&dev->pdev->dev, "burstsize=0x%08x\n", |
5be19a9d | 127 | readl(&dev->op_regs->burstsize)); |
5f81f4b0 | 128 | dev_dbg(&dev->pdev->dev, "txfilltuning=0x%08x\n", |
5be19a9d | 129 | readl(&dev->op_regs->txfilltuning)); |
5f81f4b0 | 130 | dev_dbg(&dev->pdev->dev, "txttfilltuning=0x%08x\n", |
5be19a9d | 131 | readl(&dev->op_regs->txttfilltuning)); |
5f81f4b0 | 132 | dev_dbg(&dev->pdev->dev, "ic_usb=0x%08x\n", |
5be19a9d | 133 | readl(&dev->op_regs->ic_usb)); |
5f81f4b0 | 134 | dev_dbg(&dev->pdev->dev, "ulpi_viewport=0x%08x\n", |
5be19a9d | 135 | readl(&dev->op_regs->ulpi_viewport)); |
5f81f4b0 | 136 | dev_dbg(&dev->pdev->dev, "configflag=0x%08x\n", |
5be19a9d | 137 | readl(&dev->op_regs->configflag)); |
5f81f4b0 | 138 | dev_dbg(&dev->pdev->dev, "portsc1=0x%08x\n", |
5be19a9d | 139 | readl(&dev->op_regs->portsc1)); |
5f81f4b0 | 140 | dev_dbg(&dev->pdev->dev, "devlc=0x%08x\n", |
5be19a9d | 141 | readl(&dev->op_regs->devlc)); |
5f81f4b0 | 142 | dev_dbg(&dev->pdev->dev, "otgsc=0x%08x\n", |
5be19a9d | 143 | readl(&dev->op_regs->otgsc)); |
5f81f4b0 | 144 | dev_dbg(&dev->pdev->dev, "usbmode=0x%08x\n", |
5be19a9d | 145 | readl(&dev->op_regs->usbmode)); |
5f81f4b0 | 146 | dev_dbg(&dev->pdev->dev, "endptnak=0x%08x\n", |
5be19a9d | 147 | readl(&dev->op_regs->endptnak)); |
5f81f4b0 | 148 | dev_dbg(&dev->pdev->dev, "endptnaken=0x%08x\n", |
5be19a9d | 149 | readl(&dev->op_regs->endptnaken)); |
5f81f4b0 | 150 | dev_dbg(&dev->pdev->dev, "endptsetupstat=0x%08x\n", |
5be19a9d | 151 | readl(&dev->op_regs->endptsetupstat)); |
5f81f4b0 | 152 | dev_dbg(&dev->pdev->dev, "endptprime=0x%08x\n", |
5be19a9d | 153 | readl(&dev->op_regs->endptprime)); |
5f81f4b0 | 154 | dev_dbg(&dev->pdev->dev, "endptflush=0x%08x\n", |
5be19a9d | 155 | readl(&dev->op_regs->endptflush)); |
5f81f4b0 | 156 | dev_dbg(&dev->pdev->dev, "endptstat=0x%08x\n", |
5be19a9d | 157 | readl(&dev->op_regs->endptstat)); |
5f81f4b0 | 158 | dev_dbg(&dev->pdev->dev, "endptcomplete=0x%08x\n", |
5be19a9d XS |
159 | readl(&dev->op_regs->endptcomplete)); |
160 | ||
161 | for (i = 0; i < dev->ep_max / 2; i++) { | |
5f81f4b0 | 162 | dev_dbg(&dev->pdev->dev, "endptctrl[%d]=0x%08x\n", |
5be19a9d XS |
163 | i, readl(&dev->op_regs->endptctrl[i])); |
164 | } | |
165 | } | |
5f81f4b0 J |
166 | #else |
167 | ||
168 | #define print_all_registers(dev) do { } while (0) | |
169 | ||
170 | #endif /* VERBOSE_DEBUG */ | |
5be19a9d XS |
171 | |
172 | ||
173 | /*-------------------------------------------------------------------------*/ | |
174 | ||
5f81f4b0 J |
175 | #define is_in(ep) (((ep)->ep_num == 0) ? ((ep)->dev->ep0_dir == \ |
176 | USB_DIR_IN) : (usb_endpoint_dir_in((ep)->desc))) | |
5be19a9d | 177 | |
5f81f4b0 | 178 | #define DIR_STRING(ep) (is_in(ep) ? "in" : "out") |
5be19a9d XS |
179 | |
180 | ||
5f81f4b0 | 181 | static char *type_string(const struct usb_endpoint_descriptor *desc) |
5be19a9d | 182 | { |
5f81f4b0 | 183 | switch (usb_endpoint_type(desc)) { |
5be19a9d XS |
184 | case USB_ENDPOINT_XFER_BULK: |
185 | return "bulk"; | |
186 | case USB_ENDPOINT_XFER_ISOC: | |
187 | return "iso"; | |
188 | case USB_ENDPOINT_XFER_INT: | |
189 | return "int"; | |
190 | }; | |
191 | ||
192 | return "control"; | |
193 | } | |
5be19a9d XS |
194 | |
195 | ||
196 | /* configure endpoint control registers */ | |
197 | static void ep_reset(struct langwell_ep *ep, unsigned char ep_num, | |
198 | unsigned char is_in, unsigned char ep_type) | |
199 | { | |
200 | struct langwell_udc *dev; | |
201 | u32 endptctrl; | |
202 | ||
203 | dev = ep->dev; | |
5f81f4b0 | 204 | dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
205 | |
206 | endptctrl = readl(&dev->op_regs->endptctrl[ep_num]); | |
207 | if (is_in) { /* TX */ | |
208 | if (ep_num) | |
209 | endptctrl |= EPCTRL_TXR; | |
210 | endptctrl |= EPCTRL_TXE; | |
211 | endptctrl |= ep_type << EPCTRL_TXT_SHIFT; | |
212 | } else { /* RX */ | |
213 | if (ep_num) | |
214 | endptctrl |= EPCTRL_RXR; | |
215 | endptctrl |= EPCTRL_RXE; | |
216 | endptctrl |= ep_type << EPCTRL_RXT_SHIFT; | |
217 | } | |
218 | ||
219 | writel(endptctrl, &dev->op_regs->endptctrl[ep_num]); | |
220 | ||
5f81f4b0 | 221 | dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__); |
5be19a9d XS |
222 | } |
223 | ||
224 | ||
225 | /* reset ep0 dQH and endptctrl */ | |
226 | static void ep0_reset(struct langwell_udc *dev) | |
227 | { | |
228 | struct langwell_ep *ep; | |
229 | int i; | |
230 | ||
5f81f4b0 | 231 | dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
232 | |
233 | /* ep0 in and out */ | |
234 | for (i = 0; i < 2; i++) { | |
235 | ep = &dev->ep[i]; | |
236 | ep->dev = dev; | |
237 | ||
238 | /* ep0 dQH */ | |
239 | ep->dqh = &dev->ep_dqh[i]; | |
240 | ||
241 | /* configure ep0 endpoint capabilities in dQH */ | |
242 | ep->dqh->dqh_ios = 1; | |
243 | ep->dqh->dqh_mpl = EP0_MAX_PKT_SIZE; | |
244 | ||
3eed298f | 245 | /* enable ep0-in HW zero length termination select */ |
5be19a9d XS |
246 | if (is_in(ep)) |
247 | ep->dqh->dqh_zlt = 0; | |
248 | ep->dqh->dqh_mult = 0; | |
249 | ||
3eed298f J |
250 | ep->dqh->dtd_next = DTD_TERM; |
251 | ||
5be19a9d XS |
252 | /* configure ep0 control registers */ |
253 | ep_reset(&dev->ep[0], 0, i, USB_ENDPOINT_XFER_CONTROL); | |
254 | } | |
255 | ||
5f81f4b0 | 256 | dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__); |
5be19a9d XS |
257 | } |
258 | ||
259 | ||
260 | /*-------------------------------------------------------------------------*/ | |
261 | ||
262 | /* endpoints operations */ | |
263 | ||
264 | /* configure endpoint, making it usable */ | |
265 | static int langwell_ep_enable(struct usb_ep *_ep, | |
266 | const struct usb_endpoint_descriptor *desc) | |
267 | { | |
268 | struct langwell_udc *dev; | |
269 | struct langwell_ep *ep; | |
270 | u16 max = 0; | |
271 | unsigned long flags; | |
3eed298f | 272 | int i, retval = 0; |
5be19a9d XS |
273 | unsigned char zlt, ios = 0, mult = 0; |
274 | ||
275 | ep = container_of(_ep, struct langwell_ep, ep); | |
276 | dev = ep->dev; | |
5f81f4b0 | 277 | dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
278 | |
279 | if (!_ep || !desc || ep->desc | |
280 | || desc->bDescriptorType != USB_DT_ENDPOINT) | |
281 | return -EINVAL; | |
282 | ||
283 | if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) | |
284 | return -ESHUTDOWN; | |
285 | ||
286 | max = le16_to_cpu(desc->wMaxPacketSize); | |
287 | ||
288 | /* | |
289 | * disable HW zero length termination select | |
290 | * driver handles zero length packet through req->req.zero | |
291 | */ | |
292 | zlt = 1; | |
293 | ||
294 | /* | |
295 | * sanity check type, direction, address, and then | |
296 | * initialize the endpoint capabilities fields in dQH | |
297 | */ | |
5f81f4b0 | 298 | switch (usb_endpoint_type(desc)) { |
5be19a9d XS |
299 | case USB_ENDPOINT_XFER_CONTROL: |
300 | ios = 1; | |
301 | break; | |
302 | case USB_ENDPOINT_XFER_BULK: | |
303 | if ((dev->gadget.speed == USB_SPEED_HIGH | |
304 | && max != 512) | |
305 | || (dev->gadget.speed == USB_SPEED_FULL | |
306 | && max > 64)) { | |
307 | goto done; | |
308 | } | |
309 | break; | |
310 | case USB_ENDPOINT_XFER_INT: | |
311 | if (strstr(ep->ep.name, "-iso")) /* bulk is ok */ | |
312 | goto done; | |
313 | ||
314 | switch (dev->gadget.speed) { | |
315 | case USB_SPEED_HIGH: | |
316 | if (max <= 1024) | |
317 | break; | |
318 | case USB_SPEED_FULL: | |
319 | if (max <= 64) | |
320 | break; | |
321 | default: | |
322 | if (max <= 8) | |
323 | break; | |
324 | goto done; | |
325 | } | |
326 | break; | |
327 | case USB_ENDPOINT_XFER_ISOC: | |
328 | if (strstr(ep->ep.name, "-bulk") | |
329 | || strstr(ep->ep.name, "-int")) | |
330 | goto done; | |
331 | ||
332 | switch (dev->gadget.speed) { | |
333 | case USB_SPEED_HIGH: | |
334 | if (max <= 1024) | |
335 | break; | |
336 | case USB_SPEED_FULL: | |
337 | if (max <= 1023) | |
338 | break; | |
339 | default: | |
340 | goto done; | |
341 | } | |
342 | /* | |
343 | * FIXME: | |
344 | * calculate transactions needed for high bandwidth iso | |
345 | */ | |
346 | mult = (unsigned char)(1 + ((max >> 11) & 0x03)); | |
347 | max = max & 0x8ff; /* bit 0~10 */ | |
348 | /* 3 transactions at most */ | |
349 | if (mult > 3) | |
350 | goto done; | |
351 | break; | |
352 | default: | |
353 | goto done; | |
354 | } | |
355 | ||
356 | spin_lock_irqsave(&dev->lock, flags); | |
357 | ||
5be19a9d XS |
358 | ep->ep.maxpacket = max; |
359 | ep->desc = desc; | |
360 | ep->stopped = 0; | |
5f81f4b0 | 361 | ep->ep_num = usb_endpoint_num(desc); |
5be19a9d XS |
362 | |
363 | /* ep_type */ | |
5f81f4b0 | 364 | ep->ep_type = usb_endpoint_type(desc); |
5be19a9d XS |
365 | |
366 | /* configure endpoint control registers */ | |
367 | ep_reset(ep, ep->ep_num, is_in(ep), ep->ep_type); | |
368 | ||
3eed298f J |
369 | /* configure endpoint capabilities in dQH */ |
370 | i = ep->ep_num * 2 + is_in(ep); | |
371 | ep->dqh = &dev->ep_dqh[i]; | |
372 | ep->dqh->dqh_ios = ios; | |
373 | ep->dqh->dqh_mpl = cpu_to_le16(max); | |
374 | ep->dqh->dqh_zlt = zlt; | |
375 | ep->dqh->dqh_mult = mult; | |
376 | ep->dqh->dtd_next = DTD_TERM; | |
377 | ||
5f81f4b0 | 378 | dev_dbg(&dev->pdev->dev, "enabled %s (ep%d%s-%s), max %04x\n", |
5be19a9d XS |
379 | _ep->name, |
380 | ep->ep_num, | |
5f81f4b0 J |
381 | DIR_STRING(ep), |
382 | type_string(desc), | |
5be19a9d XS |
383 | max); |
384 | ||
385 | spin_unlock_irqrestore(&dev->lock, flags); | |
386 | done: | |
5f81f4b0 | 387 | dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__); |
5be19a9d XS |
388 | return retval; |
389 | } | |
390 | ||
391 | ||
392 | /*-------------------------------------------------------------------------*/ | |
393 | ||
394 | /* retire a request */ | |
395 | static void done(struct langwell_ep *ep, struct langwell_request *req, | |
396 | int status) | |
397 | { | |
398 | struct langwell_udc *dev = ep->dev; | |
399 | unsigned stopped = ep->stopped; | |
400 | struct langwell_dtd *curr_dtd, *next_dtd; | |
401 | int i; | |
402 | ||
5f81f4b0 | 403 | dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
404 | |
405 | /* remove the req from ep->queue */ | |
406 | list_del_init(&req->queue); | |
407 | ||
408 | if (req->req.status == -EINPROGRESS) | |
409 | req->req.status = status; | |
410 | else | |
411 | status = req->req.status; | |
412 | ||
413 | /* free dTD for the request */ | |
414 | next_dtd = req->head; | |
415 | for (i = 0; i < req->dtd_count; i++) { | |
416 | curr_dtd = next_dtd; | |
417 | if (i != req->dtd_count - 1) | |
418 | next_dtd = curr_dtd->next_dtd_virt; | |
419 | dma_pool_free(dev->dtd_pool, curr_dtd, curr_dtd->dtd_dma); | |
420 | } | |
421 | ||
422 | if (req->mapped) { | |
5f81f4b0 J |
423 | dma_unmap_single(&dev->pdev->dev, |
424 | req->req.dma, req->req.length, | |
5be19a9d XS |
425 | is_in(ep) ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE); |
426 | req->req.dma = DMA_ADDR_INVALID; | |
427 | req->mapped = 0; | |
428 | } else | |
429 | dma_sync_single_for_cpu(&dev->pdev->dev, req->req.dma, | |
430 | req->req.length, | |
431 | is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE); | |
432 | ||
433 | if (status != -ESHUTDOWN) | |
5f81f4b0 J |
434 | dev_dbg(&dev->pdev->dev, |
435 | "complete %s, req %p, stat %d, len %u/%u\n", | |
436 | ep->ep.name, &req->req, status, | |
437 | req->req.actual, req->req.length); | |
5be19a9d XS |
438 | |
439 | /* don't modify queue heads during completion callback */ | |
440 | ep->stopped = 1; | |
441 | ||
442 | spin_unlock(&dev->lock); | |
443 | /* complete routine from gadget driver */ | |
444 | if (req->req.complete) | |
445 | req->req.complete(&ep->ep, &req->req); | |
446 | ||
447 | spin_lock(&dev->lock); | |
448 | ep->stopped = stopped; | |
449 | ||
5f81f4b0 | 450 | dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__); |
5be19a9d XS |
451 | } |
452 | ||
453 | ||
454 | static void langwell_ep_fifo_flush(struct usb_ep *_ep); | |
455 | ||
456 | /* delete all endpoint requests, called with spinlock held */ | |
457 | static void nuke(struct langwell_ep *ep, int status) | |
458 | { | |
459 | /* called with spinlock held */ | |
460 | ep->stopped = 1; | |
461 | ||
462 | /* endpoint fifo flush */ | |
463 | if (&ep->ep && ep->desc) | |
464 | langwell_ep_fifo_flush(&ep->ep); | |
465 | ||
466 | while (!list_empty(&ep->queue)) { | |
467 | struct langwell_request *req = NULL; | |
468 | req = list_entry(ep->queue.next, struct langwell_request, | |
469 | queue); | |
470 | done(ep, req, status); | |
471 | } | |
472 | } | |
473 | ||
474 | ||
475 | /*-------------------------------------------------------------------------*/ | |
476 | ||
477 | /* endpoint is no longer usable */ | |
478 | static int langwell_ep_disable(struct usb_ep *_ep) | |
479 | { | |
480 | struct langwell_ep *ep; | |
481 | unsigned long flags; | |
482 | struct langwell_udc *dev; | |
483 | int ep_num; | |
484 | u32 endptctrl; | |
485 | ||
486 | ep = container_of(_ep, struct langwell_ep, ep); | |
487 | dev = ep->dev; | |
5f81f4b0 | 488 | dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
489 | |
490 | if (!_ep || !ep->desc) | |
491 | return -EINVAL; | |
492 | ||
493 | spin_lock_irqsave(&dev->lock, flags); | |
494 | ||
495 | /* disable endpoint control register */ | |
496 | ep_num = ep->ep_num; | |
497 | endptctrl = readl(&dev->op_regs->endptctrl[ep_num]); | |
498 | if (is_in(ep)) | |
499 | endptctrl &= ~EPCTRL_TXE; | |
500 | else | |
501 | endptctrl &= ~EPCTRL_RXE; | |
502 | writel(endptctrl, &dev->op_regs->endptctrl[ep_num]); | |
503 | ||
504 | /* nuke all pending requests (does flush) */ | |
505 | nuke(ep, -ESHUTDOWN); | |
506 | ||
507 | ep->desc = NULL; | |
508 | ep->stopped = 1; | |
509 | ||
510 | spin_unlock_irqrestore(&dev->lock, flags); | |
511 | ||
5f81f4b0 J |
512 | dev_dbg(&dev->pdev->dev, "disabled %s\n", _ep->name); |
513 | dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__); | |
5be19a9d XS |
514 | |
515 | return 0; | |
516 | } | |
517 | ||
518 | ||
519 | /* allocate a request object to use with this endpoint */ | |
520 | static struct usb_request *langwell_alloc_request(struct usb_ep *_ep, | |
521 | gfp_t gfp_flags) | |
522 | { | |
523 | struct langwell_ep *ep; | |
524 | struct langwell_udc *dev; | |
525 | struct langwell_request *req = NULL; | |
526 | ||
527 | if (!_ep) | |
528 | return NULL; | |
529 | ||
530 | ep = container_of(_ep, struct langwell_ep, ep); | |
531 | dev = ep->dev; | |
5f81f4b0 | 532 | dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
533 | |
534 | req = kzalloc(sizeof(*req), gfp_flags); | |
535 | if (!req) | |
536 | return NULL; | |
537 | ||
538 | req->req.dma = DMA_ADDR_INVALID; | |
539 | INIT_LIST_HEAD(&req->queue); | |
540 | ||
5f81f4b0 J |
541 | dev_vdbg(&dev->pdev->dev, "alloc request for %s\n", _ep->name); |
542 | dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__); | |
5be19a9d XS |
543 | return &req->req; |
544 | } | |
545 | ||
546 | ||
547 | /* free a request object */ | |
548 | static void langwell_free_request(struct usb_ep *_ep, | |
549 | struct usb_request *_req) | |
550 | { | |
551 | struct langwell_ep *ep; | |
552 | struct langwell_udc *dev; | |
553 | struct langwell_request *req = NULL; | |
554 | ||
555 | ep = container_of(_ep, struct langwell_ep, ep); | |
556 | dev = ep->dev; | |
5f81f4b0 | 557 | dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
558 | |
559 | if (!_ep || !_req) | |
560 | return; | |
561 | ||
562 | req = container_of(_req, struct langwell_request, req); | |
563 | WARN_ON(!list_empty(&req->queue)); | |
564 | ||
565 | if (_req) | |
566 | kfree(req); | |
567 | ||
5f81f4b0 J |
568 | dev_vdbg(&dev->pdev->dev, "free request for %s\n", _ep->name); |
569 | dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__); | |
5be19a9d XS |
570 | } |
571 | ||
572 | ||
573 | /*-------------------------------------------------------------------------*/ | |
574 | ||
575 | /* queue dTD and PRIME endpoint */ | |
576 | static int queue_dtd(struct langwell_ep *ep, struct langwell_request *req) | |
577 | { | |
578 | u32 bit_mask, usbcmd, endptstat, dtd_dma; | |
579 | u8 dtd_status; | |
580 | int i; | |
581 | struct langwell_dqh *dqh; | |
582 | struct langwell_udc *dev; | |
583 | ||
584 | dev = ep->dev; | |
5f81f4b0 | 585 | dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
586 | |
587 | i = ep->ep_num * 2 + is_in(ep); | |
588 | dqh = &dev->ep_dqh[i]; | |
589 | ||
590 | if (ep->ep_num) | |
5f81f4b0 | 591 | dev_vdbg(&dev->pdev->dev, "%s\n", ep->name); |
5be19a9d XS |
592 | else |
593 | /* ep0 */ | |
5f81f4b0 | 594 | dev_vdbg(&dev->pdev->dev, "%s-%s\n", ep->name, DIR_STRING(ep)); |
5be19a9d | 595 | |
5f81f4b0 J |
596 | dev_vdbg(&dev->pdev->dev, "ep_dqh[%d] addr: 0x%08x\n", |
597 | i, (u32)&(dev->ep_dqh[i])); | |
5be19a9d XS |
598 | |
599 | bit_mask = is_in(ep) ? | |
600 | (1 << (ep->ep_num + 16)) : (1 << (ep->ep_num)); | |
601 | ||
5f81f4b0 | 602 | dev_vdbg(&dev->pdev->dev, "bit_mask = 0x%08x\n", bit_mask); |
5be19a9d XS |
603 | |
604 | /* check if the pipe is empty */ | |
605 | if (!(list_empty(&ep->queue))) { | |
606 | /* add dTD to the end of linked list */ | |
607 | struct langwell_request *lastreq; | |
608 | lastreq = list_entry(ep->queue.prev, | |
609 | struct langwell_request, queue); | |
610 | ||
611 | lastreq->tail->dtd_next = | |
612 | cpu_to_le32(req->head->dtd_dma & DTD_NEXT_MASK); | |
613 | ||
614 | /* read prime bit, if 1 goto out */ | |
615 | if (readl(&dev->op_regs->endptprime) & bit_mask) | |
616 | goto out; | |
617 | ||
618 | do { | |
619 | /* set ATDTW bit in USBCMD */ | |
620 | usbcmd = readl(&dev->op_regs->usbcmd); | |
621 | writel(usbcmd | CMD_ATDTW, &dev->op_regs->usbcmd); | |
622 | ||
623 | /* read correct status bit */ | |
624 | endptstat = readl(&dev->op_regs->endptstat) & bit_mask; | |
625 | ||
626 | } while (!(readl(&dev->op_regs->usbcmd) & CMD_ATDTW)); | |
627 | ||
628 | /* write ATDTW bit to 0 */ | |
629 | usbcmd = readl(&dev->op_regs->usbcmd); | |
630 | writel(usbcmd & ~CMD_ATDTW, &dev->op_regs->usbcmd); | |
631 | ||
632 | if (endptstat) | |
633 | goto out; | |
634 | } | |
635 | ||
636 | /* write dQH next pointer and terminate bit to 0 */ | |
637 | dtd_dma = req->head->dtd_dma & DTD_NEXT_MASK; | |
638 | dqh->dtd_next = cpu_to_le32(dtd_dma); | |
639 | ||
640 | /* clear active and halt bit */ | |
641 | dtd_status = (u8) ~(DTD_STS_ACTIVE | DTD_STS_HALTED); | |
642 | dqh->dtd_status &= dtd_status; | |
5f81f4b0 J |
643 | dev_vdbg(&dev->pdev->dev, "dqh->dtd_status = 0x%x\n", dqh->dtd_status); |
644 | ||
25985edc | 645 | /* ensure that updates to the dQH will occur before priming */ |
5f81f4b0 | 646 | wmb(); |
5be19a9d XS |
647 | |
648 | /* write 1 to endptprime register to PRIME endpoint */ | |
649 | bit_mask = is_in(ep) ? (1 << (ep->ep_num + 16)) : (1 << ep->ep_num); | |
5f81f4b0 | 650 | dev_vdbg(&dev->pdev->dev, "endprime bit_mask = 0x%08x\n", bit_mask); |
5be19a9d XS |
651 | writel(bit_mask, &dev->op_regs->endptprime); |
652 | out: | |
5f81f4b0 | 653 | dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__); |
5be19a9d XS |
654 | return 0; |
655 | } | |
656 | ||
657 | ||
658 | /* fill in the dTD structure to build a transfer descriptor */ | |
659 | static struct langwell_dtd *build_dtd(struct langwell_request *req, | |
660 | unsigned *length, dma_addr_t *dma, int *is_last) | |
661 | { | |
662 | u32 buf_ptr; | |
663 | struct langwell_dtd *dtd; | |
664 | struct langwell_udc *dev; | |
665 | int i; | |
666 | ||
667 | dev = req->ep->dev; | |
5f81f4b0 | 668 | dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
669 | |
670 | /* the maximum transfer length, up to 16k bytes */ | |
671 | *length = min(req->req.length - req->req.actual, | |
672 | (unsigned)DTD_MAX_TRANSFER_LENGTH); | |
673 | ||
674 | /* create dTD dma_pool resource */ | |
675 | dtd = dma_pool_alloc(dev->dtd_pool, GFP_KERNEL, dma); | |
676 | if (dtd == NULL) | |
677 | return dtd; | |
678 | dtd->dtd_dma = *dma; | |
679 | ||
680 | /* initialize buffer page pointers */ | |
681 | buf_ptr = (u32)(req->req.dma + req->req.actual); | |
682 | for (i = 0; i < 5; i++) | |
683 | dtd->dtd_buf[i] = cpu_to_le32(buf_ptr + i * PAGE_SIZE); | |
684 | ||
685 | req->req.actual += *length; | |
686 | ||
687 | /* fill in total bytes with transfer size */ | |
688 | dtd->dtd_total = cpu_to_le16(*length); | |
5f81f4b0 | 689 | dev_vdbg(&dev->pdev->dev, "dtd->dtd_total = %d\n", dtd->dtd_total); |
5be19a9d XS |
690 | |
691 | /* set is_last flag if req->req.zero is set or not */ | |
692 | if (req->req.zero) { | |
693 | if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0) | |
694 | *is_last = 1; | |
695 | else | |
696 | *is_last = 0; | |
697 | } else if (req->req.length == req->req.actual) { | |
698 | *is_last = 1; | |
699 | } else | |
700 | *is_last = 0; | |
701 | ||
702 | if (*is_last == 0) | |
5f81f4b0 | 703 | dev_vdbg(&dev->pdev->dev, "multi-dtd request!\n"); |
5be19a9d XS |
704 | |
705 | /* set interrupt on complete bit for the last dTD */ | |
706 | if (*is_last && !req->req.no_interrupt) | |
707 | dtd->dtd_ioc = 1; | |
708 | ||
709 | /* set multiplier override 0 for non-ISO and non-TX endpoint */ | |
710 | dtd->dtd_multo = 0; | |
711 | ||
712 | /* set the active bit of status field to 1 */ | |
713 | dtd->dtd_status = DTD_STS_ACTIVE; | |
5f81f4b0 J |
714 | dev_vdbg(&dev->pdev->dev, "dtd->dtd_status = 0x%02x\n", |
715 | dtd->dtd_status); | |
5be19a9d | 716 | |
5f81f4b0 J |
717 | dev_vdbg(&dev->pdev->dev, "length = %d, dma addr= 0x%08x\n", |
718 | *length, (int)*dma); | |
719 | dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__); | |
5be19a9d XS |
720 | return dtd; |
721 | } | |
722 | ||
723 | ||
724 | /* generate dTD linked list for a request */ | |
725 | static int req_to_dtd(struct langwell_request *req) | |
726 | { | |
727 | unsigned count; | |
728 | int is_last, is_first = 1; | |
729 | struct langwell_dtd *dtd, *last_dtd = NULL; | |
730 | struct langwell_udc *dev; | |
731 | dma_addr_t dma; | |
732 | ||
733 | dev = req->ep->dev; | |
5f81f4b0 | 734 | dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
735 | do { |
736 | dtd = build_dtd(req, &count, &dma, &is_last); | |
737 | if (dtd == NULL) | |
738 | return -ENOMEM; | |
739 | ||
740 | if (is_first) { | |
741 | is_first = 0; | |
742 | req->head = dtd; | |
743 | } else { | |
744 | last_dtd->dtd_next = cpu_to_le32(dma); | |
745 | last_dtd->next_dtd_virt = dtd; | |
746 | } | |
747 | last_dtd = dtd; | |
748 | req->dtd_count++; | |
749 | } while (!is_last); | |
750 | ||
751 | /* set terminate bit to 1 for the last dTD */ | |
752 | dtd->dtd_next = DTD_TERM; | |
753 | ||
754 | req->tail = dtd; | |
755 | ||
5f81f4b0 | 756 | dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__); |
5be19a9d XS |
757 | return 0; |
758 | } | |
759 | ||
760 | /*-------------------------------------------------------------------------*/ | |
761 | ||
762 | /* queue (submits) an I/O requests to an endpoint */ | |
763 | static int langwell_ep_queue(struct usb_ep *_ep, struct usb_request *_req, | |
764 | gfp_t gfp_flags) | |
765 | { | |
766 | struct langwell_request *req; | |
767 | struct langwell_ep *ep; | |
768 | struct langwell_udc *dev; | |
769 | unsigned long flags; | |
770 | int is_iso = 0, zlflag = 0; | |
771 | ||
772 | /* always require a cpu-view buffer */ | |
773 | req = container_of(_req, struct langwell_request, req); | |
774 | ep = container_of(_ep, struct langwell_ep, ep); | |
775 | ||
776 | if (!_req || !_req->complete || !_req->buf | |
777 | || !list_empty(&req->queue)) { | |
778 | return -EINVAL; | |
779 | } | |
780 | ||
781 | if (unlikely(!_ep || !ep->desc)) | |
782 | return -EINVAL; | |
783 | ||
784 | dev = ep->dev; | |
785 | req->ep = ep; | |
5f81f4b0 | 786 | dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d | 787 | |
5f81f4b0 | 788 | if (usb_endpoint_xfer_isoc(ep->desc)) { |
5be19a9d XS |
789 | if (req->req.length > ep->ep.maxpacket) |
790 | return -EMSGSIZE; | |
791 | is_iso = 1; | |
792 | } | |
793 | ||
794 | if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) | |
795 | return -ESHUTDOWN; | |
796 | ||
797 | /* set up dma mapping in case the caller didn't */ | |
798 | if (_req->dma == DMA_ADDR_INVALID) { | |
799 | /* WORKAROUND: WARN_ON(size == 0) */ | |
800 | if (_req->length == 0) { | |
5f81f4b0 | 801 | dev_vdbg(&dev->pdev->dev, "req->length: 0->1\n"); |
5be19a9d XS |
802 | zlflag = 1; |
803 | _req->length++; | |
804 | } | |
805 | ||
806 | _req->dma = dma_map_single(&dev->pdev->dev, | |
807 | _req->buf, _req->length, | |
808 | is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE); | |
809 | if (zlflag && (_req->length == 1)) { | |
5f81f4b0 | 810 | dev_vdbg(&dev->pdev->dev, "req->length: 1->0\n"); |
5be19a9d XS |
811 | zlflag = 0; |
812 | _req->length = 0; | |
813 | } | |
814 | ||
815 | req->mapped = 1; | |
5f81f4b0 | 816 | dev_vdbg(&dev->pdev->dev, "req->mapped = 1\n"); |
5be19a9d XS |
817 | } else { |
818 | dma_sync_single_for_device(&dev->pdev->dev, | |
819 | _req->dma, _req->length, | |
820 | is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE); | |
821 | req->mapped = 0; | |
5f81f4b0 | 822 | dev_vdbg(&dev->pdev->dev, "req->mapped = 0\n"); |
5be19a9d XS |
823 | } |
824 | ||
5f81f4b0 J |
825 | dev_dbg(&dev->pdev->dev, |
826 | "%s queue req %p, len %u, buf %p, dma 0x%08x\n", | |
827 | _ep->name, | |
828 | _req, _req->length, _req->buf, (int)_req->dma); | |
5be19a9d XS |
829 | |
830 | _req->status = -EINPROGRESS; | |
831 | _req->actual = 0; | |
832 | req->dtd_count = 0; | |
833 | ||
834 | spin_lock_irqsave(&dev->lock, flags); | |
835 | ||
836 | /* build and put dTDs to endpoint queue */ | |
837 | if (!req_to_dtd(req)) { | |
838 | queue_dtd(ep, req); | |
839 | } else { | |
840 | spin_unlock_irqrestore(&dev->lock, flags); | |
841 | return -ENOMEM; | |
842 | } | |
843 | ||
844 | /* update ep0 state */ | |
845 | if (ep->ep_num == 0) | |
846 | dev->ep0_state = DATA_STATE_XMIT; | |
847 | ||
848 | if (likely(req != NULL)) { | |
849 | list_add_tail(&req->queue, &ep->queue); | |
5f81f4b0 | 850 | dev_vdbg(&dev->pdev->dev, "list_add_tail()\n"); |
5be19a9d XS |
851 | } |
852 | ||
853 | spin_unlock_irqrestore(&dev->lock, flags); | |
854 | ||
5f81f4b0 | 855 | dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__); |
5be19a9d XS |
856 | return 0; |
857 | } | |
858 | ||
859 | ||
860 | /* dequeue (cancels, unlinks) an I/O request from an endpoint */ | |
861 | static int langwell_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) | |
862 | { | |
863 | struct langwell_ep *ep; | |
864 | struct langwell_udc *dev; | |
865 | struct langwell_request *req; | |
866 | unsigned long flags; | |
867 | int stopped, ep_num, retval = 0; | |
868 | u32 endptctrl; | |
869 | ||
870 | ep = container_of(_ep, struct langwell_ep, ep); | |
871 | dev = ep->dev; | |
5f81f4b0 | 872 | dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
873 | |
874 | if (!_ep || !ep->desc || !_req) | |
875 | return -EINVAL; | |
876 | ||
877 | if (!dev->driver) | |
878 | return -ESHUTDOWN; | |
879 | ||
880 | spin_lock_irqsave(&dev->lock, flags); | |
881 | stopped = ep->stopped; | |
882 | ||
883 | /* quiesce dma while we patch the queue */ | |
884 | ep->stopped = 1; | |
885 | ep_num = ep->ep_num; | |
886 | ||
887 | /* disable endpoint control register */ | |
888 | endptctrl = readl(&dev->op_regs->endptctrl[ep_num]); | |
889 | if (is_in(ep)) | |
890 | endptctrl &= ~EPCTRL_TXE; | |
891 | else | |
892 | endptctrl &= ~EPCTRL_RXE; | |
893 | writel(endptctrl, &dev->op_regs->endptctrl[ep_num]); | |
894 | ||
895 | /* make sure it's still queued on this endpoint */ | |
896 | list_for_each_entry(req, &ep->queue, queue) { | |
897 | if (&req->req == _req) | |
898 | break; | |
899 | } | |
900 | ||
901 | if (&req->req != _req) { | |
902 | retval = -EINVAL; | |
903 | goto done; | |
904 | } | |
905 | ||
906 | /* queue head may be partially complete. */ | |
907 | if (ep->queue.next == &req->queue) { | |
5f81f4b0 | 908 | dev_dbg(&dev->pdev->dev, "unlink (%s) dma\n", _ep->name); |
5be19a9d XS |
909 | _req->status = -ECONNRESET; |
910 | langwell_ep_fifo_flush(&ep->ep); | |
911 | ||
912 | /* not the last request in endpoint queue */ | |
913 | if (likely(ep->queue.next == &req->queue)) { | |
914 | struct langwell_dqh *dqh; | |
915 | struct langwell_request *next_req; | |
916 | ||
917 | dqh = ep->dqh; | |
918 | next_req = list_entry(req->queue.next, | |
919 | struct langwell_request, queue); | |
920 | ||
921 | /* point the dQH to the first dTD of next request */ | |
922 | writel((u32) next_req->head, &dqh->dqh_current); | |
923 | } | |
924 | } else { | |
925 | struct langwell_request *prev_req; | |
926 | ||
927 | prev_req = list_entry(req->queue.prev, | |
928 | struct langwell_request, queue); | |
929 | writel(readl(&req->tail->dtd_next), | |
930 | &prev_req->tail->dtd_next); | |
931 | } | |
932 | ||
933 | done(ep, req, -ECONNRESET); | |
934 | ||
935 | done: | |
936 | /* enable endpoint again */ | |
937 | endptctrl = readl(&dev->op_regs->endptctrl[ep_num]); | |
938 | if (is_in(ep)) | |
939 | endptctrl |= EPCTRL_TXE; | |
940 | else | |
941 | endptctrl |= EPCTRL_RXE; | |
942 | writel(endptctrl, &dev->op_regs->endptctrl[ep_num]); | |
943 | ||
944 | ep->stopped = stopped; | |
945 | spin_unlock_irqrestore(&dev->lock, flags); | |
946 | ||
5f81f4b0 | 947 | dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__); |
5be19a9d XS |
948 | return retval; |
949 | } | |
950 | ||
951 | ||
952 | /*-------------------------------------------------------------------------*/ | |
953 | ||
954 | /* endpoint set/clear halt */ | |
955 | static void ep_set_halt(struct langwell_ep *ep, int value) | |
956 | { | |
957 | u32 endptctrl = 0; | |
958 | int ep_num; | |
959 | struct langwell_udc *dev = ep->dev; | |
5f81f4b0 | 960 | dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
961 | |
962 | ep_num = ep->ep_num; | |
963 | endptctrl = readl(&dev->op_regs->endptctrl[ep_num]); | |
964 | ||
965 | /* value: 1 - set halt, 0 - clear halt */ | |
966 | if (value) { | |
967 | /* set the stall bit */ | |
968 | if (is_in(ep)) | |
969 | endptctrl |= EPCTRL_TXS; | |
970 | else | |
971 | endptctrl |= EPCTRL_RXS; | |
972 | } else { | |
973 | /* clear the stall bit and reset data toggle */ | |
974 | if (is_in(ep)) { | |
975 | endptctrl &= ~EPCTRL_TXS; | |
976 | endptctrl |= EPCTRL_TXR; | |
977 | } else { | |
978 | endptctrl &= ~EPCTRL_RXS; | |
979 | endptctrl |= EPCTRL_RXR; | |
980 | } | |
981 | } | |
982 | ||
983 | writel(endptctrl, &dev->op_regs->endptctrl[ep_num]); | |
984 | ||
5f81f4b0 | 985 | dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__); |
5be19a9d XS |
986 | } |
987 | ||
988 | ||
989 | /* set the endpoint halt feature */ | |
990 | static int langwell_ep_set_halt(struct usb_ep *_ep, int value) | |
991 | { | |
992 | struct langwell_ep *ep; | |
993 | struct langwell_udc *dev; | |
994 | unsigned long flags; | |
995 | int retval = 0; | |
996 | ||
997 | ep = container_of(_ep, struct langwell_ep, ep); | |
998 | dev = ep->dev; | |
999 | ||
5f81f4b0 | 1000 | dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
1001 | |
1002 | if (!_ep || !ep->desc) | |
1003 | return -EINVAL; | |
1004 | ||
1005 | if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) | |
1006 | return -ESHUTDOWN; | |
1007 | ||
5f81f4b0 | 1008 | if (usb_endpoint_xfer_isoc(ep->desc)) |
5be19a9d XS |
1009 | return -EOPNOTSUPP; |
1010 | ||
1011 | spin_lock_irqsave(&dev->lock, flags); | |
1012 | ||
1013 | /* | |
1014 | * attempt to halt IN ep will fail if any transfer requests | |
1015 | * are still queue | |
1016 | */ | |
1017 | if (!list_empty(&ep->queue) && is_in(ep) && value) { | |
1018 | /* IN endpoint FIFO holds bytes */ | |
5f81f4b0 | 1019 | dev_dbg(&dev->pdev->dev, "%s FIFO holds bytes\n", _ep->name); |
5be19a9d XS |
1020 | retval = -EAGAIN; |
1021 | goto done; | |
1022 | } | |
1023 | ||
1024 | /* endpoint set/clear halt */ | |
1025 | if (ep->ep_num) { | |
1026 | ep_set_halt(ep, value); | |
1027 | } else { /* endpoint 0 */ | |
1028 | dev->ep0_state = WAIT_FOR_SETUP; | |
1029 | dev->ep0_dir = USB_DIR_OUT; | |
1030 | } | |
1031 | done: | |
1032 | spin_unlock_irqrestore(&dev->lock, flags); | |
5f81f4b0 J |
1033 | dev_dbg(&dev->pdev->dev, "%s %s halt\n", |
1034 | _ep->name, value ? "set" : "clear"); | |
1035 | dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__); | |
5be19a9d XS |
1036 | return retval; |
1037 | } | |
1038 | ||
1039 | ||
1040 | /* set the halt feature and ignores clear requests */ | |
1041 | static int langwell_ep_set_wedge(struct usb_ep *_ep) | |
1042 | { | |
1043 | struct langwell_ep *ep; | |
1044 | struct langwell_udc *dev; | |
1045 | ||
1046 | ep = container_of(_ep, struct langwell_ep, ep); | |
1047 | dev = ep->dev; | |
1048 | ||
5f81f4b0 | 1049 | dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
1050 | |
1051 | if (!_ep || !ep->desc) | |
1052 | return -EINVAL; | |
1053 | ||
5f81f4b0 | 1054 | dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__); |
5be19a9d XS |
1055 | return usb_ep_set_halt(_ep); |
1056 | } | |
1057 | ||
1058 | ||
1059 | /* flush contents of a fifo */ | |
1060 | static void langwell_ep_fifo_flush(struct usb_ep *_ep) | |
1061 | { | |
1062 | struct langwell_ep *ep; | |
1063 | struct langwell_udc *dev; | |
1064 | u32 flush_bit; | |
1065 | unsigned long timeout; | |
1066 | ||
1067 | ep = container_of(_ep, struct langwell_ep, ep); | |
1068 | dev = ep->dev; | |
1069 | ||
5f81f4b0 | 1070 | dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
1071 | |
1072 | if (!_ep || !ep->desc) { | |
5f81f4b0 J |
1073 | dev_vdbg(&dev->pdev->dev, "ep or ep->desc is NULL\n"); |
1074 | dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__); | |
5be19a9d XS |
1075 | return; |
1076 | } | |
1077 | ||
5f81f4b0 J |
1078 | dev_vdbg(&dev->pdev->dev, "%s-%s fifo flush\n", |
1079 | _ep->name, DIR_STRING(ep)); | |
5be19a9d XS |
1080 | |
1081 | /* flush endpoint buffer */ | |
1082 | if (ep->ep_num == 0) | |
1083 | flush_bit = (1 << 16) | 1; | |
1084 | else if (is_in(ep)) | |
1085 | flush_bit = 1 << (ep->ep_num + 16); /* TX */ | |
1086 | else | |
1087 | flush_bit = 1 << ep->ep_num; /* RX */ | |
1088 | ||
1089 | /* wait until flush complete */ | |
1090 | timeout = jiffies + FLUSH_TIMEOUT; | |
1091 | do { | |
1092 | writel(flush_bit, &dev->op_regs->endptflush); | |
1093 | while (readl(&dev->op_regs->endptflush)) { | |
1094 | if (time_after(jiffies, timeout)) { | |
5f81f4b0 | 1095 | dev_err(&dev->pdev->dev, "ep flush timeout\n"); |
5be19a9d XS |
1096 | goto done; |
1097 | } | |
1098 | cpu_relax(); | |
1099 | } | |
1100 | } while (readl(&dev->op_regs->endptstat) & flush_bit); | |
1101 | done: | |
5f81f4b0 | 1102 | dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__); |
5be19a9d XS |
1103 | } |
1104 | ||
1105 | ||
1106 | /* endpoints operations structure */ | |
1107 | static const struct usb_ep_ops langwell_ep_ops = { | |
1108 | ||
1109 | /* configure endpoint, making it usable */ | |
1110 | .enable = langwell_ep_enable, | |
1111 | ||
1112 | /* endpoint is no longer usable */ | |
1113 | .disable = langwell_ep_disable, | |
1114 | ||
1115 | /* allocate a request object to use with this endpoint */ | |
1116 | .alloc_request = langwell_alloc_request, | |
1117 | ||
1118 | /* free a request object */ | |
1119 | .free_request = langwell_free_request, | |
1120 | ||
1121 | /* queue (submits) an I/O requests to an endpoint */ | |
1122 | .queue = langwell_ep_queue, | |
1123 | ||
1124 | /* dequeue (cancels, unlinks) an I/O request from an endpoint */ | |
1125 | .dequeue = langwell_ep_dequeue, | |
1126 | ||
1127 | /* set the endpoint halt feature */ | |
1128 | .set_halt = langwell_ep_set_halt, | |
1129 | ||
1130 | /* set the halt feature and ignores clear requests */ | |
1131 | .set_wedge = langwell_ep_set_wedge, | |
1132 | ||
1133 | /* flush contents of a fifo */ | |
1134 | .fifo_flush = langwell_ep_fifo_flush, | |
1135 | }; | |
1136 | ||
1137 | ||
1138 | /*-------------------------------------------------------------------------*/ | |
1139 | ||
1140 | /* device controller usb_gadget_ops structure */ | |
1141 | ||
1142 | /* returns the current frame number */ | |
1143 | static int langwell_get_frame(struct usb_gadget *_gadget) | |
1144 | { | |
1145 | struct langwell_udc *dev; | |
1146 | u16 retval; | |
1147 | ||
1148 | if (!_gadget) | |
1149 | return -ENODEV; | |
1150 | ||
1151 | dev = container_of(_gadget, struct langwell_udc, gadget); | |
5f81f4b0 | 1152 | dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
1153 | |
1154 | retval = readl(&dev->op_regs->frindex) & FRINDEX_MASK; | |
1155 | ||
5f81f4b0 | 1156 | dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__); |
5be19a9d XS |
1157 | return retval; |
1158 | } | |
1159 | ||
1160 | ||
513b91b6 J |
1161 | /* enter or exit PHY low power state */ |
1162 | static void langwell_phy_low_power(struct langwell_udc *dev, bool flag) | |
1163 | { | |
1164 | u32 devlc; | |
1165 | u8 devlc_byte2; | |
1166 | dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__); | |
1167 | ||
1168 | devlc = readl(&dev->op_regs->devlc); | |
1169 | dev_vdbg(&dev->pdev->dev, "devlc = 0x%08x\n", devlc); | |
1170 | ||
1171 | if (flag) | |
1172 | devlc |= LPM_PHCD; | |
1173 | else | |
1174 | devlc &= ~LPM_PHCD; | |
1175 | ||
1176 | /* FIXME: workaround for Langwell A1/A2/A3 sighting */ | |
1177 | devlc_byte2 = (devlc >> 16) & 0xff; | |
1178 | writeb(devlc_byte2, (u8 *)&dev->op_regs->devlc + 2); | |
1179 | ||
1180 | devlc = readl(&dev->op_regs->devlc); | |
1181 | dev_vdbg(&dev->pdev->dev, | |
1182 | "%s PHY low power suspend, devlc = 0x%08x\n", | |
1183 | flag ? "enter" : "exit", devlc); | |
1184 | } | |
1185 | ||
1186 | ||
5be19a9d XS |
1187 | /* tries to wake up the host connected to this gadget */ |
1188 | static int langwell_wakeup(struct usb_gadget *_gadget) | |
1189 | { | |
1190 | struct langwell_udc *dev; | |
513b91b6 | 1191 | u32 portsc1; |
5f81f4b0 | 1192 | unsigned long flags; |
5be19a9d XS |
1193 | |
1194 | if (!_gadget) | |
1195 | return 0; | |
1196 | ||
1197 | dev = container_of(_gadget, struct langwell_udc, gadget); | |
5f81f4b0 | 1198 | dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d | 1199 | |
5f81f4b0 J |
1200 | /* remote wakeup feature not enabled by host */ |
1201 | if (!dev->remote_wakeup) { | |
1202 | dev_info(&dev->pdev->dev, "remote wakeup is disabled\n"); | |
5be19a9d | 1203 | return -ENOTSUPP; |
5f81f4b0 | 1204 | } |
5be19a9d XS |
1205 | |
1206 | spin_lock_irqsave(&dev->lock, flags); | |
1207 | ||
1208 | portsc1 = readl(&dev->op_regs->portsc1); | |
1209 | if (!(portsc1 & PORTS_SUSP)) { | |
1210 | spin_unlock_irqrestore(&dev->lock, flags); | |
1211 | return 0; | |
1212 | } | |
1213 | ||
513b91b6 J |
1214 | /* LPM L1 to L0 or legacy remote wakeup */ |
1215 | if (dev->lpm && dev->lpm_state == LPM_L1) | |
1216 | dev_info(&dev->pdev->dev, "LPM L1 to L0 remote wakeup\n"); | |
1217 | else | |
1218 | dev_info(&dev->pdev->dev, "device remote wakeup\n"); | |
5be19a9d XS |
1219 | |
1220 | /* exit PHY low power suspend */ | |
513b91b6 J |
1221 | if (dev->pdev->device != 0x0829) |
1222 | langwell_phy_low_power(dev, 0); | |
1223 | ||
1224 | /* force port resume */ | |
1225 | portsc1 |= PORTS_FPR; | |
1226 | writel(portsc1, &dev->op_regs->portsc1); | |
5be19a9d XS |
1227 | |
1228 | spin_unlock_irqrestore(&dev->lock, flags); | |
1229 | ||
5f81f4b0 | 1230 | dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__); |
5be19a9d XS |
1231 | return 0; |
1232 | } | |
1233 | ||
1234 | ||
1235 | /* notify controller that VBUS is powered or not */ | |
1236 | static int langwell_vbus_session(struct usb_gadget *_gadget, int is_active) | |
1237 | { | |
1238 | struct langwell_udc *dev; | |
1239 | unsigned long flags; | |
5f81f4b0 | 1240 | u32 usbcmd; |
5be19a9d XS |
1241 | |
1242 | if (!_gadget) | |
1243 | return -ENODEV; | |
1244 | ||
1245 | dev = container_of(_gadget, struct langwell_udc, gadget); | |
5f81f4b0 | 1246 | dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
1247 | |
1248 | spin_lock_irqsave(&dev->lock, flags); | |
5f81f4b0 J |
1249 | dev_vdbg(&dev->pdev->dev, "VBUS status: %s\n", |
1250 | is_active ? "on" : "off"); | |
5be19a9d XS |
1251 | |
1252 | dev->vbus_active = (is_active != 0); | |
1253 | if (dev->driver && dev->softconnected && dev->vbus_active) { | |
1254 | usbcmd = readl(&dev->op_regs->usbcmd); | |
1255 | usbcmd |= CMD_RUNSTOP; | |
1256 | writel(usbcmd, &dev->op_regs->usbcmd); | |
1257 | } else { | |
1258 | usbcmd = readl(&dev->op_regs->usbcmd); | |
1259 | usbcmd &= ~CMD_RUNSTOP; | |
1260 | writel(usbcmd, &dev->op_regs->usbcmd); | |
1261 | } | |
1262 | ||
1263 | spin_unlock_irqrestore(&dev->lock, flags); | |
1264 | ||
5f81f4b0 | 1265 | dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__); |
5be19a9d XS |
1266 | return 0; |
1267 | } | |
1268 | ||
1269 | ||
1270 | /* constrain controller's VBUS power usage */ | |
1271 | static int langwell_vbus_draw(struct usb_gadget *_gadget, unsigned mA) | |
1272 | { | |
1273 | struct langwell_udc *dev; | |
1274 | ||
1275 | if (!_gadget) | |
1276 | return -ENODEV; | |
1277 | ||
1278 | dev = container_of(_gadget, struct langwell_udc, gadget); | |
5f81f4b0 | 1279 | dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
1280 | |
1281 | if (dev->transceiver) { | |
5f81f4b0 J |
1282 | dev_vdbg(&dev->pdev->dev, "otg_set_power\n"); |
1283 | dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__); | |
5be19a9d XS |
1284 | return otg_set_power(dev->transceiver, mA); |
1285 | } | |
1286 | ||
5f81f4b0 | 1287 | dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__); |
5be19a9d XS |
1288 | return -ENOTSUPP; |
1289 | } | |
1290 | ||
1291 | ||
1292 | /* D+ pullup, software-controlled connect/disconnect to USB host */ | |
1293 | static int langwell_pullup(struct usb_gadget *_gadget, int is_on) | |
1294 | { | |
1295 | struct langwell_udc *dev; | |
5f81f4b0 J |
1296 | u32 usbcmd; |
1297 | unsigned long flags; | |
5be19a9d XS |
1298 | |
1299 | if (!_gadget) | |
1300 | return -ENODEV; | |
1301 | ||
1302 | dev = container_of(_gadget, struct langwell_udc, gadget); | |
1303 | ||
5f81f4b0 | 1304 | dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
1305 | |
1306 | spin_lock_irqsave(&dev->lock, flags); | |
1307 | dev->softconnected = (is_on != 0); | |
1308 | ||
1309 | if (dev->driver && dev->softconnected && dev->vbus_active) { | |
1310 | usbcmd = readl(&dev->op_regs->usbcmd); | |
1311 | usbcmd |= CMD_RUNSTOP; | |
1312 | writel(usbcmd, &dev->op_regs->usbcmd); | |
1313 | } else { | |
1314 | usbcmd = readl(&dev->op_regs->usbcmd); | |
1315 | usbcmd &= ~CMD_RUNSTOP; | |
1316 | writel(usbcmd, &dev->op_regs->usbcmd); | |
1317 | } | |
1318 | spin_unlock_irqrestore(&dev->lock, flags); | |
1319 | ||
5f81f4b0 | 1320 | dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__); |
5be19a9d XS |
1321 | return 0; |
1322 | } | |
1323 | ||
1324 | ||
1325 | /* device controller usb_gadget_ops structure */ | |
1326 | static const struct usb_gadget_ops langwell_ops = { | |
1327 | ||
1328 | /* returns the current frame number */ | |
1329 | .get_frame = langwell_get_frame, | |
1330 | ||
1331 | /* tries to wake up the host connected to this gadget */ | |
1332 | .wakeup = langwell_wakeup, | |
1333 | ||
1334 | /* set the device selfpowered feature, always selfpowered */ | |
1335 | /* .set_selfpowered = langwell_set_selfpowered, */ | |
1336 | ||
1337 | /* notify controller that VBUS is powered or not */ | |
1338 | .vbus_session = langwell_vbus_session, | |
1339 | ||
1340 | /* constrain controller's VBUS power usage */ | |
1341 | .vbus_draw = langwell_vbus_draw, | |
1342 | ||
1343 | /* D+ pullup, software-controlled connect/disconnect to USB host */ | |
1344 | .pullup = langwell_pullup, | |
1345 | }; | |
1346 | ||
1347 | ||
1348 | /*-------------------------------------------------------------------------*/ | |
1349 | ||
1350 | /* device controller operations */ | |
1351 | ||
1352 | /* reset device controller */ | |
1353 | static int langwell_udc_reset(struct langwell_udc *dev) | |
1354 | { | |
1355 | u32 usbcmd, usbmode, devlc, endpointlistaddr; | |
513b91b6 | 1356 | u8 devlc_byte0, devlc_byte2; |
5be19a9d XS |
1357 | unsigned long timeout; |
1358 | ||
1359 | if (!dev) | |
1360 | return -EINVAL; | |
1361 | ||
5f81f4b0 | 1362 | dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
1363 | |
1364 | /* set controller to stop state */ | |
1365 | usbcmd = readl(&dev->op_regs->usbcmd); | |
1366 | usbcmd &= ~CMD_RUNSTOP; | |
1367 | writel(usbcmd, &dev->op_regs->usbcmd); | |
1368 | ||
1369 | /* reset device controller */ | |
1370 | usbcmd = readl(&dev->op_regs->usbcmd); | |
1371 | usbcmd |= CMD_RST; | |
1372 | writel(usbcmd, &dev->op_regs->usbcmd); | |
1373 | ||
1374 | /* wait for reset to complete */ | |
1375 | timeout = jiffies + RESET_TIMEOUT; | |
1376 | while (readl(&dev->op_regs->usbcmd) & CMD_RST) { | |
1377 | if (time_after(jiffies, timeout)) { | |
5f81f4b0 | 1378 | dev_err(&dev->pdev->dev, "device reset timeout\n"); |
5be19a9d XS |
1379 | return -ETIMEDOUT; |
1380 | } | |
1381 | cpu_relax(); | |
1382 | } | |
1383 | ||
1384 | /* set controller to device mode */ | |
1385 | usbmode = readl(&dev->op_regs->usbmode); | |
1386 | usbmode |= MODE_DEVICE; | |
1387 | ||
1388 | /* turn setup lockout off, require setup tripwire in usbcmd */ | |
1389 | usbmode |= MODE_SLOM; | |
1390 | ||
1391 | writel(usbmode, &dev->op_regs->usbmode); | |
1392 | usbmode = readl(&dev->op_regs->usbmode); | |
5f81f4b0 | 1393 | dev_vdbg(&dev->pdev->dev, "usbmode=0x%08x\n", usbmode); |
5be19a9d XS |
1394 | |
1395 | /* Write-Clear setup status */ | |
1396 | writel(0, &dev->op_regs->usbsts); | |
1397 | ||
1398 | /* if support USB LPM, ACK all LPM token */ | |
1399 | if (dev->lpm) { | |
1400 | devlc = readl(&dev->op_regs->devlc); | |
513b91b6 J |
1401 | dev_vdbg(&dev->pdev->dev, "devlc = 0x%08x\n", devlc); |
1402 | /* FIXME: workaround for Langwell A1/A2/A3 sighting */ | |
5be19a9d XS |
1403 | devlc &= ~LPM_STL; /* don't STALL LPM token */ |
1404 | devlc &= ~LPM_NYT_ACK; /* ACK LPM token */ | |
513b91b6 J |
1405 | devlc_byte0 = devlc & 0xff; |
1406 | devlc_byte2 = (devlc >> 16) & 0xff; | |
1407 | writeb(devlc_byte0, (u8 *)&dev->op_regs->devlc); | |
1408 | writeb(devlc_byte2, (u8 *)&dev->op_regs->devlc + 2); | |
1409 | devlc = readl(&dev->op_regs->devlc); | |
1410 | dev_vdbg(&dev->pdev->dev, | |
1411 | "ACK LPM token, devlc = 0x%08x\n", devlc); | |
5be19a9d XS |
1412 | } |
1413 | ||
1414 | /* fill endpointlistaddr register */ | |
1415 | endpointlistaddr = dev->ep_dqh_dma; | |
1416 | endpointlistaddr &= ENDPOINTLISTADDR_MASK; | |
1417 | writel(endpointlistaddr, &dev->op_regs->endpointlistaddr); | |
1418 | ||
5f81f4b0 J |
1419 | dev_vdbg(&dev->pdev->dev, |
1420 | "dQH base (vir: %p, phy: 0x%08x), endpointlistaddr=0x%08x\n", | |
1421 | dev->ep_dqh, endpointlistaddr, | |
1422 | readl(&dev->op_regs->endpointlistaddr)); | |
1423 | dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__); | |
5be19a9d XS |
1424 | return 0; |
1425 | } | |
1426 | ||
1427 | ||
1428 | /* reinitialize device controller endpoints */ | |
1429 | static int eps_reinit(struct langwell_udc *dev) | |
1430 | { | |
1431 | struct langwell_ep *ep; | |
1432 | char name[14]; | |
1433 | int i; | |
1434 | ||
5f81f4b0 | 1435 | dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
1436 | |
1437 | /* initialize ep0 */ | |
1438 | ep = &dev->ep[0]; | |
1439 | ep->dev = dev; | |
1440 | strncpy(ep->name, "ep0", sizeof(ep->name)); | |
1441 | ep->ep.name = ep->name; | |
1442 | ep->ep.ops = &langwell_ep_ops; | |
1443 | ep->stopped = 0; | |
1444 | ep->ep.maxpacket = EP0_MAX_PKT_SIZE; | |
1445 | ep->ep_num = 0; | |
1446 | ep->desc = &langwell_ep0_desc; | |
1447 | INIT_LIST_HEAD(&ep->queue); | |
1448 | ||
1449 | ep->ep_type = USB_ENDPOINT_XFER_CONTROL; | |
1450 | ||
1451 | /* initialize other endpoints */ | |
1452 | for (i = 2; i < dev->ep_max; i++) { | |
1453 | ep = &dev->ep[i]; | |
1454 | if (i % 2) | |
1455 | snprintf(name, sizeof(name), "ep%din", i / 2); | |
1456 | else | |
1457 | snprintf(name, sizeof(name), "ep%dout", i / 2); | |
1458 | ep->dev = dev; | |
1459 | strncpy(ep->name, name, sizeof(ep->name)); | |
1460 | ep->ep.name = ep->name; | |
1461 | ||
1462 | ep->ep.ops = &langwell_ep_ops; | |
1463 | ep->stopped = 0; | |
1464 | ep->ep.maxpacket = (unsigned short) ~0; | |
1465 | ep->ep_num = i / 2; | |
1466 | ||
1467 | INIT_LIST_HEAD(&ep->queue); | |
1468 | list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list); | |
5be19a9d XS |
1469 | } |
1470 | ||
5f81f4b0 | 1471 | dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__); |
5be19a9d XS |
1472 | return 0; |
1473 | } | |
1474 | ||
1475 | ||
1476 | /* enable interrupt and set controller to run state */ | |
1477 | static void langwell_udc_start(struct langwell_udc *dev) | |
1478 | { | |
1479 | u32 usbintr, usbcmd; | |
5f81f4b0 | 1480 | dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
1481 | |
1482 | /* enable interrupts */ | |
1483 | usbintr = INTR_ULPIE /* ULPI */ | |
1484 | | INTR_SLE /* suspend */ | |
1485 | /* | INTR_SRE SOF received */ | |
1486 | | INTR_URE /* USB reset */ | |
1487 | | INTR_AAE /* async advance */ | |
1488 | | INTR_SEE /* system error */ | |
1489 | | INTR_FRE /* frame list rollover */ | |
1490 | | INTR_PCE /* port change detect */ | |
1491 | | INTR_UEE /* USB error interrupt */ | |
1492 | | INTR_UE; /* USB interrupt */ | |
1493 | writel(usbintr, &dev->op_regs->usbintr); | |
1494 | ||
1495 | /* clear stopped bit */ | |
1496 | dev->stopped = 0; | |
1497 | ||
1498 | /* set controller to run */ | |
1499 | usbcmd = readl(&dev->op_regs->usbcmd); | |
1500 | usbcmd |= CMD_RUNSTOP; | |
1501 | writel(usbcmd, &dev->op_regs->usbcmd); | |
1502 | ||
5f81f4b0 | 1503 | dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__); |
5be19a9d XS |
1504 | } |
1505 | ||
1506 | ||
1507 | /* disable interrupt and set controller to stop state */ | |
1508 | static void langwell_udc_stop(struct langwell_udc *dev) | |
1509 | { | |
1510 | u32 usbcmd; | |
1511 | ||
5f81f4b0 | 1512 | dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
1513 | |
1514 | /* disable all interrupts */ | |
1515 | writel(0, &dev->op_regs->usbintr); | |
1516 | ||
1517 | /* set stopped bit */ | |
1518 | dev->stopped = 1; | |
1519 | ||
1520 | /* set controller to stop state */ | |
1521 | usbcmd = readl(&dev->op_regs->usbcmd); | |
1522 | usbcmd &= ~CMD_RUNSTOP; | |
1523 | writel(usbcmd, &dev->op_regs->usbcmd); | |
1524 | ||
5f81f4b0 | 1525 | dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__); |
5be19a9d XS |
1526 | } |
1527 | ||
1528 | ||
1529 | /* stop all USB activities */ | |
1530 | static void stop_activity(struct langwell_udc *dev, | |
1531 | struct usb_gadget_driver *driver) | |
1532 | { | |
1533 | struct langwell_ep *ep; | |
5f81f4b0 | 1534 | dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
1535 | |
1536 | nuke(&dev->ep[0], -ESHUTDOWN); | |
1537 | ||
1538 | list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) { | |
1539 | nuke(ep, -ESHUTDOWN); | |
1540 | } | |
1541 | ||
1542 | /* report disconnect; the driver is already quiesced */ | |
1543 | if (driver) { | |
1544 | spin_unlock(&dev->lock); | |
1545 | driver->disconnect(&dev->gadget); | |
1546 | spin_lock(&dev->lock); | |
1547 | } | |
1548 | ||
5f81f4b0 | 1549 | dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__); |
5be19a9d XS |
1550 | } |
1551 | ||
1552 | ||
1553 | /*-------------------------------------------------------------------------*/ | |
1554 | ||
1555 | /* device "function" sysfs attribute file */ | |
1556 | static ssize_t show_function(struct device *_dev, | |
1557 | struct device_attribute *attr, char *buf) | |
1558 | { | |
1559 | struct langwell_udc *dev = the_controller; | |
1560 | ||
1561 | if (!dev->driver || !dev->driver->function | |
1562 | || strlen(dev->driver->function) > PAGE_SIZE) | |
1563 | return 0; | |
1564 | ||
1565 | return scnprintf(buf, PAGE_SIZE, "%s\n", dev->driver->function); | |
1566 | } | |
1567 | static DEVICE_ATTR(function, S_IRUGO, show_function, NULL); | |
1568 | ||
1569 | ||
1570 | /* device "langwell_udc" sysfs attribute file */ | |
1571 | static ssize_t show_langwell_udc(struct device *_dev, | |
1572 | struct device_attribute *attr, char *buf) | |
1573 | { | |
1574 | struct langwell_udc *dev = the_controller; | |
1575 | struct langwell_request *req; | |
1576 | struct langwell_ep *ep = NULL; | |
1577 | char *next; | |
1578 | unsigned size; | |
1579 | unsigned t; | |
1580 | unsigned i; | |
1581 | unsigned long flags; | |
1582 | u32 tmp_reg; | |
1583 | ||
1584 | next = buf; | |
1585 | size = PAGE_SIZE; | |
1586 | spin_lock_irqsave(&dev->lock, flags); | |
1587 | ||
1588 | /* driver basic information */ | |
1589 | t = scnprintf(next, size, | |
1590 | DRIVER_DESC "\n" | |
1591 | "%s version: %s\n" | |
1592 | "Gadget driver: %s\n\n", | |
1593 | driver_name, DRIVER_VERSION, | |
1594 | dev->driver ? dev->driver->driver.name : "(none)"); | |
1595 | size -= t; | |
1596 | next += t; | |
1597 | ||
1598 | /* device registers */ | |
1599 | tmp_reg = readl(&dev->op_regs->usbcmd); | |
1600 | t = scnprintf(next, size, | |
1601 | "USBCMD reg:\n" | |
1602 | "SetupTW: %d\n" | |
1603 | "Run/Stop: %s\n\n", | |
1604 | (tmp_reg & CMD_SUTW) ? 1 : 0, | |
1605 | (tmp_reg & CMD_RUNSTOP) ? "Run" : "Stop"); | |
1606 | size -= t; | |
1607 | next += t; | |
1608 | ||
1609 | tmp_reg = readl(&dev->op_regs->usbsts); | |
1610 | t = scnprintf(next, size, | |
1611 | "USB Status Reg:\n" | |
1612 | "Device Suspend: %d\n" | |
1613 | "Reset Received: %d\n" | |
1614 | "System Error: %s\n" | |
1615 | "USB Error Interrupt: %s\n\n", | |
1616 | (tmp_reg & STS_SLI) ? 1 : 0, | |
1617 | (tmp_reg & STS_URI) ? 1 : 0, | |
1618 | (tmp_reg & STS_SEI) ? "Error" : "No error", | |
1619 | (tmp_reg & STS_UEI) ? "Error detected" : "No error"); | |
1620 | size -= t; | |
1621 | next += t; | |
1622 | ||
1623 | tmp_reg = readl(&dev->op_regs->usbintr); | |
1624 | t = scnprintf(next, size, | |
1625 | "USB Intrrupt Enable Reg:\n" | |
1626 | "Sleep Enable: %d\n" | |
1627 | "SOF Received Enable: %d\n" | |
1628 | "Reset Enable: %d\n" | |
1629 | "System Error Enable: %d\n" | |
1630 | "Port Change Dectected Enable: %d\n" | |
1631 | "USB Error Intr Enable: %d\n" | |
1632 | "USB Intr Enable: %d\n\n", | |
1633 | (tmp_reg & INTR_SLE) ? 1 : 0, | |
1634 | (tmp_reg & INTR_SRE) ? 1 : 0, | |
1635 | (tmp_reg & INTR_URE) ? 1 : 0, | |
1636 | (tmp_reg & INTR_SEE) ? 1 : 0, | |
1637 | (tmp_reg & INTR_PCE) ? 1 : 0, | |
1638 | (tmp_reg & INTR_UEE) ? 1 : 0, | |
1639 | (tmp_reg & INTR_UE) ? 1 : 0); | |
1640 | size -= t; | |
1641 | next += t; | |
1642 | ||
1643 | tmp_reg = readl(&dev->op_regs->frindex); | |
1644 | t = scnprintf(next, size, | |
1645 | "USB Frame Index Reg:\n" | |
1646 | "Frame Number is 0x%08x\n\n", | |
1647 | (tmp_reg & FRINDEX_MASK)); | |
1648 | size -= t; | |
1649 | next += t; | |
1650 | ||
1651 | tmp_reg = readl(&dev->op_regs->deviceaddr); | |
1652 | t = scnprintf(next, size, | |
1653 | "USB Device Address Reg:\n" | |
1654 | "Device Addr is 0x%x\n\n", | |
1655 | USBADR(tmp_reg)); | |
1656 | size -= t; | |
1657 | next += t; | |
1658 | ||
1659 | tmp_reg = readl(&dev->op_regs->endpointlistaddr); | |
1660 | t = scnprintf(next, size, | |
1661 | "USB Endpoint List Address Reg:\n" | |
1662 | "Endpoint List Pointer is 0x%x\n\n", | |
1663 | EPBASE(tmp_reg)); | |
1664 | size -= t; | |
1665 | next += t; | |
1666 | ||
1667 | tmp_reg = readl(&dev->op_regs->portsc1); | |
1668 | t = scnprintf(next, size, | |
1669 | "USB Port Status & Control Reg:\n" | |
1670 | "Port Reset: %s\n" | |
1671 | "Port Suspend Mode: %s\n" | |
1672 | "Over-current Change: %s\n" | |
1673 | "Port Enable/Disable Change: %s\n" | |
1674 | "Port Enabled/Disabled: %s\n" | |
5f81f4b0 J |
1675 | "Current Connect Status: %s\n" |
1676 | "LPM Suspend Status: %s\n\n", | |
5be19a9d XS |
1677 | (tmp_reg & PORTS_PR) ? "Reset" : "Not Reset", |
1678 | (tmp_reg & PORTS_SUSP) ? "Suspend " : "Not Suspend", | |
1679 | (tmp_reg & PORTS_OCC) ? "Detected" : "No", | |
1680 | (tmp_reg & PORTS_PEC) ? "Changed" : "Not Changed", | |
1681 | (tmp_reg & PORTS_PE) ? "Enable" : "Not Correct", | |
5f81f4b0 J |
1682 | (tmp_reg & PORTS_CCS) ? "Attached" : "Not Attached", |
1683 | (tmp_reg & PORTS_SLP) ? "LPM L1" : "LPM L0"); | |
5be19a9d XS |
1684 | size -= t; |
1685 | next += t; | |
1686 | ||
1687 | tmp_reg = readl(&dev->op_regs->devlc); | |
1688 | t = scnprintf(next, size, | |
1689 | "Device LPM Control Reg:\n" | |
1690 | "Parallel Transceiver : %d\n" | |
1691 | "Serial Transceiver : %d\n" | |
1692 | "Port Speed: %s\n" | |
1693 | "Port Force Full Speed Connenct: %s\n" | |
5f81f4b0 | 1694 | "PHY Low Power Suspend Clock: %s\n" |
5be19a9d XS |
1695 | "BmAttributes: %d\n\n", |
1696 | LPM_PTS(tmp_reg), | |
1697 | (tmp_reg & LPM_STS) ? 1 : 0, | |
1698 | ({ | |
1699 | char *s; | |
1700 | switch (LPM_PSPD(tmp_reg)) { | |
1701 | case LPM_SPEED_FULL: | |
1702 | s = "Full Speed"; break; | |
1703 | case LPM_SPEED_LOW: | |
1704 | s = "Low Speed"; break; | |
1705 | case LPM_SPEED_HIGH: | |
1706 | s = "High Speed"; break; | |
1707 | default: | |
1708 | s = "Unknown Speed"; break; | |
1709 | } | |
1710 | s; | |
1711 | }), | |
1712 | (tmp_reg & LPM_PFSC) ? "Force Full Speed" : "Not Force", | |
1713 | (tmp_reg & LPM_PHCD) ? "Disabled" : "Enabled", | |
1714 | LPM_BA(tmp_reg)); | |
1715 | size -= t; | |
1716 | next += t; | |
1717 | ||
1718 | tmp_reg = readl(&dev->op_regs->usbmode); | |
1719 | t = scnprintf(next, size, | |
1720 | "USB Mode Reg:\n" | |
1721 | "Controller Mode is : %s\n\n", ({ | |
1722 | char *s; | |
1723 | switch (MODE_CM(tmp_reg)) { | |
1724 | case MODE_IDLE: | |
1725 | s = "Idle"; break; | |
1726 | case MODE_DEVICE: | |
1727 | s = "Device Controller"; break; | |
1728 | case MODE_HOST: | |
1729 | s = "Host Controller"; break; | |
1730 | default: | |
1731 | s = "None"; break; | |
1732 | } | |
1733 | s; | |
1734 | })); | |
1735 | size -= t; | |
1736 | next += t; | |
1737 | ||
1738 | tmp_reg = readl(&dev->op_regs->endptsetupstat); | |
1739 | t = scnprintf(next, size, | |
1740 | "Endpoint Setup Status Reg:\n" | |
1741 | "SETUP on ep 0x%04x\n\n", | |
1742 | tmp_reg & SETUPSTAT_MASK); | |
1743 | size -= t; | |
1744 | next += t; | |
1745 | ||
1746 | for (i = 0; i < dev->ep_max / 2; i++) { | |
1747 | tmp_reg = readl(&dev->op_regs->endptctrl[i]); | |
1748 | t = scnprintf(next, size, "EP Ctrl Reg [%d]: 0x%08x\n", | |
1749 | i, tmp_reg); | |
1750 | size -= t; | |
1751 | next += t; | |
1752 | } | |
1753 | tmp_reg = readl(&dev->op_regs->endptprime); | |
1754 | t = scnprintf(next, size, "EP Prime Reg: 0x%08x\n\n", tmp_reg); | |
1755 | size -= t; | |
1756 | next += t; | |
1757 | ||
1758 | /* langwell_udc, langwell_ep, langwell_request structure information */ | |
1759 | ep = &dev->ep[0]; | |
1760 | t = scnprintf(next, size, "%s MaxPacketSize: 0x%x, ep_num: %d\n", | |
1761 | ep->ep.name, ep->ep.maxpacket, ep->ep_num); | |
1762 | size -= t; | |
1763 | next += t; | |
1764 | ||
1765 | if (list_empty(&ep->queue)) { | |
1766 | t = scnprintf(next, size, "its req queue is empty\n\n"); | |
1767 | size -= t; | |
1768 | next += t; | |
1769 | } else { | |
1770 | list_for_each_entry(req, &ep->queue, queue) { | |
1771 | t = scnprintf(next, size, | |
1772 | "req %p actual 0x%x length 0x%x buf %p\n", | |
1773 | &req->req, req->req.actual, | |
1774 | req->req.length, req->req.buf); | |
1775 | size -= t; | |
1776 | next += t; | |
1777 | } | |
1778 | } | |
1779 | /* other gadget->eplist ep */ | |
1780 | list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) { | |
1781 | if (ep->desc) { | |
1782 | t = scnprintf(next, size, | |
1783 | "\n%s MaxPacketSize: 0x%x, " | |
1784 | "ep_num: %d\n", | |
1785 | ep->ep.name, ep->ep.maxpacket, | |
1786 | ep->ep_num); | |
1787 | size -= t; | |
1788 | next += t; | |
1789 | ||
1790 | if (list_empty(&ep->queue)) { | |
1791 | t = scnprintf(next, size, | |
1792 | "its req queue is empty\n\n"); | |
1793 | size -= t; | |
1794 | next += t; | |
1795 | } else { | |
1796 | list_for_each_entry(req, &ep->queue, queue) { | |
1797 | t = scnprintf(next, size, | |
1798 | "req %p actual 0x%x length " | |
1799 | "0x%x buf %p\n", | |
1800 | &req->req, req->req.actual, | |
1801 | req->req.length, req->req.buf); | |
1802 | size -= t; | |
1803 | next += t; | |
1804 | } | |
1805 | } | |
1806 | } | |
1807 | } | |
1808 | ||
1809 | spin_unlock_irqrestore(&dev->lock, flags); | |
1810 | return PAGE_SIZE - size; | |
1811 | } | |
1812 | static DEVICE_ATTR(langwell_udc, S_IRUGO, show_langwell_udc, NULL); | |
1813 | ||
1814 | ||
3211cbc2 J |
1815 | /* device "remote_wakeup" sysfs attribute file */ |
1816 | static ssize_t store_remote_wakeup(struct device *_dev, | |
1817 | struct device_attribute *attr, const char *buf, size_t count) | |
1818 | { | |
1819 | struct langwell_udc *dev = the_controller; | |
1820 | unsigned long flags; | |
1821 | ssize_t rc = count; | |
1822 | ||
1823 | if (count > 2) | |
1824 | return -EINVAL; | |
1825 | ||
1826 | if (count > 0 && buf[count-1] == '\n') | |
1827 | ((char *) buf)[count-1] = 0; | |
1828 | ||
1829 | if (buf[0] != '1') | |
1830 | return -EINVAL; | |
1831 | ||
1832 | /* force remote wakeup enabled in case gadget driver doesn't support */ | |
1833 | spin_lock_irqsave(&dev->lock, flags); | |
1834 | dev->remote_wakeup = 1; | |
1835 | dev->dev_status |= (1 << USB_DEVICE_REMOTE_WAKEUP); | |
1836 | spin_unlock_irqrestore(&dev->lock, flags); | |
1837 | ||
1838 | langwell_wakeup(&dev->gadget); | |
1839 | ||
1840 | return rc; | |
1841 | } | |
1842 | static DEVICE_ATTR(remote_wakeup, S_IWUSR, NULL, store_remote_wakeup); | |
1843 | ||
1844 | ||
5be19a9d XS |
1845 | /*-------------------------------------------------------------------------*/ |
1846 | ||
1847 | /* | |
1848 | * when a driver is successfully registered, it will receive | |
1849 | * control requests including set_configuration(), which enables | |
1850 | * non-control requests. then usb traffic follows until a | |
1851 | * disconnect is reported. then a host may connect again, or | |
1852 | * the driver might get unbound. | |
1853 | */ | |
1854 | ||
b0fca50f UKK |
1855 | int usb_gadget_probe_driver(struct usb_gadget_driver *driver, |
1856 | int (*bind)(struct usb_gadget *)) | |
5be19a9d XS |
1857 | { |
1858 | struct langwell_udc *dev = the_controller; | |
1859 | unsigned long flags; | |
1860 | int retval; | |
1861 | ||
1862 | if (!dev) | |
1863 | return -ENODEV; | |
1864 | ||
5f81f4b0 | 1865 | dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
1866 | |
1867 | if (dev->driver) | |
1868 | return -EBUSY; | |
1869 | ||
1870 | spin_lock_irqsave(&dev->lock, flags); | |
1871 | ||
1872 | /* hook up the driver ... */ | |
1873 | driver->driver.bus = NULL; | |
1874 | dev->driver = driver; | |
1875 | dev->gadget.dev.driver = &driver->driver; | |
1876 | ||
1877 | spin_unlock_irqrestore(&dev->lock, flags); | |
1878 | ||
b0fca50f | 1879 | retval = bind(&dev->gadget); |
5be19a9d | 1880 | if (retval) { |
5f81f4b0 | 1881 | dev_dbg(&dev->pdev->dev, "bind to driver %s --> %d\n", |
5be19a9d XS |
1882 | driver->driver.name, retval); |
1883 | dev->driver = NULL; | |
1884 | dev->gadget.dev.driver = NULL; | |
1885 | return retval; | |
1886 | } | |
1887 | ||
1888 | retval = device_create_file(&dev->pdev->dev, &dev_attr_function); | |
1889 | if (retval) | |
1890 | goto err_unbind; | |
1891 | ||
1892 | dev->usb_state = USB_STATE_ATTACHED; | |
1893 | dev->ep0_state = WAIT_FOR_SETUP; | |
1894 | dev->ep0_dir = USB_DIR_OUT; | |
1895 | ||
1896 | /* enable interrupt and set controller to run state */ | |
1897 | if (dev->got_irq) | |
1898 | langwell_udc_start(dev); | |
1899 | ||
5f81f4b0 J |
1900 | dev_vdbg(&dev->pdev->dev, |
1901 | "After langwell_udc_start(), print all registers:\n"); | |
5be19a9d | 1902 | print_all_registers(dev); |
5be19a9d | 1903 | |
5f81f4b0 J |
1904 | dev_info(&dev->pdev->dev, "register driver: %s\n", |
1905 | driver->driver.name); | |
1906 | dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__); | |
5be19a9d XS |
1907 | return 0; |
1908 | ||
1909 | err_unbind: | |
1910 | driver->unbind(&dev->gadget); | |
1911 | dev->gadget.dev.driver = NULL; | |
1912 | dev->driver = NULL; | |
1913 | ||
5f81f4b0 | 1914 | dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__); |
5be19a9d XS |
1915 | return retval; |
1916 | } | |
b0fca50f | 1917 | EXPORT_SYMBOL(usb_gadget_probe_driver); |
5be19a9d XS |
1918 | |
1919 | ||
1920 | /* unregister gadget driver */ | |
1921 | int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) | |
1922 | { | |
1923 | struct langwell_udc *dev = the_controller; | |
1924 | unsigned long flags; | |
1925 | ||
1926 | if (!dev) | |
1927 | return -ENODEV; | |
1928 | ||
5f81f4b0 | 1929 | dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d | 1930 | |
b0fca50f | 1931 | if (unlikely(!driver || !driver->unbind)) |
5be19a9d XS |
1932 | return -EINVAL; |
1933 | ||
513b91b6 J |
1934 | /* exit PHY low power suspend */ |
1935 | if (dev->pdev->device != 0x0829) | |
1936 | langwell_phy_low_power(dev, 0); | |
1937 | ||
5be19a9d XS |
1938 | /* unbind OTG transceiver */ |
1939 | if (dev->transceiver) | |
1940 | (void)otg_set_peripheral(dev->transceiver, 0); | |
1941 | ||
1942 | /* disable interrupt and set controller to stop state */ | |
1943 | langwell_udc_stop(dev); | |
1944 | ||
1945 | dev->usb_state = USB_STATE_ATTACHED; | |
1946 | dev->ep0_state = WAIT_FOR_SETUP; | |
1947 | dev->ep0_dir = USB_DIR_OUT; | |
1948 | ||
1949 | spin_lock_irqsave(&dev->lock, flags); | |
1950 | ||
1951 | /* stop all usb activities */ | |
1952 | dev->gadget.speed = USB_SPEED_UNKNOWN; | |
1953 | stop_activity(dev, driver); | |
1954 | spin_unlock_irqrestore(&dev->lock, flags); | |
1955 | ||
1956 | /* unbind gadget driver */ | |
1957 | driver->unbind(&dev->gadget); | |
1958 | dev->gadget.dev.driver = NULL; | |
1959 | dev->driver = NULL; | |
1960 | ||
1961 | device_remove_file(&dev->pdev->dev, &dev_attr_function); | |
1962 | ||
5f81f4b0 J |
1963 | dev_info(&dev->pdev->dev, "unregistered driver '%s'\n", |
1964 | driver->driver.name); | |
1965 | dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__); | |
5be19a9d XS |
1966 | return 0; |
1967 | } | |
1968 | EXPORT_SYMBOL(usb_gadget_unregister_driver); | |
1969 | ||
1970 | ||
1971 | /*-------------------------------------------------------------------------*/ | |
1972 | ||
1973 | /* | |
1974 | * setup tripwire is used as a semaphore to ensure that the setup data | |
1975 | * payload is extracted from a dQH without being corrupted | |
1976 | */ | |
1977 | static void setup_tripwire(struct langwell_udc *dev) | |
1978 | { | |
1979 | u32 usbcmd, | |
1980 | endptsetupstat; | |
1981 | unsigned long timeout; | |
1982 | struct langwell_dqh *dqh; | |
1983 | ||
5f81f4b0 | 1984 | dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
1985 | |
1986 | /* ep0 OUT dQH */ | |
1987 | dqh = &dev->ep_dqh[EP_DIR_OUT]; | |
1988 | ||
1989 | /* Write-Clear endptsetupstat */ | |
1990 | endptsetupstat = readl(&dev->op_regs->endptsetupstat); | |
1991 | writel(endptsetupstat, &dev->op_regs->endptsetupstat); | |
1992 | ||
1993 | /* wait until endptsetupstat is cleared */ | |
1994 | timeout = jiffies + SETUPSTAT_TIMEOUT; | |
1995 | while (readl(&dev->op_regs->endptsetupstat)) { | |
1996 | if (time_after(jiffies, timeout)) { | |
5f81f4b0 | 1997 | dev_err(&dev->pdev->dev, "setup_tripwire timeout\n"); |
5be19a9d XS |
1998 | break; |
1999 | } | |
2000 | cpu_relax(); | |
2001 | } | |
2002 | ||
2003 | /* while a hazard exists when setup packet arrives */ | |
2004 | do { | |
2005 | /* set setup tripwire bit */ | |
2006 | usbcmd = readl(&dev->op_regs->usbcmd); | |
2007 | writel(usbcmd | CMD_SUTW, &dev->op_regs->usbcmd); | |
2008 | ||
2009 | /* copy the setup packet to local buffer */ | |
2010 | memcpy(&dev->local_setup_buff, &dqh->dqh_setup, 8); | |
2011 | } while (!(readl(&dev->op_regs->usbcmd) & CMD_SUTW)); | |
2012 | ||
2013 | /* Write-Clear setup tripwire bit */ | |
2014 | usbcmd = readl(&dev->op_regs->usbcmd); | |
2015 | writel(usbcmd & ~CMD_SUTW, &dev->op_regs->usbcmd); | |
2016 | ||
5f81f4b0 | 2017 | dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__); |
5be19a9d XS |
2018 | } |
2019 | ||
2020 | ||
2021 | /* protocol ep0 stall, will automatically be cleared on new transaction */ | |
2022 | static void ep0_stall(struct langwell_udc *dev) | |
2023 | { | |
2024 | u32 endptctrl; | |
2025 | ||
5f81f4b0 | 2026 | dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
2027 | |
2028 | /* set TX and RX to stall */ | |
2029 | endptctrl = readl(&dev->op_regs->endptctrl[0]); | |
2030 | endptctrl |= EPCTRL_TXS | EPCTRL_RXS; | |
2031 | writel(endptctrl, &dev->op_regs->endptctrl[0]); | |
2032 | ||
2033 | /* update ep0 state */ | |
2034 | dev->ep0_state = WAIT_FOR_SETUP; | |
2035 | dev->ep0_dir = USB_DIR_OUT; | |
2036 | ||
5f81f4b0 | 2037 | dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__); |
5be19a9d XS |
2038 | } |
2039 | ||
2040 | ||
2041 | /* PRIME a status phase for ep0 */ | |
2042 | static int prime_status_phase(struct langwell_udc *dev, int dir) | |
2043 | { | |
2044 | struct langwell_request *req; | |
2045 | struct langwell_ep *ep; | |
2046 | int status = 0; | |
2047 | ||
5f81f4b0 | 2048 | dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
2049 | |
2050 | if (dir == EP_DIR_IN) | |
2051 | dev->ep0_dir = USB_DIR_IN; | |
2052 | else | |
2053 | dev->ep0_dir = USB_DIR_OUT; | |
2054 | ||
2055 | ep = &dev->ep[0]; | |
2056 | dev->ep0_state = WAIT_FOR_OUT_STATUS; | |
2057 | ||
2058 | req = dev->status_req; | |
2059 | ||
2060 | req->ep = ep; | |
2061 | req->req.length = 0; | |
2062 | req->req.status = -EINPROGRESS; | |
2063 | req->req.actual = 0; | |
2064 | req->req.complete = NULL; | |
2065 | req->dtd_count = 0; | |
2066 | ||
2067 | if (!req_to_dtd(req)) | |
2068 | status = queue_dtd(ep, req); | |
2069 | else | |
2070 | return -ENOMEM; | |
2071 | ||
2072 | if (status) | |
5f81f4b0 | 2073 | dev_err(&dev->pdev->dev, "can't queue ep0 status request\n"); |
5be19a9d XS |
2074 | |
2075 | list_add_tail(&req->queue, &ep->queue); | |
2076 | ||
5f81f4b0 | 2077 | dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__); |
5be19a9d XS |
2078 | return status; |
2079 | } | |
2080 | ||
2081 | ||
2082 | /* SET_ADDRESS request routine */ | |
2083 | static void set_address(struct langwell_udc *dev, u16 value, | |
2084 | u16 index, u16 length) | |
2085 | { | |
5f81f4b0 | 2086 | dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
2087 | |
2088 | /* save the new address to device struct */ | |
2089 | dev->dev_addr = (u8) value; | |
5f81f4b0 | 2090 | dev_vdbg(&dev->pdev->dev, "dev->dev_addr = %d\n", dev->dev_addr); |
5be19a9d XS |
2091 | |
2092 | /* update usb state */ | |
2093 | dev->usb_state = USB_STATE_ADDRESS; | |
2094 | ||
2095 | /* STATUS phase */ | |
2096 | if (prime_status_phase(dev, EP_DIR_IN)) | |
2097 | ep0_stall(dev); | |
2098 | ||
5f81f4b0 | 2099 | dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__); |
5be19a9d XS |
2100 | } |
2101 | ||
2102 | ||
2103 | /* return endpoint by windex */ | |
2104 | static struct langwell_ep *get_ep_by_windex(struct langwell_udc *dev, | |
2105 | u16 wIndex) | |
2106 | { | |
2107 | struct langwell_ep *ep; | |
5f81f4b0 | 2108 | dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
2109 | |
2110 | if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0) | |
2111 | return &dev->ep[0]; | |
2112 | ||
2113 | list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) { | |
2114 | u8 bEndpointAddress; | |
2115 | if (!ep->desc) | |
2116 | continue; | |
2117 | ||
2118 | bEndpointAddress = ep->desc->bEndpointAddress; | |
2119 | if ((wIndex ^ bEndpointAddress) & USB_DIR_IN) | |
2120 | continue; | |
2121 | ||
2122 | if ((wIndex & USB_ENDPOINT_NUMBER_MASK) | |
2123 | == (bEndpointAddress & USB_ENDPOINT_NUMBER_MASK)) | |
2124 | return ep; | |
2125 | } | |
2126 | ||
5f81f4b0 | 2127 | dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__); |
5be19a9d XS |
2128 | return NULL; |
2129 | } | |
2130 | ||
2131 | ||
2132 | /* return whether endpoint is stalled, 0: not stalled; 1: stalled */ | |
2133 | static int ep_is_stall(struct langwell_ep *ep) | |
2134 | { | |
2135 | struct langwell_udc *dev = ep->dev; | |
2136 | u32 endptctrl; | |
2137 | int retval; | |
2138 | ||
5f81f4b0 | 2139 | dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
2140 | |
2141 | endptctrl = readl(&dev->op_regs->endptctrl[ep->ep_num]); | |
2142 | if (is_in(ep)) | |
2143 | retval = endptctrl & EPCTRL_TXS ? 1 : 0; | |
2144 | else | |
2145 | retval = endptctrl & EPCTRL_RXS ? 1 : 0; | |
2146 | ||
5f81f4b0 | 2147 | dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__); |
5be19a9d XS |
2148 | return retval; |
2149 | } | |
2150 | ||
2151 | ||
2152 | /* GET_STATUS request routine */ | |
2153 | static void get_status(struct langwell_udc *dev, u8 request_type, u16 value, | |
2154 | u16 index, u16 length) | |
2155 | { | |
2156 | struct langwell_request *req; | |
2157 | struct langwell_ep *ep; | |
2158 | u16 status_data = 0; /* 16 bits cpu view status data */ | |
2159 | int status = 0; | |
2160 | ||
5f81f4b0 | 2161 | dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
2162 | |
2163 | ep = &dev->ep[0]; | |
2164 | ||
2165 | if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) { | |
2166 | /* get device status */ | |
3211cbc2 | 2167 | status_data = dev->dev_status; |
5be19a9d XS |
2168 | } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) { |
2169 | /* get interface status */ | |
2170 | status_data = 0; | |
2171 | } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) { | |
2172 | /* get endpoint status */ | |
2173 | struct langwell_ep *epn; | |
2174 | epn = get_ep_by_windex(dev, index); | |
2175 | /* stall if endpoint doesn't exist */ | |
2176 | if (!epn) | |
2177 | goto stall; | |
2178 | ||
2179 | status_data = ep_is_stall(epn) << USB_ENDPOINT_HALT; | |
2180 | } | |
2181 | ||
5f81f4b0 J |
2182 | dev_dbg(&dev->pdev->dev, "get status data: 0x%04x\n", status_data); |
2183 | ||
5be19a9d XS |
2184 | dev->ep0_dir = USB_DIR_IN; |
2185 | ||
2186 | /* borrow the per device status_req */ | |
2187 | req = dev->status_req; | |
2188 | ||
2189 | /* fill in the reqest structure */ | |
2190 | *((u16 *) req->req.buf) = cpu_to_le16(status_data); | |
2191 | req->ep = ep; | |
2192 | req->req.length = 2; | |
2193 | req->req.status = -EINPROGRESS; | |
2194 | req->req.actual = 0; | |
2195 | req->req.complete = NULL; | |
2196 | req->dtd_count = 0; | |
2197 | ||
2198 | /* prime the data phase */ | |
2199 | if (!req_to_dtd(req)) | |
2200 | status = queue_dtd(ep, req); | |
2201 | else /* no mem */ | |
2202 | goto stall; | |
2203 | ||
2204 | if (status) { | |
5f81f4b0 J |
2205 | dev_err(&dev->pdev->dev, |
2206 | "response error on GET_STATUS request\n"); | |
5be19a9d XS |
2207 | goto stall; |
2208 | } | |
2209 | ||
2210 | list_add_tail(&req->queue, &ep->queue); | |
2211 | dev->ep0_state = DATA_STATE_XMIT; | |
2212 | ||
5f81f4b0 | 2213 | dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__); |
5be19a9d XS |
2214 | return; |
2215 | stall: | |
2216 | ep0_stall(dev); | |
5f81f4b0 | 2217 | dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__); |
5be19a9d XS |
2218 | } |
2219 | ||
2220 | ||
2221 | /* setup packet interrupt handler */ | |
2222 | static void handle_setup_packet(struct langwell_udc *dev, | |
2223 | struct usb_ctrlrequest *setup) | |
2224 | { | |
2225 | u16 wValue = le16_to_cpu(setup->wValue); | |
2226 | u16 wIndex = le16_to_cpu(setup->wIndex); | |
2227 | u16 wLength = le16_to_cpu(setup->wLength); | |
7fc56f0d | 2228 | u32 portsc1; |
5be19a9d | 2229 | |
5f81f4b0 | 2230 | dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
2231 | |
2232 | /* ep0 fifo flush */ | |
2233 | nuke(&dev->ep[0], -ESHUTDOWN); | |
2234 | ||
5f81f4b0 | 2235 | dev_dbg(&dev->pdev->dev, "SETUP %02x.%02x v%04x i%04x l%04x\n", |
5be19a9d XS |
2236 | setup->bRequestType, setup->bRequest, |
2237 | wValue, wIndex, wLength); | |
2238 | ||
2239 | /* RNDIS gadget delegate */ | |
2240 | if ((setup->bRequestType == 0x21) && (setup->bRequest == 0x00)) { | |
2241 | /* USB_CDC_SEND_ENCAPSULATED_COMMAND */ | |
2242 | goto delegate; | |
2243 | } | |
2244 | ||
2245 | /* USB_CDC_GET_ENCAPSULATED_RESPONSE */ | |
2246 | if ((setup->bRequestType == 0xa1) && (setup->bRequest == 0x01)) { | |
2247 | /* USB_CDC_GET_ENCAPSULATED_RESPONSE */ | |
2248 | goto delegate; | |
2249 | } | |
2250 | ||
2251 | /* We process some stardard setup requests here */ | |
2252 | switch (setup->bRequest) { | |
2253 | case USB_REQ_GET_STATUS: | |
5f81f4b0 | 2254 | dev_dbg(&dev->pdev->dev, "SETUP: USB_REQ_GET_STATUS\n"); |
5be19a9d XS |
2255 | /* get status, DATA and STATUS phase */ |
2256 | if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK)) | |
2257 | != (USB_DIR_IN | USB_TYPE_STANDARD)) | |
2258 | break; | |
2259 | get_status(dev, setup->bRequestType, wValue, wIndex, wLength); | |
2260 | goto end; | |
2261 | ||
2262 | case USB_REQ_SET_ADDRESS: | |
5f81f4b0 | 2263 | dev_dbg(&dev->pdev->dev, "SETUP: USB_REQ_SET_ADDRESS\n"); |
5be19a9d XS |
2264 | /* STATUS phase */ |
2265 | if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD | |
2266 | | USB_RECIP_DEVICE)) | |
2267 | break; | |
2268 | set_address(dev, wValue, wIndex, wLength); | |
2269 | goto end; | |
2270 | ||
2271 | case USB_REQ_CLEAR_FEATURE: | |
2272 | case USB_REQ_SET_FEATURE: | |
2273 | /* STATUS phase */ | |
2274 | { | |
2275 | int rc = -EOPNOTSUPP; | |
2276 | if (setup->bRequest == USB_REQ_SET_FEATURE) | |
5f81f4b0 J |
2277 | dev_dbg(&dev->pdev->dev, |
2278 | "SETUP: USB_REQ_SET_FEATURE\n"); | |
5be19a9d | 2279 | else if (setup->bRequest == USB_REQ_CLEAR_FEATURE) |
5f81f4b0 J |
2280 | dev_dbg(&dev->pdev->dev, |
2281 | "SETUP: USB_REQ_CLEAR_FEATURE\n"); | |
5be19a9d XS |
2282 | |
2283 | if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK)) | |
2284 | == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) { | |
2285 | struct langwell_ep *epn; | |
2286 | epn = get_ep_by_windex(dev, wIndex); | |
2287 | /* stall if endpoint doesn't exist */ | |
2288 | if (!epn) { | |
2289 | ep0_stall(dev); | |
2290 | goto end; | |
2291 | } | |
2292 | ||
2293 | if (wValue != 0 || wLength != 0 | |
2294 | || epn->ep_num > dev->ep_max) | |
2295 | break; | |
2296 | ||
2297 | spin_unlock(&dev->lock); | |
2298 | rc = langwell_ep_set_halt(&epn->ep, | |
5f81f4b0 J |
2299 | (setup->bRequest == USB_REQ_SET_FEATURE) |
2300 | ? 1 : 0); | |
5be19a9d XS |
2301 | spin_lock(&dev->lock); |
2302 | ||
2303 | } else if ((setup->bRequestType & (USB_RECIP_MASK | |
2304 | | USB_TYPE_MASK)) == (USB_RECIP_DEVICE | |
2305 | | USB_TYPE_STANDARD)) { | |
3211cbc2 J |
2306 | rc = 0; |
2307 | switch (wValue) { | |
2308 | case USB_DEVICE_REMOTE_WAKEUP: | |
2309 | if (setup->bRequest == USB_REQ_SET_FEATURE) { | |
2310 | dev->remote_wakeup = 1; | |
2311 | dev->dev_status |= (1 << wValue); | |
2312 | } else { | |
2313 | dev->remote_wakeup = 0; | |
2314 | dev->dev_status &= ~(1 << wValue); | |
2315 | } | |
2316 | break; | |
7fc56f0d LA |
2317 | case USB_DEVICE_TEST_MODE: |
2318 | dev_dbg(&dev->pdev->dev, "SETUP: TEST MODE\n"); | |
2319 | if ((wIndex & 0xff) || | |
2320 | (dev->gadget.speed != USB_SPEED_HIGH)) | |
2321 | ep0_stall(dev); | |
2322 | ||
2323 | switch (wIndex >> 8) { | |
2324 | case TEST_J: | |
2325 | case TEST_K: | |
2326 | case TEST_SE0_NAK: | |
2327 | case TEST_PACKET: | |
2328 | case TEST_FORCE_EN: | |
2329 | if (prime_status_phase(dev, EP_DIR_IN)) | |
2330 | ep0_stall(dev); | |
2331 | portsc1 = readl(&dev->op_regs->portsc1); | |
2332 | portsc1 |= (wIndex & 0xf00) << 8; | |
2333 | writel(portsc1, &dev->op_regs->portsc1); | |
2334 | goto end; | |
2335 | default: | |
2336 | rc = -EOPNOTSUPP; | |
2337 | } | |
2338 | break; | |
3211cbc2 J |
2339 | default: |
2340 | rc = -EOPNOTSUPP; | |
2341 | break; | |
2342 | } | |
2343 | ||
5be19a9d XS |
2344 | if (!gadget_is_otg(&dev->gadget)) |
2345 | break; | |
2346 | else if (setup->bRequest == USB_DEVICE_B_HNP_ENABLE) { | |
2347 | dev->gadget.b_hnp_enable = 1; | |
2348 | #ifdef OTG_TRANSCEIVER | |
2349 | if (!dev->lotg->otg.default_a) | |
2350 | dev->lotg->hsm.b_hnp_enable = 1; | |
2351 | #endif | |
2352 | } else if (setup->bRequest == USB_DEVICE_A_HNP_SUPPORT) | |
2353 | dev->gadget.a_hnp_support = 1; | |
2354 | else if (setup->bRequest == | |
2355 | USB_DEVICE_A_ALT_HNP_SUPPORT) | |
2356 | dev->gadget.a_alt_hnp_support = 1; | |
2357 | else | |
2358 | break; | |
5be19a9d XS |
2359 | } else |
2360 | break; | |
2361 | ||
2362 | if (rc == 0) { | |
2363 | if (prime_status_phase(dev, EP_DIR_IN)) | |
2364 | ep0_stall(dev); | |
2365 | } | |
2366 | goto end; | |
2367 | } | |
2368 | ||
2369 | case USB_REQ_GET_DESCRIPTOR: | |
5f81f4b0 J |
2370 | dev_dbg(&dev->pdev->dev, |
2371 | "SETUP: USB_REQ_GET_DESCRIPTOR\n"); | |
5be19a9d XS |
2372 | goto delegate; |
2373 | ||
2374 | case USB_REQ_SET_DESCRIPTOR: | |
5f81f4b0 J |
2375 | dev_dbg(&dev->pdev->dev, |
2376 | "SETUP: USB_REQ_SET_DESCRIPTOR unsupported\n"); | |
5be19a9d XS |
2377 | goto delegate; |
2378 | ||
2379 | case USB_REQ_GET_CONFIGURATION: | |
5f81f4b0 J |
2380 | dev_dbg(&dev->pdev->dev, |
2381 | "SETUP: USB_REQ_GET_CONFIGURATION\n"); | |
5be19a9d XS |
2382 | goto delegate; |
2383 | ||
2384 | case USB_REQ_SET_CONFIGURATION: | |
5f81f4b0 J |
2385 | dev_dbg(&dev->pdev->dev, |
2386 | "SETUP: USB_REQ_SET_CONFIGURATION\n"); | |
5be19a9d XS |
2387 | goto delegate; |
2388 | ||
2389 | case USB_REQ_GET_INTERFACE: | |
5f81f4b0 J |
2390 | dev_dbg(&dev->pdev->dev, |
2391 | "SETUP: USB_REQ_GET_INTERFACE\n"); | |
5be19a9d XS |
2392 | goto delegate; |
2393 | ||
2394 | case USB_REQ_SET_INTERFACE: | |
5f81f4b0 J |
2395 | dev_dbg(&dev->pdev->dev, |
2396 | "SETUP: USB_REQ_SET_INTERFACE\n"); | |
5be19a9d XS |
2397 | goto delegate; |
2398 | ||
2399 | case USB_REQ_SYNCH_FRAME: | |
5f81f4b0 J |
2400 | dev_dbg(&dev->pdev->dev, |
2401 | "SETUP: USB_REQ_SYNCH_FRAME unsupported\n"); | |
5be19a9d XS |
2402 | goto delegate; |
2403 | ||
2404 | default: | |
2405 | /* delegate USB standard requests to the gadget driver */ | |
2406 | goto delegate; | |
2407 | delegate: | |
2408 | /* USB requests handled by gadget */ | |
2409 | if (wLength) { | |
2410 | /* DATA phase from gadget, STATUS phase from udc */ | |
2411 | dev->ep0_dir = (setup->bRequestType & USB_DIR_IN) | |
2412 | ? USB_DIR_IN : USB_DIR_OUT; | |
5f81f4b0 J |
2413 | dev_vdbg(&dev->pdev->dev, |
2414 | "dev->ep0_dir = 0x%x, wLength = %d\n", | |
5be19a9d XS |
2415 | dev->ep0_dir, wLength); |
2416 | spin_unlock(&dev->lock); | |
2417 | if (dev->driver->setup(&dev->gadget, | |
2418 | &dev->local_setup_buff) < 0) | |
2419 | ep0_stall(dev); | |
2420 | spin_lock(&dev->lock); | |
2421 | dev->ep0_state = (setup->bRequestType & USB_DIR_IN) | |
2422 | ? DATA_STATE_XMIT : DATA_STATE_RECV; | |
2423 | } else { | |
2424 | /* no DATA phase, IN STATUS phase from gadget */ | |
2425 | dev->ep0_dir = USB_DIR_IN; | |
5f81f4b0 J |
2426 | dev_vdbg(&dev->pdev->dev, |
2427 | "dev->ep0_dir = 0x%x, wLength = %d\n", | |
5be19a9d XS |
2428 | dev->ep0_dir, wLength); |
2429 | spin_unlock(&dev->lock); | |
2430 | if (dev->driver->setup(&dev->gadget, | |
2431 | &dev->local_setup_buff) < 0) | |
2432 | ep0_stall(dev); | |
2433 | spin_lock(&dev->lock); | |
2434 | dev->ep0_state = WAIT_FOR_OUT_STATUS; | |
2435 | } | |
2436 | break; | |
2437 | } | |
2438 | end: | |
5f81f4b0 | 2439 | dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__); |
5be19a9d XS |
2440 | } |
2441 | ||
2442 | ||
2443 | /* transfer completion, process endpoint request and free the completed dTDs | |
2444 | * for this request | |
2445 | */ | |
2446 | static int process_ep_req(struct langwell_udc *dev, int index, | |
2447 | struct langwell_request *curr_req) | |
2448 | { | |
2449 | struct langwell_dtd *curr_dtd; | |
2450 | struct langwell_dqh *curr_dqh; | |
2451 | int td_complete, actual, remaining_length; | |
2452 | int i, dir; | |
2453 | u8 dtd_status = 0; | |
2454 | int retval = 0; | |
2455 | ||
2456 | curr_dqh = &dev->ep_dqh[index]; | |
2457 | dir = index % 2; | |
2458 | ||
2459 | curr_dtd = curr_req->head; | |
2460 | td_complete = 0; | |
2461 | actual = curr_req->req.length; | |
2462 | ||
5f81f4b0 | 2463 | dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
2464 | |
2465 | for (i = 0; i < curr_req->dtd_count; i++) { | |
5be19a9d XS |
2466 | |
2467 | /* command execution states by dTD */ | |
2468 | dtd_status = curr_dtd->dtd_status; | |
2469 | ||
c8458d59 CL |
2470 | barrier(); |
2471 | remaining_length = le16_to_cpu(curr_dtd->dtd_total); | |
2472 | actual -= remaining_length; | |
2473 | ||
5be19a9d XS |
2474 | if (!dtd_status) { |
2475 | /* transfers completed successfully */ | |
2476 | if (!remaining_length) { | |
2477 | td_complete++; | |
5f81f4b0 J |
2478 | dev_vdbg(&dev->pdev->dev, |
2479 | "dTD transmitted successfully\n"); | |
5be19a9d XS |
2480 | } else { |
2481 | if (dir) { | |
5f81f4b0 J |
2482 | dev_vdbg(&dev->pdev->dev, |
2483 | "TX dTD remains data\n"); | |
5be19a9d XS |
2484 | retval = -EPROTO; |
2485 | break; | |
2486 | ||
2487 | } else { | |
2488 | td_complete++; | |
2489 | break; | |
2490 | } | |
2491 | } | |
2492 | } else { | |
2493 | /* transfers completed with errors */ | |
2494 | if (dtd_status & DTD_STS_ACTIVE) { | |
5f81f4b0 J |
2495 | dev_dbg(&dev->pdev->dev, |
2496 | "dTD status ACTIVE dQH[%d]\n", index); | |
5be19a9d XS |
2497 | retval = 1; |
2498 | return retval; | |
2499 | } else if (dtd_status & DTD_STS_HALTED) { | |
5f81f4b0 J |
2500 | dev_err(&dev->pdev->dev, |
2501 | "dTD error %08x dQH[%d]\n", | |
2502 | dtd_status, index); | |
5be19a9d XS |
2503 | /* clear the errors and halt condition */ |
2504 | curr_dqh->dtd_status = 0; | |
2505 | retval = -EPIPE; | |
2506 | break; | |
2507 | } else if (dtd_status & DTD_STS_DBE) { | |
5f81f4b0 J |
2508 | dev_dbg(&dev->pdev->dev, |
2509 | "data buffer (overflow) error\n"); | |
5be19a9d XS |
2510 | retval = -EPROTO; |
2511 | break; | |
2512 | } else if (dtd_status & DTD_STS_TRE) { | |
5f81f4b0 J |
2513 | dev_dbg(&dev->pdev->dev, |
2514 | "transaction(ISO) error\n"); | |
5be19a9d XS |
2515 | retval = -EILSEQ; |
2516 | break; | |
2517 | } else | |
5f81f4b0 J |
2518 | dev_err(&dev->pdev->dev, |
2519 | "unknown error (0x%x)!\n", | |
2520 | dtd_status); | |
5be19a9d XS |
2521 | } |
2522 | ||
2523 | if (i != curr_req->dtd_count - 1) | |
2524 | curr_dtd = (struct langwell_dtd *) | |
2525 | curr_dtd->next_dtd_virt; | |
2526 | } | |
2527 | ||
2528 | if (retval) | |
2529 | return retval; | |
2530 | ||
2531 | curr_req->req.actual = actual; | |
2532 | ||
5f81f4b0 | 2533 | dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__); |
5be19a9d XS |
2534 | return 0; |
2535 | } | |
2536 | ||
2537 | ||
2538 | /* complete DATA or STATUS phase of ep0 prime status phase if needed */ | |
2539 | static void ep0_req_complete(struct langwell_udc *dev, | |
2540 | struct langwell_ep *ep0, struct langwell_request *req) | |
2541 | { | |
2542 | u32 new_addr; | |
5f81f4b0 | 2543 | dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
2544 | |
2545 | if (dev->usb_state == USB_STATE_ADDRESS) { | |
2546 | /* set the new address */ | |
2547 | new_addr = (u32)dev->dev_addr; | |
2548 | writel(new_addr << USBADR_SHIFT, &dev->op_regs->deviceaddr); | |
2549 | ||
2550 | new_addr = USBADR(readl(&dev->op_regs->deviceaddr)); | |
5f81f4b0 | 2551 | dev_vdbg(&dev->pdev->dev, "new_addr = %d\n", new_addr); |
5be19a9d XS |
2552 | } |
2553 | ||
2554 | done(ep0, req, 0); | |
2555 | ||
2556 | switch (dev->ep0_state) { | |
2557 | case DATA_STATE_XMIT: | |
2558 | /* receive status phase */ | |
2559 | if (prime_status_phase(dev, EP_DIR_OUT)) | |
2560 | ep0_stall(dev); | |
2561 | break; | |
2562 | case DATA_STATE_RECV: | |
2563 | /* send status phase */ | |
2564 | if (prime_status_phase(dev, EP_DIR_IN)) | |
2565 | ep0_stall(dev); | |
2566 | break; | |
2567 | case WAIT_FOR_OUT_STATUS: | |
2568 | dev->ep0_state = WAIT_FOR_SETUP; | |
2569 | break; | |
2570 | case WAIT_FOR_SETUP: | |
5f81f4b0 | 2571 | dev_err(&dev->pdev->dev, "unexpect ep0 packets\n"); |
5be19a9d XS |
2572 | break; |
2573 | default: | |
2574 | ep0_stall(dev); | |
2575 | break; | |
2576 | } | |
2577 | ||
5f81f4b0 | 2578 | dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__); |
5be19a9d XS |
2579 | } |
2580 | ||
2581 | ||
2582 | /* USB transfer completion interrupt */ | |
2583 | static void handle_trans_complete(struct langwell_udc *dev) | |
2584 | { | |
2585 | u32 complete_bits; | |
2586 | int i, ep_num, dir, bit_mask, status; | |
2587 | struct langwell_ep *epn; | |
2588 | struct langwell_request *curr_req, *temp_req; | |
2589 | ||
5f81f4b0 | 2590 | dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
2591 | |
2592 | complete_bits = readl(&dev->op_regs->endptcomplete); | |
5f81f4b0 J |
2593 | dev_vdbg(&dev->pdev->dev, "endptcomplete register: 0x%08x\n", |
2594 | complete_bits); | |
5be19a9d XS |
2595 | |
2596 | /* Write-Clear the bits in endptcomplete register */ | |
2597 | writel(complete_bits, &dev->op_regs->endptcomplete); | |
2598 | ||
2599 | if (!complete_bits) { | |
5f81f4b0 | 2600 | dev_dbg(&dev->pdev->dev, "complete_bits = 0\n"); |
5be19a9d XS |
2601 | goto done; |
2602 | } | |
2603 | ||
2604 | for (i = 0; i < dev->ep_max; i++) { | |
2605 | ep_num = i / 2; | |
2606 | dir = i % 2; | |
2607 | ||
2608 | bit_mask = 1 << (ep_num + 16 * dir); | |
2609 | ||
2610 | if (!(complete_bits & bit_mask)) | |
2611 | continue; | |
2612 | ||
2613 | /* ep0 */ | |
2614 | if (i == 1) | |
2615 | epn = &dev->ep[0]; | |
2616 | else | |
2617 | epn = &dev->ep[i]; | |
2618 | ||
2619 | if (epn->name == NULL) { | |
5f81f4b0 | 2620 | dev_warn(&dev->pdev->dev, "invalid endpoint\n"); |
5be19a9d XS |
2621 | continue; |
2622 | } | |
2623 | ||
2624 | if (i < 2) | |
2625 | /* ep0 in and out */ | |
5f81f4b0 | 2626 | dev_dbg(&dev->pdev->dev, "%s-%s transfer completed\n", |
5be19a9d XS |
2627 | epn->name, |
2628 | is_in(epn) ? "in" : "out"); | |
2629 | else | |
5f81f4b0 J |
2630 | dev_dbg(&dev->pdev->dev, "%s transfer completed\n", |
2631 | epn->name); | |
5be19a9d XS |
2632 | |
2633 | /* process the req queue until an uncomplete request */ | |
2634 | list_for_each_entry_safe(curr_req, temp_req, | |
2635 | &epn->queue, queue) { | |
2636 | status = process_ep_req(dev, i, curr_req); | |
5f81f4b0 J |
2637 | dev_vdbg(&dev->pdev->dev, "%s req status: %d\n", |
2638 | epn->name, status); | |
5be19a9d XS |
2639 | |
2640 | if (status) | |
2641 | break; | |
2642 | ||
2643 | /* write back status to req */ | |
2644 | curr_req->req.status = status; | |
2645 | ||
2646 | /* ep0 request completion */ | |
2647 | if (ep_num == 0) { | |
2648 | ep0_req_complete(dev, epn, curr_req); | |
2649 | break; | |
2650 | } else { | |
2651 | done(epn, curr_req, status); | |
2652 | } | |
2653 | } | |
2654 | } | |
2655 | done: | |
5f81f4b0 | 2656 | dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__); |
5be19a9d XS |
2657 | } |
2658 | ||
2659 | ||
2660 | /* port change detect interrupt handler */ | |
2661 | static void handle_port_change(struct langwell_udc *dev) | |
2662 | { | |
2663 | u32 portsc1, devlc; | |
2664 | u32 speed; | |
2665 | ||
5f81f4b0 | 2666 | dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
2667 | |
2668 | if (dev->bus_reset) | |
2669 | dev->bus_reset = 0; | |
2670 | ||
2671 | portsc1 = readl(&dev->op_regs->portsc1); | |
2672 | devlc = readl(&dev->op_regs->devlc); | |
5f81f4b0 | 2673 | dev_vdbg(&dev->pdev->dev, "portsc1 = 0x%08x, devlc = 0x%08x\n", |
5be19a9d XS |
2674 | portsc1, devlc); |
2675 | ||
2676 | /* bus reset is finished */ | |
2677 | if (!(portsc1 & PORTS_PR)) { | |
2678 | /* get the speed */ | |
2679 | speed = LPM_PSPD(devlc); | |
2680 | switch (speed) { | |
2681 | case LPM_SPEED_HIGH: | |
2682 | dev->gadget.speed = USB_SPEED_HIGH; | |
2683 | break; | |
2684 | case LPM_SPEED_FULL: | |
2685 | dev->gadget.speed = USB_SPEED_FULL; | |
2686 | break; | |
2687 | case LPM_SPEED_LOW: | |
2688 | dev->gadget.speed = USB_SPEED_LOW; | |
2689 | break; | |
2690 | default: | |
2691 | dev->gadget.speed = USB_SPEED_UNKNOWN; | |
2692 | break; | |
2693 | } | |
5f81f4b0 J |
2694 | dev_vdbg(&dev->pdev->dev, |
2695 | "speed = %d, dev->gadget.speed = %d\n", | |
5be19a9d XS |
2696 | speed, dev->gadget.speed); |
2697 | } | |
2698 | ||
2699 | /* LPM L0 to L1 */ | |
2700 | if (dev->lpm && dev->lpm_state == LPM_L0) | |
2701 | if (portsc1 & PORTS_SUSP && portsc1 & PORTS_SLP) { | |
5f81f4b0 J |
2702 | dev_info(&dev->pdev->dev, "LPM L0 to L1\n"); |
2703 | dev->lpm_state = LPM_L1; | |
5be19a9d XS |
2704 | } |
2705 | ||
2706 | /* LPM L1 to L0, force resume or remote wakeup finished */ | |
2707 | if (dev->lpm && dev->lpm_state == LPM_L1) | |
2708 | if (!(portsc1 & PORTS_SUSP)) { | |
5f81f4b0 | 2709 | dev_info(&dev->pdev->dev, "LPM L1 to L0\n"); |
5be19a9d XS |
2710 | dev->lpm_state = LPM_L0; |
2711 | } | |
2712 | ||
2713 | /* update USB state */ | |
2714 | if (!dev->resume_state) | |
2715 | dev->usb_state = USB_STATE_DEFAULT; | |
2716 | ||
5f81f4b0 | 2717 | dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__); |
5be19a9d XS |
2718 | } |
2719 | ||
2720 | ||
2721 | /* USB reset interrupt handler */ | |
2722 | static void handle_usb_reset(struct langwell_udc *dev) | |
2723 | { | |
2724 | u32 deviceaddr, | |
2725 | endptsetupstat, | |
2726 | endptcomplete; | |
2727 | unsigned long timeout; | |
2728 | ||
5f81f4b0 | 2729 | dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
2730 | |
2731 | /* Write-Clear the device address */ | |
2732 | deviceaddr = readl(&dev->op_regs->deviceaddr); | |
2733 | writel(deviceaddr & ~USBADR_MASK, &dev->op_regs->deviceaddr); | |
2734 | ||
2735 | dev->dev_addr = 0; | |
2736 | ||
2737 | /* clear usb state */ | |
2738 | dev->resume_state = 0; | |
2739 | ||
2740 | /* LPM L1 to L0, reset */ | |
2741 | if (dev->lpm) | |
2742 | dev->lpm_state = LPM_L0; | |
2743 | ||
2744 | dev->ep0_dir = USB_DIR_OUT; | |
2745 | dev->ep0_state = WAIT_FOR_SETUP; | |
3211cbc2 J |
2746 | |
2747 | /* remote wakeup reset to 0 when the device is reset */ | |
2748 | dev->remote_wakeup = 0; | |
2749 | dev->dev_status = 1 << USB_DEVICE_SELF_POWERED; | |
5be19a9d XS |
2750 | dev->gadget.b_hnp_enable = 0; |
2751 | dev->gadget.a_hnp_support = 0; | |
2752 | dev->gadget.a_alt_hnp_support = 0; | |
2753 | ||
2754 | /* Write-Clear all the setup token semaphores */ | |
2755 | endptsetupstat = readl(&dev->op_regs->endptsetupstat); | |
2756 | writel(endptsetupstat, &dev->op_regs->endptsetupstat); | |
2757 | ||
2758 | /* Write-Clear all the endpoint complete status bits */ | |
2759 | endptcomplete = readl(&dev->op_regs->endptcomplete); | |
2760 | writel(endptcomplete, &dev->op_regs->endptcomplete); | |
2761 | ||
2762 | /* wait until all endptprime bits cleared */ | |
2763 | timeout = jiffies + PRIME_TIMEOUT; | |
2764 | while (readl(&dev->op_regs->endptprime)) { | |
2765 | if (time_after(jiffies, timeout)) { | |
5f81f4b0 | 2766 | dev_err(&dev->pdev->dev, "USB reset timeout\n"); |
5be19a9d XS |
2767 | break; |
2768 | } | |
2769 | cpu_relax(); | |
2770 | } | |
2771 | ||
2772 | /* write 1s to endptflush register to clear any primed buffers */ | |
2773 | writel((u32) ~0, &dev->op_regs->endptflush); | |
2774 | ||
2775 | if (readl(&dev->op_regs->portsc1) & PORTS_PR) { | |
5f81f4b0 | 2776 | dev_vdbg(&dev->pdev->dev, "USB bus reset\n"); |
5be19a9d XS |
2777 | /* bus is reseting */ |
2778 | dev->bus_reset = 1; | |
2779 | ||
2780 | /* reset all the queues, stop all USB activities */ | |
2781 | stop_activity(dev, dev->driver); | |
2782 | dev->usb_state = USB_STATE_DEFAULT; | |
2783 | } else { | |
5f81f4b0 | 2784 | dev_vdbg(&dev->pdev->dev, "device controller reset\n"); |
5be19a9d XS |
2785 | /* controller reset */ |
2786 | langwell_udc_reset(dev); | |
2787 | ||
2788 | /* reset all the queues, stop all USB activities */ | |
2789 | stop_activity(dev, dev->driver); | |
2790 | ||
2791 | /* reset ep0 dQH and endptctrl */ | |
2792 | ep0_reset(dev); | |
2793 | ||
2794 | /* enable interrupt and set controller to run state */ | |
2795 | langwell_udc_start(dev); | |
2796 | ||
2797 | dev->usb_state = USB_STATE_ATTACHED; | |
2798 | } | |
2799 | ||
2800 | #ifdef OTG_TRANSCEIVER | |
2801 | /* refer to USB OTG 6.6.2.3 b_hnp_en is cleared */ | |
2802 | if (!dev->lotg->otg.default_a) | |
2803 | dev->lotg->hsm.b_hnp_enable = 0; | |
2804 | #endif | |
2805 | ||
5f81f4b0 | 2806 | dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__); |
5be19a9d XS |
2807 | } |
2808 | ||
2809 | ||
2810 | /* USB bus suspend/resume interrupt */ | |
2811 | static void handle_bus_suspend(struct langwell_udc *dev) | |
2812 | { | |
5f81f4b0 | 2813 | dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
2814 | |
2815 | dev->resume_state = dev->usb_state; | |
2816 | dev->usb_state = USB_STATE_SUSPENDED; | |
2817 | ||
2818 | #ifdef OTG_TRANSCEIVER | |
2819 | if (dev->lotg->otg.default_a) { | |
2820 | if (dev->lotg->hsm.b_bus_suspend_vld == 1) { | |
2821 | dev->lotg->hsm.b_bus_suspend = 1; | |
2822 | /* notify transceiver the state changes */ | |
2823 | if (spin_trylock(&dev->lotg->wq_lock)) { | |
2824 | langwell_update_transceiver(); | |
2825 | spin_unlock(&dev->lotg->wq_lock); | |
2826 | } | |
2827 | } | |
2828 | dev->lotg->hsm.b_bus_suspend_vld++; | |
2829 | } else { | |
2830 | if (!dev->lotg->hsm.a_bus_suspend) { | |
2831 | dev->lotg->hsm.a_bus_suspend = 1; | |
2832 | /* notify transceiver the state changes */ | |
2833 | if (spin_trylock(&dev->lotg->wq_lock)) { | |
2834 | langwell_update_transceiver(); | |
2835 | spin_unlock(&dev->lotg->wq_lock); | |
2836 | } | |
2837 | } | |
2838 | } | |
2839 | #endif | |
2840 | ||
2841 | /* report suspend to the driver */ | |
2842 | if (dev->driver) { | |
2843 | if (dev->driver->suspend) { | |
2844 | spin_unlock(&dev->lock); | |
2845 | dev->driver->suspend(&dev->gadget); | |
2846 | spin_lock(&dev->lock); | |
5f81f4b0 J |
2847 | dev_dbg(&dev->pdev->dev, "suspend %s\n", |
2848 | dev->driver->driver.name); | |
5be19a9d XS |
2849 | } |
2850 | } | |
2851 | ||
2852 | /* enter PHY low power suspend */ | |
513b91b6 J |
2853 | if (dev->pdev->device != 0x0829) |
2854 | langwell_phy_low_power(dev, 0); | |
5be19a9d | 2855 | |
5f81f4b0 | 2856 | dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__); |
5be19a9d XS |
2857 | } |
2858 | ||
2859 | ||
2860 | static void handle_bus_resume(struct langwell_udc *dev) | |
2861 | { | |
5f81f4b0 | 2862 | dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
2863 | |
2864 | dev->usb_state = dev->resume_state; | |
2865 | dev->resume_state = 0; | |
2866 | ||
2867 | /* exit PHY low power suspend */ | |
513b91b6 J |
2868 | if (dev->pdev->device != 0x0829) |
2869 | langwell_phy_low_power(dev, 0); | |
5be19a9d XS |
2870 | |
2871 | #ifdef OTG_TRANSCEIVER | |
2872 | if (dev->lotg->otg.default_a == 0) | |
2873 | dev->lotg->hsm.a_bus_suspend = 0; | |
2874 | #endif | |
2875 | ||
2876 | /* report resume to the driver */ | |
2877 | if (dev->driver) { | |
2878 | if (dev->driver->resume) { | |
2879 | spin_unlock(&dev->lock); | |
2880 | dev->driver->resume(&dev->gadget); | |
2881 | spin_lock(&dev->lock); | |
5f81f4b0 J |
2882 | dev_dbg(&dev->pdev->dev, "resume %s\n", |
2883 | dev->driver->driver.name); | |
5be19a9d XS |
2884 | } |
2885 | } | |
2886 | ||
5f81f4b0 | 2887 | dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__); |
5be19a9d XS |
2888 | } |
2889 | ||
2890 | ||
2891 | /* USB device controller interrupt handler */ | |
2892 | static irqreturn_t langwell_irq(int irq, void *_dev) | |
2893 | { | |
2894 | struct langwell_udc *dev = _dev; | |
2895 | u32 usbsts, | |
2896 | usbintr, | |
2897 | irq_sts, | |
2898 | portsc1; | |
2899 | ||
5f81f4b0 | 2900 | dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
2901 | |
2902 | if (dev->stopped) { | |
5f81f4b0 J |
2903 | dev_vdbg(&dev->pdev->dev, "handle IRQ_NONE\n"); |
2904 | dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__); | |
5be19a9d XS |
2905 | return IRQ_NONE; |
2906 | } | |
2907 | ||
2908 | spin_lock(&dev->lock); | |
2909 | ||
2910 | /* USB status */ | |
2911 | usbsts = readl(&dev->op_regs->usbsts); | |
2912 | ||
2913 | /* USB interrupt enable */ | |
2914 | usbintr = readl(&dev->op_regs->usbintr); | |
2915 | ||
2916 | irq_sts = usbsts & usbintr; | |
5f81f4b0 J |
2917 | dev_vdbg(&dev->pdev->dev, |
2918 | "usbsts = 0x%08x, usbintr = 0x%08x, irq_sts = 0x%08x\n", | |
5be19a9d XS |
2919 | usbsts, usbintr, irq_sts); |
2920 | ||
2921 | if (!irq_sts) { | |
5f81f4b0 J |
2922 | dev_vdbg(&dev->pdev->dev, "handle IRQ_NONE\n"); |
2923 | dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__); | |
5be19a9d XS |
2924 | spin_unlock(&dev->lock); |
2925 | return IRQ_NONE; | |
2926 | } | |
2927 | ||
2928 | /* Write-Clear interrupt status bits */ | |
2929 | writel(irq_sts, &dev->op_regs->usbsts); | |
2930 | ||
2931 | /* resume from suspend */ | |
2932 | portsc1 = readl(&dev->op_regs->portsc1); | |
2933 | if (dev->usb_state == USB_STATE_SUSPENDED) | |
2934 | if (!(portsc1 & PORTS_SUSP)) | |
2935 | handle_bus_resume(dev); | |
2936 | ||
2937 | /* USB interrupt */ | |
2938 | if (irq_sts & STS_UI) { | |
5f81f4b0 | 2939 | dev_vdbg(&dev->pdev->dev, "USB interrupt\n"); |
5be19a9d XS |
2940 | |
2941 | /* setup packet received from ep0 */ | |
2942 | if (readl(&dev->op_regs->endptsetupstat) | |
2943 | & EP0SETUPSTAT_MASK) { | |
5f81f4b0 J |
2944 | dev_vdbg(&dev->pdev->dev, |
2945 | "USB SETUP packet received interrupt\n"); | |
5be19a9d XS |
2946 | /* setup tripwire semaphone */ |
2947 | setup_tripwire(dev); | |
2948 | handle_setup_packet(dev, &dev->local_setup_buff); | |
2949 | } | |
2950 | ||
2951 | /* USB transfer completion */ | |
2952 | if (readl(&dev->op_regs->endptcomplete)) { | |
5f81f4b0 J |
2953 | dev_vdbg(&dev->pdev->dev, |
2954 | "USB transfer completion interrupt\n"); | |
5be19a9d XS |
2955 | handle_trans_complete(dev); |
2956 | } | |
2957 | } | |
2958 | ||
2959 | /* SOF received interrupt (for ISO transfer) */ | |
2960 | if (irq_sts & STS_SRI) { | |
2961 | /* FIXME */ | |
5f81f4b0 | 2962 | /* dev_vdbg(&dev->pdev->dev, "SOF received interrupt\n"); */ |
5be19a9d XS |
2963 | } |
2964 | ||
2965 | /* port change detect interrupt */ | |
2966 | if (irq_sts & STS_PCI) { | |
5f81f4b0 | 2967 | dev_vdbg(&dev->pdev->dev, "port change detect interrupt\n"); |
5be19a9d XS |
2968 | handle_port_change(dev); |
2969 | } | |
2970 | ||
2971 | /* suspend interrrupt */ | |
2972 | if (irq_sts & STS_SLI) { | |
5f81f4b0 | 2973 | dev_vdbg(&dev->pdev->dev, "suspend interrupt\n"); |
5be19a9d XS |
2974 | handle_bus_suspend(dev); |
2975 | } | |
2976 | ||
2977 | /* USB reset interrupt */ | |
2978 | if (irq_sts & STS_URI) { | |
5f81f4b0 | 2979 | dev_vdbg(&dev->pdev->dev, "USB reset interrupt\n"); |
5be19a9d XS |
2980 | handle_usb_reset(dev); |
2981 | } | |
2982 | ||
2983 | /* USB error or system error interrupt */ | |
2984 | if (irq_sts & (STS_UEI | STS_SEI)) { | |
2985 | /* FIXME */ | |
5f81f4b0 | 2986 | dev_warn(&dev->pdev->dev, "error IRQ, irq_sts: %x\n", irq_sts); |
5be19a9d XS |
2987 | } |
2988 | ||
2989 | spin_unlock(&dev->lock); | |
2990 | ||
5f81f4b0 | 2991 | dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__); |
5be19a9d XS |
2992 | return IRQ_HANDLED; |
2993 | } | |
2994 | ||
2995 | ||
2996 | /*-------------------------------------------------------------------------*/ | |
2997 | ||
2998 | /* release device structure */ | |
2999 | static void gadget_release(struct device *_dev) | |
3000 | { | |
3001 | struct langwell_udc *dev = the_controller; | |
3002 | ||
5f81f4b0 | 3003 | dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
3004 | |
3005 | complete(dev->done); | |
3006 | ||
5f81f4b0 | 3007 | dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__); |
5be19a9d XS |
3008 | kfree(dev); |
3009 | } | |
3010 | ||
3011 | ||
912c93d1 J |
3012 | /* enable SRAM caching if SRAM detected */ |
3013 | static void sram_init(struct langwell_udc *dev) | |
3014 | { | |
3015 | struct pci_dev *pdev = dev->pdev; | |
3016 | ||
3017 | dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__); | |
3018 | ||
3019 | dev->sram_addr = pci_resource_start(pdev, 1); | |
3020 | dev->sram_size = pci_resource_len(pdev, 1); | |
3021 | dev_info(&dev->pdev->dev, "Found private SRAM at %x size:%x\n", | |
3022 | dev->sram_addr, dev->sram_size); | |
3023 | dev->got_sram = 1; | |
3024 | ||
3025 | if (pci_request_region(pdev, 1, kobject_name(&pdev->dev.kobj))) { | |
3026 | dev_warn(&dev->pdev->dev, "SRAM request failed\n"); | |
3027 | dev->got_sram = 0; | |
3028 | } else if (!dma_declare_coherent_memory(&pdev->dev, dev->sram_addr, | |
3029 | dev->sram_addr, dev->sram_size, DMA_MEMORY_MAP)) { | |
3030 | dev_warn(&dev->pdev->dev, "SRAM DMA declare failed\n"); | |
3031 | pci_release_region(pdev, 1); | |
3032 | dev->got_sram = 0; | |
3033 | } | |
3034 | ||
3035 | dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__); | |
3036 | } | |
3037 | ||
3038 | ||
3039 | /* release SRAM caching */ | |
3040 | static void sram_deinit(struct langwell_udc *dev) | |
3041 | { | |
3042 | struct pci_dev *pdev = dev->pdev; | |
3043 | ||
3044 | dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__); | |
3045 | ||
3046 | dma_release_declared_memory(&pdev->dev); | |
3047 | pci_release_region(pdev, 1); | |
3048 | ||
3049 | dev->got_sram = 0; | |
3050 | ||
3051 | dev_info(&dev->pdev->dev, "release SRAM caching\n"); | |
3052 | dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__); | |
3053 | } | |
3054 | ||
3055 | ||
5be19a9d XS |
3056 | /* tear down the binding between this driver and the pci device */ |
3057 | static void langwell_udc_remove(struct pci_dev *pdev) | |
3058 | { | |
3059 | struct langwell_udc *dev = the_controller; | |
3060 | ||
3061 | DECLARE_COMPLETION(done); | |
3062 | ||
3063 | BUG_ON(dev->driver); | |
5f81f4b0 | 3064 | dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
3065 | |
3066 | dev->done = &done; | |
3067 | ||
912c93d1 J |
3068 | #ifndef OTG_TRANSCEIVER |
3069 | /* free dTD dma_pool and dQH */ | |
5be19a9d XS |
3070 | if (dev->dtd_pool) |
3071 | dma_pool_destroy(dev->dtd_pool); | |
3072 | ||
912c93d1 J |
3073 | if (dev->ep_dqh) |
3074 | dma_free_coherent(&pdev->dev, dev->ep_dqh_size, | |
3075 | dev->ep_dqh, dev->ep_dqh_dma); | |
3076 | ||
3077 | /* release SRAM caching */ | |
3078 | if (dev->has_sram && dev->got_sram) | |
3079 | sram_deinit(dev); | |
3080 | #endif | |
3081 | ||
5be19a9d XS |
3082 | if (dev->status_req) { |
3083 | kfree(dev->status_req->req.buf); | |
3084 | kfree(dev->status_req); | |
3085 | } | |
3086 | ||
5be19a9d XS |
3087 | kfree(dev->ep); |
3088 | ||
48e34d0f | 3089 | /* disable IRQ handler */ |
5be19a9d XS |
3090 | if (dev->got_irq) |
3091 | free_irq(pdev->irq, dev); | |
3092 | ||
3093 | #ifndef OTG_TRANSCEIVER | |
3094 | if (dev->cap_regs) | |
3095 | iounmap(dev->cap_regs); | |
3096 | ||
3097 | if (dev->region) | |
3098 | release_mem_region(pci_resource_start(pdev, 0), | |
3099 | pci_resource_len(pdev, 0)); | |
3100 | ||
3101 | if (dev->enabled) | |
3102 | pci_disable_device(pdev); | |
3103 | #else | |
3104 | if (dev->transceiver) { | |
3105 | otg_put_transceiver(dev->transceiver); | |
3106 | dev->transceiver = NULL; | |
3107 | dev->lotg = NULL; | |
3108 | } | |
3109 | #endif | |
3110 | ||
3111 | dev->cap_regs = NULL; | |
3112 | ||
5f81f4b0 J |
3113 | dev_info(&dev->pdev->dev, "unbind\n"); |
3114 | dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__); | |
5be19a9d XS |
3115 | |
3116 | device_unregister(&dev->gadget.dev); | |
3117 | device_remove_file(&pdev->dev, &dev_attr_langwell_udc); | |
3211cbc2 | 3118 | device_remove_file(&pdev->dev, &dev_attr_remote_wakeup); |
5be19a9d XS |
3119 | |
3120 | #ifndef OTG_TRANSCEIVER | |
3121 | pci_set_drvdata(pdev, NULL); | |
3122 | #endif | |
3123 | ||
3124 | /* free dev, wait for the release() finished */ | |
3125 | wait_for_completion(&done); | |
3126 | ||
3127 | the_controller = NULL; | |
3128 | } | |
3129 | ||
3130 | ||
3131 | /* | |
3132 | * wrap this driver around the specified device, but | |
3133 | * don't respond over USB until a gadget driver binds to us. | |
3134 | */ | |
3135 | static int langwell_udc_probe(struct pci_dev *pdev, | |
3136 | const struct pci_device_id *id) | |
3137 | { | |
3138 | struct langwell_udc *dev; | |
3139 | #ifndef OTG_TRANSCEIVER | |
3140 | unsigned long resource, len; | |
3141 | #endif | |
3142 | void __iomem *base = NULL; | |
3143 | size_t size; | |
3144 | int retval; | |
3145 | ||
3146 | if (the_controller) { | |
3147 | dev_warn(&pdev->dev, "ignoring\n"); | |
3148 | return -EBUSY; | |
3149 | } | |
3150 | ||
3151 | /* alloc, and start init */ | |
3152 | dev = kzalloc(sizeof *dev, GFP_KERNEL); | |
3153 | if (dev == NULL) { | |
3154 | retval = -ENOMEM; | |
3155 | goto error; | |
3156 | } | |
3157 | ||
3158 | /* initialize device spinlock */ | |
3159 | spin_lock_init(&dev->lock); | |
3160 | ||
3161 | dev->pdev = pdev; | |
5f81f4b0 | 3162 | dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
3163 | |
3164 | #ifdef OTG_TRANSCEIVER | |
3165 | /* PCI device is already enabled by otg_transceiver driver */ | |
3166 | dev->enabled = 1; | |
3167 | ||
3168 | /* mem region and register base */ | |
3169 | dev->region = 1; | |
3170 | dev->transceiver = otg_get_transceiver(); | |
3171 | dev->lotg = otg_to_langwell(dev->transceiver); | |
3172 | base = dev->lotg->regs; | |
3173 | #else | |
3174 | pci_set_drvdata(pdev, dev); | |
3175 | ||
3176 | /* now all the pci goodies ... */ | |
3177 | if (pci_enable_device(pdev) < 0) { | |
3178 | retval = -ENODEV; | |
3179 | goto error; | |
3180 | } | |
3181 | dev->enabled = 1; | |
3182 | ||
3183 | /* control register: BAR 0 */ | |
3184 | resource = pci_resource_start(pdev, 0); | |
3185 | len = pci_resource_len(pdev, 0); | |
3186 | if (!request_mem_region(resource, len, driver_name)) { | |
5f81f4b0 | 3187 | dev_err(&dev->pdev->dev, "controller already in use\n"); |
5be19a9d XS |
3188 | retval = -EBUSY; |
3189 | goto error; | |
3190 | } | |
3191 | dev->region = 1; | |
3192 | ||
3193 | base = ioremap_nocache(resource, len); | |
3194 | #endif | |
3195 | if (base == NULL) { | |
5f81f4b0 | 3196 | dev_err(&dev->pdev->dev, "can't map memory\n"); |
5be19a9d XS |
3197 | retval = -EFAULT; |
3198 | goto error; | |
3199 | } | |
3200 | ||
3201 | dev->cap_regs = (struct langwell_cap_regs __iomem *) base; | |
5f81f4b0 | 3202 | dev_vdbg(&dev->pdev->dev, "dev->cap_regs: %p\n", dev->cap_regs); |
5be19a9d XS |
3203 | dev->op_regs = (struct langwell_op_regs __iomem *) |
3204 | (base + OP_REG_OFFSET); | |
5f81f4b0 | 3205 | dev_vdbg(&dev->pdev->dev, "dev->op_regs: %p\n", dev->op_regs); |
5be19a9d XS |
3206 | |
3207 | /* irq setup after old hardware is cleaned up */ | |
3208 | if (!pdev->irq) { | |
5f81f4b0 | 3209 | dev_err(&dev->pdev->dev, "No IRQ. Check PCI setup!\n"); |
5be19a9d XS |
3210 | retval = -ENODEV; |
3211 | goto error; | |
3212 | } | |
3213 | ||
912c93d1 J |
3214 | dev->has_sram = 1; |
3215 | dev->got_sram = 0; | |
3216 | dev_vdbg(&dev->pdev->dev, "dev->has_sram: %d\n", dev->has_sram); | |
3217 | ||
5be19a9d | 3218 | #ifndef OTG_TRANSCEIVER |
912c93d1 J |
3219 | /* enable SRAM caching if detected */ |
3220 | if (dev->has_sram && !dev->got_sram) | |
3221 | sram_init(dev); | |
3222 | ||
5f81f4b0 J |
3223 | dev_info(&dev->pdev->dev, |
3224 | "irq %d, io mem: 0x%08lx, len: 0x%08lx, pci mem 0x%p\n", | |
5be19a9d XS |
3225 | pdev->irq, resource, len, base); |
3226 | /* enables bus-mastering for device dev */ | |
3227 | pci_set_master(pdev); | |
3228 | ||
3229 | if (request_irq(pdev->irq, langwell_irq, IRQF_SHARED, | |
3230 | driver_name, dev) != 0) { | |
5f81f4b0 J |
3231 | dev_err(&dev->pdev->dev, |
3232 | "request interrupt %d failed\n", pdev->irq); | |
5be19a9d XS |
3233 | retval = -EBUSY; |
3234 | goto error; | |
3235 | } | |
3236 | dev->got_irq = 1; | |
3237 | #endif | |
3238 | ||
3239 | /* set stopped bit */ | |
3240 | dev->stopped = 1; | |
3241 | ||
3242 | /* capabilities and endpoint number */ | |
3243 | dev->lpm = (readl(&dev->cap_regs->hccparams) & HCC_LEN) ? 1 : 0; | |
3244 | dev->dciversion = readw(&dev->cap_regs->dciversion); | |
3245 | dev->devcap = (readl(&dev->cap_regs->dccparams) & DEVCAP) ? 1 : 0; | |
5f81f4b0 J |
3246 | dev_vdbg(&dev->pdev->dev, "dev->lpm: %d\n", dev->lpm); |
3247 | dev_vdbg(&dev->pdev->dev, "dev->dciversion: 0x%04x\n", | |
3248 | dev->dciversion); | |
3249 | dev_vdbg(&dev->pdev->dev, "dccparams: 0x%08x\n", | |
3250 | readl(&dev->cap_regs->dccparams)); | |
3251 | dev_vdbg(&dev->pdev->dev, "dev->devcap: %d\n", dev->devcap); | |
5be19a9d | 3252 | if (!dev->devcap) { |
5f81f4b0 | 3253 | dev_err(&dev->pdev->dev, "can't support device mode\n"); |
5be19a9d XS |
3254 | retval = -ENODEV; |
3255 | goto error; | |
3256 | } | |
3257 | ||
3258 | /* a pair of endpoints (out/in) for each address */ | |
3259 | dev->ep_max = DEN(readl(&dev->cap_regs->dccparams)) * 2; | |
5f81f4b0 | 3260 | dev_vdbg(&dev->pdev->dev, "dev->ep_max: %d\n", dev->ep_max); |
5be19a9d XS |
3261 | |
3262 | /* allocate endpoints memory */ | |
3263 | dev->ep = kzalloc(sizeof(struct langwell_ep) * dev->ep_max, | |
3264 | GFP_KERNEL); | |
3265 | if (!dev->ep) { | |
5f81f4b0 | 3266 | dev_err(&dev->pdev->dev, "allocate endpoints memory failed\n"); |
5be19a9d XS |
3267 | retval = -ENOMEM; |
3268 | goto error; | |
3269 | } | |
3270 | ||
3271 | /* allocate device dQH memory */ | |
3272 | size = dev->ep_max * sizeof(struct langwell_dqh); | |
5f81f4b0 | 3273 | dev_vdbg(&dev->pdev->dev, "orig size = %d\n", size); |
5be19a9d XS |
3274 | if (size < DQH_ALIGNMENT) |
3275 | size = DQH_ALIGNMENT; | |
3276 | else if ((size % DQH_ALIGNMENT) != 0) { | |
3277 | size += DQH_ALIGNMENT + 1; | |
3278 | size &= ~(DQH_ALIGNMENT - 1); | |
3279 | } | |
3280 | dev->ep_dqh = dma_alloc_coherent(&pdev->dev, size, | |
3281 | &dev->ep_dqh_dma, GFP_KERNEL); | |
3282 | if (!dev->ep_dqh) { | |
5f81f4b0 | 3283 | dev_err(&dev->pdev->dev, "allocate dQH memory failed\n"); |
5be19a9d XS |
3284 | retval = -ENOMEM; |
3285 | goto error; | |
3286 | } | |
3287 | dev->ep_dqh_size = size; | |
5f81f4b0 | 3288 | dev_vdbg(&dev->pdev->dev, "ep_dqh_size = %d\n", dev->ep_dqh_size); |
5be19a9d XS |
3289 | |
3290 | /* initialize ep0 status request structure */ | |
3291 | dev->status_req = kzalloc(sizeof(struct langwell_request), GFP_KERNEL); | |
3292 | if (!dev->status_req) { | |
5f81f4b0 J |
3293 | dev_err(&dev->pdev->dev, |
3294 | "allocate status_req memory failed\n"); | |
5be19a9d XS |
3295 | retval = -ENOMEM; |
3296 | goto error; | |
3297 | } | |
3298 | INIT_LIST_HEAD(&dev->status_req->queue); | |
3299 | ||
3300 | /* allocate a small amount of memory to get valid address */ | |
3301 | dev->status_req->req.buf = kmalloc(8, GFP_KERNEL); | |
3302 | dev->status_req->req.dma = virt_to_phys(dev->status_req->req.buf); | |
3303 | ||
3304 | dev->resume_state = USB_STATE_NOTATTACHED; | |
3305 | dev->usb_state = USB_STATE_POWERED; | |
3306 | dev->ep0_dir = USB_DIR_OUT; | |
3211cbc2 J |
3307 | |
3308 | /* remote wakeup reset to 0 when the device is reset */ | |
3309 | dev->remote_wakeup = 0; | |
3310 | dev->dev_status = 1 << USB_DEVICE_SELF_POWERED; | |
5be19a9d XS |
3311 | |
3312 | #ifndef OTG_TRANSCEIVER | |
3313 | /* reset device controller */ | |
3314 | langwell_udc_reset(dev); | |
3315 | #endif | |
3316 | ||
3317 | /* initialize gadget structure */ | |
3318 | dev->gadget.ops = &langwell_ops; /* usb_gadget_ops */ | |
3319 | dev->gadget.ep0 = &dev->ep[0].ep; /* gadget ep0 */ | |
3320 | INIT_LIST_HEAD(&dev->gadget.ep_list); /* ep_list */ | |
3321 | dev->gadget.speed = USB_SPEED_UNKNOWN; /* speed */ | |
3322 | dev->gadget.is_dualspeed = 1; /* support dual speed */ | |
3323 | #ifdef OTG_TRANSCEIVER | |
3324 | dev->gadget.is_otg = 1; /* support otg mode */ | |
3325 | #endif | |
3326 | ||
3327 | /* the "gadget" abstracts/virtualizes the controller */ | |
3328 | dev_set_name(&dev->gadget.dev, "gadget"); | |
3329 | dev->gadget.dev.parent = &pdev->dev; | |
3330 | dev->gadget.dev.dma_mask = pdev->dev.dma_mask; | |
3331 | dev->gadget.dev.release = gadget_release; | |
3332 | dev->gadget.name = driver_name; /* gadget name */ | |
3333 | ||
3334 | /* controller endpoints reinit */ | |
3335 | eps_reinit(dev); | |
3336 | ||
3337 | #ifndef OTG_TRANSCEIVER | |
3338 | /* reset ep0 dQH and endptctrl */ | |
3339 | ep0_reset(dev); | |
3340 | #endif | |
3341 | ||
3342 | /* create dTD dma_pool resource */ | |
3343 | dev->dtd_pool = dma_pool_create("langwell_dtd", | |
3344 | &dev->pdev->dev, | |
3345 | sizeof(struct langwell_dtd), | |
3346 | DTD_ALIGNMENT, | |
3347 | DMA_BOUNDARY); | |
3348 | ||
3349 | if (!dev->dtd_pool) { | |
3350 | retval = -ENOMEM; | |
3351 | goto error; | |
3352 | } | |
3353 | ||
3354 | /* done */ | |
5f81f4b0 J |
3355 | dev_info(&dev->pdev->dev, "%s\n", driver_desc); |
3356 | dev_info(&dev->pdev->dev, "irq %d, pci mem %p\n", pdev->irq, base); | |
3357 | dev_info(&dev->pdev->dev, "Driver version: " DRIVER_VERSION "\n"); | |
3358 | dev_info(&dev->pdev->dev, "Support (max) %d endpoints\n", dev->ep_max); | |
3359 | dev_info(&dev->pdev->dev, "Device interface version: 0x%04x\n", | |
3360 | dev->dciversion); | |
3361 | dev_info(&dev->pdev->dev, "Controller mode: %s\n", | |
3362 | dev->devcap ? "Device" : "Host"); | |
3363 | dev_info(&dev->pdev->dev, "Support USB LPM: %s\n", | |
3364 | dev->lpm ? "Yes" : "No"); | |
3365 | ||
3366 | dev_vdbg(&dev->pdev->dev, | |
3367 | "After langwell_udc_probe(), print all registers:\n"); | |
5be19a9d | 3368 | print_all_registers(dev); |
5be19a9d XS |
3369 | |
3370 | the_controller = dev; | |
3371 | ||
3372 | retval = device_register(&dev->gadget.dev); | |
3373 | if (retval) | |
3374 | goto error; | |
3375 | ||
3376 | retval = device_create_file(&pdev->dev, &dev_attr_langwell_udc); | |
3377 | if (retval) | |
3378 | goto error; | |
3379 | ||
3211cbc2 J |
3380 | retval = device_create_file(&pdev->dev, &dev_attr_remote_wakeup); |
3381 | if (retval) | |
3382 | goto error_attr1; | |
3383 | ||
5f81f4b0 | 3384 | dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__); |
5be19a9d XS |
3385 | return 0; |
3386 | ||
3211cbc2 J |
3387 | error_attr1: |
3388 | device_remove_file(&pdev->dev, &dev_attr_langwell_udc); | |
5be19a9d XS |
3389 | error: |
3390 | if (dev) { | |
5f81f4b0 | 3391 | dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__); |
5be19a9d XS |
3392 | langwell_udc_remove(pdev); |
3393 | } | |
3394 | ||
3395 | return retval; | |
3396 | } | |
3397 | ||
3398 | ||
3399 | /* device controller suspend */ | |
3400 | static int langwell_udc_suspend(struct pci_dev *pdev, pm_message_t state) | |
3401 | { | |
3402 | struct langwell_udc *dev = the_controller; | |
5be19a9d | 3403 | |
5f81f4b0 | 3404 | dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
3405 | |
3406 | /* disable interrupt and set controller to stop state */ | |
3407 | langwell_udc_stop(dev); | |
3408 | ||
48e34d0f | 3409 | /* disable IRQ handler */ |
5be19a9d XS |
3410 | if (dev->got_irq) |
3411 | free_irq(pdev->irq, dev); | |
3412 | dev->got_irq = 0; | |
3413 | ||
5be19a9d XS |
3414 | /* save PCI state */ |
3415 | pci_save_state(pdev); | |
3416 | ||
cf7d3c8e PS |
3417 | spin_lock_irq(&dev->lock); |
3418 | /* stop all usb activities */ | |
3419 | stop_activity(dev, dev->driver); | |
3420 | spin_unlock_irq(&dev->lock); | |
3421 | ||
912c93d1 J |
3422 | /* free dTD dma_pool and dQH */ |
3423 | if (dev->dtd_pool) | |
3424 | dma_pool_destroy(dev->dtd_pool); | |
3425 | ||
3426 | if (dev->ep_dqh) | |
3427 | dma_free_coherent(&pdev->dev, dev->ep_dqh_size, | |
3428 | dev->ep_dqh, dev->ep_dqh_dma); | |
3429 | ||
3430 | /* release SRAM caching */ | |
3431 | if (dev->has_sram && dev->got_sram) | |
3432 | sram_deinit(dev); | |
3433 | ||
5be19a9d XS |
3434 | /* set device power state */ |
3435 | pci_set_power_state(pdev, PCI_D3hot); | |
3436 | ||
3437 | /* enter PHY low power suspend */ | |
513b91b6 J |
3438 | if (dev->pdev->device != 0x0829) |
3439 | langwell_phy_low_power(dev, 1); | |
5be19a9d | 3440 | |
5f81f4b0 | 3441 | dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__); |
5be19a9d XS |
3442 | return 0; |
3443 | } | |
3444 | ||
3445 | ||
3446 | /* device controller resume */ | |
3447 | static int langwell_udc_resume(struct pci_dev *pdev) | |
3448 | { | |
3449 | struct langwell_udc *dev = the_controller; | |
912c93d1 | 3450 | size_t size; |
5be19a9d | 3451 | |
5f81f4b0 | 3452 | dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
3453 | |
3454 | /* exit PHY low power suspend */ | |
513b91b6 J |
3455 | if (dev->pdev->device != 0x0829) |
3456 | langwell_phy_low_power(dev, 0); | |
5be19a9d XS |
3457 | |
3458 | /* set device D0 power state */ | |
3459 | pci_set_power_state(pdev, PCI_D0); | |
3460 | ||
912c93d1 J |
3461 | /* enable SRAM caching if detected */ |
3462 | if (dev->has_sram && !dev->got_sram) | |
3463 | sram_init(dev); | |
3464 | ||
3465 | /* allocate device dQH memory */ | |
3466 | size = dev->ep_max * sizeof(struct langwell_dqh); | |
3467 | dev_vdbg(&dev->pdev->dev, "orig size = %d\n", size); | |
3468 | if (size < DQH_ALIGNMENT) | |
3469 | size = DQH_ALIGNMENT; | |
3470 | else if ((size % DQH_ALIGNMENT) != 0) { | |
3471 | size += DQH_ALIGNMENT + 1; | |
3472 | size &= ~(DQH_ALIGNMENT - 1); | |
3473 | } | |
3474 | dev->ep_dqh = dma_alloc_coherent(&pdev->dev, size, | |
3475 | &dev->ep_dqh_dma, GFP_KERNEL); | |
3476 | if (!dev->ep_dqh) { | |
3477 | dev_err(&dev->pdev->dev, "allocate dQH memory failed\n"); | |
3478 | return -ENOMEM; | |
3479 | } | |
3480 | dev->ep_dqh_size = size; | |
3481 | dev_vdbg(&dev->pdev->dev, "ep_dqh_size = %d\n", dev->ep_dqh_size); | |
3482 | ||
3483 | /* create dTD dma_pool resource */ | |
3484 | dev->dtd_pool = dma_pool_create("langwell_dtd", | |
3485 | &dev->pdev->dev, | |
3486 | sizeof(struct langwell_dtd), | |
3487 | DTD_ALIGNMENT, | |
3488 | DMA_BOUNDARY); | |
3489 | ||
3490 | if (!dev->dtd_pool) | |
3491 | return -ENOMEM; | |
3492 | ||
5be19a9d XS |
3493 | /* restore PCI state */ |
3494 | pci_restore_state(pdev); | |
3495 | ||
3496 | /* enable IRQ handler */ | |
5f81f4b0 J |
3497 | if (request_irq(pdev->irq, langwell_irq, IRQF_SHARED, |
3498 | driver_name, dev) != 0) { | |
3499 | dev_err(&dev->pdev->dev, "request interrupt %d failed\n", | |
3500 | pdev->irq); | |
3501 | return -EBUSY; | |
5be19a9d XS |
3502 | } |
3503 | dev->got_irq = 1; | |
3504 | ||
3505 | /* reset and start controller to run state */ | |
3506 | if (dev->stopped) { | |
3507 | /* reset device controller */ | |
3508 | langwell_udc_reset(dev); | |
3509 | ||
3510 | /* reset ep0 dQH and endptctrl */ | |
3511 | ep0_reset(dev); | |
3512 | ||
3513 | /* start device if gadget is loaded */ | |
3514 | if (dev->driver) | |
3515 | langwell_udc_start(dev); | |
3516 | } | |
3517 | ||
3518 | /* reset USB status */ | |
3519 | dev->usb_state = USB_STATE_ATTACHED; | |
3520 | dev->ep0_state = WAIT_FOR_SETUP; | |
3521 | dev->ep0_dir = USB_DIR_OUT; | |
3522 | ||
5f81f4b0 | 3523 | dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__); |
5be19a9d XS |
3524 | return 0; |
3525 | } | |
3526 | ||
3527 | ||
3528 | /* pci driver shutdown */ | |
3529 | static void langwell_udc_shutdown(struct pci_dev *pdev) | |
3530 | { | |
3531 | struct langwell_udc *dev = the_controller; | |
3532 | u32 usbmode; | |
3533 | ||
5f81f4b0 | 3534 | dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__); |
5be19a9d XS |
3535 | |
3536 | /* reset controller mode to IDLE */ | |
3537 | usbmode = readl(&dev->op_regs->usbmode); | |
5f81f4b0 | 3538 | dev_dbg(&dev->pdev->dev, "usbmode = 0x%08x\n", usbmode); |
5be19a9d XS |
3539 | usbmode &= (~3 | MODE_IDLE); |
3540 | writel(usbmode, &dev->op_regs->usbmode); | |
3541 | ||
5f81f4b0 | 3542 | dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__); |
5be19a9d XS |
3543 | } |
3544 | ||
3545 | /*-------------------------------------------------------------------------*/ | |
3546 | ||
3547 | static const struct pci_device_id pci_ids[] = { { | |
3548 | .class = ((PCI_CLASS_SERIAL_USB << 8) | 0xfe), | |
3549 | .class_mask = ~0, | |
3550 | .vendor = 0x8086, | |
3551 | .device = 0x0811, | |
3552 | .subvendor = PCI_ANY_ID, | |
3553 | .subdevice = PCI_ANY_ID, | |
3554 | }, { /* end: all zeroes */ } | |
3555 | }; | |
3556 | ||
5be19a9d XS |
3557 | MODULE_DEVICE_TABLE(pci, pci_ids); |
3558 | ||
3559 | ||
3560 | static struct pci_driver langwell_pci_driver = { | |
3561 | .name = (char *) driver_name, | |
3562 | .id_table = pci_ids, | |
3563 | ||
3564 | .probe = langwell_udc_probe, | |
3565 | .remove = langwell_udc_remove, | |
3566 | ||
3567 | /* device controller suspend/resume */ | |
3568 | .suspend = langwell_udc_suspend, | |
3569 | .resume = langwell_udc_resume, | |
3570 | ||
3571 | .shutdown = langwell_udc_shutdown, | |
3572 | }; | |
3573 | ||
3574 | ||
5be19a9d XS |
3575 | static int __init init(void) |
3576 | { | |
3577 | #ifdef OTG_TRANSCEIVER | |
3578 | return langwell_register_peripheral(&langwell_pci_driver); | |
3579 | #else | |
3580 | return pci_register_driver(&langwell_pci_driver); | |
3581 | #endif | |
3582 | } | |
3583 | module_init(init); | |
3584 | ||
3585 | ||
3586 | static void __exit cleanup(void) | |
3587 | { | |
3588 | #ifdef OTG_TRANSCEIVER | |
3589 | return langwell_unregister_peripheral(&langwell_pci_driver); | |
3590 | #else | |
3591 | pci_unregister_driver(&langwell_pci_driver); | |
3592 | #endif | |
3593 | } | |
3594 | module_exit(cleanup); | |
3595 | ||
5f81f4b0 J |
3596 | |
3597 | MODULE_DESCRIPTION(DRIVER_DESC); | |
3598 | MODULE_AUTHOR("Xiaochen Shen <xiaochen.shen@intel.com>"); | |
3599 | MODULE_VERSION(DRIVER_VERSION); | |
3600 | MODULE_LICENSE("GPL"); | |
3601 |