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Commit | Line | Data |
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6b92487d | 1 | /* |
1b719e66 | 2 | * (C) Copyright 2009, 2011 Freescale Semiconductor, Inc. |
4ef01010 | 3 | * |
6b92487d MT |
4 | * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB |
5 | * | |
6 | * Author: Tor Krill tor@excito.com | |
7 | * | |
1a459660 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
6b92487d MT |
9 | */ |
10 | ||
11 | #include <common.h> | |
12 | #include <pci.h> | |
13 | #include <usb.h> | |
6b92487d | 14 | #include <asm/io.h> |
4ef01010 | 15 | #include <usb/ehci-fsl.h> |
1b719e66 | 16 | #include <hwconfig.h> |
6b92487d | 17 | |
2731b9a8 | 18 | #include "ehci.h" |
6b92487d | 19 | |
047cea36 SL |
20 | /* Check USB PHY clock valid */ |
21 | static int usb_phy_clk_valid(struct usb_ehci *ehci) | |
22 | { | |
23 | if (!((in_be32(&ehci->control) & PHY_CLK_VALID) || | |
24 | in_be32(&ehci->prictrl))) { | |
25 | printf("USB PHY clock invalid!\n"); | |
26 | return 0; | |
27 | } else { | |
28 | return 1; | |
29 | } | |
30 | } | |
31 | ||
6b92487d MT |
32 | /* |
33 | * Create the appropriate control structures to manage | |
34 | * a new EHCI host controller. | |
35 | * | |
36 | * Excerpts from linux ehci fsl driver. | |
37 | */ | |
676ae068 | 38 | int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) |
6b92487d | 39 | { |
4ef01010 | 40 | struct usb_ehci *ehci; |
1b719e66 RM |
41 | const char *phy_type = NULL; |
42 | size_t len; | |
dd22f7cf KG |
43 | #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
44 | char usb_phy[5]; | |
1b719e66 RM |
45 | |
46 | usb_phy[0] = '\0'; | |
dd22f7cf | 47 | #endif |
6b92487d | 48 | |
29c6fbe0 | 49 | ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR; |
676ae068 LS |
50 | *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); |
51 | *hcor = (struct ehci_hcor *)((uint32_t) *hccr + | |
52 | HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); | |
6b92487d | 53 | |
6b92487d | 54 | /* Set to Host mode */ |
08066152 | 55 | setbits_le32(&ehci->usbmode, CM_HOST); |
6b92487d | 56 | |
08066152 VM |
57 | out_be32(&ehci->snoop1, SNOOP_SIZE_2GB); |
58 | out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB); | |
6b92487d MT |
59 | |
60 | /* Init phy */ | |
1b719e66 RM |
61 | if (hwconfig_sub("usb1", "phy_type")) |
62 | phy_type = hwconfig_subarg("usb1", "phy_type", &len); | |
4ef01010 | 63 | else |
1b719e66 RM |
64 | phy_type = getenv("usb_phy_type"); |
65 | ||
66 | if (!phy_type) { | |
67 | #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY | |
68 | /* if none specified assume internal UTMI */ | |
69 | strcpy(usb_phy, "utmi"); | |
70 | phy_type = usb_phy; | |
71 | #else | |
72 | printf("WARNING: USB phy type not defined !!\n"); | |
73 | return -1; | |
74 | #endif | |
75 | } | |
76 | ||
77 | if (!strcmp(phy_type, "utmi")) { | |
78 | #if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY) | |
79 | setbits_be32(&ehci->control, PHY_CLK_SEL_UTMI); | |
80 | setbits_be32(&ehci->control, UTMI_PHY_EN); | |
81 | udelay(1000); /* delay required for PHY Clk to appear */ | |
82 | #endif | |
676ae068 | 83 | out_le32(&(*hcor)->or_portsc[0], PORT_PTS_UTMI); |
047cea36 | 84 | setbits_be32(&ehci->control, USB_EN); |
1b719e66 | 85 | } else { |
1b719e66 | 86 | setbits_be32(&ehci->control, PHY_CLK_SEL_ULPI); |
047cea36 | 87 | clrsetbits_be32(&ehci->control, UTMI_PHY_EN, USB_EN); |
1b719e66 | 88 | udelay(1000); /* delay required for PHY Clk to appear */ |
047cea36 SL |
89 | if (!usb_phy_clk_valid(ehci)) |
90 | return -EINVAL; | |
676ae068 | 91 | out_le32(&(*hcor)->or_portsc[0], PORT_PTS_ULPI); |
1b719e66 | 92 | } |
6b92487d | 93 | |
08066152 VM |
94 | out_be32(&ehci->prictrl, 0x0000000c); |
95 | out_be32(&ehci->age_cnt_limit, 0x00000040); | |
96 | out_be32(&ehci->sictrl, 0x00000001); | |
6b92487d | 97 | |
08066152 | 98 | in_le32(&ehci->usbmode); |
6b92487d MT |
99 | |
100 | return 0; | |
101 | } | |
102 | ||
103 | /* | |
104 | * Destroy the appropriate control structures corresponding | |
105 | * the the EHCI host controller. | |
106 | */ | |
676ae068 | 107 | int ehci_hcd_stop(int index) |
6b92487d MT |
108 | { |
109 | return 0; | |
110 | } |