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1ca56202 WG |
1 | /* |
2 | * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> | |
3 | * Copyright (C) 2010 Freescale Semiconductor, Inc. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
1ca56202 WG |
6 | */ |
7 | ||
8 | #include <common.h> | |
9 | #include <usb.h> | |
10 | #include <errno.h> | |
11 | #include <linux/compiler.h> | |
e162c6b1 | 12 | #include <usb/ehci-ci.h> |
1ca56202 WG |
13 | #include <asm/io.h> |
14 | #include <asm/arch/imx-regs.h> | |
15 | #include <asm/arch/clock.h> | |
1ca56202 WG |
16 | |
17 | #include "ehci.h" | |
1ca56202 WG |
18 | |
19 | #define MX5_USBOTHER_REGS_OFFSET 0x800 | |
20 | ||
21 | ||
bdc52020 BT |
22 | #define MXC_OTG_OFFSET 0 |
23 | #define MXC_H1_OFFSET 0x200 | |
24 | #define MXC_H2_OFFSET 0x400 | |
2cfe0b8f | 25 | #define MXC_H3_OFFSET 0x600 |
1ca56202 WG |
26 | |
27 | #define MXC_USBCTRL_OFFSET 0 | |
28 | #define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8 | |
29 | #define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc | |
30 | #define MXC_USB_CTRL_1_OFFSET 0x10 | |
31 | #define MXC_USBH2CTRL_OFFSET 0x14 | |
2cfe0b8f | 32 | #define MXC_USBH3CTRL_OFFSET 0x18 |
1ca56202 WG |
33 | |
34 | /* USB_CTRL */ | |
bdc52020 BT |
35 | /* OTG wakeup intr enable */ |
36 | #define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) | |
37 | /* OTG power mask */ | |
38 | #define MXC_OTG_UCTRL_OPM_BIT (1 << 24) | |
31ac2d0c BT |
39 | /* OTG power pin polarity */ |
40 | #define MXC_OTG_UCTRL_O_PWR_POL_BIT (1 << 24) | |
bdc52020 BT |
41 | /* Host1 ULPI interrupt enable */ |
42 | #define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) | |
43 | /* HOST1 wakeup intr enable */ | |
44 | #define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) | |
45 | /* HOST1 power mask */ | |
46 | #define MXC_H1_UCTRL_H1PM_BIT (1 << 8) | |
31ac2d0c BT |
47 | /* HOST1 power pin polarity */ |
48 | #define MXC_H1_UCTRL_H1_PWR_POL_BIT (1 << 8) | |
1ca56202 WG |
49 | |
50 | /* USB_PHY_CTRL_FUNC */ | |
31ac2d0c BT |
51 | /* OTG Polarity of Overcurrent */ |
52 | #define MXC_OTG_PHYCTRL_OC_POL_BIT (1 << 9) | |
bdc52020 BT |
53 | /* OTG Disable Overcurrent Event */ |
54 | #define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) | |
31ac2d0c BT |
55 | /* UH1 Polarity of Overcurrent */ |
56 | #define MXC_H1_OC_POL_BIT (1 << 6) | |
bdc52020 BT |
57 | /* UH1 Disable Overcurrent Event */ |
58 | #define MXC_H1_OC_DIS_BIT (1 << 5) | |
31ac2d0c BT |
59 | /* OTG Power Pin Polarity */ |
60 | #define MXC_OTG_PHYCTRL_PWR_POL_BIT (1 << 3) | |
1ca56202 WG |
61 | |
62 | /* USBH2CTRL */ | |
31ac2d0c | 63 | #define MXC_H2_UCTRL_H2_OC_POL_BIT (1 << 31) |
2cfe0b8f | 64 | #define MXC_H2_UCTRL_H2_OC_DIS_BIT (1 << 30) |
bdc52020 BT |
65 | #define MXC_H2_UCTRL_H2UIE_BIT (1 << 8) |
66 | #define MXC_H2_UCTRL_H2WIE_BIT (1 << 7) | |
67 | #define MXC_H2_UCTRL_H2PM_BIT (1 << 4) | |
31ac2d0c | 68 | #define MXC_H2_UCTRL_H2_PWR_POL_BIT (1 << 4) |
1ca56202 | 69 | |
2cfe0b8f | 70 | /* USBH3CTRL */ |
31ac2d0c | 71 | #define MXC_H3_UCTRL_H3_OC_POL_BIT (1 << 31) |
2cfe0b8f BT |
72 | #define MXC_H3_UCTRL_H3_OC_DIS_BIT (1 << 30) |
73 | #define MXC_H3_UCTRL_H3UIE_BIT (1 << 8) | |
74 | #define MXC_H3_UCTRL_H3WIE_BIT (1 << 7) | |
31ac2d0c | 75 | #define MXC_H3_UCTRL_H3_PWR_POL_BIT (1 << 4) |
2cfe0b8f | 76 | |
1ca56202 | 77 | /* USB_CTRL_1 */ |
bdc52020 | 78 | #define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25) |
1ca56202 WG |
79 | |
80 | int mxc_set_usbcontrol(int port, unsigned int flags) | |
81 | { | |
82 | unsigned int v; | |
83 | void __iomem *usb_base = (void __iomem *)OTG_BASE_ADDR; | |
84 | void __iomem *usbother_base; | |
85 | int ret = 0; | |
86 | ||
87 | usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; | |
88 | ||
89 | switch (port) { | |
90 | case 0: /* OTG port */ | |
91 | if (flags & MXC_EHCI_INTERNAL_PHY) { | |
92 | v = __raw_readl(usbother_base + | |
93 | MXC_USB_PHY_CTR_FUNC_OFFSET); | |
31ac2d0c BT |
94 | if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW) |
95 | v |= MXC_OTG_PHYCTRL_OC_POL_BIT; | |
96 | else | |
97 | v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT; | |
1ca56202 | 98 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) |
1ca56202 WG |
99 | /* OC/USBPWR is used */ |
100 | v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT; | |
7d42432d BT |
101 | else |
102 | /* OC/USBPWR is not used */ | |
103 | v |= MXC_OTG_PHYCTRL_OC_DIS_BIT; | |
31ac2d0c BT |
104 | #ifdef CONFIG_MX51 |
105 | if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) | |
106 | v |= MXC_OTG_PHYCTRL_PWR_POL_BIT; | |
107 | else | |
108 | v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT; | |
109 | #endif | |
1ca56202 WG |
110 | __raw_writel(v, usbother_base + |
111 | MXC_USB_PHY_CTR_FUNC_OFFSET); | |
112 | ||
113 | v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); | |
661052f4 | 114 | #ifdef CONFIG_MX51 |
1ca56202 | 115 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) |
1ca56202 | 116 | v &= ~MXC_OTG_UCTRL_OPM_BIT; |
394c00dc BT |
117 | else |
118 | v |= MXC_OTG_UCTRL_OPM_BIT; | |
31ac2d0c BT |
119 | #endif |
120 | #ifdef CONFIG_MX53 | |
121 | if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) | |
122 | v |= MXC_OTG_UCTRL_O_PWR_POL_BIT; | |
123 | else | |
124 | v &= ~MXC_OTG_UCTRL_O_PWR_POL_BIT; | |
661052f4 | 125 | #endif |
1ca56202 WG |
126 | __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); |
127 | } | |
128 | break; | |
bdc52020 | 129 | case 1: /* Host 1 ULPI */ |
1ca56202 WG |
130 | #ifdef CONFIG_MX51 |
131 | /* The clock for the USBH1 ULPI port will come externally | |
132 | from the PHY. */ | |
133 | v = __raw_readl(usbother_base + MXC_USB_CTRL_1_OFFSET); | |
134 | __raw_writel(v | MXC_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + | |
135 | MXC_USB_CTRL_1_OFFSET); | |
136 | #endif | |
137 | ||
138 | v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); | |
661052f4 | 139 | #ifdef CONFIG_MX51 |
1ca56202 | 140 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) |
bdc52020 | 141 | v &= ~MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask unused */ |
1ca56202 | 142 | else |
bdc52020 | 143 | v |= MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask used */ |
31ac2d0c BT |
144 | #endif |
145 | #ifdef CONFIG_MX53 | |
146 | if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) | |
147 | v |= MXC_H1_UCTRL_H1_PWR_POL_BIT; | |
148 | else | |
149 | v &= ~MXC_H1_UCTRL_H1_PWR_POL_BIT; | |
661052f4 | 150 | #endif |
1ca56202 WG |
151 | __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); |
152 | ||
153 | v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); | |
31ac2d0c BT |
154 | if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW) |
155 | v |= MXC_H1_OC_POL_BIT; | |
156 | else | |
157 | v &= ~MXC_H1_OC_POL_BIT; | |
1ca56202 WG |
158 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) |
159 | v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */ | |
160 | else | |
161 | v |= MXC_H1_OC_DIS_BIT; /* OC is not used */ | |
162 | __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); | |
163 | ||
164 | break; | |
165 | case 2: /* Host 2 ULPI */ | |
166 | v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET); | |
661052f4 | 167 | #ifdef CONFIG_MX51 |
1ca56202 | 168 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) |
bdc52020 | 169 | v &= ~MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask unused */ |
1ca56202 | 170 | else |
bdc52020 | 171 | v |= MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask used */ |
2cfe0b8f BT |
172 | #endif |
173 | #ifdef CONFIG_MX53 | |
31ac2d0c BT |
174 | if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW) |
175 | v |= MXC_H2_UCTRL_H2_OC_POL_BIT; | |
176 | else | |
177 | v &= ~MXC_H2_UCTRL_H2_OC_POL_BIT; | |
2cfe0b8f BT |
178 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) |
179 | v &= ~MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is used */ | |
180 | else | |
181 | v |= MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is not used */ | |
31ac2d0c BT |
182 | if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) |
183 | v |= MXC_H2_UCTRL_H2_PWR_POL_BIT; | |
184 | else | |
185 | v &= ~MXC_H2_UCTRL_H2_PWR_POL_BIT; | |
661052f4 | 186 | #endif |
1ca56202 WG |
187 | __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET); |
188 | break; | |
2cfe0b8f BT |
189 | #ifdef CONFIG_MX53 |
190 | case 3: /* Host 3 ULPI */ | |
191 | v = __raw_readl(usbother_base + MXC_USBH3CTRL_OFFSET); | |
31ac2d0c BT |
192 | if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW) |
193 | v |= MXC_H3_UCTRL_H3_OC_POL_BIT; | |
194 | else | |
195 | v &= ~MXC_H3_UCTRL_H3_OC_POL_BIT; | |
2cfe0b8f BT |
196 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) |
197 | v &= ~MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is used */ | |
198 | else | |
199 | v |= MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is not used */ | |
31ac2d0c BT |
200 | if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) |
201 | v |= MXC_H3_UCTRL_H3_PWR_POL_BIT; | |
202 | else | |
203 | v &= ~MXC_H3_UCTRL_H3_PWR_POL_BIT; | |
2cfe0b8f BT |
204 | __raw_writel(v, usbother_base + MXC_USBH3CTRL_OFFSET); |
205 | break; | |
206 | #endif | |
1ca56202 WG |
207 | } |
208 | ||
209 | return ret; | |
210 | } | |
211 | ||
f22e4fae | 212 | int __weak board_ehci_hcd_init(int port) |
1b80f270 | 213 | { |
f22e4fae | 214 | return 0; |
1b80f270 MV |
215 | } |
216 | ||
f22e4fae BT |
217 | void __weak board_ehci_hcd_postinit(struct usb_ehci *ehci, int port) |
218 | { | |
219 | } | |
1b80f270 | 220 | |
deb8508c SG |
221 | __weak void mx5_ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg, |
222 | uint32_t *reg) | |
223 | { | |
224 | mdelay(50); | |
225 | } | |
226 | ||
227 | static const struct ehci_ops mx5_ehci_ops = { | |
228 | .powerup_fixup = mx5_ehci_powerup_fixup, | |
229 | }; | |
230 | ||
127efc4f TK |
231 | int ehci_hcd_init(int index, enum usb_init_type init, |
232 | struct ehci_hccr **hccr, struct ehci_hcor **hcor) | |
1ca56202 WG |
233 | { |
234 | struct usb_ehci *ehci; | |
1ca56202 | 235 | |
deb8508c SG |
236 | /* The only user for this is efikamx-usb */ |
237 | ehci_set_controller_priv(index, NULL, &mx5_ehci_ops); | |
1ca56202 | 238 | set_usboh3_clk(); |
76b6b196 | 239 | enable_usboh3_clk(true); |
414e1660 | 240 | set_usb_phy_clk(); |
76b6b196 FE |
241 | enable_usb_phy1_clk(true); |
242 | enable_usb_phy2_clk(true); | |
1ca56202 WG |
243 | mdelay(1); |
244 | ||
1b80f270 | 245 | /* Do board specific initialization */ |
1ca56202 WG |
246 | board_ehci_hcd_init(CONFIG_MXC_USB_PORT); |
247 | ||
248 | ehci = (struct usb_ehci *)(OTG_BASE_ADDR + | |
249 | (0x200 * CONFIG_MXC_USB_PORT)); | |
676ae068 LS |
250 | *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); |
251 | *hcor = (struct ehci_hcor *)((uint32_t)*hccr + | |
252 | HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); | |
1ca56202 WG |
253 | setbits_le32(&ehci->usbmode, CM_HOST); |
254 | ||
255 | __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); | |
256 | setbits_le32(&ehci->portsc, USB_EN); | |
257 | ||
258 | mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS); | |
1ca56202 WG |
259 | mdelay(10); |
260 | ||
1b80f270 MV |
261 | /* Do board specific post-initialization */ |
262 | board_ehci_hcd_postinit(ehci, CONFIG_MXC_USB_PORT); | |
263 | ||
1ca56202 WG |
264 | return 0; |
265 | } | |
266 | ||
676ae068 | 267 | int ehci_hcd_stop(int index) |
1ca56202 WG |
268 | { |
269 | return 0; | |
270 | } |