[people/ms/u-boot.git] / drivers / usb / host / ehci-mx6.c

/*
 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
 * Copyright (C) 2010 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <usb.h>
#include <errno.h>
#include <wait_bit.h>
#include <linux/compiler.h>
#include <usb/ehci-ci.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/imx-common/iomux-v3.h>

#include "ehci.h"

#define USB_OTGREGS_OFFSET	0x000
#define USB_H1REGS_OFFSET	0x200
#define USB_H2REGS_OFFSET	0x400
#define USB_H3REGS_OFFSET	0x600
#define USB_OTHERREGS_OFFSET	0x800

#define USB_H1_CTRL_OFFSET	0x04

#define USBPHY_CTRL				0x00000030
#define USBPHY_CTRL_SET				0x00000034
#define USBPHY_CTRL_CLR				0x00000038
#define USBPHY_CTRL_TOG				0x0000003c

#define USBPHY_PWD				0x00000000
#define USBPHY_CTRL_SFTRST			0x80000000
#define USBPHY_CTRL_CLKGATE			0x40000000
#define USBPHY_CTRL_ENUTMILEVEL3		0x00008000
#define USBPHY_CTRL_ENUTMILEVEL2		0x00004000
#define USBPHY_CTRL_OTG_ID			0x08000000

#define ANADIG_USB2_CHRG_DETECT_EN_B		0x00100000
#define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B	0x00080000

#define ANADIG_USB2_PLL_480_CTRL_BYPASS		0x00010000
#define ANADIG_USB2_PLL_480_CTRL_ENABLE		0x00002000
#define ANADIG_USB2_PLL_480_CTRL_POWER		0x00001000
#define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS	0x00000040

#define USBNC_OFFSET		0x200
#define USBNC_PHYSTATUS_ID_DIG	(1 << 4) /* otg_id status */
#define USBNC_PHYCFG2_ACAENB	(1 << 4) /* otg_id detection enable */
#define UCTRL_PWR_POL		(1 << 9) /* OTG Polarity of Power Pin */
#define UCTRL_OVER_CUR_POL	(1 << 8) /* OTG Polarity of Overcurrent */
#define UCTRL_OVER_CUR_DIS	(1 << 7) /* Disable OTG Overcurrent Detection */

/* USBCMD */
#define UCMD_RUN_STOP           (1 << 0) /* controller run/stop */
#define UCMD_RESET		(1 << 1) /* controller reset */

#if defined(CONFIG_MX6)
static const unsigned phy_bases[] = {
	USB_PHY0_BASE_ADDR,
	USB_PHY1_BASE_ADDR,
};

static void usb_internal_phy_clock_gate(int index, int on)
{
	void __iomem *phy_reg;

	if (index >= ARRAY_SIZE(phy_bases))
		return;

	phy_reg = (void __iomem *)phy_bases[index];
	phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
	writel(USBPHY_CTRL_CLKGATE, phy_reg);
}

static void usb_power_config(int index)
{
	struct anatop_regs __iomem *anatop =
		(struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
	void __iomem *chrg_detect;
	void __iomem *pll_480_ctrl_clr;
	void __iomem *pll_480_ctrl_set;

	switch (index) {
	case 0:
		chrg_detect = &anatop->usb1_chrg_detect;
		pll_480_ctrl_clr = &anatop->usb1_pll_480_ctrl_clr;
		pll_480_ctrl_set = &anatop->usb1_pll_480_ctrl_set;
		break;
	case 1:
		chrg_detect = &anatop->usb2_chrg_detect;
		pll_480_ctrl_clr = &anatop->usb2_pll_480_ctrl_clr;
		pll_480_ctrl_set = &anatop->usb2_pll_480_ctrl_set;
		break;
	default:
		return;
	}
	/*
	 * Some phy and power's special controls
	 * 1. The external charger detector needs to be disabled
	 * or the signal at DP will be poor
	 * 2. The PLL's power and output to usb
	 * is totally controlled by IC, so the Software only needs
	 * to enable them at initializtion.
	 */
	writel(ANADIG_USB2_CHRG_DETECT_EN_B |
		     ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
		     chrg_detect);

	writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
		     pll_480_ctrl_clr);

	writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
		     ANADIG_USB2_PLL_480_CTRL_POWER |
		     ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
		     pll_480_ctrl_set);
}

/* Return 0 : host node, <>0 : device mode */
static int usb_phy_enable(int index, struct usb_ehci *ehci)
{
	void __iomem *phy_reg;
	void __iomem *phy_ctrl;
	void __iomem *usb_cmd;
	int ret;

	if (index >= ARRAY_SIZE(phy_bases))
		return 0;

	phy_reg = (void __iomem *)phy_bases[index];
	phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
	usb_cmd = (void __iomem *)&ehci->usbcmd;

	/* Stop then Reset */
	clrbits_le32(usb_cmd, UCMD_RUN_STOP);
	ret = wait_for_bit(__func__, usb_cmd, UCMD_RUN_STOP, false, 10000,
			   false);
	if (ret)
		return ret;

	setbits_le32(usb_cmd, UCMD_RESET);
	ret = wait_for_bit(__func__, usb_cmd, UCMD_RESET, false, 10000, false);
	if (ret)
		return ret;

	/* Reset USBPHY module */
	setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST);
	udelay(10);

	/* Remove CLKGATE and SFTRST */
	clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
	udelay(10);

	/* Power up the PHY */
	writel(0, phy_reg + USBPHY_PWD);
	/* enable FS/LS device */
	setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 |
			USBPHY_CTRL_ENUTMILEVEL3);

	return 0;
}

int usb_phy_mode(int port)
{
	void __iomem *phy_reg;
	void __iomem *phy_ctrl;
	u32 val;

	phy_reg = (void __iomem *)phy_bases[port];
	phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);

	val = readl(phy_ctrl);

	if (val & USBPHY_CTRL_OTG_ID)
		return USB_INIT_DEVICE;
	else
		return USB_INIT_HOST;
}

/* Base address for this IP block is 0x02184800 */
struct usbnc_regs {
	u32	ctrl[4];	/* otg/host1-3 */
	u32	uh2_hsic_ctrl;
	u32	uh3_hsic_ctrl;
	u32	otg_phy_ctrl_0;
	u32	uh1_phy_ctrl_0;
};
#elif defined(CONFIG_MX7)
struct usbnc_regs {
	u32 ctrl1;
	u32 ctrl2;
	u32 reserve1[10];
	u32 phy_cfg1;
	u32 phy_cfg2;
	u32 reserve2;
	u32 phy_status;
	u32 reserve3[4];
	u32 adp_cfg1;
	u32 adp_cfg2;
	u32 adp_status;
};

static void usb_power_config(int index)
{
	struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
			(0x10000 * index) + USBNC_OFFSET);
	void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2);
	void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1);

	/*
	 * Clear the ACAENB to enable usb_otg_id detection,
	 * otherwise it is the ACA detection enabled.
	 */
	clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB);

	/* Set power polarity to high active */
#ifdef CONFIG_MXC_USB_OTG_HACTIVE
	setbits_le32(ctrl, UCTRL_PWR_POL);
#else
	clrbits_le32(ctrl, UCTRL_PWR_POL);
#endif
}

int usb_phy_mode(int port)
{
	struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
			(0x10000 * port) + USBNC_OFFSET);
	void __iomem *status = (void __iomem *)(&usbnc->phy_status);
	u32 val;

	val = readl(status);

	if (val & USBNC_PHYSTATUS_ID_DIG)
		return USB_INIT_DEVICE;
	else
		return USB_INIT_HOST;
}
#endif

static void usb_oc_config(int index)
{
#if defined(CONFIG_MX6)
	struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
			USB_OTHERREGS_OFFSET);
	void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
#elif defined(CONFIG_MX7)
	struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
			(0x10000 * index) + USBNC_OFFSET);
	void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1);
#endif

#if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2
	/* mx6qarm2 seems to required a different setting*/
	clrbits_le32(ctrl, UCTRL_OVER_CUR_POL);
#else
	setbits_le32(ctrl, UCTRL_OVER_CUR_POL);
#endif

	setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
}

/**
 * board_usb_phy_mode - override usb phy mode
 * @port:	usb host/otg port
 *
 * Target board specific, override usb_phy_mode.
 * When usb-otg is used as usb host port, iomux pad usb_otg_id can be
 * left disconnected in this case usb_phy_mode will not be able to identify
 * the phy mode that usb port is used.
 * Machine file overrides board_usb_phy_mode.
 *
 * Return: USB_INIT_DEVICE or USB_INIT_HOST
 */
int __weak board_usb_phy_mode(int port)
{
	return usb_phy_mode(port);
}

/**
 * board_ehci_hcd_init - set usb vbus voltage
 * @port:      usb otg port
 *
 * Target board specific, setup iomux pad to setup supply vbus voltage
 * for usb otg port. Machine board file overrides board_ehci_hcd_init
 *
 * Return: 0 Success
 */
int __weak board_ehci_hcd_init(int port)
{
	return 0;
}

/**
 * board_ehci_power - enables/disables usb vbus voltage
 * @port:      usb otg port
 * @on:        on/off vbus voltage
 *
 * Enables/disables supply vbus voltage for usb otg port.
 * Machine board file overrides board_ehci_power
 *
 * Return: 0 Success
 */
int __weak board_ehci_power(int port, int on)
{
	return 0;
}

int ehci_hcd_init(int index, enum usb_init_type init,
		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
	enum usb_init_type type;
#if defined(CONFIG_MX6)
	u32 controller_spacing = 0x200;
#elif defined(CONFIG_MX7)
	u32 controller_spacing = 0x10000;
#endif
	struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
		(controller_spacing * index));
	int ret;

	if (index > 3)
		return -EINVAL;
	enable_usboh3_clk(1);
	mdelay(1);

	/* Do board specific initialization */
	ret = board_ehci_hcd_init(index);
	if (ret)
		return ret;

	usb_power_config(index);
	usb_oc_config(index);

#if defined(CONFIG_MX6)
	usb_internal_phy_clock_gate(index, 1);
	usb_phy_enable(index, ehci);
#endif
	type = board_usb_phy_mode(index);

	*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
	*hcor = (struct ehci_hcor *)((uint32_t)*hccr +
			HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));

	if ((type == init) || (type == USB_INIT_DEVICE))
		board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1);
	if (type != init)
		return -ENODEV;
	if (type == USB_INIT_DEVICE)
		return 0;

	setbits_le32(&ehci->usbmode, CM_HOST);
	writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
	setbits_le32(&ehci->portsc, USB_EN);

	mdelay(10);

	return 0;
}

int ehci_hcd_stop(int index)
{
	return 0;
}
Commit	Line	Data
3f467529 WG	1	/*
	2	* Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
	3	* Copyright (C) 2010 Freescale Semiconductor, Inc.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
3f467529 WG	6	*/
	7
	8	#include <common.h>
	9	#include <usb.h>
	10	#include <errno.h>
8c25c259	11	#include <wait_bit.h>
3f467529	12	#include <linux/compiler.h>
e162c6b1	13	#include <usb/ehci-ci.h>
3f467529 WG	14	#include <asm/io.h>
	15	#include <asm/arch/imx-regs.h>
	16	#include <asm/arch/clock.h>
af2a35fb	17	#include <asm/imx-common/iomux-v3.h>
3f467529 WG	18
3f467529 WG	19	#include "ehci.h"
3f467529 WG	20
	21	#define USB_OTGREGS_OFFSET 0x000
	22	#define USB_H1REGS_OFFSET 0x200
	23	#define USB_H2REGS_OFFSET 0x400
	24	#define USB_H3REGS_OFFSET 0x600
	25	#define USB_OTHERREGS_OFFSET 0x800
	26
	27	#define USB_H1_CTRL_OFFSET 0x04
	28
	29	#define USBPHY_CTRL 0x00000030
	30	#define USBPHY_CTRL_SET 0x00000034
	31	#define USBPHY_CTRL_CLR 0x00000038
	32	#define USBPHY_CTRL_TOG 0x0000003c
	33
	34	#define USBPHY_PWD 0x00000000
	35	#define USBPHY_CTRL_SFTRST 0x80000000
	36	#define USBPHY_CTRL_CLKGATE 0x40000000
	37	#define USBPHY_CTRL_ENUTMILEVEL3 0x00008000
	38	#define USBPHY_CTRL_ENUTMILEVEL2 0x00004000
d1a52860	39	#define USBPHY_CTRL_OTG_ID 0x08000000
3f467529	40
3f467529 WG	41	#define ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000
	42	#define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000
	43
3f467529 WG	44	#define ANADIG_USB2_PLL_480_CTRL_BYPASS 0x00010000
	45	#define ANADIG_USB2_PLL_480_CTRL_ENABLE 0x00002000
	46	#define ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000
	47	#define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040
	48
35554fc9 AA	49	#define USBNC_OFFSET 0x200
	50	#define USBNC_PHYSTATUS_ID_DIG (1 << 4) /* otg_id status */
	51	#define USBNC_PHYCFG2_ACAENB (1 << 4) /* otg_id detection enable */
9a88180b	52	#define UCTRL_PWR_POL (1 << 9) /* OTG Polarity of Power Pin */
3f467529 WG	53	#define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */
	54	#define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */
	55
	56	/* USBCMD */
3f467529 WG	57	#define UCMD_RUN_STOP (1 << 0) /* controller run/stop */
	58	#define UCMD_RESET (1 << 1) /* controller reset */
	59
35554fc9	60	#if defined(CONFIG_MX6)
d1a52860 TK	61	static const unsigned phy_bases[] = {
	62	USB_PHY0_BASE_ADDR,
	63	USB_PHY1_BASE_ADDR,
	64	};
	65
	66	static void usb_internal_phy_clock_gate(int index, int on)
3f467529	67	{
d1a52860 TK	68	void __iomem *phy_reg;
	69
	70	if (index >= ARRAY_SIZE(phy_bases))
	71	return;
3f467529	72
d1a52860	73	phy_reg = (void __iomem *)phy_bases[index];
3f467529	74	phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
e38ff30a	75	writel(USBPHY_CTRL_CLKGATE, phy_reg);
3f467529 WG	76	}
3f467529 WG	77
d1a52860	78	static void usb_power_config(int index)
3f467529	79	{
3f29d962 WG	80	struct anatop_regs __iomem *anatop =
3f29d962 WG	81	(struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
d1a52860 TK	82	void __iomem *chrg_detect;
	83	void __iomem *pll_480_ctrl_clr;
	84	void __iomem *pll_480_ctrl_set;
	85
	86	switch (index) {
	87	case 0:
	88	chrg_detect = &anatop->usb1_chrg_detect;
	89	pll_480_ctrl_clr = &anatop->usb1_pll_480_ctrl_clr;
	90	pll_480_ctrl_set = &anatop->usb1_pll_480_ctrl_set;
	91	break;
	92	case 1:
	93	chrg_detect = &anatop->usb2_chrg_detect;
	94	pll_480_ctrl_clr = &anatop->usb2_pll_480_ctrl_clr;
	95	pll_480_ctrl_set = &anatop->usb2_pll_480_ctrl_set;
	96	break;
	97	default:
	98	return;
	99	}
3f467529	100	/*
d1a52860	101	* Some phy and power's special controls
3f467529 WG	102	* 1. The external charger detector needs to be disabled
3f467529 WG	103	* or the signal at DP will be poor
d1a52860	104	* 2. The PLL's power and output to usb
3f467529 WG	105	* is totally controlled by IC, so the Software only needs
	106	* to enable them at initializtion.
	107	*/
e38ff30a	108	writel(ANADIG_USB2_CHRG_DETECT_EN_B \|
3f467529	109	ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
d1a52860	110	chrg_detect);
3f467529	111
e38ff30a	112	writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
d1a52860	113	pll_480_ctrl_clr);
3f467529	114
e38ff30a	115	writel(ANADIG_USB2_PLL_480_CTRL_ENABLE \|
3f467529 WG	116	ANADIG_USB2_PLL_480_CTRL_POWER \|
3f467529 WG	117	ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
d1a52860	118	pll_480_ctrl_set);
3f467529 WG	119	}
3f467529 WG	120
d1a52860 TK	121	/* Return 0 : host node, <>0 : device mode */
d1a52860 TK	122	static int usb_phy_enable(int index, struct usb_ehci *ehci)
3f467529	123	{
d1a52860 TK	124	void __iomem *phy_reg;
	125	void __iomem *phy_ctrl;
	126	void __iomem *usb_cmd;
f0c89d54	127	int ret;
3f467529	128
d1a52860 TK	129	if (index >= ARRAY_SIZE(phy_bases))
	130	return 0;
	131
	132	phy_reg = (void __iomem *)phy_bases[index];
	133	phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
	134	usb_cmd = (void __iomem *)&ehci->usbcmd;
	135
3f467529	136	/* Stop then Reset */
e38ff30a	137	clrbits_le32(usb_cmd, UCMD_RUN_STOP);
8c25c259 MK	138	ret = wait_for_bit(__func__, usb_cmd, UCMD_RUN_STOP, false, 10000,
8c25c259 MK	139	false);
f0c89d54 AA	140	if (ret)
f0c89d54 AA	141	return ret;
3f467529	142
e38ff30a	143	setbits_le32(usb_cmd, UCMD_RESET);
8c25c259	144	ret = wait_for_bit(__func__, usb_cmd, UCMD_RESET, false, 10000, false);
f0c89d54 AA	145	if (ret)
f0c89d54 AA	146	return ret;
3f467529 WG	147
3f467529 WG	148	/* Reset USBPHY module */
e38ff30a	149	setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST);
3f467529 WG	150	udelay(10);
	151
	152	/* Remove CLKGATE and SFTRST */
e38ff30a	153	clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE \| USBPHY_CTRL_SFTRST);
3f467529 WG	154	udelay(10);
	155
	156	/* Power up the PHY */
e38ff30a	157	writel(0, phy_reg + USBPHY_PWD);
3f467529	158	/* enable FS/LS device */
e38ff30a AA	159	setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 \|
e38ff30a AA	160	USBPHY_CTRL_ENUTMILEVEL3);
3f467529	161
229dbba9	162	return 0;
3f467529 WG	163	}
3f467529 WG	164
35554fc9 AA	165	int usb_phy_mode(int port)
	166	{
	167	void __iomem *phy_reg;
	168	void __iomem *phy_ctrl;
	169	u32 val;
	170
	171	phy_reg = (void __iomem *)phy_bases[port];
	172	phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
	173
	174	val = readl(phy_ctrl);
	175
	176	if (val & USBPHY_CTRL_OTG_ID)
	177	return USB_INIT_DEVICE;
	178	else
	179	return USB_INIT_HOST;
	180	}
	181
d1a52860 TK	182	/* Base address for this IP block is 0x02184800 */
	183	struct usbnc_regs {
	184	u32 ctrl[4]; /* otg/host1-3 */
	185	u32 uh2_hsic_ctrl;
	186	u32 uh3_hsic_ctrl;
	187	u32 otg_phy_ctrl_0;
	188	u32 uh1_phy_ctrl_0;
	189	};
35554fc9 AA	190	#elif defined(CONFIG_MX7)
	191	struct usbnc_regs {
	192	u32 ctrl1;
	193	u32 ctrl2;
	194	u32 reserve1[10];
	195	u32 phy_cfg1;
	196	u32 phy_cfg2;
429ff447	197	u32 reserve2;
35554fc9	198	u32 phy_status;
429ff447	199	u32 reserve3[4];
35554fc9 AA	200	u32 adp_cfg1;
	201	u32 adp_cfg2;
	202	u32 adp_status;
	203	};
	204
	205	static void usb_power_config(int index)
	206	{
	207	struct usbnc_regs usbnc = (struct usbnc_regs )(USB_BASE_ADDR +
	208	(0x10000 * index) + USBNC_OFFSET);
	209	void __iomem phy_cfg2 = (void __iomem )(&usbnc->phy_cfg2);
9a88180b	210	void __iomem ctrl = (void __iomem )(&usbnc->ctrl1);
35554fc9	211
57de41e9 PF	212	/*
	213	* Clear the ACAENB to enable usb_otg_id detection,
	214	* otherwise it is the ACA detection enabled.
	215	*/
	216	clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB);
9a88180b SA	217
9a88180b SA	218	/* Set power polarity to high active */
c4483093	219	#ifdef CONFIG_MXC_USB_OTG_HACTIVE
9a88180b	220	setbits_le32(ctrl, UCTRL_PWR_POL);
c4483093 SA	221	#else
	222	clrbits_le32(ctrl, UCTRL_PWR_POL);
	223	#endif
35554fc9 AA	224	}
	225
	226	int usb_phy_mode(int port)
	227	{
	228	struct usbnc_regs usbnc = (struct usbnc_regs )(USB_BASE_ADDR +
	229	(0x10000 * port) + USBNC_OFFSET);
	230	void __iomem status = (void __iomem )(&usbnc->phy_status);
	231	u32 val;
	232
	233	val = readl(status);
	234
	235	if (val & USBNC_PHYSTATUS_ID_DIG)
	236	return USB_INIT_DEVICE;
	237	else
	238	return USB_INIT_HOST;
	239	}
	240	#endif
d1a52860 TK	241
d1a52860 TK	242	static void usb_oc_config(int index)
3f467529	243	{
35554fc9	244	#if defined(CONFIG_MX6)
5546ad07	245	struct usbnc_regs usbnc = (struct usbnc_regs )(USB_BASE_ADDR +
d1a52860 TK	246	USB_OTHERREGS_OFFSET);
d1a52860 TK	247	void __iomem ctrl = (void __iomem )(&usbnc->ctrl[index]);
35554fc9 AA	248	#elif defined(CONFIG_MX7)
	249	struct usbnc_regs usbnc = (struct usbnc_regs )(USB_BASE_ADDR +
	250	(0x10000 * index) + USBNC_OFFSET);
	251	void __iomem ctrl = (void __iomem )(&usbnc->ctrl1);
	252	#endif
3f467529	253
3f467529 WG	254	#if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2
3f467529 WG	255	/* mx6qarm2 seems to required a different setting*/
e38ff30a	256	clrbits_le32(ctrl, UCTRL_OVER_CUR_POL);
3f467529	257	#else
e38ff30a	258	setbits_le32(ctrl, UCTRL_OVER_CUR_POL);
3f467529	259	#endif
3f467529	260
e38ff30a	261	setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
229dbba9 PF	262	}
229dbba9 PF	263
74f0610e	264	/**
79d867c2	265	* board_usb_phy_mode - override usb phy mode
74f0610e AA	266	* @port: usb host/otg port
	267	*
	268	* Target board specific, override usb_phy_mode.
	269	* When usb-otg is used as usb host port, iomux pad usb_otg_id can be
	270	* left disconnected in this case usb_phy_mode will not be able to identify
	271	* the phy mode that usb port is used.
	272	* Machine file overrides board_usb_phy_mode.
	273	*
	274	* Return: USB_INIT_DEVICE or USB_INIT_HOST
	275	*/
229dbba9 PF	276	int __weak board_usb_phy_mode(int port)
	277	{
	278	return usb_phy_mode(port);
	279	}
	280
74f0610e AA	281	/**
	282	* board_ehci_hcd_init - set usb vbus voltage
	283	* @port: usb otg port
	284	*
	285	* Target board specific, setup iomux pad to setup supply vbus voltage
	286	* for usb otg port. Machine board file overrides board_ehci_hcd_init
	287	*
	288	* Return: 0 Success
	289	*/
f22e4fae BT	290	int __weak board_ehci_hcd_init(int port)
	291	{
	292	return 0;
	293	}
	294
74f0610e AA	295	/**
	296	* board_ehci_power - enables/disables usb vbus voltage
	297	* @port: usb otg port
	298	* @on: on/off vbus voltage
	299	*
	300	* Enables/disables supply vbus voltage for usb otg port.
	301	* Machine board file overrides board_ehci_power
	302	*
	303	* Return: 0 Success
	304	*/
d1a52860 TK	305	int __weak board_ehci_power(int port, int on)
	306	{
	307	return 0;
	308	}
	309
127efc4f TK	310	int ehci_hcd_init(int index, enum usb_init_type init,
127efc4f TK	311	struct ehci_hccr hccr, struct ehci_hcor hcor)
3f467529	312	{
d1a52860	313	enum usb_init_type type;
35554fc9 AA	314	#if defined(CONFIG_MX6)
	315	u32 controller_spacing = 0x200;
	316	#elif defined(CONFIG_MX7)
	317	u32 controller_spacing = 0x10000;
	318	#endif
5546ad07	319	struct usb_ehci ehci = (struct usb_ehci )(USB_BASE_ADDR +
35554fc9	320	(controller_spacing * index));
79d867c2	321	int ret;
3f467529	322
d1a52860 TK	323	if (index > 3)
d1a52860 TK	324	return -EINVAL;
3f467529 WG	325	enable_usboh3_clk(1);
	326	mdelay(1);
	327
	328	/* Do board specific initialization */
79d867c2 SA	329	ret = board_ehci_hcd_init(index);
	330	if (ret)
	331	return ret;
d1a52860 TK	332
	333	usb_power_config(index);
	334	usb_oc_config(index);
35554fc9 AA	335
35554fc9 AA	336	#if defined(CONFIG_MX6)
d1a52860	337	usb_internal_phy_clock_gate(index, 1);
229dbba9	338	usb_phy_enable(index, ehci);
35554fc9	339	#endif
229dbba9	340	type = board_usb_phy_mode(index);
3f467529	341
676ae068 LS	342	hccr = (struct ehci_hccr )((uint32_t)&ehci->caplength);
	343	hcor = (struct ehci_hcor )((uint32_t)*hccr +
	344	HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
3f467529	345
d1a52860 TK	346	if ((type == init) \|\| (type == USB_INIT_DEVICE))
	347	board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1);
	348	if (type != init)
	349	return -ENODEV;
	350	if (type == USB_INIT_DEVICE)
	351	return 0;
35554fc9	352
d1a52860	353	setbits_le32(&ehci->usbmode, CM_HOST);
e38ff30a	354	writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
3f467529 WG	355	setbits_le32(&ehci->portsc, USB_EN);
	356
	357	mdelay(10);
	358
	359	return 0;
	360	}
	361
676ae068	362	int ehci_hcd_stop(int index)
3f467529 WG	363	{
	364	return 0;
	365	}