[thirdparty/u-boot.git] / drivers / usb / host / ehci-mxs.c

/*
 * Freescale i.MX28 USB Host driver
 *
 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
 * on behalf of DENX Software Engineering GmbH
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <errno.h>

#include "ehci.h"

/* This DIGCTL register ungates clock to USB */
#define	HW_DIGCTL_CTRL			0x8001c000
#define	HW_DIGCTL_CTRL_USB0_CLKGATE	(1 << 2)
#define	HW_DIGCTL_CTRL_USB1_CLKGATE	(1 << 16)

struct ehci_mxs_port {
	uint32_t		usb_regs;
	struct mxs_usbphy_regs	*phy_regs;

	struct mxs_register_32	*pll;
	uint32_t		pll_en_bits;
	uint32_t		pll_dis_bits;
	uint32_t		gate_bits;
};

static const struct ehci_mxs_port mxs_port[] = {
#ifdef CONFIG_EHCI_MXS_PORT0
	{
		MXS_USBCTRL0_BASE,
		(struct mxs_usbphy_regs *)MXS_USBPHY0_BASE,
		(struct mxs_register_32 *)(MXS_CLKCTRL_BASE +
			offsetof(struct mxs_clkctrl_regs,
			hw_clkctrl_pll0ctrl0_reg)),
		CLKCTRL_PLL0CTRL0_EN_USB_CLKS | CLKCTRL_PLL0CTRL0_POWER,
		CLKCTRL_PLL0CTRL0_EN_USB_CLKS,
		HW_DIGCTL_CTRL_USB0_CLKGATE,
	},
#endif
#ifdef CONFIG_EHCI_MXS_PORT1
	{
		MXS_USBCTRL1_BASE,
		(struct mxs_usbphy_regs *)MXS_USBPHY1_BASE,
		(struct mxs_register_32 *)(MXS_CLKCTRL_BASE +
			offsetof(struct mxs_clkctrl_regs,
			hw_clkctrl_pll1ctrl0_reg)),
		CLKCTRL_PLL1CTRL0_EN_USB_CLKS | CLKCTRL_PLL1CTRL0_POWER,
		CLKCTRL_PLL1CTRL0_EN_USB_CLKS,
		HW_DIGCTL_CTRL_USB1_CLKGATE,
	},
#endif
};

static int ehci_mxs_toggle_clock(const struct ehci_mxs_port *port, int enable)
{
	struct mxs_register_32 *digctl_ctrl =
		(struct mxs_register_32 *)HW_DIGCTL_CTRL;
	int pll_offset, dig_offset;

	if (enable) {
		pll_offset = offsetof(struct mxs_register_32, reg_set);
		dig_offset = offsetof(struct mxs_register_32, reg_clr);
		writel(port->gate_bits, (u32)&digctl_ctrl->reg + dig_offset);
		writel(port->pll_en_bits, (u32)port->pll + pll_offset);
	} else {
		pll_offset = offsetof(struct mxs_register_32, reg_clr);
		dig_offset = offsetof(struct mxs_register_32, reg_set);
		writel(port->pll_dis_bits, (u32)port->pll + pll_offset);
		writel(port->gate_bits, (u32)&digctl_ctrl->reg + dig_offset);
	}

	return 0;
}

int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{

	int ret;
	uint32_t usb_base, cap_base;
	const struct ehci_mxs_port *port;

	if ((index < 0) || (index >= ARRAY_SIZE(mxs_port))) {
		printf("Invalid port index (index = %d)!\n", index);
		return -EINVAL;
	}

	port = &mxs_port[index];

	/* Reset the PHY block */
	writel(USBPHY_CTRL_SFTRST, &port->phy_regs->hw_usbphy_ctrl_set);
	udelay(10);
	writel(USBPHY_CTRL_SFTRST | USBPHY_CTRL_CLKGATE,
		&port->phy_regs->hw_usbphy_ctrl_clr);

	/* Enable USB clock */
	ret = ehci_mxs_toggle_clock(port, 1);
	if (ret)
		return ret;

	/* Start USB PHY */
	writel(0, &port->phy_regs->hw_usbphy_pwd);

	/* Enable UTMI+ Level 2 and Level 3 compatibility */
	writel(USBPHY_CTRL_ENUTMILEVEL3 | USBPHY_CTRL_ENUTMILEVEL2 | 1,
		&port->phy_regs->hw_usbphy_ctrl_set);

	usb_base = port->usb_regs + 0x100;
	*hccr = (struct ehci_hccr *)usb_base;

	cap_base = ehci_readl(&(*hccr)->cr_capbase);
	*hcor = (struct ehci_hcor *)(usb_base + HC_LENGTH(cap_base));

	return 0;
}

int ehci_hcd_stop(int index)
{
	int ret;
	uint32_t usb_base, cap_base, tmp;
	struct ehci_hccr *hccr;
	struct ehci_hcor *hcor;
	const struct ehci_mxs_port *port;

	if ((index < 0) || (index >= ARRAY_SIZE(mxs_port))) {
		printf("Invalid port index (index = %d)!\n", index);
		return -EINVAL;
	}

	port = &mxs_port[index];

	/* Stop the USB port */
	usb_base = port->usb_regs + 0x100;
	hccr = (struct ehci_hccr *)usb_base;
	cap_base = ehci_readl(&hccr->cr_capbase);
	hcor = (struct ehci_hcor *)(usb_base + HC_LENGTH(cap_base));

	tmp = ehci_readl(&hcor->or_usbcmd);
	tmp &= ~CMD_RUN;
	ehci_writel(tmp, &hcor->or_usbcmd);

	/* Disable the PHY */
	tmp = USBPHY_PWD_RXPWDRX | USBPHY_PWD_RXPWDDIFF |
		USBPHY_PWD_RXPWD1PT1 | USBPHY_PWD_RXPWDENV |
		USBPHY_PWD_TXPWDV2I | USBPHY_PWD_TXPWDIBIAS |
		USBPHY_PWD_TXPWDFS;
	writel(tmp, &port->phy_regs->hw_usbphy_pwd);

	/* Disable USB clock */
	ret = ehci_mxs_toggle_clock(port, 0);

	return ret;
}
Commit	Line	Data
dbb8f279 MV	1	/*
	2	* Freescale i.MX28 USB Host driver
	3	*
	4	* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
	5	* on behalf of DENX Software Engineering GmbH
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
dbb8f279 MV	8	*/
	9
	10	#include <common.h>
	11	#include <asm/io.h>
47f13315	12	#include <asm/arch/imx-regs.h>
afa87210	13	#include <errno.h>
dbb8f279	14
dbb8f279 MV	15	#include "ehci.h"
dbb8f279 MV	16
afa87210 MV	17	/* This DIGCTL register ungates clock to USB */
	18	#define HW_DIGCTL_CTRL 0x8001c000
	19	#define HW_DIGCTL_CTRL_USB0_CLKGATE (1 << 2)
	20	#define HW_DIGCTL_CTRL_USB1_CLKGATE (1 << 16)
dbb8f279	21
afa87210 MV	22	struct ehci_mxs_port {
afa87210 MV	23	uint32_t usb_regs;
9c471142	24	struct mxs_usbphy_regs *phy_regs;
dbb8f279	25
afa87210 MV	26	struct mxs_register_32 *pll;
	27	uint32_t pll_en_bits;
	28	uint32_t pll_dis_bits;
	29	uint32_t gate_bits;
	30	};
	31
	32	static const struct ehci_mxs_port mxs_port[] = {
	33	#ifdef CONFIG_EHCI_MXS_PORT0
	34	{
	35	MXS_USBCTRL0_BASE,
	36	(struct mxs_usbphy_regs *)MXS_USBPHY0_BASE,
	37	(struct mxs_register_32 *)(MXS_CLKCTRL_BASE +
	38	offsetof(struct mxs_clkctrl_regs,
	39	hw_clkctrl_pll0ctrl0_reg)),
	40	CLKCTRL_PLL0CTRL0_EN_USB_CLKS \| CLKCTRL_PLL0CTRL0_POWER,
	41	CLKCTRL_PLL0CTRL0_EN_USB_CLKS,
	42	HW_DIGCTL_CTRL_USB0_CLKGATE,
	43	},
	44	#endif
	45	#ifdef CONFIG_EHCI_MXS_PORT1
	46	{
	47	MXS_USBCTRL1_BASE,
	48	(struct mxs_usbphy_regs *)MXS_USBPHY1_BASE,
	49	(struct mxs_register_32 *)(MXS_CLKCTRL_BASE +
	50	offsetof(struct mxs_clkctrl_regs,
	51	hw_clkctrl_pll1ctrl0_reg)),
	52	CLKCTRL_PLL1CTRL0_EN_USB_CLKS \| CLKCTRL_PLL1CTRL0_POWER,
	53	CLKCTRL_PLL1CTRL0_EN_USB_CLKS,
	54	HW_DIGCTL_CTRL_USB1_CLKGATE,
	55	},
	56	#endif
	57	};
	58
	59	static int ehci_mxs_toggle_clock(const struct ehci_mxs_port *port, int enable)
dbb8f279	60	{
afa87210 MV	61	struct mxs_register_32 *digctl_ctrl =
	62	(struct mxs_register_32 *)HW_DIGCTL_CTRL;
	63	int pll_offset, dig_offset;
	64
	65	if (enable) {
	66	pll_offset = offsetof(struct mxs_register_32, reg_set);
	67	dig_offset = offsetof(struct mxs_register_32, reg_clr);
	68	writel(port->gate_bits, (u32)&digctl_ctrl->reg + dig_offset);
	69	writel(port->pll_en_bits, (u32)port->pll + pll_offset);
	70	} else {
	71	pll_offset = offsetof(struct mxs_register_32, reg_clr);
	72	dig_offset = offsetof(struct mxs_register_32, reg_set);
	73	writel(port->pll_dis_bits, (u32)port->pll + pll_offset);
	74	writel(port->gate_bits, (u32)&digctl_ctrl->reg + dig_offset);
dbb8f279 MV	75	}
dbb8f279 MV	76
dbb8f279 MV	77	return 0;
	78	}
	79
676ae068	80	int ehci_hcd_init(int index, struct ehci_hccr hccr, struct ehci_hcor hcor)
dbb8f279 MV	81	{
	82
	83	int ret;
	84	uint32_t usb_base, cap_base;
afa87210	85	const struct ehci_mxs_port *port;
dbb8f279	86
afa87210 MV	87	if ((index < 0) \|\| (index >= ARRAY_SIZE(mxs_port))) {
	88	printf("Invalid port index (index = %d)!\n", index);
	89	return -EINVAL;
	90	}
	91
	92	port = &mxs_port[index];
dbb8f279 MV	93
dbb8f279 MV	94	/* Reset the PHY block */
afa87210	95	writel(USBPHY_CTRL_SFTRST, &port->phy_regs->hw_usbphy_ctrl_set);
dbb8f279 MV	96	udelay(10);
dbb8f279 MV	97	writel(USBPHY_CTRL_SFTRST \| USBPHY_CTRL_CLKGATE,
afa87210	98	&port->phy_regs->hw_usbphy_ctrl_clr);
dbb8f279 MV	99
dbb8f279 MV	100	/* Enable USB clock */
afa87210 MV	101	ret = ehci_mxs_toggle_clock(port, 1);
	102	if (ret)
	103	return ret;
dbb8f279 MV	104
dbb8f279 MV	105	/* Start USB PHY */
afa87210	106	writel(0, &port->phy_regs->hw_usbphy_pwd);
dbb8f279 MV	107
	108	/* Enable UTMI+ Level 2 and Level 3 compatibility */
	109	writel(USBPHY_CTRL_ENUTMILEVEL3 \| USBPHY_CTRL_ENUTMILEVEL2 \| 1,
afa87210	110	&port->phy_regs->hw_usbphy_ctrl_set);
dbb8f279	111
afa87210	112	usb_base = port->usb_regs + 0x100;
676ae068	113	hccr = (struct ehci_hccr )usb_base;
dbb8f279	114
676ae068 LS	115	cap_base = ehci_readl(&(*hccr)->cr_capbase);
676ae068 LS	116	hcor = (struct ehci_hcor )(usb_base + HC_LENGTH(cap_base));
dbb8f279 MV	117
	118	return 0;
	119	}
	120
676ae068	121	int ehci_hcd_stop(int index)
dbb8f279 MV	122	{
dbb8f279 MV	123	int ret;
676ae068	124	uint32_t usb_base, cap_base, tmp;
676ae068 LS	125	struct ehci_hccr *hccr;
676ae068 LS	126	struct ehci_hcor *hcor;
afa87210	127	const struct ehci_mxs_port *port;
dbb8f279	128
afa87210 MV	129	if ((index < 0) \|\| (index >= ARRAY_SIZE(mxs_port))) {
	130	printf("Invalid port index (index = %d)!\n", index);
	131	return -EINVAL;
	132	}
	133
	134	port = &mxs_port[index];
dbb8f279 MV	135
dbb8f279 MV	136	/* Stop the USB port */
afa87210	137	usb_base = port->usb_regs + 0x100;
676ae068 LS	138	hccr = (struct ehci_hccr *)usb_base;
	139	cap_base = ehci_readl(&hccr->cr_capbase);
	140	hcor = (struct ehci_hcor *)(usb_base + HC_LENGTH(cap_base));
	141
dbb8f279 MV	142	tmp = ehci_readl(&hcor->or_usbcmd);
	143	tmp &= ~CMD_RUN;
	144	ehci_writel(tmp, &hcor->or_usbcmd);
	145
	146	/* Disable the PHY */
	147	tmp = USBPHY_PWD_RXPWDRX \| USBPHY_PWD_RXPWDDIFF \|
	148	USBPHY_PWD_RXPWD1PT1 \| USBPHY_PWD_RXPWDENV \|
	149	USBPHY_PWD_TXPWDV2I \| USBPHY_PWD_TXPWDIBIAS \|
	150	USBPHY_PWD_TXPWDFS;
afa87210	151	writel(tmp, &port->phy_regs->hw_usbphy_pwd);
dbb8f279 MV	152
dbb8f279 MV	153	/* Disable USB clock */
afa87210	154	ret = ehci_mxs_toggle_clock(port, 0);
dbb8f279	155
afa87210	156	return ret;
dbb8f279	157	}