[people/ms/u-boot.git] / drivers / usb / host / ehci-omap.c

/*
 * (C) Copyright 2011 Ilya Yanok, Emcraft Systems
 * (C) Copyright 2004-2008
 * Texas Instruments, <www.ti.com>
 *
 * Derived from Beagle Board code by
 *	Sunil Kumar <sunilsaini05@gmail.com>
 *	Shashi Ranjan <shashiranjanmca05@gmail.com>
 *
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <usb.h>
#include <usb/ulpi.h>
#include <errno.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/ehci.h>
#include <asm/ehci-omap.h>

#include "ehci.h"

static struct omap_uhh *const uhh = (struct omap_uhh *)OMAP_UHH_BASE;
static struct omap_usbtll *const usbtll = (struct omap_usbtll *)OMAP_USBTLL_BASE;
static struct omap_ehci *const ehci = (struct omap_ehci *)OMAP_EHCI_BASE;

static int omap_uhh_reset(void)
{
	int timeout = 0;
	u32 rev;

	rev = readl(&uhh->rev);

	/* Soft RESET */
	writel(OMAP_UHH_SYSCONFIG_SOFTRESET, &uhh->sysc);

	switch (rev) {
	case OMAP_USBHS_REV1:
		/* Wait for soft RESET to complete */
		while (!(readl(&uhh->syss) & 0x1)) {
			if (timeout > 100) {
				printf("%s: RESET timeout\n", __func__);
				return -1;
			}
			udelay(10);
			timeout++;
		}

		/* Set No-Idle, No-Standby */
		writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
		break;

	default:	/* Rev. 2 onwards */

		udelay(2); /* Need to wait before accessing SYSCONFIG back */

		/* Wait for soft RESET to complete */
		while ((readl(&uhh->sysc) & 0x1)) {
			if (timeout > 100) {
				printf("%s: RESET timeout\n", __func__);
				return -1;
			}
			udelay(10);
			timeout++;
		}

		writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
		break;
	}

	return 0;
}

static int omap_ehci_tll_reset(void)
{
	unsigned long init = get_timer(0);

	/* perform TLL soft reset, and wait until reset is complete */
	writel(OMAP_USBTLL_SYSCONFIG_SOFTRESET, &usbtll->sysc);

	/* Wait for TLL reset to complete */
	while (!(readl(&usbtll->syss) & OMAP_USBTLL_SYSSTATUS_RESETDONE))
		if (get_timer(init) > CONFIG_SYS_HZ) {
			debug("OMAP EHCI error: timeout resetting TLL\n");
			return -EL3RST;
	}

	return 0;
}

static void omap_usbhs_hsic_init(int port)
{
	unsigned int reg;

	/* Enable channels now */
	reg = readl(&usbtll->channel_conf + port);

	setbits_le32(&reg, (OMAP_TLL_CHANNEL_CONF_CHANMODE_TRANSPARENT_UTMI
		| OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF
		| OMAP_TLL_CHANNEL_CONF_DRVVBUS
		| OMAP_TLL_CHANNEL_CONF_CHRGVBUS
		| OMAP_TLL_CHANNEL_CONF_CHANEN));

	writel(reg, &usbtll->channel_conf + port);
}

#ifdef CONFIG_USB_ULPI
static void omap_ehci_soft_phy_reset(int port)
{
	struct ulpi_viewport ulpi_vp;

	ulpi_vp.viewport_addr = (u32)&ehci->insreg05_utmi_ulpi;
	ulpi_vp.port_num = port;

	ulpi_reset(&ulpi_vp);
}
#else
static void omap_ehci_soft_phy_reset(int port)
{
	return;
}
#endif

#if defined(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO) || \
	defined(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO) || \
	defined(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO)
/* controls PHY(s) reset signal(s) */
static inline void omap_ehci_phy_reset(int on, int delay)
{
	/*
	 * Refer ISSUE1:
	 * Hold the PHY in RESET for enough time till
	 * PHY is settled and ready
	 */
	if (delay && !on)
		udelay(delay);
#ifdef CONFIG_OMAP_EHCI_PHY1_RESET_GPIO
	gpio_request(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, "USB PHY1 reset");
	gpio_direction_output(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, !on);
#endif
#ifdef CONFIG_OMAP_EHCI_PHY2_RESET_GPIO
	gpio_request(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, "USB PHY2 reset");
	gpio_direction_output(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, !on);
#endif
#ifdef CONFIG_OMAP_EHCI_PHY3_RESET_GPIO
	gpio_request(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, "USB PHY3 reset");
	gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, !on);
#endif

	/* Hold the PHY in RESET for enough time till DIR is high */
	/* Refer: ISSUE1 */
	if (delay && on)
		udelay(delay);
}
#else
#define omap_ehci_phy_reset(on, delay)	do {} while (0)
#endif

/* Reset is needed otherwise the kernel-driver will throw an error. */
int omap_ehci_hcd_stop(void)
{
	debug("Resetting OMAP EHCI\n");
	omap_ehci_phy_reset(1, 0);

	if (omap_uhh_reset() < 0)
		return -1;

	if (omap_ehci_tll_reset() < 0)
		return -1;

	return 0;
}

/*
 * Initialize the OMAP EHCI controller and PHY.
 * Based on "drivers/usb/host/ehci-omap.c" from Linux 3.1
 * See there for additional Copyrights.
 */
int omap_ehci_hcd_init(int index, struct omap_usbhs_board_data *usbhs_pdata,
		       struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
	int ret;
	unsigned int i, reg = 0, rev = 0;

	debug("Initializing OMAP EHCI\n");

	ret = board_usb_init(index, USB_INIT_HOST);
	if (ret < 0)
		return ret;

	/* Put the PHY in RESET */
	omap_ehci_phy_reset(1, 10);

	ret = omap_uhh_reset();
	if (ret < 0)
		return ret;

	ret = omap_ehci_tll_reset();
	if (ret)
		return ret;

	writel(OMAP_USBTLL_SYSCONFIG_ENAWAKEUP |
		OMAP_USBTLL_SYSCONFIG_SIDLEMODE |
		OMAP_USBTLL_SYSCONFIG_CACTIVITY, &usbtll->sysc);

	/* Put UHH in NoIdle/NoStandby mode */
	writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);

	/* setup ULPI bypass and burst configurations */
	clrsetbits_le32(&reg, OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN,
		(OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN |
		OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN |
		OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN));

	rev = readl(&uhh->rev);
	if (rev == OMAP_USBHS_REV1) {
		if (is_ehci_phy_mode(usbhs_pdata->port_mode[0]))
			clrbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS);
		else
			setbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS);

		if (is_ehci_phy_mode(usbhs_pdata->port_mode[1]))
			clrbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS);
		else
			setbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS);

		if (is_ehci_phy_mode(usbhs_pdata->port_mode[2]))
			clrbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS);
		else
			setbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS);
	} else if (rev == OMAP_USBHS_REV2) {

		clrsetbits_le32(&reg, (OMAP_P1_MODE_CLEAR | OMAP_P2_MODE_CLEAR),
					OMAP4_UHH_HOSTCONFIG_APP_START_CLK);

		/* Clear port mode fields for PHY mode */

		if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0]))
			setbits_le32(&reg, OMAP_P1_MODE_HSIC);

		if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1]))
			setbits_le32(&reg, OMAP_P2_MODE_HSIC);

	} else if (rev == OMAP_USBHS_REV2_1) {

		clrsetbits_le32(&reg,
				(OMAP_P1_MODE_CLEAR |
				 OMAP_P2_MODE_CLEAR |
				 OMAP_P3_MODE_CLEAR),
				OMAP4_UHH_HOSTCONFIG_APP_START_CLK);

		/* Clear port mode fields for PHY mode */

		if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0]))
			setbits_le32(&reg, OMAP_P1_MODE_HSIC);

		if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1]))
			setbits_le32(&reg, OMAP_P2_MODE_HSIC);

		if (is_ehci_hsic_mode(usbhs_pdata->port_mode[2]))
			setbits_le32(&reg, OMAP_P3_MODE_HSIC);
	}

	debug("OMAP UHH_REVISION 0x%x\n", rev);
	writel(reg, &uhh->hostconfig);

	for (i = 0; i < OMAP_HS_USB_PORTS; i++)
		if (is_ehci_hsic_mode(usbhs_pdata->port_mode[i]))
			omap_usbhs_hsic_init(i);

	omap_ehci_phy_reset(0, 10);

	/*
	 * An undocumented "feature" in the OMAP3 EHCI controller,
	 * causes suspended ports to be taken out of suspend when
	 * the USBCMD.Run/Stop bit is cleared (for example when
	 * we do ehci_bus_suspend).
	 * This breaks suspend-resume if the root-hub is allowed
	 * to suspend. Writing 1 to this undocumented register bit
	 * disables this feature and restores normal behavior.
	 */
	writel(EHCI_INSNREG04_DISABLE_UNSUSPEND, &ehci->insreg04);

	for (i = 0; i < OMAP_HS_USB_PORTS; i++)
		if (is_ehci_phy_mode(usbhs_pdata->port_mode[i]))
			omap_ehci_soft_phy_reset(i);

	*hccr = (struct ehci_hccr *)(OMAP_EHCI_BASE);
	*hcor = (struct ehci_hcor *)(OMAP_EHCI_BASE + 0x10);

	debug("OMAP EHCI init done\n");
	return 0;
}
Commit	Line	Data
29321c05 IY	1	/*
	2	* (C) Copyright 2011 Ilya Yanok, Emcraft Systems
	3	* (C) Copyright 2004-2008
	4	* Texas Instruments, <www.ti.com>
	5	*
	6	* Derived from Beagle Board code by
	7	* Sunil Kumar <sunilsaini05@gmail.com>
	8	* Shashi Ranjan <shashiranjanmca05@gmail.com>
	9	*
	10	*
1a459660	11	* SPDX-License-Identifier: GPL-2.0+
29321c05	12	*/
1a459660	13
29321c05 IY	14	#include <common.h>
29321c05 IY	15	#include <usb.h>
43b62393 G	16	#include <usb/ulpi.h>
43b62393 G	17	#include <errno.h>
29321c05 IY	18	#include <asm/io.h>
29321c05 IY	19	#include <asm/gpio.h>
43b62393 G	20	#include <asm/arch/ehci.h>
43b62393 G	21	#include <asm/ehci-omap.h>
676ae068 LS	22
676ae068 LS	23	#include "ehci.h"
29321c05	24
43b62393 G	25	static struct omap_uhh const uhh = (struct omap_uhh )OMAP_UHH_BASE;
	26	static struct omap_usbtll const usbtll = (struct omap_usbtll )OMAP_USBTLL_BASE;
	27	static struct omap_ehci const ehci = (struct omap_ehci )OMAP_EHCI_BASE;
	28
	29	static int omap_uhh_reset(void)
	30	{
835a5559 RQ	31	int timeout = 0;
	32	u32 rev;
	33
	34	rev = readl(&uhh->rev);
	35
	36	/* Soft RESET */
	37	writel(OMAP_UHH_SYSCONFIG_SOFTRESET, &uhh->sysc);
	38
	39	switch (rev) {
	40	case OMAP_USBHS_REV1:
	41	/* Wait for soft RESET to complete */
	42	while (!(readl(&uhh->syss) & 0x1)) {
	43	if (timeout > 100) {
	44	printf("%s: RESET timeout\n", __func__);
	45	return -1;
	46	}
	47	udelay(10);
	48	timeout++;
	49	}
	50
	51	/* Set No-Idle, No-Standby */
	52	writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
	53	break;
	54
	55	default: /* Rev. 2 onwards */
	56
	57	udelay(2); /* Need to wait before accessing SYSCONFIG back */
	58
	59	/* Wait for soft RESET to complete */
	60	while ((readl(&uhh->sysc) & 0x1)) {
	61	if (timeout > 100) {
	62	printf("%s: RESET timeout\n", __func__);
	63	return -1;
	64	}
	65	udelay(10);
	66	timeout++;
	67	}
	68
	69	writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
	70	break;
	71	}
	72
43b62393 G	73	return 0;
	74	}
	75
	76	static int omap_ehci_tll_reset(void)
	77	{
	78	unsigned long init = get_timer(0);
	79
	80	/* perform TLL soft reset, and wait until reset is complete */
	81	writel(OMAP_USBTLL_SYSCONFIG_SOFTRESET, &usbtll->sysc);
	82
	83	/* Wait for TLL reset to complete */
	84	while (!(readl(&usbtll->syss) & OMAP_USBTLL_SYSSTATUS_RESETDONE))
	85	if (get_timer(init) > CONFIG_SYS_HZ) {
	86	debug("OMAP EHCI error: timeout resetting TLL\n");
	87	return -EL3RST;
	88	}
	89
	90	return 0;
	91	}
	92
	93	static void omap_usbhs_hsic_init(int port)
	94	{
	95	unsigned int reg;
	96
	97	/* Enable channels now */
	98	reg = readl(&usbtll->channel_conf + port);
	99
	100	setbits_le32(&reg, (OMAP_TLL_CHANNEL_CONF_CHANMODE_TRANSPARENT_UTMI
	101	\| OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF
	102	\| OMAP_TLL_CHANNEL_CONF_DRVVBUS
	103	\| OMAP_TLL_CHANNEL_CONF_CHRGVBUS
	104	\| OMAP_TLL_CHANNEL_CONF_CHANEN));
	105
	106	writel(reg, &usbtll->channel_conf + port);
	107	}
	108
120503f3	109	#ifdef CONFIG_USB_ULPI
43b62393 G	110	static void omap_ehci_soft_phy_reset(int port)
	111	{
	112	struct ulpi_viewport ulpi_vp;
	113
	114	ulpi_vp.viewport_addr = (u32)&ehci->insreg05_utmi_ulpi;
	115	ulpi_vp.port_num = port;
	116
	117	ulpi_reset(&ulpi_vp);
	118	}
120503f3 DM	119	#else
	120	static void omap_ehci_soft_phy_reset(int port)
	121	{
	122	return;
	123	}
	124	#endif
43b62393	125
29321c05	126	#if defined(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO) \|\| \
d3d037ae DM	127	defined(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO) \|\| \
d3d037ae DM	128	defined(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO)
29321c05 IY	129	/* controls PHY(s) reset signal(s) */
	130	static inline void omap_ehci_phy_reset(int on, int delay)
	131	{
	132	/*
	133	* Refer ISSUE1:
	134	* Hold the PHY in RESET for enough time till
	135	* PHY is settled and ready
	136	*/
	137	if (delay && !on)
	138	udelay(delay);
	139	#ifdef CONFIG_OMAP_EHCI_PHY1_RESET_GPIO
	140	gpio_request(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, "USB PHY1 reset");
	141	gpio_direction_output(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, !on);
	142	#endif
	143	#ifdef CONFIG_OMAP_EHCI_PHY2_RESET_GPIO
	144	gpio_request(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, "USB PHY2 reset");
	145	gpio_direction_output(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, !on);
	146	#endif
d3d037ae DM	147	#ifdef CONFIG_OMAP_EHCI_PHY3_RESET_GPIO
	148	gpio_request(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, "USB PHY3 reset");
	149	gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, !on);
	150	#endif
29321c05 IY	151
	152	/* Hold the PHY in RESET for enough time till DIR is high */
	153	/* Refer: ISSUE1 */
	154	if (delay && on)
	155	udelay(delay);
	156	}
	157	#else
	158	#define omap_ehci_phy_reset(on, delay) do {} while (0)
	159	#endif
	160
	161	/* Reset is needed otherwise the kernel-driver will throw an error. */
43b62393	162	int omap_ehci_hcd_stop(void)
29321c05	163	{
43b62393	164	debug("Resetting OMAP EHCI\n");
29321c05	165	omap_ehci_phy_reset(1, 0);
43b62393 G	166
	167	if (omap_uhh_reset() < 0)
	168	return -1;
	169
	170	if (omap_ehci_tll_reset() < 0)
	171	return -1;
	172
29321c05 IY	173	return 0;
	174	}
	175
	176	/*
43b62393 G	177	* Initialize the OMAP EHCI controller and PHY.
43b62393 G	178	* Based on "drivers/usb/host/ehci-omap.c" from Linux 3.1
29321c05 IY	179	* See there for additional Copyrights.
29321c05 IY	180	*/
16297cfb MZ	181	int omap_ehci_hcd_init(int index, struct omap_usbhs_board_data *usbhs_pdata,
16297cfb MZ	182	struct ehci_hccr hccr, struct ehci_hcor hcor)
29321c05 IY	183	{
29321c05 IY	184	int ret;
43b62393	185	unsigned int i, reg = 0, rev = 0;
29321c05	186
43b62393	187	debug("Initializing OMAP EHCI\n");
29321c05	188
16297cfb	189	ret = board_usb_init(index, USB_INIT_HOST);
29321c05 IY	190	if (ret < 0)
	191	return ret;
	192
	193	/* Put the PHY in RESET */
	194	omap_ehci_phy_reset(1, 10);
	195
43b62393 G	196	ret = omap_uhh_reset();
	197	if (ret < 0)
	198	return ret;
29321c05	199
43b62393 G	200	ret = omap_ehci_tll_reset();
	201	if (ret)
	202	return ret;
29321c05 IY	203
	204	writel(OMAP_USBTLL_SYSCONFIG_ENAWAKEUP \|
	205	OMAP_USBTLL_SYSCONFIG_SIDLEMODE \|
43b62393	206	OMAP_USBTLL_SYSCONFIG_CACTIVITY, &usbtll->sysc);
29321c05 IY	207
29321c05 IY	208	/* Put UHH in NoIdle/NoStandby mode */
43b62393 G	209	writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
	210
	211	/* setup ULPI bypass and burst configurations */
	212	clrsetbits_le32(&reg, OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN,
	213	(OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN \|
	214	OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN \|
	215	OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN));
	216
	217	rev = readl(&uhh->rev);
	218	if (rev == OMAP_USBHS_REV1) {
	219	if (is_ehci_phy_mode(usbhs_pdata->port_mode[0]))
	220	clrbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS);
	221	else
	222	setbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS);
	223
	224	if (is_ehci_phy_mode(usbhs_pdata->port_mode[1]))
	225	clrbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS);
	226	else
90579fdd	227	setbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS);
43b62393 G	228
	229	if (is_ehci_phy_mode(usbhs_pdata->port_mode[2]))
	230	clrbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS);
	231	else
90579fdd	232	setbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS);
43b62393	233	} else if (rev == OMAP_USBHS_REV2) {
d3d037ae	234
43b62393 G	235	clrsetbits_le32(&reg, (OMAP_P1_MODE_CLEAR \| OMAP_P2_MODE_CLEAR),
	236	OMAP4_UHH_HOSTCONFIG_APP_START_CLK);
	237
d3d037ae DM	238	/* Clear port mode fields for PHY mode */
	239
	240	if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0]))
	241	setbits_le32(&reg, OMAP_P1_MODE_HSIC);
	242
	243	if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1]))
	244	setbits_le32(&reg, OMAP_P2_MODE_HSIC);
	245
	246	} else if (rev == OMAP_USBHS_REV2_1) {
	247
	248	clrsetbits_le32(&reg,
	249	(OMAP_P1_MODE_CLEAR \|
	250	OMAP_P2_MODE_CLEAR \|
	251	OMAP_P3_MODE_CLEAR),
	252	OMAP4_UHH_HOSTCONFIG_APP_START_CLK);
	253
	254	/* Clear port mode fields for PHY mode */
43b62393 G	255
	256	if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0]))
	257	setbits_le32(&reg, OMAP_P1_MODE_HSIC);
	258
	259	if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1]))
	260	setbits_le32(&reg, OMAP_P2_MODE_HSIC);
	261
	262	if (is_ehci_hsic_mode(usbhs_pdata->port_mode[2]))
	263	setbits_le32(&reg, OMAP_P3_MODE_HSIC);
	264	}
	265
	266	debug("OMAP UHH_REVISION 0x%x\n", rev);
	267	writel(reg, &uhh->hostconfig);
	268
	269	for (i = 0; i < OMAP_HS_USB_PORTS; i++)
	270	if (is_ehci_hsic_mode(usbhs_pdata->port_mode[i]))
	271	omap_usbhs_hsic_init(i);
29321c05 IY	272
	273	omap_ehci_phy_reset(0, 10);
	274
43b62393 G	275	/*
	276	* An undocumented "feature" in the OMAP3 EHCI controller,
	277	* causes suspended ports to be taken out of suspend when
	278	* the USBCMD.Run/Stop bit is cleared (for example when
	279	* we do ehci_bus_suspend).
	280	* This breaks suspend-resume if the root-hub is allowed
	281	* to suspend. Writing 1 to this undocumented register bit
	282	* disables this feature and restores normal behavior.
	283	*/
	284	writel(EHCI_INSNREG04_DISABLE_UNSUSPEND, &ehci->insreg04);
	285
	286	for (i = 0; i < OMAP_HS_USB_PORTS; i++)
	287	if (is_ehci_phy_mode(usbhs_pdata->port_mode[i]))
	288	omap_ehci_soft_phy_reset(i);
	289
676ae068 LS	290	hccr = (struct ehci_hccr )(OMAP_EHCI_BASE);
676ae068 LS	291	hcor = (struct ehci_hcor )(OMAP_EHCI_BASE + 0x10);
29321c05	292
43b62393	293	debug("OMAP EHCI init done\n");
29321c05 IY	294	return 0;
29321c05 IY	295	}